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| author | Jagan Teki <jagan@amarulasolutions.com> | 2021-12-11 17:30:34 +0530 |
|---|---|---|
| committer | umpf <entwicklung@pengutronix.de> | 2022-07-31 14:03:01 -0700 |
| commit | ff80b273eb22de5fe6493e8fc4e74440653a5624 (patch) | |
| tree | fb4a54bdcb03df20c8e822dc640ddf85641d6f3d | |
| parent | 222280fe9fb36af828e79f6f7023014d77b65620 (diff) | |
| download | linux-ff80b273eb22de5fe6493e8fc4e74440653a5624.tar.gz linux-ff80b273eb22de5fe6493e8fc4e74440653a5624.tar.xz | |
arm64: dts: imx8mm: Add MIPI DSI pipeline
Add MIPI DSI pipeline for i.MX8MM.
Video pipeline start from eLCDIF to MIPI DSI and respective
Panel or Bridge on the backend side.
Add support for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mm.dtsi | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index cd7c918df5b9..921033fa5bc3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1109,6 +1109,59 @@ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>; status = "disabled"; + + port { + lcdif_out_dsi: endpoint { + remote-endpoint = <&dsi_in_lcdif>; + }; + }; + }; + + dsi: dsi@32e10000 { + compatible = "fsl,imx8mm-mipi-dsim"; + reg = <0x32e10000 0x400>; + clocks = <&clk IMX8MM_CLK_DSI_CORE>, + <&clk IMX8MM_CLK_DSI_PHY_REF>; + clock-names = "bus_clk", "sclk_mipi"; + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>, + <&clk IMX8MM_VIDEO_PLL1_OUT>, + <&clk IMX8MM_CLK_DSI_PHY_REF>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, + <&clk IMX8MM_VIDEO_PLL1_BYPASS>, + <&clk IMX8MM_VIDEO_PLL1_OUT>; + assigned-clock-rates = <266000000>, <594000000>, <27000000>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>; + samsung,burst-clock-frequency = <891000000>; + samsung,esc-clock-frequency = <20000000>; + samsung,pll-clock-frequency = <27000000>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dsi_in_lcdif: endpoint@0 { + reg = <0>; + remote-endpoint = <&lcdif_out_dsi>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dsi_out: endpoint@0 { + reg = <0>; + }; + }; + }; }; csi: csi@32e20000 { |