v7a: tf-a: update to v2.4

Trusted Firmware-A v2.4 was released last month and adds amongst others,
enhancements to make use of the trusted boot chain possible with
upstream components.

The patch stack has now been posted upstream in hope we can eventually
drop it:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/7339
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/7340

For now, it was rebased with following modifications:
  - Sync with upstream device tree and new TF-A requirements
  - CLK_ETH_PLL4P is enabled for possible PTP use

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>

5 files changed, 167 insertions, 88 deletions

diff --git a/configs/platform-v7a/patches/tf-a-v2.3/series b/configs/platform-v7a/patches/tf-a-v2.3/series
deleted file mode 100644
index 2f7ede3..0000000
--- a/configs/platform-v7a/patches/tf-a-v2.3/series
+++ /dev/null
@@ -1 +0,0 @@
-0001-fdts-stm32mp1-add-support-for-Linux-Automation-MC-1-.patch
diff --git a/configs/platform-v7a/patches/tf-a-v2.3/0001-fdts-stm32mp1-add-support-for-Linux-Automation-MC-1-.patch b/configs/platform-v7a/patches/tf-a-v2.4/0001-fdts-stm32mp1-add-support-for-Linux-Automation-MC-1-.patch
index abfbd7e..cc8dd07 100644
--- a/configs/platform-v7a/patches/tf-a-v2.3/0001-fdts-stm32mp1-add-support-for-Linux-Automation-MC-1-.patch
+++ b/configs/platform-v7a/patches/tf-a-v2.4/0001-fdts-stm32mp1-add-support-for-Linux-Automation-MC-1-.patch
@@ -1,27 +1,32 @@
-From 8713c33c448dddcaee33d71fe3d5d2ed40c49283 Mon Sep 17 00:00:00 2001
 From: Ahmad Fatoum <a.fatoum@pengutronix.de>
 Date: Wed, 29 Jan 2020 16:04:18 +0100
-Subject: [PATCH] fdts: stm32mp1: add support for Linux Automation MC-1
- board
+Subject: [PATCH] fdts: stm32mp1: add support for Linux Automation MC-1 board
 
 The Linux Automation MC-1 is a SBC built around the Octavo Systems
 OSD32MP15x SiP. The SiP features up to 1 GB DDR3 RAM, EEPROM and
 PMIC. The board has eMMC and a SD slot for storage.
 
+The SDRAM calibration values are taken as is from the DKx boards, which
+seem to be suitable for operation at German room temperature.
+
+This is deemed ok for now, but for use in the field, the SiP will likely
+need to have its timings determined in a climate chamber.
+
+Change-Id: I5f43a61930151ae9d1df2ea7d0f6f9697c813ce0
 Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
 ---
- fdts/stm32mp157c-lxa-mc1.dts | 110 ++++++++++++++
- fdts/stm32mp15xx-osd32.dtsi  | 271 +++++++++++++++++++++++++++++++++++
- 2 files changed, 381 insertions(+)
+ fdts/stm32mp157c-lxa-mc1.dts | 106 +++++++++++++++++
+ fdts/stm32mp15xx-osd32.dtsi  | 278 +++++++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 384 insertions(+)
  create mode 100644 fdts/stm32mp157c-lxa-mc1.dts
  create mode 100644 fdts/stm32mp15xx-osd32.dtsi
 
 diff --git a/fdts/stm32mp157c-lxa-mc1.dts b/fdts/stm32mp157c-lxa-mc1.dts
 new file mode 100644
-index 000000000000..e75e7b5ba28b
+index 000000000000..47b96852496f
 --- /dev/null
 +++ b/fdts/stm32mp157c-lxa-mc1.dts
-@@ -0,0 +1,110 @@
+@@ -0,0 +1,106 @@
 +/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */
 +/*
 + * Copyright (C) 2020 STMicroelectronics - All Rights Reserved
@@ -30,14 +35,14 @@ index 000000000000..e75e7b5ba28b
 +
 +/dts-v1/;
 +
-+#include "stm32mp157c.dtsi"
-+#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
-+#include "stm32mp157c-security.dtsi"
++#include "stm32mp157.dtsi"
++#include "stm32mp15xc.dtsi"
 +#include "stm32mp15xx-osd32.dtsi"
++#include "stm32mp15xxac-pinctrl.dtsi"
 +
 +/ {
 +	model = "Linux Automation MC-1 board";
-+	compatible = "lxa,stm32mp157c-mc1", "oct,stm32mp157c-osd32", "st,stm32mp157";
++	compatible = "lxa,stm32mp157c-mc1", "oct,stm32mp15xx-osd32", "st,stm32mp157";
 +
 +	aliases {
 +		mmc0 = &sdmmc1;
@@ -52,11 +57,10 @@ index 000000000000..e75e7b5ba28b
 +	led-act {
 +		compatible = "gpio-leds";
 +
-+		green {
++		led-green {
 +			label = "mc1:green:act";
 +			gpios = <&gpioa 13 1>;
 +			linux,default-trigger = "heartbeat";
-+			default-state = "off";
 +		};
 +	};
 +
@@ -65,32 +69,48 @@ index 000000000000..e75e7b5ba28b
 +		regulator-name = "3V3";
 +		regulator-min-microvolt = <3300000>;
 +		regulator-max-microvolt = <3300000>;
++		regulator-always-on;
 +		vin-supply = <&v3v3>;
 +	};
 +};
 +
 +&sdmmc1 {
 +	pinctrl-names = "default";
-+	pinctrl-0 = <&sdmmc1_b4_pu_pins_a>;
++	pinctrl-0 = <&sdmmc1_b4_pins_a>;
++	bus-width = <4>;
 +	cd-gpios = <&gpioh 3 1>;
++	disable-wp;
++	no-1-8-v;
 +	st,neg-edge;
-+	bus-width = <4>;
 +	vmmc-supply = <&reg_3v3>;
-+	no-1-8-v;
 +	status = "okay";
 +};
 +
++&sdmmc1_b4_pins_a {
++	/*
++	 * board lacks external pull-ups on SDMMC lines. Class 10 SD refuses to
++	 * work, thus enable internal pull-ups.
++	 */
++	pins1 {
++		/delete-property/ bias-disable;
++		bias-pull-up;
++	};
++	pins2 {
++		/delete-property/ bias-disable;
++		bias-pull-up;
++	};
++};
++
 +&sdmmc2 {
 +	pinctrl-names = "default";
-+	pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>;
-+	non-removable;
++	pinctrl-0 = <&sdmmc2_b4_pins_a &mc1_sdmmc2_d47_pins_b>;
++	bus-width = <8>;
++	no-1-8-v;
 +	no-sd;
 +	no-sdio;
++	non-removable;
 +	st,neg-edge;
-+	bus-width = <8>;
 +	vmmc-supply = <&reg_3v3>;
-+	no-1-8-v;
-+	mmc-ddr-3_3v;
 +	status = "okay";
 +};
 +
@@ -101,31 +121,12 @@ index 000000000000..e75e7b5ba28b
 +};
 +
 +&pinctrl {
-+	sdmmc1_b4_pu_pins_a: sdmmc1-pu-b4-0 {
-+		pins1 {
-+			pinmux = <STM32_PINMUX('C',  8, AF12)>, /* SDMMC1_D0 */
-+				 <STM32_PINMUX('C',  9, AF12)>, /* SDMMC1_D1 */
-+				 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
-+				 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
-+				 <STM32_PINMUX('D',  2, AF12)>; /* SDMMC1_CMD */
-+			slew-rate = <1>;
-+			drive-push-pull;
-+			bias-pull-up;
-+		};
-+		pins2 {
-+			pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
-+			slew-rate = <2>;
-+			drive-push-pull;
-+			bias-pull-up;
-+		};
-+	};
-+
-+	sdmmc2_d47_pins_b: sdmmc2-d47-1 {
++	mc1_sdmmc2_d47_pins_b: mc1-sdmmc2-d47-1 {
 +		pins {
-+			pinmux = <STM32_PINMUX('A', 8, AF9)>,  /* eMMC_D4 */
-+			         <STM32_PINMUX('A', 9, AF10)>, /* eMMC_D5 */
-+			         <STM32_PINMUX('C', 6, AF10)>, /* eMMC_D6 */
-+			         <STM32_PINMUX('C', 7, AF10)>; /* eMMC_D7 */
++			pinmux = <STM32_PINMUX('A', 8, AF9)>,  /* SDMMC2_D4 */
++				 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
++				 <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
++				 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
 +			slew-rate = <1>;
 +			drive-push-pull;
 +			bias-disable;
@@ -134,29 +135,27 @@ index 000000000000..e75e7b5ba28b
 +};
 diff --git a/fdts/stm32mp15xx-osd32.dtsi b/fdts/stm32mp15xx-osd32.dtsi
 new file mode 100644
-index 000000000000..453f18c30873
+index 000000000000..9db838ea6b56
 --- /dev/null
 +++ b/fdts/stm32mp15xx-osd32.dtsi
-@@ -0,0 +1,271 @@
+@@ -0,0 +1,278 @@
 +/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */
 +/*
 + * Copyright (C) 2020 STMicroelectronics - All Rights Reserved
 + * Copyright (C) 2020 Ahmad Fatoum, Pengutronix
 + */
 +
-+#include "stm32mp157cac-pinctrl.dtsi"
++#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
++#include "stm32mp15-pinctrl.dtsi"
 +
 +&i2c4 {
 +	pinctrl-names = "default";
 +	pinctrl-0 = <&i2c4_pins_a>;
++	clock-frequency = <400000>;
 +	i2c-scl-rising-time-ns = <185>;
 +	i2c-scl-falling-time-ns = <20>;
 +	status = "okay";
 +
-+	/* spare dmas for other usage */
-+	/delete-property/ dmas;
-+	/delete-property/ dma-names;
-+
 +	pmic: stpmic@33 {
 +		compatible = "st,stpmic1";
 +		reg = <0x33>;
@@ -168,10 +167,8 @@ index 000000000000..453f18c30873
 +			compatible = "st,stpmic1-regulators";
 +
 +			ldo1-supply = <&v3v3>;
-+			ldo3-supply = <&vdd_ddr>;
 +			ldo6-supply = <&v3v3>;
 +			pwr_sw1-supply = <&bst_out>;
-+			pwr_sw2-supply = <&bst_out>;
 +
 +			vddcore: buck1 {
 +				regulator-name = "vddcore";
@@ -215,7 +212,6 @@ index 000000000000..453f18c30873
 +				regulator-min-microvolt = <1800000>;
 +				regulator-max-microvolt = <1800000>;
 +				regulator-always-on;
-+
 +			};
 +
 +			v3v3_hdmi: ldo2 {
@@ -223,7 +219,6 @@ index 000000000000..453f18c30873
 +				regulator-min-microvolt = <3300000>;
 +				regulator-max-microvolt = <3300000>;
 +				regulator-always-on;
-+
 +			};
 +
 +			vtt_ddr: ldo3 {
@@ -252,7 +247,6 @@ index 000000000000..453f18c30873
 +				regulator-min-microvolt = <1200000>;
 +				regulator-max-microvolt = <1200000>;
 +				regulator-always-on;
-+
 +			};
 +
 +			vref_ddr: vref_ddr {
@@ -261,19 +255,19 @@ index 000000000000..453f18c30873
 +				regulator-over-current-protection;
 +			};
 +
-+			 bst_out: boost {
++			bst_out: boost {
 +				regulator-name = "bst_out";
-+			 };
++			};
 +
 +			vbus_otg: pwr_sw1 {
 +				regulator-name = "vbus_otg";
 +				regulator-active-discharge;
-+			 };
++			};
 +
-+			 vbus_sw: pwr_sw2 {
++			vbus_sw: pwr_sw2 {
 +				regulator-name = "vbus_sw";
 +				regulator-active-discharge;
-+			 };
++			};
 +		};
 +
 +		pmic_watchdog: watchdog {
@@ -281,11 +275,6 @@ index 000000000000..453f18c30873
 +			status = "disabled";
 +		};
 +	};
-+
-+	sip_eeprom: eeprom@50 {
-+		compatible = "atmel,24c32";
-+		reg = <0x50>;
-+	};
 +};
 +
 +&rng1 {
@@ -311,6 +300,25 @@ index 000000000000..453f18c30873
 +	};
 +};
 +
++&bsec {
++	board_id: board_id@ec {
++		reg = <0xec 0x4>;
++		st,non-secure-otp;
++	};
++};
++
++&clk_hse {
++	st,digbypass;
++};
++
++&cpu0{
++	cpu-supply = <&vddcore>;
++};
++
++&cpu1{
++	cpu-supply = <&vddcore>;
++};
++
 +/* CLOCK init */
 +&rcc {
 +	secure-status = "disabled";
@@ -344,7 +352,7 @@ index 000000000000..453f18c30873
 +		CLK_CKPER_HSE
 +		CLK_FMC_ACLK
 +		CLK_QSPI_ACLK
-+		CLK_ETH_DISABLED
++		CLK_ETH_PLL4P
 +		CLK_SDMMC12_PLL4P
 +		CLK_DSI_DSIPLL
 +		CLK_STGEN_HSE
@@ -380,35 +388,32 @@ index 000000000000..453f18c30873
 +
 +	/* VCO = 1300.0 MHz => P = 650 (CPU) */
 +	pll1: st,pll@0 {
++		compatible = "st,stm32mp1-pll";
++		reg = <0>;
 +		cfg = < 2 80 0 0 0 PQR(1,0,0) >;
 +		frac = < 0x800 >;
 +	};
 +
 +	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
 +	pll2: st,pll@1 {
-+		cfg = < 2 65 1 0 0 PQR(1,1,1) >;
-+		frac = < 0x1400 >;
++		compatible = "st,stm32mp1-pll";
++		reg = <1>;
++		cfg = <2 65 1 0 0 PQR(1,1,1)>;
++		frac = <0x1400>;
 +	};
 +
 +	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
 +	pll3: st,pll@2 {
-+		cfg = < 1 33 1 16 36 PQR(1,1,1) >;
-+		frac = < 0x1a04 >;
++		compatible = "st,stm32mp1-pll";
++		reg = <2>;
++		cfg = <1 33 1 16 36 PQR(1,1,1)>;
++		frac = <0x1a04>;
 +	};
 +
 +	/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
 +	pll4: st,pll@3 {
-+		cfg = < 3 98 5 7 7 PQR(1,1,1) >;
++		compatible = "st,stm32mp1-pll";
++		reg = <3>;
++		cfg = <3 98 5 7 7 PQR(1,1,1)>;
 +	};
 +};
-+
-+&bsec {
-+	board_id: board_id@ec {
-+		reg = <0xec 0x4>;
-+		status = "okay";
-+		secure-status = "okay";
-+	};
-+};
--- 
-2.25.0
-
diff --git a/configs/platform-v7a/patches/tf-a-v2.4/0101-fdts-stm32mp1-enable-hash1-unconditionally.patch b/configs/platform-v7a/patches/tf-a-v2.4/0101-fdts-stm32mp1-enable-hash1-unconditionally.patch
new file mode 100644
index 0000000..c05c02c
--- /dev/null
+++ b/configs/platform-v7a/patches/tf-a-v2.4/0101-fdts-stm32mp1-enable-hash1-unconditionally.patch
@@ -0,0 +1,63 @@
+From: Ahmad Fatoum <a.fatoum@pengutronix.de>
+Date: Thu, 3 Dec 2020 20:24:53 +0100
+Subject: [PATCH] fdts: stm32mp1: enable hash1 unconditionally
+
+&hash1 is an internal IP that can be enabled always as it has no
+dependencies. Indeed we must enable it, because TF-A panics otherwise
+during stm32mp_init_auth(). Instead of duplicating the enabling
+line in every board device tree, stick it into the SoC dtsi.
+
+This likely fixes boot on the Avenger board that lacks the status =
+"okay" line for the &hash1 device tree node.
+
+Change-Id: I5901029f29af0cf213510878b5daaf5240f96f17
+Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
+---
+ fdts/stm32mp151.dtsi      | 2 +-
+ fdts/stm32mp157c-ed1.dts  | 4 ----
+ fdts/stm32mp15xx-dkx.dtsi | 4 ----
+ 3 files changed, 1 insertion(+), 9 deletions(-)
+
+diff --git a/fdts/stm32mp151.dtsi b/fdts/stm32mp151.dtsi
+index 8f175a6492a1..d908b710bbb9 100644
+--- a/fdts/stm32mp151.dtsi
++++ b/fdts/stm32mp151.dtsi
+@@ -253,7 +253,7 @@
+ 			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&rcc HASH1>;
+ 			resets = <&rcc HASH1_R>;
+-			status = "disabled";
++			status = "okay";
+ 		};
+ 
+ 		rng1: rng@54003000 {
+diff --git a/fdts/stm32mp157c-ed1.dts b/fdts/stm32mp157c-ed1.dts
+index a6b98b7d9337..615e2cc07578 100644
+--- a/fdts/stm32mp157c-ed1.dts
++++ b/fdts/stm32mp157c-ed1.dts
+@@ -55,10 +55,6 @@
+ 	status="okay";
+ };
+ 
+-&hash1 {
+-	status = "okay";
+-};
+-
+ &i2c4 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&i2c4_pins_a>;
+diff --git a/fdts/stm32mp15xx-dkx.dtsi b/fdts/stm32mp15xx-dkx.dtsi
+index 52b914b84e45..e59a65fb5555 100644
+--- a/fdts/stm32mp15xx-dkx.dtsi
++++ b/fdts/stm32mp15xx-dkx.dtsi
+@@ -41,10 +41,6 @@
+ 	cpu-supply = <&vddcore>;
+ };
+ 
+-&hash1 {
+-	status = "okay";
+-};
+-
+ &i2c4 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&i2c4_pins_a>;
diff --git a/configs/platform-v7a/patches/tf-a-v2.4/series b/configs/platform-v7a/patches/tf-a-v2.4/series
new file mode 100644
index 0000000..39ffbf3
--- /dev/null
+++ b/configs/platform-v7a/patches/tf-a-v2.4/series
@@ -0,0 +1,12 @@
+# umpf-base: v2.4
+# umpf-name: 2.4/customers/pengutronix/distrokit-v7a
+# umpf-version: 2.4/customers/pengutronix/distrokit-v7a/20201203-3
+# umpf-topic: v2.4/customers/pengutronix/mc1
+# umpf-hashinfo: 21a3904995b9fbfe16f6b4d4e9db1c03d102a485
+# umpf-topic-range: e2c509a39c6cc4dda8734e6509cdbe6e3603cdfc..ffb9bfe900a2d98486ed63f8041d63cfa39620db
+0001-fdts-stm32mp1-add-support-for-Linux-Automation-MC-1-.patch
+# umpf-topic: v2.4/topic/stm32mp1-hash1-enable
+# umpf-hashinfo: c23c95a1eca7d557650836929252eb3c5cb3ca86
+# umpf-topic-range: ffb9bfe900a2d98486ed63f8041d63cfa39620db..10935b6d4379f0e8f8634cca1ac1cb69a66436e0
+0101-fdts-stm32mp1-enable-hash1-unconditionally.patch
+# umpf-end
diff --git a/configs/platform-v7a/platformconfig b/configs/platform-v7a/platformconfig
index 3c9312c..fa80ea4 100644
--- a/configs/platform-v7a/platformconfig
+++ b/configs/platform-v7a/platformconfig
@@ -193,8 +193,8 @@ PTXCONF_BOOTLOADER=y
 # PTXCONF_HOST_MXS_UTILS is not set
 # PTXCONF_OPTEE is not set
 PTXCONF_TF_A=y
-PTXCONF_TF_A_VERSION="v2.3"
-PTXCONF_TF_A_MD5="95ccde0f7e96cd8e72d44420a5406252"
+PTXCONF_TF_A_VERSION="v2.4"
+PTXCONF_TF_A_MD5="a1e9d1fab56bc2930355318dce80910e"
 PTXCONF_TF_A_ARCH_STRING="aarch32"
 PTXCONF_TF_A_ARM_ARCH_MAJOR_7=y
 # PTXCONF_TF_A_ARM_ARCH_MAJOR_8_32_BIT is not set