diff options
Diffstat (limited to 'configs/platform-friendlyarm-mini2440/patches/barebox-2011.05.0/0001-mini2440-Add-more-info-about-possible-SDRAM-and-flas.patch')
| -rw-r--r-- | configs/platform-friendlyarm-mini2440/patches/barebox-2011.05.0/0001-mini2440-Add-more-info-about-possible-SDRAM-and-flas.patch | 88 |
1 files changed, 88 insertions, 0 deletions
diff --git a/configs/platform-friendlyarm-mini2440/patches/barebox-2011.05.0/0001-mini2440-Add-more-info-about-possible-SDRAM-and-flas.patch b/configs/platform-friendlyarm-mini2440/patches/barebox-2011.05.0/0001-mini2440-Add-more-info-about-possible-SDRAM-and-flas.patch new file mode 100644 index 0000000..1d03668 --- /dev/null +++ b/configs/platform-friendlyarm-mini2440/patches/barebox-2011.05.0/0001-mini2440-Add-more-info-about-possible-SDRAM-and-flas.patch @@ -0,0 +1,88 @@ +From f9e0fe306dd80cf9dfb43e7be056e805638dc073 Mon Sep 17 00:00:00 2001 +From: Juergen Beisert <juergen@kreuzholzen.de> +Date: Sun, 2 Nov 2014 16:38:11 +0100 +Subject: [PATCH 01/10] mini2440: Add more info about possible SDRAM and flash + devices + +It seems there are various combinations of the mini2440 in the wild. Not only +the SDRAM differ, but more important the NAND also differs. + +Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de> +--- + arch/arm/boards/mini2440/mini2440.c | 56 ++++++++++++++++++++++++++----------- + 1 file changed, 39 insertions(+), 17 deletions(-) + +diff --git a/arch/arm/boards/mini2440/mini2440.c b/arch/arm/boards/mini2440/mini2440.c +index 448aa40..2eb6eba 100644 +--- a/arch/arm/boards/mini2440/mini2440.c ++++ b/arch/arm/boards/mini2440/mini2440.c +@@ -312,27 +312,49 @@ console_initcall(mini2440_console_init); + + This system is based on a Samsung S3C2440 CPU. The card is shipped with: + +-- S3C2440\@400 MHz or 533 MHz (ARM920T/ARMv4T) ++- S3C2440\@400 MHz (ARM920T/ARMv4T) + - 12 MHz crystal reference + - 32.768 kHz crystal reference + - SDRAM 64 MiB (one bank only) +- - HY57V561620 (two devices for 64 MiB to form a 32 bit bus) +- - 4M x 16bit x 4 Banks Mobile SDRAM +- - 8192 refresh cycles / 64 ms +- - CL2\@100 MHz +- - 133 MHz max +- - collumn address size is 9 bits +- - row address size is 13 bits +- - MT48LC16M16 (two devices for 64 MiB to form a 32 bit bus) +- - 4M x 16bit x 4 Banks Mobile SDRAM +- - commercial & industrial type +- - 8192 refresh cycles / 64 ms +- - CL2\@100 MHz +- - 133 MHz max +- - collumn address size is 9 bits +- - row address size is 13 bits ++ - Hynix SDRAM ++ - HY57V561620FTP-H (two devices for 64 MiB to form a 32 bit bus) ++ - 4M x 16bit x 4 Banks Mobile SDRAM ++ - 8192 refresh cycles / 64 ms ++ - CL2\@100 MHz ++ - 133 MHz max ++ - collumn address size is 9 bits ++ - row address size is 13 bits ++ - Micron SDRAM ++ - MT48LC16M16A2-75IT (two devices for 64 MiB to form a 32 bit bus) ++ - MT48LC16M16A2-7E (two devices for 64 MiB to form a 32 bit bus) ++ - 4M x 16bit x 4 Banks Mobile SDRAM ++ - commercial & industrial type ++ - 8192 refresh cycles / 64 ms ++ - CL2\@100 MHz ++ - 133 MHz max ++ - collumn address size is 9 bits ++ - row address size is 13 bits + - NAND Flash 128MiB...1GiB +- - K9Fxx08 ++ - K9F1208U0C ++ - VID: 0xec, DID: 0x76 ++ - Samsung/64MiB 3,3V 8-bit ++ - 512 + 8 bytes per page ++ - 16 kiB block size ++ - K9F1G08UOB ++ - VID: 0xec, DID: 0xf1 ++ - Samsung/128MiB 3,3V 8-bit ++ - 2048 + 64 bytes per page ++ - 128 kiB block size ++ - K9F2G08UOB ++ - VID: 0xec, DID: 0xda ++ - Samsung/256MiB 3,3V 8-bit ++ - 2048 + 64 bytes per page ++ - 128 kiB block size ++ - K9K8G08U0A ++ - VID: 0xec, DID: 0xd3 ++ - Samsung/1GiB 3,3V 8-bit ++ - 2048 + 64 bytes per page ++ - 128 kiB block size + - NOR Flash (up to 22 address lines available) + - AM29LV160DB, 2 MiB + - SST39VF1601, 2 MiB +-- +1.8.1 + |