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From 01a36bb280f0af0d84bbf09f37372919395f9de8 Mon Sep 17 00:00:00 2001
From: Stephan Linz <linz@li-pro.net>
Date: Tue, 19 Apr 2011 00:23:01 +0200
Subject: [PATCH 8/9] Add support for devices with 16 gp registers
Add support for a bunch of new AVR devices, especially tiny devices
with 16 gp registers: attiny4, attiny5, attiny9, attiny10, attiny20,
attiny40
Original ATMEL patch from:
http://distribute.atmel.no/tools/opensource/avr-gcc/binutils-2.20.1/52-binutils-2.20.1-avrtiny10.patch
Signed-off-by: Stephan Linz <linz@li-pro.net>
---
bfd/archures.c | 1 +
bfd/bfd-in2.h | 1 +
bfd/cpu-avr.c | 5 ++++-
bfd/elf32-avr.c | 8 ++++++++
gas/config/tc-avr.c | 19 +++++++++++++++++++
include/elf/avr.h | 1 +
include/opcode/avr.h | 14 +++++++-------
ld/Makefile.am | 5 +++++
ld/Makefile.in | 5 +++++
ld/configure.tgt | 2 +-
ld/emulparams/avrtiny10.sh | 12 ++++++++++++
11 files changed, 64 insertions(+), 9 deletions(-)
create mode 100644 ld/emulparams/avrtiny10.sh
diff --git a/bfd/archures.c b/bfd/archures.c
index 390ccec..6a1062c 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -375,6 +375,7 @@ DESCRIPTION
.#define bfd_mach_avrxmega5 105
.#define bfd_mach_avrxmega6 106
.#define bfd_mach_avrxmega7 107
+.#define bfd_mach_avrtiny10 201
. bfd_arch_bfin, {* ADI Blackfin *}
.#define bfd_mach_bfin 1
. bfd_arch_cr16, {* National Semiconductor CompactRISC (ie CR16). *}
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 0821cd0..c093108 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -2049,6 +2049,7 @@ enum bfd_architecture
#define bfd_mach_avrxmega5 105
#define bfd_mach_avrxmega6 106
#define bfd_mach_avrxmega7 107
+#define bfd_mach_avrtiny10 201
bfd_arch_bfin, /* ADI Blackfin */
#define bfd_mach_bfin 1
bfd_arch_cr16, /* National Semiconductor CompactRISC (ie CR16). */
diff --git a/bfd/cpu-avr.c b/bfd/cpu-avr.c
index 6562ee5..0cc66fc 100644
--- a/bfd/cpu-avr.c
+++ b/bfd/cpu-avr.c
@@ -154,7 +154,10 @@ static const bfd_arch_info_type arch_info_struct[] =
N (24, bfd_mach_avrxmega6, "avr:106", FALSE, & arch_info_struct[16]),
/* Xmega 7 */
- N (24, bfd_mach_avrxmega7, "avr:107", FALSE, NULL)
+ N (24, bfd_mach_avrxmega7, "avr:107", FALSE, & arch_info_struct[17]),
+
+ /* attiny 10 */
+ N (16, bfd_mach_avrtiny10, "avr:201", FALSE, NULL)
};
diff --git a/bfd/elf32-avr.c b/bfd/elf32-avr.c
index 62ce9fb..af85301 100644
--- a/bfd/elf32-avr.c
+++ b/bfd/elf32-avr.c
@@ -1356,6 +1356,10 @@ bfd_elf_avr_final_write_processing (bfd *abfd,
case bfd_mach_avrxmega7:
val = E_AVR_MACH_XMEGA7;
break;
+
+ case bfd_mach_avrtiny10:
+ val = E_AVR_MACH_AVRTINY10;
+ break;
}
elf_elfheader (abfd)->e_machine = EM_AVR;
@@ -1446,6 +1450,10 @@ elf32_avr_object_p (bfd *abfd)
case E_AVR_MACH_XMEGA7:
e_set = bfd_mach_avrxmega7;
break;
+
+ case E_AVR_MACH_AVRTINY10:
+ e_set = bfd_mach_avrtiny10;
+ break;
}
}
return bfd_default_set_arch_mach (abfd, bfd_arch_avr,
diff --git a/gas/config/tc-avr.c b/gas/config/tc-avr.c
index 90918df..20501bb 100644
--- a/gas/config/tc-avr.c
+++ b/gas/config/tc-avr.c
@@ -88,6 +88,7 @@ static struct mcu_type_s mcu_types[] =
{"avrxmega5", AVR_ISA_XMEGA, bfd_mach_avrxmega5},
{"avrxmega6", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
{"avrxmega7", AVR_ISA_XMEGA, bfd_mach_avrxmega7},
+ {"avrtiny10", AVR_ISA_AVRTINY10, bfd_mach_avrtiny10},
{"at90s1200", AVR_ISA_1200, bfd_mach_avr1},
{"attiny11", AVR_ISA_AVR1, bfd_mach_avr1},
{"attiny12", AVR_ISA_AVR1, bfd_mach_avr1},
@@ -264,6 +265,12 @@ static struct mcu_type_s mcu_types[] =
{"atxmega256a3b",AVR_ISA_XMEGA, bfd_mach_avrxmega6},
{"atxmega256d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
{"atxmega128a1", AVR_ISA_XMEGA, bfd_mach_avrxmega7},
+ {"attiny4", AVR_ISA_AVRTINY10, bfd_mach_avrtiny10},
+ {"attiny5", AVR_ISA_AVRTINY10, bfd_mach_avrtiny10},
+ {"attiny9", AVR_ISA_AVRTINY10, bfd_mach_avrtiny10},
+ {"attiny10", AVR_ISA_AVRTINY10, bfd_mach_avrtiny10},
+ {"attiny20", AVR_ISA_AVRTINY10, bfd_mach_avrtiny10},
+ {"attiny40", AVR_ISA_AVRTINY10, bfd_mach_avrtiny10},
{NULL, 0, 0}
};
@@ -446,6 +453,7 @@ md_show_usage (FILE *stream)
" avrxmega5 - XMEGA, > 64K, <= 128K FLASH, > 64K RAM\n"
" avrxmega6 - XMEGA, > 128K, <= 256K FLASH, <= 64K RAM\n"
" avrxmega7 - XMEGA, > 128K, <= 256K FLASH, > 64K RAM\n"
+ " avrtiny10 - tiny devices with 16 gp registers\n"
" or immediate microcontroller name.\n"));
fprintf (stream,
_(" -mall-opcodes accept all AVR opcodes, even if not supported by MCU\n"
@@ -793,6 +801,17 @@ avr_operand (struct avr_opcodes_s *opcode,
op_mask = avr_get_constant (str, 31);
str = input_line_pointer;
}
+ if (strcmp(avr_mcu->name, "avrtiny10") == 0
+ || strcmp(avr_mcu->name, "attiny10") == 0
+ || strcmp(avr_mcu->name, "attiny4") == 0
+ || strcmp(avr_mcu->name, "attiny5") == 0
+ || strcmp(avr_mcu->name, "attiny9") == 0
+ || strcmp(avr_mcu->name, "attiny20") == 0
+ || strcmp(avr_mcu->name, "attiny40") == 0)
+ {
+ if(op_mask < 16)
+ as_bad (_("register number above 15 required"));
+ }
if (op_mask <= 31)
{
diff --git a/include/elf/avr.h b/include/elf/avr.h
index e86eb11..d334870 100644
--- a/include/elf/avr.h
+++ b/include/elf/avr.h
@@ -47,6 +47,7 @@
#define E_AVR_MACH_XMEGA5 105
#define E_AVR_MACH_XMEGA6 106
#define E_AVR_MACH_XMEGA7 107
+#define E_AVR_MACH_AVRTINY10 201
/* Relocations. */
START_RELOC_NUMBERS (elf_avr_reloc_type)
diff --git a/include/opcode/avr.h b/include/opcode/avr.h
index cff7b06..3f0417d 100644
--- a/include/opcode/avr.h
+++ b/include/opcode/avr.h
@@ -69,7 +69,7 @@
AVR_ISA_ELPM | AVR_ISA_ELPMX | AVR_ISA_SPM | \
AVR_ISA_SPM | AVR_ISA_BRK | AVR_ISA_EIND | \
AVR_ISA_MOVW)
-
+#define AVR_ISA_AVRTINY10 (AVR_ISA_1200 | AVR_ISA_BRK | AVR_ISA_SRAM)
#define REGISTER_P(x) ((x) == 'r' \
|| (x) == 'd' \
|| (x) == 'w' \
@@ -159,8 +159,8 @@ AVR_INSN (sez, "", "1001010000011000", 1, AVR_ISA_1200, 0x9418)
AVR_INSN (bclr, "S", "100101001SSS1000", 1, AVR_ISA_1200, 0x9488)
AVR_INSN (bset, "S", "100101000SSS1000", 1, AVR_ISA_1200, 0x9408)
-AVR_INSN (icall,"", "1001010100001001", 1, AVR_ISA_2xxx, 0x9509)
-AVR_INSN (ijmp, "", "1001010000001001", 1, AVR_ISA_2xxx, 0x9409)
+AVR_INSN (icall,"", "1001010100001001", 1, AVR_ISA_SRAM, 0x9509)
+AVR_INSN (ijmp, "", "1001010000001001", 1, AVR_ISA_SRAM, 0x9409)
AVR_INSN (lpm, "?", "1001010111001000", 1, AVR_ISA_TINY1,0x95c8)
AVR_INSN (lpm, "r,z", "1001000ddddd010+", 1, AVR_ISA_LPMX, 0x9004)
@@ -260,8 +260,8 @@ AVR_INSN (dec, "r", "1001010rrrrr1010", 1, AVR_ISA_1200, 0x940a)
AVR_INSN (inc, "r", "1001010rrrrr0011", 1, AVR_ISA_1200, 0x9403)
AVR_INSN (lsr, "r", "1001010rrrrr0110", 1, AVR_ISA_1200, 0x9406)
AVR_INSN (neg, "r", "1001010rrrrr0001", 1, AVR_ISA_1200, 0x9401)
-AVR_INSN (pop, "r", "1001000rrrrr1111", 1, AVR_ISA_2xxx, 0x900f)
-AVR_INSN (push, "r", "1001001rrrrr1111", 1, AVR_ISA_2xxx, 0x920f)
+AVR_INSN (pop, "r", "1001000rrrrr1111", 1, AVR_ISA_SRAM, 0x900f)
+AVR_INSN (push, "r", "1001001rrrrr1111", 1, AVR_ISA_SRAM, 0x920f)
AVR_INSN (ror, "r", "1001010rrrrr0111", 1, AVR_ISA_1200, 0x9407)
AVR_INSN (swap, "r", "1001010rrrrr0010", 1, AVR_ISA_1200, 0x9402)
@@ -273,8 +273,8 @@ AVR_INSN (fmul, "a,a", "000000110ddd1rrr", 1, AVR_ISA_MUL, 0x0308)
AVR_INSN (fmuls,"a,a", "000000111ddd0rrr", 1, AVR_ISA_MUL, 0x0380)
AVR_INSN (fmulsu,"a,a","000000111ddd1rrr", 1, AVR_ISA_MUL, 0x0388)
-AVR_INSN (sts, "i,r", "1001001ddddd0000", 2, AVR_ISA_2xxx, 0x9200)
-AVR_INSN (lds, "r,i", "1001000ddddd0000", 2, AVR_ISA_2xxx, 0x9000)
+AVR_INSN (sts, "i,r", "1001001ddddd0000", 2, AVR_ISA_SRAM, 0x9200)
+AVR_INSN (lds, "r,i", "1001000ddddd0000", 2, AVR_ISA_SRAM, 0x9000)
/* Special case for b+0, `e' must be next entry after `b',
b={Y=1,Z=0}, ee={X=11,Y=10,Z=00}, !=1 if -e or e+ or X. */
diff --git a/ld/Makefile.am b/ld/Makefile.am
index 80b8f22..484b944 100644
--- a/ld/Makefile.am
+++ b/ld/Makefile.am
@@ -155,6 +155,7 @@ ALL_EMULATIONS = \
eavrxmega5.o \
eavrxmega6.o \
eavrxmega7.o \
+ eavrtiny10.o \
ecoff_i860.o \
ecoff_sparc.o \
eelf32_spu.o \
@@ -762,6 +763,10 @@ eavrxmega7.c: $(srcdir)/emulparams/avrxmega7.sh \
$(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \
${GEN_DEPENDS}
${GENSCRIPTS} avrxmega7 "$(tdir_avr2)"
+eavrtiny10.c: $(srcdir)/emulparams/avrtiny10.sh \
+ $(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \
+ ${GEN_DEPENDS}
+ ${GENSCRIPTS} avrtiny10 "$(tdir_avr2)"
ecoff_i860.c: $(srcdir)/emulparams/coff_i860.sh \
$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/i860coff.sc ${GEN_DEPENDS}
${GENSCRIPTS} coff_i860 "$(tdir_coff_i860)"
diff --git a/ld/Makefile.in b/ld/Makefile.in
index 2d5c8a0..c1e9e9c 100644
--- a/ld/Makefile.in
+++ b/ld/Makefile.in
@@ -441,6 +441,7 @@ ALL_EMULATIONS = \
eavrxmega5.o \
eavrxmega6.o \
eavrxmega7.o \
+ eavrtiny10.o \
ecoff_i860.o \
ecoff_sparc.o \
eelf32_spu.o \
@@ -2104,6 +2105,10 @@ eavrxmega7.c: $(srcdir)/emulparams/avrxmega7.sh \
$(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \
${GEN_DEPENDS}
${GENSCRIPTS} avrxmega7 "$(tdir_avr2)"
+eavrtiny10.c: $(srcdir)/emulparams/avrtiny10.sh \
+ $(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \
+ ${GEN_DEPENDS}
+ ${GENSCRIPTS} avrtiny10 "$(tdir_avr2)"
ecoff_i860.c: $(srcdir)/emulparams/coff_i860.sh \
$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/i860coff.sc ${GEN_DEPENDS}
${GENSCRIPTS} coff_i860 "$(tdir_coff_i860)"
diff --git a/ld/configure.tgt b/ld/configure.tgt
index 9ceefa5..f64dd5b 100644
--- a/ld/configure.tgt
+++ b/ld/configure.tgt
@@ -110,7 +110,7 @@ xscale-*-coff) targ_emul=armcoff ;;
xscale-*-elf) targ_emul=armelf
;;
avr-*-*) targ_emul=avr2
- targ_extra_emuls="avr1 avr25 avr3 avr31 avr35 avr4 avr5 avr51 avr6 avrxmega1 avrxmega2 avrxmega3 avrxmega4 avrxmega5 avrxmega6 avrxmega7"
+ targ_extra_emuls="avr1 avr25 avr3 avr31 avr35 avr4 avr5 avr51 avr6 avrxmega1 avrxmega2 avrxmega3 avrxmega4 avrxmega5 avrxmega6 avrxmega7 avrtiny10"
;;
bfin-*-elf) targ_emul=elf32bfin;
targ_extra_emuls="elf32bfinfd"
diff --git a/ld/emulparams/avrtiny10.sh b/ld/emulparams/avrtiny10.sh
new file mode 100644
index 0000000..d530097
--- /dev/null
+++ b/ld/emulparams/avrtiny10.sh
@@ -0,0 +1,12 @@
+ARCH=avr:201
+MACHINE=
+SCRIPT_NAME=avr
+OUTPUT_FORMAT="elf32-avr"
+MAXPAGESIZE=1
+EMBEDDED=yes
+TEMPLATE_NAME=elf32
+
+TEXT_LENGTH=4K
+DATA_ORIGIN=0x800040
+DATA_LENGTH=0x140
+EXTRA_EM_FILE=avrelf
--
1.6.0.4
|
