path: root/dts/Bindings/cpufreq/nvidia,tegra124-cpufreq.txt
blob: b1669fbfb74040dea99faee3b6df90bea443ed05 (plain) (tree)

Tegra124 CPU frequency scaling driver bindings

Both required and optional properties listed below must be defined
under node /cpus/cpu@0.

Required properties:
- clocks: Must contain an entry for each entry in clock-names.
  See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
  - cpu_g: Clock mux for the fast CPU cluster.
  - cpu_lp: Clock mux for the low-power CPU cluster.
  - pll_x: Fast PLL clocksource.
  - pll_p: Auxiliary PLL used during fast PLL rate changes.
  - dfll: Fast DFLL clocksource that also automatically scales CPU voltage.
- vdd-cpu-supply: Regulator for CPU voltage

Optional properties:
- clock-latency: Specify the possible maximum transition latency for clock,
  in unit of nanoseconds.

cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu@0 {
		device_type = "cpu";
		compatible = "arm,cortex-a15";
		reg = <0>;

		clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
			 <&tegra_car TEGRA124_CLK_CCLK_LP>,
			 <&tegra_car TEGRA124_CLK_PLL_X>,
			 <&tegra_car TEGRA124_CLK_PLL_P>,
		clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
		clock-latency = <300000>;
		vdd-cpu-supply: <&vdd_cpu>;