mx35: u-boot-v1 lowlevel_init

Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>

3 files changed, 842 insertions, 346 deletions

diff --git a/board/freescale-mx35-3-stack/board-mx35_3stack.h b/board/freescale-mx35-3-stack/board-mx35_3stack.h
new file mode 100644
index 0000000000..c18066ad9c
--- /dev/null
+++ b/board/freescale-mx35-3-stack/board-mx35_3stack.h
@@ -0,0 +1,107 @@
+/*
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * (C) Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __BOARD_MX35_3STACK_H
+#define __BOARD_MX35_3STACK_H
+
+#define UNALIGNED_ACCESS_ENABLE
+#define LOW_INT_LATENCY_ENABLE
+#define BRANCH_PREDICTION_ENABLE
+
+#define L2CC_AUX_CTL_CONFIG	0x00030024
+
+#define AIPS_MPR_CONFIG		0x77777777
+#define AIPS_OPACR_CONFIG	0x00000000
+
+/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+#define MAX_MPR_CONFIG		0x00302154
+/* SGPCR - always park on last master */
+#define MAX_SGPCR_CONFIG	0x00000010
+/* MGPCR - restore default values */
+#define MAX_MGPCR_CONFIG	0x00000000
+
+/*
+ * M3IF Control Register (M3IFCTL)
+ * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
+ * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[2] = MBX not on priority list (0 << 0)   = 0x00000000
+ * MRRP[3] = MAX1 not on priority list (0 << 0)  = 0x00000000
+ * MRRP[4] = SDMA not on priority list (0 << 0)  = 0x00000000
+ * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
+ * MRRP[6] = IPU1 on priority list (1 << 6)      = 0x00000040
+ * MRRP[7] = IPU2 not on priority list (0 << 0)  = 0x00000000
+ *                                               ------------
+ *                                                 0x00000040
+ */
+#define M3IF_CONFIG	0x00000040
+
+#define DBG_BASE_ADDR		WEIM_CTRL_CS5
+#define DBG_CSCR_U_CONFIG	0x0000D843
+#define DBG_CSCR_L_CONFIG	0x22252521
+#define DBG_CSCR_A_CONFIG	0x22220A00
+
+#define CCM_CCMR_CONFIG		0x003F4208
+#define CCM_PDR0_CONFIG		0x00821000
+
+#define PLL_BRM_OFFSET	31
+#define PLL_PD_OFFSET	26
+#define PLL_MFD_OFFSET	16
+#define PLL_MFI_OFFSET	10
+
+#define _PLL_BRM(x)	((x) << PLL_BRM_OFFSET)
+#define _PLL_PD(x)	(((x) - 1) << PLL_PD_OFFSET)
+#define _PLL_MFD(x)	(((x) - 1) << PLL_MFD_OFFSET)
+#define _PLL_MFI(x)	((x) << PLL_MFI_OFFSET)
+#define _PLL_MFN(x)	(x)
+#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \
+	(_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\
+	 _PLL_MFN(mfn))
+
+#define CCM_MPLL_532_HZ	_PLL_SETTING(1, 1, 12, 11, 1)
+#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5)
+#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1)
+
+/*MEMORY SETING*/
+#define ESDCTL_0x92220000	0x92220000
+#define ESDCTL_0xA2220000	0xA2220000
+#define ESDCTL_0xB2220000	0xB2220000
+#define ESDCTL_0x82228080 	0x82228080
+
+#define ESDCTL_PRECHARGE	0x00000400
+
+#define ESDCTL_MDDR_CONFIG 	0x007FFC3F
+#define ESDCTL_MDDR_MR		0x00000033
+#define ESDCTL_MDDR_EMR		0x02000000
+
+#define ESDCTL_DDR2_CONFIG 	0x007FFC3F
+#define ESDCTL_DDR2_EMR2	0x04000000
+#define ESDCTL_DDR2_EMR3	0x06000000
+#define ESDCTL_DDR2_EN_DLL	0x02000400
+#define ESDCTL_DDR2_RESET_DLL	0x00000333
+#define ESDCTL_DDR2_MR		0x00000233
+#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
+
+#define ESDCTL_DELAY_LINE5	0x00F49F00
+#endif				/* __BOARD_MX35_3STACK_H */
diff --git a/board/freescale-mx35-3-stack/lowlevel_init.S b/board/freescale-mx35-3-stack/lowlevel_init.S
index f912a3a1b0..07c012bfc5 100644
--- a/board/freescale-mx35-3-stack/lowlevel_init.S
+++ b/board/freescale-mx35-3-stack/lowlevel_init.S
@@ -1,156 +1,175 @@
 /*
- * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
- * Applications Processor Reference Manual, Rev. 0.2".
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
  *
+ * (C) Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
  */
 
 #include <config.h>
 #include <mach/imx-regs.h>
+#include "board-mx35_3stack.h"
 
 #define writel(val, reg) \
 	ldr		r0,	=reg;	\
 	ldr		r1,	=val;	\
-	str		r1,   [r0];
-#define IIM_BASE_ADDR           0x53FF0000
-#define SDRAM_BASE_ADDR             CSD0_BASE_ADDR
-#define CSD0_BASE_ADDR          0x80000000
-#define IIM_SREV_OFF            0x24
-#define AIPS1_CTRL_BASE_ADDR    AIPS1_BASE_ADDR
-#define AIPS1_BASE_ADDR         0x43F00000
-#define AIPS2_CTRL_BASE_ADDR    AIPS2_BASE_ADDR
-#define AIPS2_BASE_ADDR         0x53F00000
-#define MAX_BASE_ADDR           0x43F04000
-#define CLKCTL_BASE_ADDR        0x43F0C000
-#define ESDCTL_BASE             0xB8001000
-#define M3IF_BASE               0xB8003000
-#define IOMUXC_BASE_ADDR        0x43FAC000
-#define MPCTL_PARAM_399     (((1-1) << 26) + ((16-1) << 16) + (8  << 10) + (5 << 0))
-#define MPCTL_PARAM_532     ((1 << 31) + ((1-1) << 26) + ((12-1) << 16) + (11  << 10) + (1 << 0))
-#define PPCTL_PARAM_300     (((1-1) << 26) + ((4-1) << 16) + (6  << 10) + (1  << 0))
-#define SDRAM_SIZE                  0x08000000
-#define CCM_BASE_ADDR           0x53F80000
-#define IPU_CTRL_BASE_ADDR      0x53FC0000
-#define WEIM_CTRL_CS5           (WEIM_BASE_ADDR + 0x50)
-#define WEIM_BASE_ADDR          0xB8002000
-#define WEIM_CTRL_CS0           WEIM_BASE_ADDR
+	str		r1,	[r0];
 
-ARM_PPMRR:              .word   0x40000015
-L2CACHE_PARAM:          .word   0x00030024
-IIM_SREV_REG_VAL:       .word   IIM_BASE_ADDR + IIM_SREV_OFF
-AIPS1_CTRL_BASE_ADDR_W: .word   AIPS1_CTRL_BASE_ADDR
-AIPS2_CTRL_BASE_ADDR_W: .word   AIPS2_CTRL_BASE_ADDR
-AIPS1_PARAM_W:          .word   0x77777777
-MAX_BASE_ADDR_W:        .word   MAX_BASE_ADDR
-MAX_PARAM1:             .word   0x00302154
-CLKCTL_BASE_ADDR_W:     .word   CLKCTL_BASE_ADDR
-ESDCTL_BASE_W:          .word   ESDCTL_BASE
-M3IF_BASE_W:            .word   M3IF_BASE
-RAM_PARAM1_MDDR:	.word	0x00000400
-RAM_PARAM2_MDDR:	.word	0x00000333
-RAM_PARAM3_MDDR:	.word	0x02000400
-			.word	0x02000000
-RAM_PARAM4_MDDR:	.word	0x04000000
-RAM_PARAM5_MDDR:	.word	0x06000000
-RAM_PARAM6_MDDR:	.word	0x00000233
-			.word	0x00000033
-RAM_PARAM7_MDDR:	.word	0x02000780
-ESDCTL_0x92220000:      .word   0x92220000
-ESDCTL_0xA2220000:      .word   0xA2220000
-ESDCTL_0xB2220000:      .word   0xB2220000
-ESDCTL_0x82226080:      .word   0x82226080
-ESDCTL_CONFIG:       	.word   0x007FFC3F	//DDR2
-			.word 	0x00295729	//MDDR
-ESDCTL_DELAY5:		.word   0x00F49F00
-IOMUXC_BASE_ADDR_W:     .word   IOMUXC_BASE_ADDR
-CCM_CCMR_W:             .word   0x003F4208
-//CCM_PDR0_W:             .word   0x00801000
-CCM_PDR0_W:             .word   0x00801c00
-MPCTL_PARAM_399_W:      .word   MPCTL_PARAM_399
-MPCTL_PARAM_532_W:      .word   MPCTL_PARAM_532
-PPCTL_PARAM_W:    	.word   PPCTL_PARAM_300
-MXC_REDBOOT_ROM_START:  .word   SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000
-CONST_0x0FFF:           .word   0x0FFF
-CCM_BASE_ADDR_W:        .word   CCM_BASE_ADDR
-IPU_CTRL_BASE_ADDR_W:   .word   IPU_CTRL_BASE_ADDR
-WEIM_CTRL_CS5_W:    .word   WEIM_CTRL_CS5
-WEIM_CTRL_CS0_W:    .word   WEIM_CTRL_CS0
-CS0_CSCRU_0x0000CC03:   .word   0x0000DCF6
-CS0_CSCRL_0xA0330D01:   .word   0x444A4541
-CS0_CSCRA_0x00220800:   .word   0x44443302
-CS5_CSCRU_0x0000D843:   .word   0x0000D843
-CS5_CSCRL_0x22252521:   .word   0x22252521
-CS5_CSCRA_0x22220A00:   .word   0x22220A00
-
-#define L2CC_BASE_ADDR          0x30000000
-#define L2_CACHE_CTL_REG                0x100
-#define L2_CACHE_AUX_CTL_REG            0x104
-#define L2_CACHE_DBG_CTL_REG      0xF40
-#define L2_CACHE_INV_WAY_REG            0x77C
+#define writeb(val, reg) \
+	ldr		r0,	=reg;	\
+	ldr		r1,	=val;	\
+	strb		r1,	[r0];
 
-/* Assuming 24MHz input clock */
-/*                            PD             MFD              MFI          MFN */
-#define MPCTL_PARAM_399     (((1-1) << 26) + ((16-1) << 16) + (8  << 10) + (5 << 0))
-#define MPCTL_PARAM_532     ((1 << 31) + ((1-1) << 26) + ((12-1) << 16) + (11  << 10) + (1 << 0))
-#define MPCTL_PARAM_665     (((1-1) << 26) + ((48-1) << 16) + (13  << 10) + (41 << 0))
-#define PPCTL_PARAM_300     (((1-1) << 26) + ((4-1) << 16) + (6  << 10) + (1  << 0))
+#define IIM_SREV		0x24
+#define ROMPATCH_REV		0x40
 
-#define M3IF_BASE               0xB8003000
+#define CHIP_REV_1_0		0x10
+#define CHIP_REV_2_0		0x20
 
-#define UNALIGNED_ACCESS_ENABLE
-#define LOW_INT_LATENCY_ENABLE
-#define BRANCH_PREDICTION_ENABLE
+#define BOARD_REV_1_0		0x0
+#define BOARD_REV_2_0		0x1
 
-.globl board_init_lowlevel
-board_init_lowlevel:
-	mov     r10, lr
+#define CLKMODE_AUTO            0
+#define CLKMODE_CONSUMER        1
 
-    mrc 15, 0, r1, c1, c0, 0
-    bic r1, r1, #(0x3<<21)
-    bic r1, r1, #(0x3<<11)
-    bic r1, r1, #0x5
+#define PHYS_SDRAM_1		CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE	(128 * 1024 * 1024)
 
-    bic r1, r1, #(1<<3)
+#define L2CC_BASE_ADDR		0x30000000
+#define ROMPATCH_BASE_ADDR      0x60000000
 
-#ifndef BRANCH_PREDICTION_ENABLE
-    mrc 15, 0, r0, c1, c0, 1
-    bic r0, r0, #7
-    mcr 15, 0, r0, c1, c0, 1
-#else
-    mrc 15, 0, r0, c1, c0, 1
-    orr r0, r0, #7
-    mcr 15, 0, r0, c1, c0, 1
-    orr r1, r1, #(1<<11)
-#endif
+#define CSD0_BASE_ADDR		0x80000000
+#define CSD1_BASE_ADDR		0x90000000
 
-#ifdef UNALIGNED_ACCESS_ENABLE
-    orr r1, r1, #(1<<22)
-#endif
+#define NFC_BASE_ADDR		0xBB000000
+#define NFC_BUF_SIZE		0x1000
 
-#ifdef LOW_INT_LATENCY_ENABLE
-    orr r1, r1, #(1<<21)
-#endif
-    mcr 15, 0, r1, c1, c0, 0
 
-#ifdef BRANCH_PREDICTION_ENABLE
-    mov r0, #0
-    mcr 15, 0, r0, c15, c2, 4
-#endif
+/* L210 */
+#define L2CC_BASE_ADDR                  0x30000000
+#define L2_CACHE_LINE_SIZE              32
+#define L2_CACHE_CTL_REG                0x100
+#define L2_CACHE_AUX_CTL_REG            0x104
+#define L2_CACHE_SYNC_REG               0x730
+#define L2_CACHE_INV_LINE_REG           0x770
+#define L2_CACHE_INV_WAY_REG            0x77C
+#define L2_CACHE_CLEAN_LINE_REG         0x7B0
+#define L2_CACHE_CLEAN_INV_LINE_REG     0x7F0
+#define L2_CACHE_DBG_CTL_REG            0xF40
 
-    mov r0, #0
-    mcr 15, 0, r0, c7, c7, 0        /* invalidate I cache and D cache */
-    mcr 15, 0, r0, c8, c7, 0        /* invalidate TLBs */
-    mcr 15, 0, r0, c7, c10, 4       /* Drain the write buffer */
+/*
+ * AIPS 1
+ */
+#define AIPS1_BASE_ADDR         0x43F00000
+#define AIPS1_CTRL_BASE_ADDR    AIPS1_BASE_ADDR
+#define MAX_BASE_ADDR           0x43F04000
+#define EVTMON_BASE_ADDR        0x43F08000
+#define CLKCTL_BASE_ADDR        0x43F0C000
+#define I2C_BASE_ADDR           0x43F80000
+#define I2C3_BASE_ADDR          0x43F84000
+#define ATA_BASE_ADDR           0x43F8C000
+#define UART1_BASE_ADDR         0x43F90000
+#define UART2_BASE_ADDR         0x43F94000
+#define I2C2_BASE_ADDR          0x43F98000
+#define CSPI1_BASE_ADDR         0x43FA4000
+#define IOMUXC_BASE_ADDR        0x43FAC000
 
-    /* Also setup the Peripheral Port Remap register inside the core */
-    ldr r0, ARM_PPMRR        /* start from AIPS 2GB region */
-    mcr p15, 0, r0, c15, c2, 4
+/*
+ * AIPS 2
+ */
+#define AIPS2_BASE_ADDR         0x53F00000
+#define AIPS2_CTRL_BASE_ADDR    AIPS2_BASE_ADDR
+#define CCM_BASE_ADDR           0x53F80000
+#define GPT1_BASE_ADDR          0x53F90000
+#define EPIT1_BASE_ADDR         0x53F94000
+#define EPIT2_BASE_ADDR         0x53F98000
+#define GPIO3_BASE_ADDR         0x53FA4000
+#define MMC_SDHC1_BASE_ADDR 	0x53FB4000
+#define MMC_SDHC2_BASE_ADDR 	0x53FB8000
+#define MMC_SDHC3_BASE_ADDR 	0x53FBC000
+#define IPU_CTRL_BASE_ADDR      0x53FC0000
+#define GPIO3_BASE_ADDR         0x53FA4000
+#define GPIO1_BASE_ADDR         0x53FCC000
+#define GPIO2_BASE_ADDR         0x53FD0000
+#define SDMA_BASE_ADDR          0x53FD4000
+#define RTC_BASE_ADDR           0x53FD8000
+#define WDOG_BASE_ADDR          0x53FDC000
+#define PWM_BASE_ADDR           0x53FE0000
+#define RTIC_BASE_ADDR          0x53FEC000
+#define IIM_BASE_ADDR           0x53FF0000
 
-    /*** L2 Cache setup/invalidation/disable ***/
+/* CCM */
+#define CLKCTL_CCMR                     0x00
+#define CLKCTL_PDR0                     0x04
+#define CLKCTL_PDR1                     0x08
+#define CLKCTL_PDR2                     0x0C
+#define CLKCTL_PDR3                     0x10
+#define CLKCTL_PDR4                     0x14
+#define CLKCTL_RCSR                     0x18
+#define CLKCTL_MPCTL                    0x1C
+#define CLKCTL_PPCTL                    0x20
+#define CLKCTL_ACMR                     0x24
+#define CLKCTL_COSR                     0x28
+#define CLKCTL_CGR0                     0x2C
+#define CLKCTL_CGR1                     0x30
+#define CLKCTL_CGR2                     0x34
+#define CLKCTL_CGR3                     0x38
+
+/*
+ * NAND, SDRAM, WEIM, M3IF, EMI controllers
+ */
+#define EXT_MEM_CTRL_BASE       0xB8000000
+#define ESDCTL_BASE_ADDR        0xB8001000
+#define WEIM_BASE_ADDR          0xB8002000
+#define WEIM_CTRL_CS0           WEIM_BASE_ADDR
+#define WEIM_CTRL_CS1           (WEIM_BASE_ADDR + 0x10)
+#define WEIM_CTRL_CS2           (WEIM_BASE_ADDR + 0x20)
+#define WEIM_CTRL_CS3           (WEIM_BASE_ADDR + 0x30)
+#define WEIM_CTRL_CS4           (WEIM_BASE_ADDR + 0x40)
+#define WEIM_CTRL_CS5           (WEIM_BASE_ADDR + 0x50)
+#define M3IF_BASE_ADDR		0xB8003000
+#define EMI_BASE_ADDR		0xB8004000
+
+
+/*
+ * return soc version
+ * 	0x10:  TO1
+ *	0x20:  TO2
+ *	0x30:  TO3
+ */
+.macro check_soc_version ret, tmp
+	ldr \tmp, =IIM_BASE_ADDR
+	ldr \ret, [\tmp, #IIM_SREV]
+	cmp \ret, #0x00
+	moveq \tmp, #ROMPATCH_REV
+	ldreq \ret, [\tmp]
+	moveq \ret, \ret, lsl #4
+	addne \ret, \ret, #0x10
+.endm
+
+/*
+ * L2CC Cache setup/invalidation/disable
+ */
+.macro init_l2cc
     /* Disable L2 cache first */
     mov r0, #L2CC_BASE_ADDR
-    ldr r2, [r0, #L2_CACHE_CTL_REG]
-    bic r2, r2, #0x1
-    str r2, [r0, #L2_CACHE_CTL_REG]
+    ldr r1, [r0, #L2_CACHE_CTL_REG]
+    bic r1, r1, #0x1
+    str r1, [r0, #L2_CACHE_CTL_REG]
+
     /*
      * Configure L2 Cache:
      * - 128k size(16k way)
@@ -160,290 +179,413 @@ board_init_lowlevel:
      */
     ldr r1, [r0, #L2_CACHE_AUX_CTL_REG]
     and r1, r1, #0xFE000000
-    ldr r2, L2CACHE_PARAM
+    ldr r2, =L2CC_AUX_CTL_CONFIG
     orr r1, r1, r2
     str r1, [r0, #L2_CACHE_AUX_CTL_REG]
-/* Workaournd for DDR issue:WT*/
-    ldr r1, [r0, #L2_CACHE_DBG_CTL_REG]
-    orr r1, r1, #2
-    str r1, [r0, #L2_CACHE_DBG_CTL_REG]
 
-    /* Invalidate L2 */
+    /* Workaournd for TO1 DDR issue:WT*/
+    check_soc_version r1, r2
+    cmp r1, #CHIP_REV_2_0
+    ldrlo r1, [r0, #L2_CACHE_DBG_CTL_REG]
+    orrlo r1, r1, #2
+    strlo r1, [r0, #L2_CACHE_DBG_CTL_REG]
+
+   /* Invalidate L2 */
     mov r1, #0x000000FF
     str r1, [r0, #L2_CACHE_INV_WAY_REG]
-L2_loop:
+1:
     /* Poll Invalidate By Way register */
     ldr r2, [r0, #L2_CACHE_INV_WAY_REG]
     cmp r2, #0
-    bne L2_loop
-    /*** End of L2 operations ***/
+    bne 1b
+.endm /* init_l2cc */
 
-/*
- * End of ARM1136 init
- */
+/* AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.*/
+.macro init_aips
+	/*
+	 * Set all MPROTx to be non-bufferable, trusted for R/W,
+	 * not forced to user-mode.
+	 */
+	ldr r0, =AIPS1_BASE_ADDR
+	ldr r1, =AIPS_MPR_CONFIG
+	str r1, [r0, #0x00]
+	str r1, [r0, #0x04]
+	ldr r0, =AIPS2_BASE_ADDR
+	str r1, [r0, #0x00]
+	str r1, [r0, #0x04]
 
-        /*
-         * Set all MPROTx to be non-bufferable, trusted for R/W,
-         * not forced to user-mode.
-         */
-        ldr r0, AIPS1_CTRL_BASE_ADDR_W
-        ldr r1, AIPS1_PARAM_W
-        str r1, [r0, #0x00]
-        str r1, [r0, #0x04]
-        ldr r0, AIPS2_CTRL_BASE_ADDR_W
-        str r1, [r0, #0x00]
-        str r1, [r0, #0x04]
-
-        /*
-         * Clear the on and off peripheral modules Supervisor Protect bit
-         * for SDMA to access them. Did not change the AIPS control registers
-         * (offset 0x20) access type
-         */
-        ldr r0, AIPS1_CTRL_BASE_ADDR_W
-        ldr r1, =0x0
-        str r1, [r0, #0x40]
-        str r1, [r0, #0x44]
-        str r1, [r0, #0x48]
-        str r1, [r0, #0x4C]
-        ldr r1, [r0, #0x50]
-        and r1, r1, #0x00FFFFFF
-        str r1, [r0, #0x50]
-
-        ldr r0, AIPS2_CTRL_BASE_ADDR_W
-        ldr r1, =0x0
-        str r1, [r0, #0x40]
-        str r1, [r0, #0x44]
-        str r1, [r0, #0x48]
-        str r1, [r0, #0x4C]
-        ldr r1, [r0, #0x50]
-        and r1, r1, #0x00FFFFFF
-        str r1, [r0, #0x50]
-
-        ldr r0, MAX_BASE_ADDR_W
-        /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
-        ldr r1, MAX_PARAM1
-        str r1, [r0, #0x000]        /* for S0 */
-        str r1, [r0, #0x100]        /* for S1 */
-        str r1, [r0, #0x200]        /* for S2 */
-        str r1, [r0, #0x300]        /* for S3 */
-        str r1, [r0, #0x400]        /* for S4 */
-        /* SGPCR - always park on last master */
-        ldr r1, =0x10
-        str r1, [r0, #0x010]        /* for S0 */
-        str r1, [r0, #0x110]        /* for S1 */
-        str r1, [r0, #0x210]        /* for S2 */
-        str r1, [r0, #0x310]        /* for S3 */
-        str r1, [r0, #0x410]        /* for S4 */
-        /* MGPCR - restore default values */
-        ldr r1, =0x0
-        str r1, [r0, #0x800]        /* for M0 */
-        str r1, [r0, #0x900]        /* for M1 */
-        str r1, [r0, #0xA00]        /* for M2 */
-        str r1, [r0, #0xB00]        /* for M3 */
-        str r1, [r0, #0xC00]        /* for M4 */
-        str r1, [r0, #0xD00]        /* for M5 */
-
-	ldr r1, M3IF_BASE_W
 	/*
-	 * M3IF Control Register (M3IFCTL)
-	 * MRRP[0] = L2CC0 not on priority list (0 << 0)	= 0x00000000
-	 * MRRP[1] = MAX1 not on priority list (0 << 0)		= 0x00000000
-	 * MRRP[2] = L2CC1 not on priority list (0 << 0)	= 0x00000000
-	 * MRRP[3] = USB  not on priority list (0 << 0)		= 0x00000000
-	 * MRRP[4] = SDMA not on priority list (0 << 0)		= 0x00000000
-	 * MRRP[5] = GPU not on priority list (0 << 0)		= 0x00000000
-	 * MRRP[6] = IPU1 on priority list (1 << 6)		= 0x00000040
-	 * MRRP[7] = IPU2 not on priority list (0 << 0)		= 0x00000000
-	 *                                                       ------------
-	 *                                                        0x00000040
+	 * Clear the on and off peripheral modules Supervisor Protect bit
+	 * for SDMA to access them. Did not change the AIPS control registers
+	 * (offset 0x20) access type
 	 */
-	ldr r0, =0x00000040
+	ldr r0, =AIPS1_BASE_ADDR
+	ldr r1, =AIPS_OPACR_CONFIG
+	str r1, [r0, #0x40]
+	str r1, [r0, #0x44]
+	str r1, [r0, #0x48]
+	str r1, [r0, #0x4C]
+	str r1, [r0, #0x50]
+	ldr r0, =AIPS2_BASE_ADDR
+	str r1, [r0, #0x40]
+	str r1, [r0, #0x44]
+	str r1, [r0, #0x48]
+	str r1, [r0, #0x4C]
+	str r1, [r0, #0x50]
+.endm /* init_aips */
+
+/* MAX (Multi-Layer AHB Crossbar Switch) setup */
+.macro init_max
+	ldr r0, =MAX_BASE_ADDR
+	/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+	ldr r1, =MAX_MPR_CONFIG
+	str r1, [r0, #0x000]        /* for S0 */
+	str r1, [r0, #0x100]        /* for S1 */
+	str r1, [r0, #0x200]        /* for S2 */
+	str r1, [r0, #0x300]        /* for S3 */
+	str r1, [r0, #0x400]        /* for S4 */
+	/* SGPCR - always park on last master */
+	ldr r1, =MAX_SGPCR_CONFIG
+	str r1, [r0, #0x010]        /* for S0 */
+	str r1, [r0, #0x110]        /* for S1 */
+	str r1, [r0, #0x210]        /* for S2 */
+	str r1, [r0, #0x310]        /* for S3 */
+	str r1, [r0, #0x410]        /* for S4 */
+	/* MGPCR - restore default values */
+	ldr r1, =MAX_MGPCR_CONFIG
+	str r1, [r0, #0x800]        /* for M0 */
+	str r1, [r0, #0x900]        /* for M1 */
+	str r1, [r0, #0xA00]        /* for M2 */
+	str r1, [r0, #0xB00]        /* for M3 */
+	str r1, [r0, #0xC00]        /* for M4 */
+	str r1, [r0, #0xD00]        /* for M5 */
+.endm /* init_max */
+
+/* M3IF setup */
+.macro init_m3if
+	/* Configure M3IF registers */
+	ldr r1, =M3IF_BASE_ADDR
+	/*
+	* M3IF Control Register (M3IFCTL)
+	* MRRP[0] = L2CC0 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[1] = L2CC1 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[2] = MBX not on priority list (0 << 0)	= 0x00000000
+	* MRRP[3] = MAX1 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[4] = SDMA not on priority list (0 << 0)	= 0x00000000
+	* MRRP[5] = MPEG4 not on priority list (0 << 0)	= 0x00000000
+	* MRRP[6] = IPU1 on priority list (1 << 6)	= 0x00000040
+	* MRRP[7] = IPU2 not on priority list (0 << 0)	= 0x00000000
+	*						------------
+	*						  0x00000040
+	*/
+	ldr r0, =M3IF_CONFIG
 	str r0, [r1]  /* M3IF control reg */
+.endm /* init_m3if */
 
-#if 1
-	ldr r0, CCM_BASE_ADDR_W
-
-	/* default CLKO to 1/32 of the ARM core*/
-	ldr r1, [r0, #CCM_COSR]
-	bic r1, r1, #0x00000FF00
-	bic r1, r1, #0x0000000FF
-	mov r2, #0x00006C00
-	add r2, r2, #0x67
-	orr r1, r1, r2
-	str r1, [r0, #CCM_COSR]
+/* To support 133MHz DDR */
+.macro  init_drive_strength
+/*
+	mov r0, #0x2
+	ldr r1, =IOMUXC_BASE_ADDR
+	add r1, r1, #0x368
+        add r2, r1, #0x4C8 - 0x368
+1:      str r0, [r1], #4
+	cmp r1, r2
+        ble 1b
+*/
+.endm /* init_drive_strength */
+
+/* CPLD on CS5 setup */
+.macro init_debug_board
+	ldr r0, =DBG_BASE_ADDR
+	ldr r1, =DBG_CSCR_U_CONFIG
+	str r1, [r0, #0x00]
+	ldr r1, =DBG_CSCR_L_CONFIG
+	str r1, [r0, #0x04]
+	ldr r1, =DBG_CSCR_A_CONFIG
+	str r1, [r0, #0x08]
+.endm /* init_debug_board */
+
+/* clock setup */
+.macro init_clock
+	ldr r0, =CCM_BASE_ADDR
+
+        /* default CLKO to 1/32 of the ARM core*/
+        ldr r1, [r0, #CLKCTL_COSR]
+        bic r1, r1, #0x00000FF00
+        bic r1, r1, #0x0000000FF
+        mov r2, #0x00006C00
+        add r2, r2, #0x67
+        orr r1, r1, r2
+        str r1, [r0, #CLKCTL_COSR]
+
+        ldr r2, =CCM_CCMR_CONFIG
+        str r2, [r0, #CLKCTL_CCMR]
+
+    	check_soc_version r1, r2
+    	cmp r1, #CHIP_REV_2_0
+	ldrhs r3, =CCM_MPLL_399_HZ
+	bhs 1f
+	ldr r2, [r0, #CLKCTL_PDR0]
+        tst r2, #CLKMODE_CONSUMER
+        ldrne r3, =CCM_MPLL_532_HZ  /* consumer path*/
+        ldreq r3, =CCM_MPLL_399_HZ  /* auto path*/
+1:
+	str r3, [r0, #CLKCTL_MPCTL]
+
+        ldr r1, =CCM_PPLL_300_HZ
+        str r1, [r0, #CLKCTL_PPCTL]
+
+        ldr r1, [r0, #CLKCTL_PDR0]
+        orr r1, r1, #0x800000
+        str r1, [r0, #CLKCTL_PDR0]
+
+        ldr r1, =CCM_PDR0_CONFIG
+        str r1, [r0, #CLKCTL_PDR0]
+
+        ldr r1, [r0, #CLKCTL_CGR0]
+        orr r1, r1, #0x00300000
+        str r1, [r0, #CLKCTL_CGR0]
+
+        ldr r1, [r0, #CLKCTL_CGR1]
+        orr r1, r1, #0x00000C00
+        orr r1, r1, #0x00000003
+        str r1, [r0, #CLKCTL_CGR1]
+.endm /* init_clock */
+
+.macro init_sdram
+        writel(0x0000d843, 0xB8002050)
+        writel(0x22252521, 0xB8002054)
+        writel(0x22220a00, 0xB8002058)
+        writel(0x00000304, 0xB8001010)
+        writel(0x0000030C, 0xB8001010)
+        writel(0x007ffc3f, 0xB8001004)
+        writel(0x92220000, 0xB8001000)
+        writel(0x12345678, 0x80000400)
+        writel(0xA2220000, 0xB8001000)
+        writel(0x87654321, 0x80000000)
+        writel(0x87654321, 0x80000000)
+        writel(0xB2220000, 0xB8001000)
+        writeb(0xda, 0x80000233)
+        writeb(0xda, 0x82000780)
+        writeb(0xda, 0x82000400)
+        writel(0x82226080, 0xB8001000)
+        writel(0x007ffc3f, 0xB8001004)
+        writel(0x007ffc3f, 0xB800100C)
+        writel(0x00000304, 0xB8001010)
+        writel(0x00002000, 0xB8001008)
+.endm /* init_sdram */
+	
+.macro setup_sdram
+        ldr r0, =ESDCTL_BASE_ADDR
+        mov r3, #0x2000
+        str r3, [r0, #0x0]
+        str r3, [r0, #0x8]
+
+	/*ip(r12) has used to save lr register in upper calling*/
+        mov fp, lr
+
+	mov r5, #0x00
+        mov r2, #0x00
+        mov r1, #CSD0_BASE_ADDR
+        bl setup_sdram_bank
+        cmp r3, #0x0
+        orreq r5, r5, #1
+        eorne r2, r2, #0x1
+        blne setup_sdram_bank
+
+        mov lr, fp
+
+	check_soc_version r3, r4
+	cmp r1, #CHIP_REV_2_0
+	bhs 1f
+	cmp r5, #0
+        movne r3, #L2CC_BASE_ADDR
+        ldrne r4, [r3, #L2_CACHE_AUX_CTL_REG]
+        orrne r4, r4, #0x1000
+        strne r4, [r3, #L2_CACHE_AUX_CTL_REG]
+1:
+        ldr r3, =ESDCTL_DELAY_LINE5
+        str r3, [r0, #0x30]
+.endm /* setup_sdram */
 
-	ldr r2, CCM_CCMR_W
-	str r2, [r0, #CCM_CCMR]
+.section ".text.init", "x"
 
-	/* check clock path */
-	ldr r2, [r0, #CCM_PDR0]
-	tst r2, #0x1
-	ldrne r3, MPCTL_PARAM_532_W  /* consumer path*/
-	ldreq r3, MPCTL_PARAM_399_W  /* auto path*/
+.globl board_init_lowlevel
+board_init_lowlevel:
+	mov     r10, lr
 
-	/*Set MPLL , arm clock and ahb clock*/
-	str r3, [r0, #CCM_MPCTL]
+	/* Platform CHIP level init*/
+#ifdef TURN_OFF_IMPRECISE_ABORT
+	mrs r0, cpsr
+	bic r0, r0, #0x100
+	msr cpsr, r0
+#endif
 
-	ldr r1, PPCTL_PARAM_W
-	str r1, [r0, #CCM_PPCTL]
+	mrc 15, 0, r1, c1, c0, 0
 
-	ldr r1, [r0, #CCM_PDR0]
-	orr r1, r1, #0x800000
-	str r1, [r0, #CCM_PDR0]
+#ifndef BRANCH_PREDICTION_ENABLE
+    	mrc 15, 0, r0, c1, c0, 1
+    	bic r0, r0, #7
+    	mcr 15, 0, r0, c1, c0, 1
+#else
+    	mrc 15, 0, r0, c1, c0, 1
+    	orr r0, r0, #7
+    	mcr 15, 0, r0, c1, c0, 1
+    	orr r1, r1, #(1<<11)
+#endif
 
-	ldr r1, CCM_PDR0_W
-	str r1, [r0, #CCM_PDR0]
+#ifdef UNALIGNED_ACCESS_ENABLE
+    	orr r1, r1, #(1<<22)
+#endif
 
-	ldr r1, [r0, #CCM_CGR0]
-	orr r1, r1, #0x00300000
-	str r1, [r0, #CCM_CGR0]
+#ifdef LOW_INT_LATENCY_ENABLE
+    	orr r1, r1, #(1<<21)
+#endif
+    	mcr 15, 0, r1, c1, c0, 0
 
-	ldr r1, [r0, #CCM_CGR1]
-	orr r1, r1, #0x00000C00
-	orr r1, r1, #0x00000003
-	str r1, [r0, #CCM_CGR1]
+    	mov r0, #0
+#ifdef BRANCH_PREDICTION_ENABLE
+   	mcr 15, 0, r0, c15, c2, 4
 #endif
+	mcr 15, 0, r0, c7, c10, 4       /* Drain the write buffer */
 
-	/* Skip SDRAM initialization if we run from RAM */
-	cmp	pc, #0x80000000
-	bls	1f
-	cmp	pc, #0x90000000
-	bhi	1f
+	/* initializes very early AIPS, what for?
+	 * Then it also initializes Multi-Layer AHB Crossbar Switch,
+	 * M3IF */
+	/* Also setup the Peripheral Port Remap register inside the core */
+	ldr r0, =0x40000015        /* start from AIPS 2GB region */
+	mcr p15, 0, r0, c15, c2, 4
 
-	mov	pc, lr
+	init_l2cc
+
+	init_aips
+
+	init_max
+
+	init_m3if
+
+	init_drive_strength
+
+	cmp pc, #PHYS_SDRAM_1
+	blo init_clock_start
+	cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
+	blo skip_sdram_setup
+
+init_clock_start:
+	init_clock
+	init_debug_board
+	init_sdram
+	setup_sdram
 
-1:
-	ldr r0, ESDCTL_BASE_W
-	mov r3, #0x2000
-	str r3, [r0, #0x0]
-	str r3, [r0, #0x8]
-
-	mov r12, #0x00
-	mov r2, #0x00
-	mov r1, #IMX_SDRAM_CS0
-
-	ldr r0, ESDCTL_BASE_W
-	mov r3, #0x2000
-	str r3, [r0, #0x0]
-	str r3, [r0, #0x8]
-
-	mov r12, #0x00
-	mov r2, #0x00
-	mov r1, #IMX_SDRAM_CS0
-	bl setup_sdram_bank
-	cmp r3, #0x0
-	orreq r12, r12, #1
-	eorne r2, r2, #0x1
-	blne setup_sdram_bank
-
-	cmp r12, #0
-	movne r3, #L2CC_BASE_ADDR
-	ldrne r4, [r3, #L2_CACHE_AUX_CTL_REG]
-	orrne r4, r4, #0x1000
-	strne r4, [r3, #L2_CACHE_AUX_CTL_REG]
-
-	ldr r3, ESDCTL_DELAY5
-	str r3, [r0, #0x30]
 ret:
-	mov	pc,r10
+	mov     pc,r10
+
+skip_sdram_setup:
+	mov r0, #NFC_BASE_ADDR
+	add r1, r0, #NFC_BUF_SIZE
+	cmp pc, r0
+	movlo pc, lr
+	cmp pc, r1
+	movhi pc, lr
+	/* return from mxc_nand_load */
+	/* r12 saved upper lr*/
+	//b mxc_nand_load
 
 /*
- * r0: control base, r1: ram bank base
- * r2: ddr type(0:DDR2, 1:MDDR) r3, r4: working
+ * r0: ESDCTL control base, r1: sdram slot base
+ * r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base
  */
 setup_sdram_bank:
-
-	mov r3, #0xE /*0xA + 0x4*/
-	tst r2, #0x1
-	orreq r3, r3, #0x300 /*DDR2*/
-	str r3, [r0, #0x10]
-	bic r3, r3, #0x00A
-	str r3, [r0, #0x10]
-	beq 2f
-
-	mov r3, #0x20000
-1:	subs r3, r3, #1
-	bne 1b
-
-2:      adr r4, ESDCTL_CONFIG
-	tst r2, #0x1
-	ldreq r3, [r4, #0x0]
-	ldrne r3, [r4, #0x4]
-	cmp r1, #IMX_SDRAM_CS1
+        mov r3, #0xE /*0xA + 0x4*/
+        tst r2, #0x1
+        orreq r3, r3, #0x300 /*DDR2*/
+        str r3, [r0, #0x10]
+        bic r3, r3, #0x00A
+        str r3, [r0, #0x10]
+        beq 2f
+
+        mov r3, #0x20000
+1:      subs r3, r3, #1
+        bne 1b
+
+2:      tst r2, #0x1
+        ldreq r3, =ESDCTL_DDR2_CONFIG
+        ldrne r3, =ESDCTL_MDDR_CONFIG
+        cmp r1, #CSD1_BASE_ADDR
         strlo r3, [r0, #0x4]
         strhs r3, [r0, #0xC]
 
-        ldr r3, ESDCTL_0x92220000
+        ldr r3, =ESDCTL_0x92220000
         strlo r3, [r0, #0x0]
         strhs r3, [r0, #0x8]
-	mov r3, #0xDA
-        ldr r4, RAM_PARAM1_MDDR
+        mov r3, #0xDA
+        ldr r4, =ESDCTL_PRECHARGE
         strb r3, [r1, r4]
 
-	tst r2, #0x1
-	bne skip_set_mode
+        tst r2, #0x1
+        bne skip_set_mode
 
-	cmp r1, #IMX_SDRAM_CS1
-	ldr r3, ESDCTL_0xB2220000
+        cmp r1, #CSD1_BASE_ADDR
+        ldr r3, =ESDCTL_0xB2220000
         strlo r3, [r0, #0x0]
         strhs r3, [r0, #0x8]
-	mov r3, #0xDA
-	ldr r4, RAM_PARAM4_MDDR
+        mov r3, #0xDA
+        ldr r4, =ESDCTL_DDR2_EMR2
         strb r3, [r1, r4]
-        ldr r4, RAM_PARAM5_MDDR
+        ldr r4, =ESDCTL_DDR2_EMR3
         strb r3, [r1, r4]
-        ldr r4, RAM_PARAM3_MDDR
+        ldr r4, =ESDCTL_DDR2_EN_DLL
         strb r3, [r1, r4]
-        ldr r4, RAM_PARAM2_MDDR
+        ldr r4, =ESDCTL_DDR2_RESET_DLL
         strb r3, [r1, r4]
 
-        ldr r3, ESDCTL_0x92220000
+        ldr r3, =ESDCTL_0x92220000
         strlo r3, [r0, #0x0]
         strhs r3, [r0, #0x8]
-	mov r3, #0xDA
-        ldr r4, RAM_PARAM1_MDDR
+        mov r3, #0xDA
+        ldr r4, =ESDCTL_PRECHARGE
         strb r3, [r1, r4]
 
 skip_set_mode:
-	cmp r1, #IMX_SDRAM_CS1
-        ldr r3, ESDCTL_0xA2220000
+        cmp r1, #CSD1_BASE_ADDR
+        ldr r3, =ESDCTL_0xA2220000
         strlo r3, [r0, #0x0]
         strhs r3, [r0, #0x8]
         mov r3, #0xDA
         strb r3, [r1]
         strb r3, [r1]
 
-        ldr r3, ESDCTL_0xB2220000
+        ldr r3, =ESDCTL_0xB2220000
         strlo r3, [r0, #0x0]
         strhs r3, [r0, #0x8]
-	adr r4, RAM_PARAM6_MDDR
-	tst r2, #0x1
-	ldreq r4, [r4, #0x0]
-	ldrne r4, [r4, #0x4]
-        mov r3, #0xDA
+        tst r2, #0x1
+        ldreq r4, =ESDCTL_DDR2_MR
+        ldrne r4, =ESDCTL_MDDR_MR
+       	mov r3, #0xDA
         strb r3, [r1, r4]
-        ldreq r4, RAM_PARAM7_MDDR
+        ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT
         streqb r3, [r1, r4]
-	adr r4, RAM_PARAM3_MDDR
-	ldreq r4, [r4, #0x0]
-	ldrne r4, [r4, #0x4]
+        ldreq r4, =ESDCTL_DDR2_EN_DLL
+        ldrne r4, =ESDCTL_MDDR_EMR
         strb r3, [r1, r4]
 
-	cmp r1, #IMX_SDRAM_CS1
-        ldr r3, ESDCTL_0x82226080
+        cmp r1, #CSD1_BASE_ADDR
+        ldr r3, =ESDCTL_0x82228080
         strlo r3, [r0, #0x0]
         strhs r3, [r0, #0x8]
 
-	tst r2, #0x1
-	moveq r4, #0x20000
-	movne r4, #0x200
-1:	subs r4, r4, #1
-	bne 1b
+        tst r2, #0x1
+        moveq r4, #0x20000
+        movne r4, #0x200
+1:      subs r4, r4, #1
+        bne 1b
 
-	str r3, [r1, #0x100]
-	ldr r4, [r1, #0x100]
-	cmp r3, r4
-	movne r3, #1
-	moveq r3, #0
-	mov pc, lr
+       	str r3, [r1, #0x100]
+        ldr r4, [r1, #0x100]
+        cmp r3, r4
+        movne r3, #1
+        moveq r3, #0
 
+        mov pc, lr
diff --git a/board/freescale-mx35-3-stack/mx35_3stack.h b/board/freescale-mx35-3-stack/mx35_3stack.h
new file mode 100644
index 0000000000..7316fc2601
--- /dev/null
+++ b/board/freescale-mx35-3-stack/mx35_3stack.h
@@ -0,0 +1,247 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX31ADS Freescale board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/mx35.h>
+
+/* High Level Configuration Options */
+#define CONFIG_ARM1136		1	/* This is an arm1136 CPU core */
+#define CONFIG_MXC		1
+#define CONFIG_MX35		1	/* in a mx31 */
+#define CONFIG_MX35_HCLK_FREQ	24000000	/* RedBoot says 26MHz */
+#define CONFIG_MX35_CLK32	32768
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define BOARD_LATE_INIT
+/*
+ * Disabled for now due to build problems under Debian and a significant increase
+ * in the final file size: 144260 vs. 109536 Bytes.
+ */
+#if 0
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_FIT			1
+#define CONFIG_FIT_VERBOSE		1
+#endif
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG		1
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 512 * 1024)
+#define CFG_GBL_DATA_SIZE	128/* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_HARD_I2C		1
+#define CONFIG_I2C_MXC		1
+#define CFG_I2C_PORT		I2C_BASE_ADDR
+#define CFG_I2C_SPEED		100000
+#define CFG_I2C_SLAVE		0xfe
+
+#define CONFIG_MX35_UART	1
+#define CFG_MX35_UART1		1
+
+#define CONFIG_MMC		1
+#define CONFIG_DOS_PARTITION	1
+#define CONFIG_CMD_FAT		1
+
+#ifdef CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_FLASH_HEADER
+#define FHEADER_OFFSET	0x400
+#endif
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
+
+#define CFG_MMC_BASE		0x0
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+/*#define CONFIG_CMD_SPI*/
+/*#define CONFIG_CMD_DATE*/
+#define CONFIG_CMD_NAND
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+
+#define CONFIG_BOOTDELAY	3
+
+#define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+		"netdev=eth0\0"						\
+		"ethprime=smc911x\0"					\
+		"uboot_addr=0xa0000000\0"				\
+		"uboot=u-boot.bin\0"			\
+		"kernel=uImage\0"				\
+		"nfsroot=/opt/eldk/arm\0"				\
+		"bootargs_base=setenv bootargs console=ttymxc0,115200\0"\
+		"bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
+			"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\
+		"bootcmd=run bootcmd_net\0"				\
+		"bootcmd_net=run bootargs_base bootargs_nfs; "		\
+			"tftpboot ${loadaddr} ${kernel}; bootm\0"	\
+		"prg_uboot=tftpboot ${loadaddr} ${uboot}; "		\
+			"protect off ${uboot_addr} 0xa003ffff; "	\
+			"erase ${uboot_addr} 0xa003ffff; "		\
+			"cp.b ${loadaddr} ${uboot_addr} ${filesize}; "	\
+			"setenv filesize; saveenv\0"
+
+/*Support LAN9217*/
+#define CONFIG_DRIVER_SMC911X	1
+#define CONFIG_DRIVER_SMC911X_16_BIT 1
+#define CONFIG_DRIVER_SMC911X_BASE CS5_BASE_ADDR
+
+#define CONFIG_HAS_ETH1
+#define CONFIG_NET_MULTI 1
+#define CONFIG_MXC_FEC
+#define CONFIG_MII
+#define CFG_DISCOVER_PHY
+
+#define CFG_FEC0_IOBASE FEC_BASE_ADDR
+#define CFG_FEC0_PINMUX	-1
+#define CFG_FEC0_PHY_ADDR	0x1F
+#define CFG_FEC0_MIIBASE -1
+
+/*
+#define NAND_MAX_CHIPS                1
+#define CFG_NAND_BASE         (NFC_BASE_ADDR + 0x1E00)
+#define CFG_MAX_NAND_DEVICE 1
+*/
+
+/*
+ * The MX31ADS board seems to have a hardware "peculiarity" confirmed under
+ * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A
+ * controller inverted. The controller is capable of detecting and correcting
+ * this, but it needs 4 network packets for that. Which means, at startup, you
+ * will not receive answers to the first 4 packest, unless there have been some
+ * broadcasts on the network, or your board is on a hub. Reducing the ARP
+ * timeout from default 5 seconds to 200ms we speed up the initial TFTP
+ * transfer, should the user wish one, significantly.
+ */
+#define CONFIG_ARP_TIMEOUT	200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP		/* undef to save memory */
+#define CFG_PROMPT		"=> "
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_MAXARGS		16	/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START	0	/* memtest works on */
+#define CFG_MEMTEST_END		0x10000
+
+#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CFG_HZ			CONFIG_MX35_CLK32/* use 32kHz clock as source */
+
+#define CONFIG_CMDLINE_EDITING	1
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 * 1024)	/* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM_1		CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE	(128 * 1024 * 1024)
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_FLASH_BASE		CS0_BASE_ADDR
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip */
+/* Monitor at beginning of flash */
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 256KiB */
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_SECT_SIZE	(128 * 1024)
+#define CFG_ENV_SIZE		CFG_ENV_SECT_SIZE
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET + CFG_ENV_SIZE)
+#define CFG_ENV_SIZE_REDUND	CFG_ENV_SIZE
+
+/*
+ * S29WS256N NOR flash has 4 32KiB small sectors at the beginning and at the
+ * end. The rest of 32MiB is in 128KiB big sectors. U-Boot occupies the low
+ * 4 sectors, if we put environment next to it, we will have to occupy 128KiB
+ * for it. Putting it at the top of flash we use only 32KiB.
+ */
+#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_ENV_SECT_SIZE)
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+#define CFG_FLASH_CFI			1/* Flash memory is CFI compliant */
+#define CFG_FLASH_CFI_DRIVER		1/* Use drivers/cfi_flash.c */
+/* A non-standard buffered write algorithm */
+#define CONFIG_FLASH_SPANSION_S29WS_N	1
+#define CFG_FLASH_USE_BUFFER_WRITE	1/* Use buffered writes (~10x faster) */
+#define CFG_FLASH_PROTECTION		1/* Use hardware sector protection */
+
+/*-----------------------------------------------------------------------
+ * NAND FLASH driver setup
+ */
+#define NAND_MAX_CHIPS         1
+#define CFG_MAX_NAND_DEVICE    1
+#define CFG_NAND_BASE          0x40000000
+/*
+ * JFFS2 partitions
+ */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV	"nor0"
+
+#endif				/* __CONFIG_H */