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authorLucas Stach <dev@lynxeye.de>2019-11-09 15:28:37 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2019-11-11 09:15:56 +0100
commit096d308b6b780dba72538cf86c5031beaffe5e04 (patch)
tree2ee8ebd9ba40d02def6bd782380f30904d07fc59
parentdb3ea7aae9266e5f9328b25e440ac9cd095f8d17 (diff)
downloadbarebox-096d308b6b780dba72538cf86c5031beaffe5e04.tar.gz
ARM: zynq: add bootsource detection
Implement the bootsource detection by reading the BOOT_MODE SLCR register which holds the strap values used to select the boot source. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--arch/arm/mach-zynq/include/mach/zynq7000-regs.h1
-rw-r--r--arch/arm/mach-zynq/zynq.c27
2 files changed, 26 insertions, 2 deletions
diff --git a/arch/arm/mach-zynq/include/mach/zynq7000-regs.h b/arch/arm/mach-zynq/include/mach/zynq7000-regs.h
index dd02f5b..eeecfe1 100644
--- a/arch/arm/mach-zynq/include/mach/zynq7000-regs.h
+++ b/arch/arm/mach-zynq/include/mach/zynq7000-regs.h
@@ -63,6 +63,7 @@
#define ZYNQ_FPGA3_CLK_CTRL 0x0A0
#define ZYNQ_CLK_621_TRUE 0x0C4
#define ZYNQ_RST_CTRL_BASE (ZYNQ_SLCR_BASE + 0x200)
+#define ZYNQ_SLCR_BOOT_MODE (ZYNQ_SLCR_BASE + 0x25C)
#define ZYNQ_PSS_RST_CTRL (ZYNQ_RST_CTRL_BASE + 0x000)
#define ZYNQ_DDR_RST_CTRL (ZYNQ_RST_CTRL_BASE + 0x004)
#define ZYNQ_TOPSW_RST_CTRL (ZYNQ_RST_CTRL_BASE + 0x008)
diff --git a/arch/arm/mach-zynq/zynq.c b/arch/arm/mach-zynq/zynq.c
index ad06c62..79a6b90 100644
--- a/arch/arm/mach-zynq/zynq.c
+++ b/arch/arm/mach-zynq/zynq.c
@@ -14,11 +14,12 @@
*/
#include <asm/system.h>
-#include <io.h>
+#include <bootsource.h>
#include <common.h>
#include <init.h>
-#include <restart.h>
+#include <io.h>
#include <mach/zynq7000-regs.h>
+#include <restart.h>
static void __noreturn zynq_restart_soc(struct restart_handler *rst)
{
@@ -30,6 +31,26 @@ static void __noreturn zynq_restart_soc(struct restart_handler *rst)
hang();
}
+static enum bootsource zynq_bootsource_get(void)
+{
+ u32 boot_mode = readl(ZYNQ_SLCR_BOOT_MODE);
+
+ switch (boot_mode & 0x7) {
+ case 0x0:
+ return BOOTSOURCE_JTAG;
+ case 0x1:
+ return BOOTSOURCE_SPI;
+ case 0x2:
+ return BOOTSOURCE_NOR;
+ case 0x4:
+ return BOOTSOURCE_NAND;
+ case 0x5:
+ return BOOTSOURCE_MMC;
+ default:
+ return BOOTSOURCE_UNKNOWN;
+ }
+}
+
static int zynq_init(void)
{
u32 val;
@@ -50,6 +71,8 @@ static int zynq_init(void)
restart_handler_register_fn(zynq_restart_soc);
+ bootsource_set(zynq_bootsource_get());
+
return 0;
}
postcore_initcall(zynq_init);