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authorSascha Hauer <s.hauer@pengutronix.de>2019-11-25 10:35:23 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2019-11-27 12:17:00 +0100
commit9f7d69b7ee822bcd7fefd9dce1a472af07215225 (patch)
tree10e07edb6c827a71cebb0d5dec130759359405a0
parente08daf4b91fd6e390b5a7766c8f614edffe631bd (diff)
downloadbarebox-9f7d69b7ee822bcd7fefd9dce1a472af07215225.tar.gz
barebox-9f7d69b7ee822bcd7fefd9dce1a472af07215225.tar.xz
PCI: dwc: Add dw_pcie_disable_atu()
This adds dw_pcie_disable_atu() taken from Linux-5.4. This is needed by the upcoming Layerscape driver. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--drivers/pci/pcie-designware.c20
-rw-r--r--drivers/pci/pcie-designware.h8
2 files changed, 28 insertions, 0 deletions
diff --git a/drivers/pci/pcie-designware.c b/drivers/pci/pcie-designware.c
index 5747704cd5..9728964ec9 100644
--- a/drivers/pci/pcie-designware.c
+++ b/drivers/pci/pcie-designware.c
@@ -188,6 +188,26 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
dev_err(pci->dev, "Outbound iATU is not being enabled\n");
}
+void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
+ enum dw_pcie_region_type type)
+{
+ int region;
+
+ switch (type) {
+ case DW_PCIE_REGION_INBOUND:
+ region = PCIE_ATU_REGION_INBOUND;
+ break;
+ case DW_PCIE_REGION_OUTBOUND:
+ region = PCIE_ATU_REGION_OUTBOUND;
+ break;
+ default:
+ return;
+ }
+
+ dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index);
+ dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, (u32)~PCIE_ATU_ENABLE);
+}
+
int dw_pcie_wait_for_link(struct dw_pcie *pci)
{
int retries;
diff --git a/drivers/pci/pcie-designware.h b/drivers/pci/pcie-designware.h
index f989ef2bd9..1659d8f60b 100644
--- a/drivers/pci/pcie-designware.h
+++ b/drivers/pci/pcie-designware.h
@@ -103,6 +103,12 @@
struct pcie_port;
struct dw_pcie;
+enum dw_pcie_region_type {
+ DW_PCIE_REGION_UNKNOWN,
+ DW_PCIE_REGION_INBOUND,
+ DW_PCIE_REGION_OUTBOUND,
+};
+
struct dw_pcie_host_ops {
int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val);
@@ -176,6 +182,8 @@ int dw_pcie_wait_for_link(struct dw_pcie *pci);
void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
int type, u64 cpu_addr, u64 pci_addr,
u32 size);
+void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
+ enum dw_pcie_region_type type);
void dw_pcie_setup(struct dw_pcie *pci);
static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)