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authorLucas Stach <dev@lynxeye.de>2019-11-09 15:28:29 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2019-11-11 09:15:55 +0100
commitfee27d41640f4732f7df1648ba8c44b0f91153e3 (patch)
tree49e5b612581e2dc2d40da743fbb801844c18fb8a
parent73671592a41dd39051339c8e17742cae31e53823 (diff)
downloadbarebox-fee27d41640f4732f7df1648ba8c44b0f91153e3.tar.gz
clk: zynq: use base address of clock controller
The clock controller is a subregion of the SLCR, use the real base of this region for mapping the registers. This will allow to switch to DT based probing later. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--arch/arm/mach-zynq/zynq.c3
-rw-r--r--drivers/clk/zynq/clkc.c30
2 files changed, 17 insertions, 16 deletions
diff --git a/arch/arm/mach-zynq/zynq.c b/arch/arm/mach-zynq/zynq.c
index f6112fd..ec22b16 100644
--- a/arch/arm/mach-zynq/zynq.c
+++ b/arch/arm/mach-zynq/zynq.c
@@ -48,7 +48,8 @@ static int zynq_init(void)
writel(val, 0xf8f00000);
dmb();
- add_generic_device("zynq-clock", 0, NULL, ZYNQ_SLCR_BASE, 0x4000, IORESOURCE_MEM, NULL);
+ add_generic_device("zynq-clock", 0, NULL, ZYNQ_SLCR_BASE + 0x100,
+ 0x4000, IORESOURCE_MEM, NULL);
add_generic_device("smp_twd", 0, NULL, CORTEXA9_SCU_TIMER_BASE_ADDR,
0x4000, IORESOURCE_MEM, NULL);
restart_handler_register_fn(zynq_restart_soc);
diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c
index cd49d84..ba44174 100644
--- a/drivers/clk/zynq/clkc.c
+++ b/drivers/clk/zynq/clkc.c
@@ -360,38 +360,38 @@ static struct clk *zynq_cpu_subclk(const char *name,
static int zynq_clock_probe(struct device_d *dev)
{
struct resource *iores;
- void __iomem *slcr_base;
+ void __iomem *clk_base;
unsigned long ps_clk_rate = 33333330;
iores = dev_request_mem_resource(dev, 0);
if (IS_ERR(iores))
return PTR_ERR(iores);
- slcr_base = IOMEM(iores->start);
+ clk_base = IOMEM(iores->start);
clks[ps_clk] = clk_fixed("ps_clk", ps_clk_rate);
- clks[arm_pll] = zynq_pll_clk(ZYNQ_PLL_ARM, "arm_pll", slcr_base + 0x100);
- clks[ddr_pll] = zynq_pll_clk(ZYNQ_PLL_DDR, "ddr_pll", slcr_base + 0x104);
- clks[io_pll] = zynq_pll_clk(ZYNQ_PLL_IO, "io_pll", slcr_base + 0x108);
+ clks[arm_pll] = zynq_pll_clk(ZYNQ_PLL_ARM, "arm_pll", clk_base + 0x0);
+ clks[ddr_pll] = zynq_pll_clk(ZYNQ_PLL_DDR, "ddr_pll", clk_base + 0x4);
+ clks[io_pll] = zynq_pll_clk(ZYNQ_PLL_IO, "io_pll", clk_base + 0x8);
- clks[uart_clk] = zynq_periph_clk("uart_clk", slcr_base + 0x154);
+ clks[uart_clk] = zynq_periph_clk("uart_clk", clk_base + 0x54);
- clks[uart0] = clk_gate("uart0", "uart_clk", slcr_base + 0x154, 0, 0, 0);
- clks[uart1] = clk_gate("uart1", "uart_clk", slcr_base + 0x154, 1, 0, 0);
+ clks[uart0] = clk_gate("uart0", "uart_clk", clk_base + 0x54, 0, 0, 0);
+ clks[uart1] = clk_gate("uart1", "uart_clk", clk_base + 0x54, 1, 0, 0);
- clks[gem0] = clk_gate("gem0", "io_pll", slcr_base + 0x140, 0, 0, 0);
- clks[gem1] = clk_gate("gem1", "io_pll", slcr_base + 0x144, 1, 0, 0);
+ clks[gem0] = clk_gate("gem0", "io_pll", clk_base + 0x40, 0, 0, 0);
+ clks[gem1] = clk_gate("gem1", "io_pll", clk_base + 0x44, 1, 0, 0);
- clks[cpu_clk] = zynq_cpu_clk("cpu_clk", slcr_base + 0x120);
+ clks[cpu_clk] = zynq_cpu_clk("cpu_clk", clk_base + 0x20);
clks[cpu_6x4x] = zynq_cpu_subclk("cpu_6x4x", CPU_SUBCLK_6X4X,
- slcr_base + 0x120, slcr_base + 0x1C4);
+ clk_base + 0x20, clk_base + 0xC4);
clks[cpu_3x2x] = zynq_cpu_subclk("cpu_3x2x", CPU_SUBCLK_3X2X,
- slcr_base + 0x120, slcr_base + 0x1C4);
+ clk_base + 0x20, clk_base + 0xC4);
clks[cpu_2x] = zynq_cpu_subclk("cpu_2x", CPU_SUBCLK_2X,
- slcr_base + 0x120, slcr_base + 0x1C4);
+ clk_base + 0x20, clk_base + 0xC4);
clks[cpu_1x] = zynq_cpu_subclk("cpu_1x", CPU_SUBCLK_1X,
- slcr_base + 0x120, slcr_base + 0x1C4);
+ clk_base + 0x20, clk_base + 0xC4);
clk_register_clkdev(clks[cpu_3x2x], NULL, "arm_smp_twd");
clk_register_clkdev(clks[uart0], NULL, "zynq_serial0");