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authorLucas Stach <dev@lynxeye.de>2014-11-12 21:24:36 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2014-11-17 08:35:54 +0100
commit81e3bac87768495ccb6697e6c7b7a514f7f35007 (patch)
tree4044ec51d1a37ae3d8f7fed2a0e02490641d31a6
parentcc9026585ae3f93797de7625b2ac9612537e44bb (diff)
downloadbarebox-81e3bac87768495ccb6697e6c7b7a514f7f35007.tar.gz
pci: align bridge windows
The bridge filtering logic needs a minimum alignment of 1MB for mem and 4KB for io resources. Take this into account while assigning resources to devices in oredr to not produce overlapping windows between different bridges. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--drivers/pci/pci.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 87c2fca..7f8ebcf 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -1,4 +1,5 @@
#include <common.h>
+#include <sizes.h>
#include <linux/pci.h>
#ifdef DEBUG
@@ -259,14 +260,17 @@ static void postscan_setup_bridge(struct pci_dev *dev)
pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, bus_index - 1);
if (last_mem)
+ last_mem = ALIGN(last_mem, SZ_1M);
pci_write_config_word(dev, PCI_MEMORY_LIMIT,
((last_mem - 1) & 0xfff00000) >> 16);
if (last_mem_pref)
+ last_mem_pref = ALIGN(last_mem_pref, SZ_1M);
pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT,
((last_mem_pref - 1) & 0xfff00000) >> 16);
if (last_io) {
+ last_io = ALIGN(last_io, SZ_4K);
pci_write_config_byte(dev, PCI_IO_LIMIT,
((last_io - 1) & 0x0000f000) >> 8);
pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16,