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authorLucas Stach <dev@lynxeye.de>2014-11-03 23:52:24 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2014-11-04 12:16:52 +0100
commitc202b7c8d9e66082853ac1b131ddcedf53e9ca99 (patch)
treea99931c33f15981cb7c89b62bead145f2cc28a94
parent566c1630c3164e4e790ca1bfce462034a2639947 (diff)
downloadbarebox-c202b7c8d9e66082853ac1b131ddcedf53e9ca99.tar.gz
clk: tegra: don't enable UART clocks by default
Now that we are registering a proper driver for the UARTs we no longer need to enable the clocks unconditionally. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--drivers/clk/tegra/clk-tegra124.c8
-rw-r--r--drivers/clk/tegra/clk-tegra20.c10
-rw-r--r--drivers/clk/tegra/clk-tegra30.c10
3 files changed, 14 insertions, 14 deletions
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index d597a23..7a2f7c0 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -322,10 +322,10 @@ static struct tegra_clk_init_table init_table[] = {
{TEGRA124_CLK_PLL_P_OUT3, TEGRA124_CLK_CLK_MAX, 102000000, 1},
{TEGRA124_CLK_PLL_P_OUT4, TEGRA124_CLK_CLK_MAX, 204000000, 1},
{TEGRA124_CLK_MSELECT, TEGRA124_CLK_PLL_P, 102000000, 1},
- {TEGRA124_CLK_UARTA, TEGRA124_CLK_PLL_P, 0, 1},
- {TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 0, 1},
- {TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 0, 1},
- {TEGRA124_CLK_UARTD, TEGRA124_CLK_PLL_P, 0, 1},
+ {TEGRA124_CLK_UARTA, TEGRA124_CLK_PLL_P, 0, 0},
+ {TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 0, 0},
+ {TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 0, 0},
+ {TEGRA124_CLK_UARTD, TEGRA124_CLK_PLL_P, 0, 0},
{TEGRA124_CLK_SDMMC1, TEGRA124_CLK_PLL_P, 48000000, 0},
{TEGRA124_CLK_SDMMC2, TEGRA124_CLK_PLL_P, 48000000, 0},
{TEGRA124_CLK_SDMMC3, TEGRA124_CLK_PLL_P, 48000000, 0},
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 5b4365d..2ff42d8 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -324,11 +324,11 @@ static struct tegra_clk_init_table init_table[] = {
{TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1},
{TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 1},
{TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 120000000, 1},
- {TEGRA20_CLK_UARTA, TEGRA20_CLK_PLL_P, 0, 1},
- {TEGRA20_CLK_UARTB, TEGRA20_CLK_PLL_P, 0, 1},
- {TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P, 0, 1},
- {TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P, 0, 1},
- {TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P, 0, 1},
+ {TEGRA20_CLK_UARTA, TEGRA20_CLK_PLL_P, 0, 0},
+ {TEGRA20_CLK_UARTB, TEGRA20_CLK_PLL_P, 0, 0},
+ {TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P, 0, 0},
+ {TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P, 0, 0},
+ {TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P, 0, 0},
{TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0},
{TEGRA20_CLK_SDMMC2, TEGRA20_CLK_PLL_P, 48000000, 0},
{TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0},
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 7210053..46fd6dd 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -352,11 +352,11 @@ static struct tegra_clk_init_table init_table[] = {
{TEGRA30_CLK_PLL_P_OUT3, TEGRA30_CLK_CLK_MAX, 102000000, 1},
{TEGRA30_CLK_PLL_P_OUT4, TEGRA30_CLK_CLK_MAX, 204000000, 1},
{TEGRA30_CLK_MSELECT, TEGRA30_CLK_PLL_P, 102000000, 1},
- {TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 0, 1},
- {TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 0, 1},
- {TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 0, 1},
- {TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 0, 1},
- {TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 0, 1},
+ {TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 0, 0},
+ {TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 0, 0},
+ {TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 0, 0},
+ {TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 0, 0},
+ {TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 0, 0},
{TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0},
{TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0},
{TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0},