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authorLucas Stach <dev@lynxeye.de>2017-03-19 17:31:50 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2017-03-30 08:23:22 +0200
commit37e882cf3178e7672c0dafc10929980019d016c0 (patch)
tree1e76d9cb80d64191b74f3d0abf638b06d4ca5df2
parenta6414afa5d24590f5d3791042c4d902f66237f10 (diff)
downloadbarebox-37e882cf3178e7672c0dafc10929980019d016c0.tar.gz
ARM: tegra124: use old XUSB binding
The XUSB binding was changed upstream, to allow for more flexibility needed to support USB3. The barebox driver has not been adapted to this change. Add back the old DT properties in the Barebox internal DT to keep the existing PCIe functionality working. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--arch/arm/dts/tegra124.dtsi34
1 files changed, 34 insertions, 0 deletions
diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra124.dtsi
index 8af3a58..ce618db 100644
--- a/arch/arm/dts/tegra124.dtsi
+++ b/arch/arm/dts/tegra124.dtsi
@@ -1,3 +1,5 @@
+#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
+
/ {
aliases {
mmc0 = "/sdhci@700b0000/";
@@ -5,4 +7,36 @@
mmc2 = "/sdhci@700b0400/";
mmc3 = "/sdhci@700b0600/";
};
+
+ pcie-controller@01003000 {
+ phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
+ phy-names = "pcie";
+ };
+
+ padctl@7009f000 {
+ pinctrl-0 = <&padctl_default>;
+ pinctrl-names = "default";
+ #phy-cells = <1>;
+
+ padctl_default: pinmux {
+ usb3 {
+ nvidia,lanes = "pcie-0", "pcie-1";
+ nvidia,function = "usb3";
+ nvidia,iddq = <0>;
+ };
+
+ pcie {
+ nvidia,lanes = "pcie-2", "pcie-3",
+ "pcie-4";
+ nvidia,function = "pcie";
+ nvidia,iddq = <0>;
+ };
+
+ sata {
+ nvidia,lanes = "sata-0";
+ nvidia,function = "sata";
+ nvidia,iddq = <0>;
+ };
+ };
+ };
};