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authorSascha Hauer <s.hauer@pengutronix.de>2017-04-20 09:17:33 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2017-04-21 08:06:32 +0200
commitc0befa7cd0a16c6f3512124dac377fc9e1f46e34 (patch)
treef875b53a1123efd75ddd1a55372191ff45866471
parentd11584df3d8c311f8d12a16badc8fbe18e592f87 (diff)
downloadbarebox-c0befa7cd0a16c6f3512124dac377fc9e1f46e34.tar.gz
ARM: cache-l2x0: honour aux_val when determing way size
l2x0_init() allows to overwrite bits in the AUX_CTRL register using the aux_val/aux_mask arguments. On i.MX35 this is used to pass a correct AUX_CTRL value to overwrite bogus reset values for this register. To make this work we have to apply aux_val/aux_mask before using the AUX_CTRL value to determine the way size. This fixes: 3f7e890da7 ARM: l2x0: Implement L310 support Before this commit the way size was hardcoded to 8. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--arch/arm/cpu/cache-l2x0.c7
1 files changed, 3 insertions, 4 deletions
diff --git a/arch/arm/cpu/cache-l2x0.c b/arch/arm/cpu/cache-l2x0.c
index 0aa2482..8e0fff6 100644
--- a/arch/arm/cpu/cache-l2x0.c
+++ b/arch/arm/cpu/cache-l2x0.c
@@ -139,6 +139,9 @@ void l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
cache_id = readl(l2x0_base + L2X0_CACHE_ID);
aux = readl(l2x0_base + L2X0_AUX_CTRL);
+ aux &= aux_mask;
+ aux |= aux_val;
+
/* Determine the number of ways */
switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
case L2X0_CACHE_ID_PART_L310:
@@ -169,10 +172,6 @@ void l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
if (!(readl(l2x0_base + L2X0_CTRL) & 1)) {
/* l2x0 controller is disabled */
-
- aux = readl(l2x0_base + L2X0_AUX_CTRL);
- aux &= aux_mask;
- aux |= aux_val;
writel(aux, l2x0_base + L2X0_AUX_CTRL);
l2x0_inv_all();