diff options
authorMatt Reimer <>2017-04-14 11:32:05 -0700
committerSascha Hauer <>2017-04-19 10:09:38 +0200
commitdec7b4d2bf9c94a4760413a79d885842db902b65 (patch)
parent340a6e834801a318e355e950182b7af0fc08a364 (diff)
mtd: nand_omap_gpmc: fix BCH error correction
BCH error detection and correction was only looking at the first of four syndrome polynomials, which meant it was failing to detect and correct bitflips in the last 3/4 of the data. In effect, only the first 512 bytes of a 2048 byte page were being protected by ECC. The syndrome polynomials (BCH error codes) are stored in the NAND's OOB, each of which protects 512 bytes of data. The driver used eccsteps = 1 which effectively made it only use the first polynomial, and therefore was only protecting the first 512 bytes of the page. The fix is to pull over a bit of code from the kernel's omap_correct_data() that sets eccsteps = 4 when the page size is 2048 bytes and hardware ECC is being used. Signed-off-by: Matt Reimer <> Signed-off-by: Sascha Hauer <>
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/mtd/nand/nand_omap_gpmc.c b/drivers/mtd/nand/nand_omap_gpmc.c
index a4e6452..e18ce63 100644
--- a/drivers/mtd/nand/nand_omap_gpmc.c
+++ b/drivers/mtd/nand/nand_omap_gpmc.c
@@ -303,7 +303,8 @@ static int omap_correct_bch(struct mtd_info *mtd, uint8_t *dat,
int bitflip_count;
int bch_max_err;
- int eccsteps = oinfo->nand.ecc.steps;
+ int eccsteps = (nand->ecc.mode == NAND_ECC_HW) &&
+ (nand->ecc.size == 2048) ? 4 : 1;
int eccsize = oinfo->nand.ecc.bytes;
switch (oinfo->ecc_mode) {