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authorSteffen Trumtrar <s.trumtrar@pengutronix.de>2018-07-31 12:44:38 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2018-08-08 09:22:48 +0200
commit1466d7d0e485fe43258aea423d2e4deba7d83c1e (patch)
treecb8c6b6263b64a22f1ff907cc1a5ce480825a9f8
parentef7a2a150477ff55e0e7ba74b9d4e86a1482c497 (diff)
downloadbarebox-1466d7d0e485fe43258aea423d2e4deba7d83c1e.tar.gz
ARM: socfpga: arria10-reset-manager: don't reset bootsource
Arria10 init code resets all peripherals. Convert this to keep the bootmedium out of reset and keep the setup done by the boot ROM. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--arch/arm/mach-socfpga/arria10-bootsource.c16
-rw-r--r--arch/arm/mach-socfpga/arria10-reset-manager.c33
-rw-r--r--arch/arm/mach-socfpga/include/mach/arria10-system-manager.h4
-rw-r--r--arch/arm/mach-socfpga/include/mach/generic.h3
4 files changed, 43 insertions, 13 deletions
diff --git a/arch/arm/mach-socfpga/arria10-bootsource.c b/arch/arm/mach-socfpga/arria10-bootsource.c
index 26af64a..3319dc4 100644
--- a/arch/arm/mach-socfpga/arria10-bootsource.c
+++ b/arch/arm/mach-socfpga/arria10-bootsource.c
@@ -15,16 +15,17 @@
#include <bootsource.h>
#include <init.h>
#include <io.h>
+#include <mach/generic.h>
#include <mach/arria10-system-manager.h>
-static int arria10_boot_save_loc(void)
-{
+enum bootsource arria10_get_bootsource(void) {
enum bootsource src = BOOTSOURCE_UNKNOWN;
uint32_t val;
+ uint32_t mask = ARRIA10_SYSMGR_BOOTINFO_BSEL_MASK;
val = readl(ARRIA10_SYSMGR_BOOTINFO);
- switch ((val & 0x7000) >> 12) {
+ switch ((val & mask) >> ARRIA10_SYSMGR_BOOTINFO_BSEL_SHIFT) {
case 0:
/* reserved */
break;
@@ -45,6 +46,15 @@ static int arria10_boot_save_loc(void)
break;
}
+ return src;
+}
+
+static int arria10_boot_save_loc(void)
+{
+ enum bootsource src;
+
+ src = arria10_get_bootsource();
+
bootsource_set(src);
bootsource_set_instance(0);
diff --git a/arch/arm/mach-socfpga/arria10-reset-manager.c b/arch/arm/mach-socfpga/arria10-reset-manager.c
index a7e4bd6..76adc17 100644
--- a/arch/arm/mach-socfpga/arria10-reset-manager.c
+++ b/arch/arm/mach-socfpga/arria10-reset-manager.c
@@ -5,8 +5,10 @@
*/
#include <common.h>
+#include <bootsource.h>
#include <errno.h>
#include <io.h>
+#include <mach/generic.h>
#include <mach/arria10-pinmux.h>
#include <mach/arria10-regs.h>
#include <mach/arria10-reset-manager.h>
@@ -14,23 +16,35 @@
void arria10_reset_peripherals(void)
{
- unsigned mask_ecc_ocp = ARRIA10_RSTMGR_PER0MODRST_EMAC0OCP |
+ enum bootsource src;
+
+ uint32_t mask = ARRIA10_RSTMGR_PER0MODRST_EMAC0OCP |
ARRIA10_RSTMGR_PER0MODRST_EMAC1OCP |
ARRIA10_RSTMGR_PER0MODRST_EMAC2OCP |
ARRIA10_RSTMGR_PER0MODRST_USB0OCP |
ARRIA10_RSTMGR_PER0MODRST_USB1OCP |
ARRIA10_RSTMGR_PER0MODRST_NANDOCP |
- ARRIA10_RSTMGR_PER0MODRST_QSPIOCP |
- ARRIA10_RSTMGR_PER0MODRST_SDMMCOCP;
+ ARRIA10_RSTMGR_PER0MODRST_QSPIOCP;
+
+ src = arria10_get_bootsource();
+ if (src == BOOTSOURCE_MMC) {
+ mask |= ARRIA10_RSTMGR_PER0MODRST_SDMMC;
+ mask |= ARRIA10_RSTMGR_PER0MODRST_SDMMCOCP;
+ }
- /* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
+ /* disable all components except the ECC_OCP and bootsource */
writel(0xffffffff, ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER1MODRST);
- setbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST,
- ~mask_ecc_ocp);
+ writel(~mask, ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST);
+
+ mask = 0xffffffff;
+
+ if (src == BOOTSOURCE_MMC) {
+ mask &= ~ARRIA10_RSTMGR_PER0MODRST_SDMMC;
+ mask &= ~ARRIA10_RSTMGR_PER0MODRST_SDMMCOCP;
+ }
/* Finally disable the ECC_OCP */
- setbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST,
- mask_ecc_ocp);
+ writel(mask, ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST);
}
void arria10_reset_deassert_dedicated_peripherals(void)
@@ -45,8 +59,7 @@ void arria10_reset_deassert_dedicated_peripherals(void)
/* enable ECC OCP first */
clrbits_le32(ARRIA10_RSTMGR_ADDR + ARRIA10_RSTMGR_PER0MODRST, mask);
- mask = ARRIA10_RSTMGR_PER0MODRST_SDMMC |
- ARRIA10_RSTMGR_PER0MODRST_QSPI |
+ mask = ARRIA10_RSTMGR_PER0MODRST_QSPI |
ARRIA10_RSTMGR_PER0MODRST_NAND |
ARRIA10_RSTMGR_PER0MODRST_DMA;
diff --git a/arch/arm/mach-socfpga/include/mach/arria10-system-manager.h b/arch/arm/mach-socfpga/include/mach/arria10-system-manager.h
index f98cc36..20bd352 100644
--- a/arch/arm/mach-socfpga/include/mach/arria10-system-manager.h
+++ b/arch/arm/mach-socfpga/include/mach/arria10-system-manager.h
@@ -52,6 +52,10 @@
#define ARRIA10_SYSMGR_NOC_IDLESTATUS (ARRIA10_SYSMGR_ADDR + 0xd4)
#define ARRIA10_SYSMGR_FPGA2SOC_CTRL (ARRIA10_SYSMGR_ADDR + 0xd8)
+
+#define ARRIA10_SYSMGR_BOOTINFO_BSEL_MASK 0x00007000
+#define ARRIA10_SYSMGR_BOOTINFO_BSEL_SHIFT 12
+
/* pin mux */
#define ARRIA10_SYSMGR_PINMUXGRP (ARRIA10_SYSMGR_ADDR + 0x400)
#define ARRIA10_SYSMGR_PINMUXGRP_NANDUSEFPGA (ARRIA10_SYSMGR_PINMUXGRP + 0x2F0)
diff --git a/arch/arm/mach-socfpga/include/mach/generic.h b/arch/arm/mach-socfpga/include/mach/generic.h
index da90289..5fcbc9e 100644
--- a/arch/arm/mach-socfpga/include/mach/generic.h
+++ b/arch/arm/mach-socfpga/include/mach/generic.h
@@ -45,6 +45,9 @@ static inline void socfpga_cyclone5_qspi_init(void)
return;
}
#endif
+#if defined(CONFIG_ARCH_SOCFPGA_ARRIA10)
+enum bootsource arria10_get_bootsource(void);
+#endif
static inline void __udelay(unsigned us)
{