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authorSteffen Trumtrar <s.trumtrar@pengutronix.de>2018-07-31 12:44:40 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2018-08-08 09:22:48 +0200
commit21fbe47970155751bb913afa81496eea341a40a1 (patch)
treeede19275f19c0b214b5ccfdb09f14366df28609e
parent8a680e3c9b5dd8470b7437654877d5439e9a6407 (diff)
downloadbarebox-21fbe47970155751bb913afa81496eea341a40a1.tar.gz
ARM: socfpga: achilles: convert to PBL barebox
Previously the FPGA was configured externally on the Achilles. On newer versions this is changed and barebox has to configure the FPGA before the SDRAM can be used. If the FPGA is configured via JTAG or from an external memory, the *-bringup version can be used. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--arch/arm/boards/reflex-achilles/Makefile4
-rw-r--r--arch/arm/boards/reflex-achilles/board.c19
-rw-r--r--arch/arm/boards/reflex-achilles/lowlevel.c86
-rw-r--r--images/Makefile.socfpga6
4 files changed, 106 insertions, 9 deletions
diff --git a/arch/arm/boards/reflex-achilles/Makefile b/arch/arm/boards/reflex-achilles/Makefile
index 6b42141..092c31d 100644
--- a/arch/arm/boards/reflex-achilles/Makefile
+++ b/arch/arm/boards/reflex-achilles/Makefile
@@ -1,2 +1,2 @@
-obj-y += lowlevel.o
-pbl-y += lowlevel.o
+lwl-y += lowlevel.o
+obj-y += board.o
diff --git a/arch/arm/boards/reflex-achilles/board.c b/arch/arm/boards/reflex-achilles/board.c
new file mode 100644
index 0000000..29011ba
--- /dev/null
+++ b/arch/arm/boards/reflex-achilles/board.c
@@ -0,0 +1,19 @@
+#include <common.h>
+#include <init.h>
+#include <io.h>
+#include <bbu.h>
+
+static int achilles_init(void)
+{
+ int pbl_index = 0;
+
+ if (!of_machine_is_compatible("reflex,achilles"))
+ return 0;
+
+ pbl_index = readl(0xFFD06210);
+
+ pr_debug("Current barebox instance %d\n", pbl_index);
+
+ return 0;
+}
+postcore_initcall(achilles_init);
diff --git a/arch/arm/boards/reflex-achilles/lowlevel.c b/arch/arm/boards/reflex-achilles/lowlevel.c
index 4c18fa6..2265aa8 100644
--- a/arch/arm/boards/reflex-achilles/lowlevel.c
+++ b/arch/arm/boards/reflex-achilles/lowlevel.c
@@ -1,24 +1,39 @@
#include <common.h>
#include <linux/sizes.h>
#include <io.h>
-#include <asm/barebox-arm-head.h>
+#include <memory.h>
#include <asm/barebox-arm.h>
#include <asm/cache.h>
+#include <asm/sections.h>
+#include <asm/unaligned.h>
#include <debug_ll.h>
+#include <pbl.h>
#include <mach/arria10-sdram.h>
#include <mach/arria10-regs.h>
#include <mach/arria10-reset-manager.h>
#include <mach/arria10-clock-manager.h>
#include <mach/arria10-pinmux.h>
+#include <mach/arria10-fpga.h>
#include "pll-config-arria10.c"
#include "pinmux-config-arria10.c"
#include <mach/generic.h>
+#define BAREBOX_PART 0
+#define BITSTREAM_PART 1
+#define BAREBOX1_OFFSET SZ_1M
+#define BAREBOX2_OFFSET BAREBOX1_OFFSET + SZ_512K
+#define BAREBOX3_OFFSET BAREBOX2_OFFSET + SZ_512K
+#define BAREBOX4_OFFSET BAREBOX3_OFFSET + SZ_512K
+#define BITSTREAM1_OFFSET 0x0
+#define BITSTREAM2_OFFSET BITSTREAM1_OFFSET + SZ_64M
+
extern char __dtb_socfpga_arria10_achilles_start[];
-static noinline void achilles_entry(void)
+static noinline void achilles_start(void)
{
- void *fdt;
+ int pbl_index = 0;
+ int barebox = 0;
+ int bitstream = 0;
arm_early_mmu_cache_invalidate();
@@ -26,20 +41,79 @@ static noinline void achilles_entry(void)
setup_c();
arria10_init(&mainpll_cfg, &perpll_cfg, pinmux);
+
+ arria10_prepare_mmc(BAREBOX_PART, BITSTREAM_PART);
+
+ pbl_index = readl(ARRIA10_SYSMGR_ROM_INITSWLASTLD);
+
+ switch (pbl_index) {
+ case 0:
+ barebox = BAREBOX1_OFFSET;
+ bitstream = BITSTREAM1_OFFSET;
+ break;
+ case 1:
+ barebox = BAREBOX2_OFFSET;
+ bitstream = BITSTREAM1_OFFSET;
+ break;
+ case 2:
+ barebox = BAREBOX3_OFFSET;
+ bitstream = BITSTREAM2_OFFSET;
+ break;
+ case 3:
+ barebox = BAREBOX4_OFFSET;
+ bitstream = BITSTREAM2_OFFSET;
+ break;
+ }
+
+ arria10_load_fpga(bitstream, SZ_64M);
+
arria10_finish_io(&mainpll_cfg, &perpll_cfg, pinmux);
arria10_ddr_calibration_sequence();
+ arria10_start_image(barebox);
+}
+
+ENTRY_FUNCTION(start_socfpga_achilles, r0, r1, r2)
+{
+ void *fdt;
+
+ if (get_pc() > ARRIA10_OCRAM_ADDR) {
+ arm_cpu_lowlevel_init();
+
+ arm_setup_stack(ARRIA10_OCRAM_ADDR + SZ_256K - 32);
+
+ achilles_start();
+ }
+
fdt = __dtb_socfpga_arria10_achilles_start + get_runtime_offset();
barebox_arm_entry(0x0, SZ_2G + SZ_1G, fdt);
}
-ENTRY_FUNCTION(start_socfpga_achilles, r0, r1, r2)
+ENTRY_FUNCTION(start_socfpga_achilles_bringup, r0, r1, r2)
{
+ void *fdt;
+
arm_cpu_lowlevel_init();
- arm_setup_stack(0xffe00000 + SZ_256K - SZ_32K - SZ_4K - 16);
+ arm_setup_stack(ARRIA10_OCRAM_ADDR + SZ_256K - 16);
+
+ arm_early_mmu_cache_invalidate();
+
+ relocate_to_current_adr();
+ setup_c();
+
+ arria10_init(&mainpll_cfg, &perpll_cfg, pinmux);
- achilles_entry();
+ /* wait for fpga_usermode */
+ a10_wait_for_usermode(0x1000000);
+
+ arria10_finish_io(&mainpll_cfg, &perpll_cfg, pinmux);
+
+ arria10_ddr_calibration_sequence();
+
+ fdt = __dtb_socfpga_arria10_achilles_start + get_runtime_offset();
+
+ barebox_arm_entry(0x0, SZ_2G + SZ_1G, fdt);
}
diff --git a/images/Makefile.socfpga b/images/Makefile.socfpga
index bba01a3..a075b36 100644
--- a/images/Makefile.socfpga
+++ b/images/Makefile.socfpga
@@ -42,9 +42,13 @@ FILE_barebox-socfpga-de0_nano_soc.img = start_socfpga_de0_nano_soc.pblx
socfpga-barebox-$(CONFIG_MACH_SOCFPGA_TERASIC_DE0_NANO_SOC) += barebox-socfpga-de0_nano_soc.img
pblx-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += start_socfpga_achilles
-FILE_barebox-socfpga-achilles.img = start_socfpga_achilles.pblx.socfpgaimg
+FILE_barebox-socfpga-achilles.img = start_socfpga_achilles.socfpga-ocram-img
socfpga-barebox-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += barebox-socfpga-achilles.img
+pblx-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += start_socfpga_achilles_bringup
+FILE_barebox-socfpga-achilles-bringup.img = start_socfpga_achilles_bringup.pblx
+socfpga-barebox-$(CONFIG_MACH_SOCFPGA_REFLEX_ACHILLES) += barebox-socfpga-achilles-bringup.img
+
pblx-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += start_socfpga_sockit_xload
FILE_barebox-socfpga-sockit-xload.img = start_socfpga_sockit_xload.pblx.socfpgaimg
socfpga-xload-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += barebox-socfpga-sockit-xload.img