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authorSascha Hauer <s.hauer@pengutronix.de>2018-08-15 15:39:22 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2018-08-15 15:39:24 +0200
commitc05d6d09ba48b69b423bd5542128504083190465 (patch)
tree1d52c09c51f8282d285c85dbb5be8549d4b85f34
parente634843aa3833ee0fb5a9f13aa71d06bf8271326 (diff)
downloadbarebox-c05d6d09ba48b69b423bd5542128504083190465.tar.gz
ARM: MMU: fix wrong dma_flush_range in arm_create_pte()
Since 7ba0f2d299 arm_create_pte() flushes the page table entries itself and it's no longer done in arch_remap_range(). Unfortunately it does not flush the modified 1st level page table entry, but instead the base of the page table. Fix it up. Fixes: 7ba0f2d299 ARM: mmu: fix cache flushing when replacing a section with a PTE Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--arch/arm/cpu/mmu.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
index 88ee11c..f6c44e3 100644
--- a/arch/arm/cpu/mmu.c
+++ b/arch/arm/cpu/mmu.c
@@ -151,7 +151,7 @@ static u32 *arm_create_pte(unsigned long virt, uint32_t flags)
dma_flush_range(table, PTRS_PER_PTE * sizeof(u32));
ttb[ttb_idx] = (unsigned long)table | PMD_TYPE_TABLE;
- dma_flush_range(ttb, sizeof(u32));
+ dma_flush_range(&ttb[ttb_idx], sizeof(u32));
return table;
}