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authorJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2009-11-02 19:54:27 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2009-11-03 09:48:53 +0100
commit7aa3778f6d7dfa7d7b10d4bbda73d316a9b285a6 (patch)
tree5156aaffef5873bac129f574f5b6b1b6e1ab638b
parent7dcef1bb2096a2392b6e4ac3e98c2403e9b59f8e (diff)
downloadbarebox-7aa3778f6d7dfa7d7b10d4bbda73d316a9b285a6.tar.gz
barebox-7aa3778f6d7dfa7d7b10d4bbda73d316a9b285a6.tar.xz
arm: add Debug Communications Channel serial driver support
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--drivers/serial/Kconfig4
-rw-r--r--drivers/serial/Makefile1
-rw-r--r--drivers/serial/arm_dcc.c169
3 files changed, 174 insertions, 0 deletions
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 12854ef479..b0ff5fa133 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -1,5 +1,9 @@
menu "serial drivers "
+config DRIVER_SERIAL_ARM_DCC
+ depends on ARM
+ bool "ARM Debug Communications Channel (DCC) serial driver"
+
config DRIVER_SERIAL_IMX
depends on ARCH_IMX
default y
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 3bc965c6e3..8ab680de7a 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -5,6 +5,7 @@
# serial_pl010.o
# serial_pl011.o
# serial_xuartlite.o
+obj-$(CONFIG_DRIVER_SERIAL_ARM_DCC) += arm_dcc.o
obj-$(CONFIG_DRIVER_SERIAL_IMX) += serial_imx.o
obj-$(CONFIG_DRIVER_SERIAL_ATMEL) += atmel.o
obj-$(CONFIG_DRIVER_SERIAL_NETX) += serial_netx.o
diff --git a/drivers/serial/arm_dcc.c b/drivers/serial/arm_dcc.c
new file mode 100644
index 0000000000..151730b188
--- /dev/null
+++ b/drivers/serial/arm_dcc.c
@@ -0,0 +1,169 @@
+/*
+ * Copyright (C) 2004-2007 ARM Limited.
+ * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * As a special exception, if other files instantiate templates or use macros
+ * or inline functions from this file, or you compile this file and link it
+ * with other works to produce a work based on this file, this file does not
+ * by itself cause the resulting work to be covered by the GNU General Public
+ * License. However the source code for this file must still be made available
+ * in accordance with section (3) of the GNU General Public License.
+
+ * This exception does not invalidate any other reasons why a work based on
+ * this file might be covered by the GNU General Public License.
+ */
+
+#include <common.h>
+#include <driver.h>
+#include <init.h>
+
+#if defined(CONFIG_CPU_V6)
+/*
+ * ARMV6
+ */
+#define DCC_RBIT (1 << 30)
+#define DCC_WBIT (1 << 29)
+
+#define write_dcc(x) \
+ __asm__ volatile ("mcr p14, 0, %0, c0, c5, 0\n" : : "r" (x))
+
+#define read_dcc(x) \
+ __asm__ volatile ("mrc p14, 0, %0, c0, c5, 0\n" : "=r" (x))
+
+#define status_dcc(x) \
+ __asm__ volatile ("mrc p14, 0, %0, c0, c1, 0\n" : "=r" (x))
+
+#elif defined(CONFIG_CPU_XSCALE)
+/*
+ * XSCALE
+ */
+#define DCC_RBIT (1 << 31)
+#define DCC_WBIT (1 << 28)
+
+#define write_dcc(x) \
+ __asm__ volatile ("mcr p14, 0, %0, c8, c0, 0\n" : : "r" (x))
+
+#define read_dcc(x) \
+ __asm__ volatile ("mrc p14, 0, %0, c9, c0, 0\n" : "=r" (x))
+
+#define status_dcc(x) \
+ __asm__ volatile ("mrc p14, 0, %0, c14, c0, 0\n" : "=r" (x))
+
+#else
+#define DCC_RBIT (1 << 0)
+#define DCC_WBIT (1 << 1)
+
+#define write_dcc(x) \
+ __asm__ volatile ("mcr p14, 0, %0, c1, c0, 0\n" : : "r" (x))
+
+#define read_dcc(x) \
+ __asm__ volatile ("mrc p14, 0, %0, c1, c0, 0\n" : "=r" (x))
+
+#define status_dcc(x) \
+ __asm__ volatile ("mrc p14, 0, %0, c0, c0, 0\n" : "=r" (x))
+
+#endif
+
+#define can_read_dcc(x) do { \
+ status_dcc(x); \
+ x &= DCC_RBIT; \
+ } while (0);
+
+#define can_write_dcc(x) do { \
+ status_dcc(x); \
+ x &= DCC_WBIT; \
+ x = (x == 0); \
+ } while (0);
+
+#define TIMEOUT_COUNT 0x4000000
+
+static int arm_dcc_getc(struct console_device *cdev)
+{
+ int c;
+ register unsigned int reg;
+
+ do {
+ can_read_dcc(reg);
+ } while (!reg);
+ read_dcc(c);
+
+ return c;
+}
+
+static void arm_dcc_putc(struct console_device *cdev, char c)
+{
+ register unsigned int reg;
+ unsigned int timeout_count = TIMEOUT_COUNT;
+
+ while (--timeout_count) {
+ can_write_dcc(reg);
+ if (reg)
+ break;
+ }
+ if (timeout_count == 0)
+ return;
+ else
+ write_dcc(c);
+}
+
+static int arm_dcc_tstc(struct console_device *cdev)
+{
+ register unsigned int reg;
+
+ can_read_dcc(reg);
+
+ return reg;
+}
+
+static struct console_device arm_dcc_dev;
+
+static int arm_dcc_probe(struct device_d *dev)
+{
+ struct console_device *cdev;
+
+ cdev = &arm_dcc_dev;
+ dev->type_data = cdev;
+ cdev->dev = dev;
+ cdev->f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR;
+ cdev->tstc = arm_dcc_tstc;
+ cdev->putc = arm_dcc_putc;
+ cdev->getc = arm_dcc_getc;
+
+ /* Enable UART */
+
+ console_register(cdev);
+
+ return 0;
+}
+
+static struct driver_d arm_dcc_driver = {
+ .name = "arm_dcc",
+ .probe = arm_dcc_probe,
+};
+
+static struct device_d arm_dcc_device = {
+ .name = "arm_dcc",
+ .size = 4096,
+};
+
+static int arm_dcc_init(void)
+{
+ register_device(&arm_dcc_device);
+ register_driver(&arm_dcc_driver);
+ return 0;
+}
+
+console_initcall(arm_dcc_init);