Adapt pcm043 platform to boot from NAND

Adapt the pcm043 plattform to be able to boot from NOR and NAND

Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

4 files changed, 107 insertions, 23 deletions

diff --git a/board/pcm043/env/config b/board/pcm043/env/config
index 9aab89fc5c..3558c3a119 100644
--- a/board/pcm043/env/config
+++ b/board/pcm043/env/config
@@ -1,8 +1,8 @@
 #!/bin/sh
 
 # can be either 'net', 'nor' or 'nand''
-kernel=net
-root=net
+kernel=nor
+root=nor
 
 uimage=uImage-pcm043
 jffs2=root-pcm043.jffs2
@@ -14,6 +14,8 @@ bootargs="console=ttymxc0,115200"
 
 nor_parts="256k(uboot)ro,128k(ubootenv),2048k(kernel),-(root)"
 rootpart_nor="/dev/mtdblock3"
+nand_parts="256k(uboot)ro,128k(ubootenv),2048k(kernel),-(root)"
+rootpart_nand="/dev/mtdblock3"
 
 # use 'dhcp' to do dhcp in uboot and in kernel
 ip=dhcp
diff --git a/board/pcm043/lowlevel_init.S b/board/pcm043/lowlevel_init.S
index 649bf387ed..a7cb300ad2 100644
--- a/board/pcm043/lowlevel_init.S
+++ b/board/pcm043/lowlevel_init.S
@@ -41,6 +41,8 @@
 #define MPCTL_PARAM_532     ((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1))
 #define PPCTL_PARAM_300     (IMX_PLL_PD(0) | IMX_PLL_MFD(3) | IMX_PLL_MFI(6) | IMX_PLL_MFN(1))
 
+	.section ".text_bare_init","ax"
+
 ARM_PPMRR:              .word   0x40000015
 L2CACHE_PARAM:          .word   0x00030024
 CCM_CCMR_W:             .word   0x003F4208
@@ -129,11 +131,13 @@ board_init_lowlevel:
 
 	#define DDRTYPE	0x00000800
 
-	writel(DDRTYPE, IMX_IOMUXC_BASE + 0x794)
-	writel(DDRTYPE, IMX_IOMUXC_BASE + 0x798)
-	writel(DDRTYPE, IMX_IOMUXC_BASE + 0x79c)
-	writel(DDRTYPE, IMX_IOMUXC_BASE + 0x7a0)
-	writel(DDRTYPE, IMX_IOMUXC_BASE + 0x7a4)
+	ldr	r0, =IMX_IOMUXC_BASE + 0x794
+	ldr	r1, =DDRTYPE
+	str	r1, [r0], #4	/* IMX_IOMUXC_BASE + 0x794 */
+	str	r1, [r0], #4	/* IMX_IOMUXC_BASE + 0x798 */
+	str	r1, [r0], #4	/* IMX_IOMUXC_BASE + 0x79c */
+	str	r1, [r0], #4	/* IMX_IOMUXC_BASE + 0x7a0 */
+	str	r1, [r0]	/* IMX_IOMUXC_BASE + 0x7a4 */
 
 	/* MDDR init, enable mDDR*/
 	writel(0x00000304, ESDMISC) /* was 0x00000004 */
@@ -192,5 +196,36 @@ board_init_lowlevel:
 	orr r1, r1, #0x1000
 	str r1, [r0, #L2X0_AUX_CTRL]
 
-	mov pc, lr
+#ifdef CONFIG_NAND_IMX_BOOT
+	ldr	sp, =TEXT_BASE - 4	/* Setup a temporary stack in SDRAM */
+
+	ldr	r0, =IMX_NFC_BASE		/* start of NFC SRAM                */
+	ldr	r2, =IMX_NFC_BASE + 0x800	/* end of NFC SRAM                  */
+
+	/* skip NAND boot if not running from NFC space */
+	cmp	pc, r0
+	blo	ret
+	cmp	pc, r2
+	bhs	ret
+
+	/* Move ourselves out of NFC SRAM */
+	ldr	r1, =TEXT_BASE
+
+copy_loop:
+	ldmia	r0!, {r3-r9}		/* copy from source address [r0]    */
+	stmia	r1!, {r3-r9}		/* copy to   target address [r1]    */
+	cmp	r0, r2			/* until source end addreee [r2]    */
+	ble	copy_loop
+
+	ldr	pc, =1f			/* Jump to SDRAM                    */
+1:
+	bl	nand_boot		/* Load U-Boot from NAND Flash      */
+
+	/* rebase the return address */
+	ldr	r1, =IMX_NFC_BASE - TEXT_BASE
+	sub	r10, r10, r1		/* adjust return address from NFC SRAM */
+ret:
+#endif /* CONFIG_NAND_IMX_BOOT */
+
+	mov pc, r10
 
diff --git a/board/pcm043/pcm043.c b/board/pcm043/pcm043.c
index e977e8d7da..889093a9cd 100644
--- a/board/pcm043/pcm043.c
+++ b/board/pcm043/pcm043.c
@@ -1,5 +1,6 @@
 /*
  * (C) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ * (C) 2009 Pengutronix, Juergen Beisert <kernel@pengutronix.de>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -27,16 +28,18 @@
 #include <init.h>
 #include <driver.h>
 #include <environment.h>
+#include <fs.h>
 #include <asm/arch/imx-regs.h>
+#include <asm/arch/imx-pll.h>
+#include <asm/arch/iomux-mx35.h>
 #include <asm/armlinux.h>
 #include <asm/arch/gpio.h>
 #include <asm/io.h>
 #include <partition.h>
+#include <nand.h>
 #include <asm/mach-types.h>
-#include <asm/arch/imx-nand.h>
 #include <fec.h>
-#include <asm/arch/imx-pll.h>
-#include <asm/arch/iomux-mx35.h>
+#include <asm/arch/imx-nand.h>
 
 #define CYG_MACRO_START
 #define CYG_MACRO_END
@@ -79,6 +82,7 @@ static struct device_d sdram0_dev = {
 struct imx_nand_platform_data nand_info = {
 	.width	= 1,
 	.hw_ecc	= 1,
+	.flash_bbt = 1,
 };
 
 static struct device_d nand_dev = {
@@ -89,25 +93,43 @@ static struct device_d nand_dev = {
 
 static int imx35_devices_init(void)
 {
+	uint32_t reg;
+
 	/* CS0: Nor Flash */
 	writel(0x0000cf03, CSCR_U(0));
 	writel(0x10000d03, CSCR_L(0));
 	writel(0x00720900, CSCR_A(0));
 
-	register_device(&cfi_dev);
+	reg = readl(IMX_CCM_BASE + CCM_RCSR);
+	/* some fuses provide us vital information about connected hardware */
+	if (reg & 0x20000000)
+		nand_info.width = 2;    /* 16 bit */
+	else
+		nand_info.width = 1;    /* 8 bit */
 
+	register_device(&fec_dev);
 	/*
-	 * Create partitions that should be
-	 * not touched by any regular user
+	 * This platform supports NOR and NAND
 	 */
-	devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0");	/* ourself */
-	devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0");	/* environment */
-
-	protect_file("/dev/env0", 1);
-
 	register_device(&nand_dev);
+	register_device(&cfi_dev);
 
-	register_device(&fec_dev);
+	if ((reg & 0xc00) == 0x800) {   /* reset mode: external boot */
+		switch ( (reg >> 25) & 0x3) {
+		case 0x01:              /* NAND is the source */
+			devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
+			dev_add_bb_dev("self_raw", "self0");
+			devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
+			dev_add_bb_dev("env_raw", "env0");
+			break;
+
+		case 0x00:              /* NOR is the source */
+			devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0"); /* ourself */
+			devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0");  /* environment */
+			protect_file("/dev/env0", 1);
+			break;
+		}
+	}
 
 	register_device(&sdram0_dev);
 
@@ -288,3 +310,13 @@ U_BOOT_CMD_START(cpufreq)
 	U_BOOT_CMD_HELP(cmd_cpufreq_help)
 U_BOOT_CMD_END
 
+#ifdef CONFIG_NAND_IMX_BOOT
+void __bare_init nand_boot(void)
+{
+	/*
+	 * The driver is able to detect NAND's pagesize by CPU internal
+	 * fuses or external pull ups. But not the blocksize...
+	 */
+	imx_nand_load_image((void *)TEXT_BASE, 256 * 1024);
+}
+#endif
diff --git a/board/pcm043/pcm043.dox b/board/pcm043/pcm043.dox
index 263d1d2621..c6715fffcf 100644
--- a/board/pcm043/pcm043.dox
+++ b/board/pcm043/pcm043.dox
@@ -4,9 +4,24 @@ This CPU card is based on a Freescale i.MX35 CPU. The card is shipped with:
 
 
 FIXME:
-- up to 64MiB NOR type Flash Memory
-- up to 2MiB static RAM
-- 64MiB NAND type Flash Memory
+- up to 64 MiB NOR type Flash Memory
+- up to 2 MiB static RAM
+- 1 GiB or 2 GiB NAND type Flash Memory
+  - Micron NAND 1 GiB 3,3V 8-bit
+    - 256 kiB block size
+    - ? kiB page size
+    - Manufacturer ID: 0x2c
+    - Device ID: 0xd3
+  - Samsung K9K8G08, 1 GiB
+    - 128 kiB block size
+    - 2 kiB page size
+    - Manufacturer ID: ?
+    - Device ID: ?
+  - ST NAND08G, 1 GiB
+    - 128 kiB block size
+    - 2 kiB page size
+    - Manufacturer ID: ?
+    - Device ID: ?
 - 128MiB synchronous dynamic RAM