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| author | Eric Benard <eric@eukrea.com> | 2009-10-22 16:46:12 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2009-12-03 10:46:09 +0100 |
| commit | bf33c6976424dbaed6a92407e397e77080a8d0c4 (patch) | |
| tree | d877cdb24206256d8e3474e6b039b503e101e32d | |
| parent | ce96b9c05e918d6eea5933c53f4ad975b4d25176 (diff) | |
| download | barebox-bf33c6976424dbaed6a92407e397e77080a8d0c4.tar.gz barebox-bf33c6976424dbaed6a92407e397e77080a8d0c4.tar.xz | |
Eukrea CPUIMX27 : add SDRAM size choice
Add a menu entry and proper settings for 128MB and 256MB
RAM size.
Signed-off-by: Eric Benard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| -rw-r--r-- | arch/arm/mach-imx/Kconfig | 9 | ||||
| -rw-r--r-- | board/eukrea_cpuimx27/eukrea_cpuimx27.c | 8 | ||||
| -rw-r--r-- | board/eukrea_cpuimx27/lowlevel_init.S | 17 |
3 files changed, 30 insertions, 4 deletions
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 6585c878bf..a9e649e623 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -249,6 +249,15 @@ config PCM037_SDRAM_BANK1_256MB endchoice endif +if MACH_EUKREA_CPUIMX27 +choice + prompt "SDRAM Size" +config EUKREA_CPUIMX27_SDRAM_128MB + bool "128 MB" +config EUKREA_CPUIMX27_SDRAM_256MB + bool "256 MB" +endchoice +endif endmenu menu "i.MX specific settings " diff --git a/board/eukrea_cpuimx27/eukrea_cpuimx27.c b/board/eukrea_cpuimx27/eukrea_cpuimx27.c index 6ffc40b394..148a4fbe97 100644 --- a/board/eukrea_cpuimx27/eukrea_cpuimx27.c +++ b/board/eukrea_cpuimx27/eukrea_cpuimx27.c @@ -52,10 +52,16 @@ static struct memory_platform_data ram_pdata = { .flags = DEVFS_RDWR, }; +#if defined CONFIG_EUKREA_CPUIMX27_SDRAM_256MB +#define SDRAM0 256 +#elif defined CONFIG_EUKREA_CPUIMX27_SDRAM_128MB +#define SDRAM0 128 +#endif + static struct device_d sdram_dev = { .name = "mem", .map_base = 0xa0000000, - .size = 128 * 1024 * 1024, + .size = SDRAM0 * 1024 * 1024, .platform_data = &ram_pdata, }; diff --git a/board/eukrea_cpuimx27/lowlevel_init.S b/board/eukrea_cpuimx27/lowlevel_init.S index c7ac3410cc..5cab984e34 100644 --- a/board/eukrea_cpuimx27/lowlevel_init.S +++ b/board/eukrea_cpuimx27/lowlevel_init.S @@ -6,14 +6,21 @@ ldr r1, =val; \ str r1, [r0]; +#if defined CONFIG_EUKREA_CPUIMX27_SDRAM_256MB +#define ROWS0 ESDCTL_ROW14 +#define CFG0 0x00695729 +#elif defined CONFIG_EUKREA_CPUIMX27_SDRAM_128MB +#define ROWS0 ESDCTL_ROW13 +#define CFG0 0x00395B28 +#endif -#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10) +#define ESDCTL0_VAL (ESDCTL0_SDE | ROWS0 | ESDCTL0_COL10) .macro sdram_init /* * DDR on CSD0 */ - writel(0x00000008, ESDMISC) /* Enable DDR SDRAM operation */ + writel(0x0000000C, ESDMISC) /* Enable DDR SDRAM operation */ writel(0x55555555, DSCR(3)) /* Set the driving strength */ writel(0x55555555, DSCR(5)) @@ -22,7 +29,7 @@ writel(0x15555555, DSCR(8)) writel(0x00000004, ESDMISC) /* Initial reset */ - writel(0x0039572A, ESDCFG0) + writel(CFG0, ESDCFG0) writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, ESDCTL0) /* precharge CSD0 all banks */ writel(0x00000000, 0xA0000F00) /* CSD0 precharge address (A10 = 1) */ @@ -40,7 +47,11 @@ ldr r0, =0xA0000033 mov r1, #0xda strb r1, [r0] +#if defined CONFIG_EUKREA_CPUIMX27_SDRAM_256MB + ldr r0, =0xA2000000 +#elif defined CONFIG_EUKREA_CPUIMX27_SDRAM_128MB ldr r0, =0xA1000000 +#endif mov r1, #0xff strb r1, [r0] writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, ESDCTL0) |