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| author | Marc Kleine-Budde <mkl@pengutronix.de> | 2009-12-07 12:40:11 +0100 |
|---|---|---|
| committer | Marc Kleine-Budde <mkl@pengutronix.de> | 2009-12-10 14:32:50 +0100 |
| commit | b8d58b14a27b126433d89135f174c9e25c78da43 (patch) | |
| tree | 308c332f1d89a63c18ec220112b9efae1f9bcc54 | |
| parent | 26950ce364ac3bff7ead6d49adfca7723518af50 (diff) | |
| download | barebox-b8d58b14a27b126433d89135f174c9e25c78da43.tar.gz barebox-b8d58b14a27b126433d89135f174c9e25c78da43.tar.xz | |
start-arm: disable I-cache
<HACK>
For some yet unknown reason the processor on the i.MX35 3stack board (at
least on our board) has problem with an activated instruction cache and
booting from NAND: The copy-from-NFC-RAM-to-SDRAM routine doesn't loop.
It looks basically like this:
1:
ldmia
stmia
cmp
ble 1b
If the "cmp" instruction lives on address 0xbb000640 it doesn't work
with an activated i-cache. The processor flags are not properly updated.
So the ble won't jump back. This obviously break booting from nand.
This is why this patch disables the i-cache.
</HACK>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
| -rw-r--r-- | arch/arm/cpu/start-arm.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/start-arm.S b/arch/arm/cpu/start-arm.S index 8ad03e410a..d683c24083 100644 --- a/arch/arm/cpu/start-arm.S +++ b/arch/arm/cpu/start-arm.S @@ -198,7 +198,7 @@ finished_inval: bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ - orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ + bic r0, r0, #0x00001000 /* clear bit 12 (I) I-Cache */ mcr p15, 0, r0, c1, c0, 0 /* |