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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2008-08-13 08:31:34 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2008-08-13 16:52:14 +0200 |
| commit | c5934b3a8b3e3cdacce254d9847567013e0a644d (patch) | |
| tree | 77e828b00b16385c173e1ade6e4d2c95c63d7d1a | |
| parent | ccd76741c4714e60711e0a84f0c25c768fdc2f19 (diff) | |
| download | barebox-c5934b3a8b3e3cdacce254d9847567013e0a644d.tar.gz barebox-c5934b3a8b3e3cdacce254d9847567013e0a644d.tar.xz | |
imx27: Add BOOT bitfield definitions
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| -rw-r--r-- | include/asm-arm/arch-imx/imx27-regs.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/include/asm-arm/arch-imx/imx27-regs.h b/include/asm-arm/arch-imx/imx27-regs.h index 2a47572107..1ebf5d3f2a 100644 --- a/include/asm-arm/arch-imx/imx27-regs.h +++ b/include/asm-arm/arch-imx/imx27-regs.h @@ -43,6 +43,15 @@ #define WBCR __REG(IMX_SYSTEM_CTL_BASE + 0x1C) /* Well Bias Control Register */ #define DSCR(x) __REG(IMX_SYSTEM_CTL_BASE + 0x1C + ((x) << 2)) /* Driving Strength Control Register 1 - 13 */ +#define GPCR_BOOT_SHIFT 16 +#define GPCR_BOOT_MASK (0xf << GPCR_BOOT_SHIFT) +#define GPCR_BOOT_UART_USB 0 +#define GPCR_BOOT_8BIT_NAND_2k 2 +#define GPCR_BOOT_16BIT_NAND_2k 3 +#define GPCR_BOOT_16BIT_NAND_512 4 +#define GPCR_BOOT_16BIT_CS0 5 +#define GPCR_BOOT_32BIT_CS0 6 +#define GPCR_BOOT_8BIT_NAND_512 7 /* Chip Select Registers */ #define CS0U __REG(IMX_WEIM_BASE + 0x00) /* Chip Select 0 Upper Register */ |