imx: Add Phytec Phycore i.MX35 aka PCM043 support

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

14 files changed, 653 insertions, 2 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a6cbdd9f3a..48e6f5395d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -12,7 +12,8 @@ config ARCH_TEXT_BASE
 	default 0x87f00000 if MACH_PCM037
 	default 0x23f00000 if MACH_AT91SAM9260_EK
 	default 0x23f00000 if MACH_PM9263
-	default 0x80000000 if MACH_FREESCALE_MX35_3STACK
+	default 0x87f00000 if MACH_FREESCALE_MX35_3STACK
+	default 0x87f00000 if MACH_PCM043
 
 config BOARDINFO
 	default "Synertronixx scb9328" if MACH_SCB9328
@@ -23,6 +24,7 @@ config BOARDINFO
 	default "Atmel 91SAM9260-EK" if MACH_AT91SAM9260_EK
 	default "Ronetix PM9263" if MACH_PM9263
 	default "Freescale MX35 3Stack" if MACH_FREESCALE_MX35_3STACK
+	default "Phytec phyCORE-i.MX35" if MACH_PCM043
 
 config BOARD_LINKER_SCRIPT
 	bool
@@ -50,7 +52,7 @@ config ARM926EJS
 config ARMCORTEXA8
 	bool
 
-# i.MX1, i.MXL, i.MX27 and i.MX31 are quite similar and thus
+# i.MX1, i.MXL, i.MX27, i.MX31  and i.MX35 are quite similar and thus
 # handled in one arch
 config ARCH_IMX
 	bool
@@ -134,6 +136,15 @@ config MACH_IMX27ADS
 	  Say Y here if you are using the Freescale i.MX27ads board equipped
 	  with a Freescale i.MX27 Processor
 
+config MACH_PCM043
+        bool "phyCORE-i.MX35"
+        select HAS_CFI
+        select ARCH_IMX35
+        select MACH_HAS_LOWLEVEL_INIT
+        help
+          Say Y here if you are using Phytec's phyCORE-i.MX35 (pcm043) equipped
+          with a Freescale i.MX35 Processor
+
 config MACH_FREESCALE_MX35_3STACK
 	bool "Freescale MX35 3stack"
 	select HAS_CFI
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 690558aa72..5f85a3f142 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -18,6 +18,7 @@ board-$(CONFIG_MACH_OMAP)	   := omap
 board-$(CONFIG_MACH_AT91SAM9260_EK):= at91sam9260ek
 board-$(CONFIG_MACH_PM9263)        := pm9263
 board-$(CONFIG_MACH_FREESCALE_MX35_3STACK) := freescale-mx35-3-stack
+board-$(CONFIG_MACH_PCM043)        := pcm043
 
 # FIXME "cpu-y" never used on ARM!
 cpu-$(CONFIG_ARM920T)              := arm920t
diff --git a/board/pcm043/Makefile b/board/pcm043/Makefile
new file mode 100644
index 0000000000..62c0ba5b24
--- /dev/null
+++ b/board/pcm043/Makefile
@@ -0,0 +1,24 @@
+#
+# (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+obj-y += lowlevel_init.o
+obj-y += pcm043.o
diff --git a/board/pcm043/config.h b/board/pcm043/config.h
new file mode 100644
index 0000000000..0e3b175a62
--- /dev/null
+++ b/board/pcm043/config.h
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Definitions related to passing arguments to kernel.
+ */
+
+#define CONFIG_MX35_HCLK_FREQ	24000000
+
+#endif
+
+/* nothing to do here yet */
diff --git a/board/pcm043/env/bin/_update b/board/pcm043/env/bin/_update
new file mode 100644
index 0000000000..fb7cbe8619
--- /dev/null
+++ b/board/pcm043/env/bin/_update
@@ -0,0 +1,36 @@
+#!/bin/sh
+
+if [ -z "$part" -o -z "$image" ]; then
+	echo "define \$part and \$image"
+	exit 1
+fi
+
+if [ \! -e "$part" ]; then
+	echo "Partition $part does not exist"
+	exit 1
+fi
+
+if [ $# = 1 ]; then
+	image=$1
+fi
+
+if [ x$ip = xdhcp ]; then
+	dhcp
+fi
+
+ping $eth0.serverip
+if [ $? -ne 0 ] ; then
+	echo "update aborted"
+	exit 1
+fi
+
+unprotect $part
+
+echo
+echo "erasing partition $part"
+erase $part
+
+echo
+echo "flashing $image to $part"
+echo
+tftp $image $part
diff --git a/board/pcm043/env/bin/boot b/board/pcm043/env/bin/boot
new file mode 100644
index 0000000000..7bbff2d1f6
--- /dev/null
+++ b/board/pcm043/env/bin/boot
@@ -0,0 +1,47 @@
+#!/bin/sh
+
+. /env/config
+
+if [ x$1 = xnand ]; then
+	root=nand
+	kernel=nand
+fi
+
+if [ x$1 = xnet ]; then
+	root=net
+	kernel=net
+fi
+
+if [ x$1 = xnor ]; then
+	root=nor
+	kernel=nor
+fi
+
+if [ x$ip = xdhcp ]; then
+	bootargs="$bootargs ip=dhcp"
+else
+	bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::"
+fi
+
+if [ x$root = xnand ]; then
+	bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2"
+elif [ x$root = xnor ]; then
+	bootargs="$bootargs root=$rootpart_nor rootfstype=jffs2"
+else
+	bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp"
+fi
+
+bootargs="$bootargs mtdparts=physmap-flash.0:$nor_parts;mxc_nand:$nand_parts"
+
+if [ $kernel = net ]; then
+	if [ x$ip = xdhcp ]; then
+		dhcp
+	fi
+	tftp $uimage uImage || exit 1
+	bootm uImage
+elif [ $kernel = nor ]; then
+	bootm /dev/nor0.kernel
+else
+	bootm /dev/nand0.kernel.bb
+fi
+
diff --git a/board/pcm043/env/bin/hush_hack b/board/pcm043/env/bin/hush_hack
new file mode 100644
index 0000000000..5fffa92ecd
--- /dev/null
+++ b/board/pcm043/env/bin/hush_hack
@@ -0,0 +1 @@
+nand -a /dev/nand0.*
diff --git a/board/pcm043/env/bin/init b/board/pcm043/env/bin/init
new file mode 100644
index 0000000000..3bfd194913
--- /dev/null
+++ b/board/pcm043/env/bin/init
@@ -0,0 +1,37 @@
+#!/bin/sh
+
+PATH=/env/bin
+export PATH
+
+. /env/config
+if [ -e /dev/nor0 ]; then
+	addpart /dev/nor0 $nor_parts
+fi
+
+if [ -e /dev/nand0 ]; then
+	addpart /dev/nand0 $nand_parts
+
+	# Uh, oh, hush first expands wildcards and then starts executing
+	# commands. What a bug!
+	source /env/bin/hush_hack 
+fi
+
+if [ -z $eth0.ethaddr ]; then
+	while [ -z $eth0.ethaddr ]; do
+		readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr
+	done
+	echo -a /env/config "eth0.ethaddr=$eth0.ethaddr"
+fi
+
+echo
+echo -n "Hit any key to stop autoboot: "
+timeout -a $autoboot_timeout
+if [ $? != 0 ]; then
+	echo
+	echo "type update_kernel nand|nor [<imagename>] to update kernel into flash"
+	echo "type update_root nand|nor [<imagename>] to update rootfs into flash"
+	echo
+	exit
+fi
+
+boot
diff --git a/board/pcm043/env/bin/update_kernel b/board/pcm043/env/bin/update_kernel
new file mode 100644
index 0000000000..05c822d860
--- /dev/null
+++ b/board/pcm043/env/bin/update_kernel
@@ -0,0 +1,15 @@
+#!/bin/sh
+
+. /env/config
+
+image=$uimage
+if [ x$1 = xnand ]; then
+	part=/dev/nand0.kernel.bb
+elif [ x$1 = xnor ]; then
+	part=/dev/nor0.kernel
+else
+	echo "usage: $0 nor|nand [imagename]"
+	exit 1
+fi
+
+. /env/bin/_update $2
diff --git a/board/pcm043/env/bin/update_root b/board/pcm043/env/bin/update_root
new file mode 100644
index 0000000000..eaf36ebcea
--- /dev/null
+++ b/board/pcm043/env/bin/update_root
@@ -0,0 +1,16 @@
+#!/bin/sh
+
+. /env/config
+
+image=$uimage
+if [ x$1 = xnand ]; then
+	part=/dev/nand0.root.bb
+elif [ x$1 = xnor ]; then
+	part=/dev/nor0.root
+else
+	echo "usage: $0 nor|nand [imagename]"
+	exit 1
+fi
+
+. /env/bin/_update $2
+
diff --git a/board/pcm043/env/config b/board/pcm043/env/config
new file mode 100644
index 0000000000..42f6a400c8
--- /dev/null
+++ b/board/pcm043/env/config
@@ -0,0 +1,29 @@
+#!/bin/sh
+
+# can be either 'net', 'nor' or 'nand''
+kernel=net
+root=net
+
+uimage=uImage-pcm043
+jffs2=root-pcm043.jffs2
+
+autoboot_timeout=3
+
+nfsroot="/ptx/work/octopus/rsc/svn/oselas/bsp/phytec/phyCORE-i.MX27/OSELAS.BSP-Phytec-phyCORE-i.MX27-trunk/root"
+bootargs="console=ttymxc0,115200"
+
+nor_parts="256k(uboot)ro,128k(ubootenv),2048k(kernel),-(root)"
+rootpart_nor="/dev/mtdblock3"
+
+nand_parts="256k(uboot)ro,128k(ubootenv),2048k(kernel),-(root)"
+rootpart_nand="/dev/mtdblock7"
+
+# use 'dhcp' to do dhcp in uboot and in kernel
+#ip=dhcp
+
+# or set your networking parameters here
+eth0.ipaddr=192.168.3.11
+eth0.netmask=255.255.255.0
+#eth0.gateway=a.b.c.d
+eth0.serverip=192.168.3.10
+eth0.ethaddr=00:50:c2:8c:e6:0e
diff --git a/board/pcm043/lowlevel_init.S b/board/pcm043/lowlevel_init.S
new file mode 100644
index 0000000000..e8bcd23de2
--- /dev/null
+++ b/board/pcm043/lowlevel_init.S
@@ -0,0 +1,233 @@
+/*
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/imx-pll.h>
+#include <asm/arch/esdctl.h>
+#include <asm/cache-l2x0.h>
+
+#define writel(val, reg) \
+	ldr		r0,	=reg;	\
+	ldr		r1,	=val;	\
+	str		r1,	[r0];
+
+#define writeb(val, reg) \
+	ldr		r0,	=reg;	\
+	ldr		r1,	=val;	\
+	strb		r1,	[r0];
+
+/* Assuming 24MHz input clock */
+#define MPCTL_PARAM_399     (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5))
+#define MPCTL_PARAM_532     (IMX_PLL_PD(1) | IMX_PLL_MFD(0) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1))
+#define PPCTL_PARAM_300     (IMX_PLL_PD(0) | IMX_PLL_MFD(3) | IMX_PLL_MFI(6) | IMX_PLL_MFN(1))
+
+ARM_PPMRR:              .word   0x40000015
+L2CACHE_PARAM:          .word   0x00030024
+CCM_CCMR_W:             .word   0x003F4208
+CCM_PDR0_W:             .word   0x00801000
+MPCTL_PARAM_399_W:      .word   MPCTL_PARAM_399
+MPCTL_PARAM_532_W:      .word   MPCTL_PARAM_532
+PPCTL_PARAM_W:    	.word   PPCTL_PARAM_300
+CCM_BASE_ADDR_W:        .word   IMX_CCM_BASE
+
+.globl board_init_lowlevel
+board_init_lowlevel:
+	mov     r10, lr
+
+	mrc 15, 0, r1, c1, c0, 0
+//	bic r1, r1, #(0x3<<21)
+	bic r1, r1, #(0x3<<11)
+//	bic r1, r1, #0x5
+
+//	bic r1, r1, #(1<<3)
+
+	mrc 15, 0, r0, c1, c0, 1
+	orr r0, r0, #7
+	mcr 15, 0, r0, c1, c0, 1
+
+	orr r1, r1, #(1<<11) /* Flow prediction (Z) */
+	orr r1, r1, #(1<<22) /* unaligned accesses  */
+	orr r1, r1, #(1<<21)
+
+	mcr 15, 0, r1, c1, c0, 0
+
+	mov r0, #0
+	mcr 15, 0, r0, c15, c2, 4
+
+	mov r0, #0
+	mcr 15, 0, r0, c7, c7, 0        /* invalidate I cache and D cache */
+	mcr 15, 0, r0, c8, c7, 0        /* invalidate TLBs */
+	mcr 15, 0, r0, c7, c10, 4       /* Drain the write buffer */
+
+	/* Also setup the Peripheral Port Remap register inside the core */
+	ldr r0, ARM_PPMRR        /* start from AIPS 2GB region */
+	mcr p15, 0, r0, c15, c2, 4
+
+	/* L2 Cache setup / invalidation / disable
+	 */
+#ifdef L2_INVAL
+	/* Disable L2 cache first */
+	mov r0, #IMX_L2CC_BASE
+	ldr r2, [r0, #L2X0_CTRL]
+	bic r2, r2, #0x1
+	str r2, [r0, #L2X0_CTRL]
+	/*
+	 * Configure L2 Cache:
+	 * - 128k size(16k way)
+	 * - 8-way associativity
+	 * - 0 ws TAG/VALID/DIRTY
+	 * - 4 ws DATA R/W
+	 */
+	ldr r1, [r0, #L2X0_AUX_CTRL]
+	and r1, r1, #0xFE000000
+	ldr r2, L2CACHE_PARAM
+	orr r1, r1, r2
+	str r1, [r0, #L2X0_AUX_CTRL]
+
+	/* Workaround for DDR issue:WT*/
+	ldr r1, [r0, #L2X0_DEBUG_CTRL]
+	orr r1, r1, #2
+	str r1, [r0, #L2X0_DEBUG_CTRL]
+
+	/* Invalidate L2 */
+	mov r1, #0x000000FF
+	str r1, [r0, #L2X0_CLEAN_INV_WAY]
+L2_loop:
+	/* Poll Invalidate By Way register */
+	ldr r2, [r0, #L2X0_CLEAN_INV_WAY]
+	cmp r2, #0
+	bne L2_loop
+#endif
+/*
+ * End of ARM1136 init
+ */
+	ldr r0, CCM_BASE_ADDR_W
+
+	/* default CLKO to 1/32 of the ARM core*/
+	ldr r1, [r0, #CCM_COSR]
+	bic r1, r1, #0x00000FF00
+	bic r1, r1, #0x0000000FF
+	mov r2, #0x00006C00
+	add r2, r2, #0x67
+	orr r1, r1, r2
+	str r1, [r0, #CCM_COSR]
+
+	ldr r2, CCM_CCMR_W
+	str r2, [r0, #CCM_CCMR]
+
+	/* check clock path */
+	ldr r2, [r0, #CCM_PDR0]
+	tst r2, #0x1
+	ldrne r3, MPCTL_PARAM_532_W  /* consumer path*/
+	ldreq r3, MPCTL_PARAM_399_W  /* auto path*/
+
+	/*Set MPLL , arm clock and ahb clock*/
+	str r3, [r0, #CCM_MPCTL]
+
+	ldr r1, PPCTL_PARAM_W
+	str r1, [r0, #CCM_PPCTL]
+
+	ldr r1, [r0, #CCM_PDR0]
+	orr r1, r1, #0x800000
+	str r1, [r0, #CCM_PDR0]
+
+	ldr r1, CCM_PDR0_W
+	str r1, [r0, #CCM_PDR0]
+
+	ldr r1, [r0, #CCM_CGR0]
+	orr r1, r1, #0x00300000
+	str r1, [r0, #CCM_CGR0]
+
+	ldr r1, [r0, #CCM_CGR1]
+	orr r1, r1, #0x00000C00
+	orr r1, r1, #0x00000003
+	str r1, [r0, #CCM_CGR1]
+
+	/* Skip SDRAM initialization if we run from RAM */
+	cmp	pc, #0x80000000
+	bls	1f
+	cmp	pc, #0x90000000
+	bhi	1f
+
+	mov	pc, lr
+
+1:
+	/* MDDR init, enable mDDR*/
+	writel(0x00000304, ESDMISC) /* was 0x00000004 */
+
+	/* set timing paramters */
+	writel(0x007ffc2f, ESDCFG0) /* was 0x007ffc3f */
+	/* select Prechare-All mode */
+	writel(0x92220000, ESDCTL0)
+	/* Prechare-All */
+	writel(0x12345678, IMX_SDRAM_CS0 + 0x400)
+
+	/* select Load-Mode-Register mode */
+	writel(0xB8001000, ESDCTL0)
+	/* Load reg EMR2 */
+	writeb(0xda, 0x84000000)
+	/* Load reg EMR3 */
+	writeb(0xda, 0x86000000)
+	/* Load reg EMR1 -- enable DLL */
+	writeb(0xda, 0x82000400)
+	/* Load reg MR -- reset DLL */
+	writeb(0xda, 0x80000333)
+
+	/* select Prechare-All mode */
+	writel(0x92220000, ESDCTL0)
+	/* Prechare-All */
+	writel(0x12345678, IMX_SDRAM_CS0 + 0x400)
+
+	/* select Manual-Refresh mode */
+	writel(0xA2220000, ESDCTL0)
+	/* Manual-Refresh 2 times */
+	writel(0x87654321, IMX_SDRAM_CS0)
+	writel(0x87654321, IMX_SDRAM_CS0)
+
+	/* select Load-Mode-Register mode */
+	writel(0xB2220000, ESDCTL0)
+	/* Load reg MR -- CL3, BL8, end DLL reset */
+	writeb(0xda, 0x80000233)
+	/* Load reg EMR1 -- OCD default */
+	writeb(0xda, 0x82000780)
+	/* Load reg EMR1 -- OCD exit */
+	writeb(0xda, 0x82000400)
+
+	/* select normal-operation mode
+	 * DSIZ32-bit, BL8, COL10-bit, ROW13-bit
+	 * disable PWT & PRCT
+	 * disable Auto-Refresh */
+	writel(0x82220080, ESDCTL0)
+
+	/* enable Auto-Refresh */
+	writel(0x82228080, ESDCTL0)
+	/* enable Auto-Refresh */
+	writel(0x00002000, ESDCTL1)
+
+	mov r0, #IMX_L2CC_BASE
+	ldr r1, [r0, #L2X0_AUX_CTRL]
+	orr r1, r1, #0x1000
+	str r1, [r0, #L2X0_AUX_CTRL]
+
+	mov pc, lr
+
diff --git a/board/pcm043/pcm043.c b/board/pcm043/pcm043.c
new file mode 100644
index 0000000000..60e8480e02
--- /dev/null
+++ b/board/pcm043/pcm043.c
@@ -0,0 +1,157 @@
+/*
+ * (C) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Board support for Phytec's, i.MX35 based CPU card, called: PCM043
+ */
+
+#include <common.h>
+#include <init.h>
+#include <driver.h>
+#include <environment.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/armlinux.h>
+#include <asm/arch/gpio.h>
+#include <asm/io.h>
+#include <partition.h>
+#include <asm/mach-types.h>
+#include <asm/arch/imx-nand.h>
+#include <fec.h>
+
+/*
+ * Up to 32MiB NOR type flash, connected to
+ * CS line 0, data width is 16 bit
+ */
+static struct device_d cfi_dev = {
+	.name     = "cfi_flash",
+	.id       = "nor0",
+	.map_base = IMX_CS0_BASE,
+	.size     = 32 * 1024 * 1024,	/* area size */
+};
+
+static struct fec_platform_data fec_info = {
+	.xcv_type = MII100,
+};
+
+static struct device_d fec_dev = {
+	.name     = "fec_imx27",
+	.id       = "eth0",
+	.map_base = 0x50038000,
+	.platform_data	= &fec_info,
+	.type     = DEVICE_TYPE_ETHER,
+};
+
+static struct device_d sdram0_dev = {
+	.name     = "ram",
+	.id       = "ram0",
+
+	.map_base = IMX_SDRAM_CS0,
+	.size     = 128 * 1024 * 1024,
+
+	.type     = DEVICE_TYPE_DRAM,
+};
+
+struct imx_nand_platform_data nand_info = {
+	.width	= 1,
+	.hw_ecc	= 1,
+};
+
+static struct device_d nand_dev = {
+	.name     = "imx_nand",
+	.map_base = IMX_NAND_BASE,
+	.platform_data	= &nand_info,
+};
+
+static int imx35_devices_init(void)
+{
+	__REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash from pcm037*/
+	__REG(CSCR_L(0)) = 0x10000d03;
+	__REG(CSCR_A(0)) = 0x00720900;
+
+	/* setup pins for I2C1 (for EEPROM, RTC) */
+	imx_gpio_mode(MUX_I2C1_CLK_I2C1_SLC);
+	imx_gpio_mode(MUX_I2C1_DAT_I2C1_SDA);
+
+	register_device(&cfi_dev);
+
+	/*
+	 * Create partitions that should be
+	 * not touched by any regular user
+	 */
+#ifdef CONFIG_PARTITION
+	dev_add_partition(&cfi_dev, 0x00000, 0x40000, PARTITION_FIXED, "self");	/* ourself */
+	dev_add_partition(&cfi_dev, 0x40000, 0x20000, PARTITION_FIXED, "env");	/* environment */
+#endif
+	dev_protect(&cfi_dev, 0x20000, 0, 1);
+
+	register_device(&nand_dev);
+	
+	imx_gpio_mode(MUX_FEC_TX_CLK_FEC_TX_CLK);
+	imx_gpio_mode(MUX_FEC_RX_CLK_FEC_RX_CLK);
+	imx_gpio_mode(MUX_FEC_RX_DV_FEC_RX_DV);
+	imx_gpio_mode(MUX_FEC_COL_FEC_COL);
+	imx_gpio_mode(MUX_FEC_TX_EN_FEC_TX_EN);
+	imx_gpio_mode(MUX_FEC_MDC_FEC_MDC);
+	imx_gpio_mode(MUX_FEC_MDIO_FEC_MDIO);
+	imx_gpio_mode(MUX_FEC_TX_ERR_FEC_TX_ERR);
+	imx_gpio_mode(MUX_FEC_RX_ERR_FEC_RX_ERR);
+	imx_gpio_mode(MUX_FEC_CRS_FEC_CRS);
+	imx_gpio_mode(MUX_FEC_RDATA0_FEC_RDATA0);
+	imx_gpio_mode(MUX_FEC_TDATA0_FEC_TDATA0);
+	imx_gpio_mode(MUX_FEC_RDATA1_FEC_RDATA1);
+	imx_gpio_mode(MUX_FEC_TDATA1_FEC_TDATA1);
+	imx_gpio_mode(MUX_FEC_RDATA2_FEC_RDATA2);
+	imx_gpio_mode(MUX_FEC_TDATA2_FEC_TDATA2);
+	imx_gpio_mode(MUX_FEC_RDATA3_FEC_RDATA3);
+	imx_gpio_mode(MUX_FEC_TDATA3_FEC_TDATA3);
+
+	register_device(&fec_dev);
+
+	register_device(&sdram0_dev);
+	
+	armlinux_set_bootparams((void *)0x80000100);
+	armlinux_set_architecture(MACH_TYPE_PCM043);
+
+	return 0;
+}
+
+device_initcall(imx35_devices_init);
+
+static struct device_d imx35_serial_device = {
+	.name     = "imx_serial",
+	.id       = "cs0",
+	.map_base = IMX_UART1_BASE,
+	.size     = 16 * 1024,
+	.type     = DEVICE_TYPE_CONSOLE,
+};
+
+static int imx35_console_init(void)
+{
+	/* init gpios for serial port */
+	imx_gpio_mode(MUX_RXD1_UART1_RXD_MUX);
+	imx_gpio_mode(MUX_TXD1_UART1_TXD_MUX);
+	imx_gpio_mode(MUX_RTS1_UART1_RTS_B);
+	imx_gpio_mode(MUX_RTS1_UART1_CTS_B);
+
+	register_device(&imx35_serial_device);
+	return 0;
+}
+
+console_initcall(imx35_console_init);
diff --git a/board/pcm043/pcm043.dox b/board/pcm043/pcm043.dox
new file mode 100644
index 0000000000..263d1d2621
--- /dev/null
+++ b/board/pcm043/pcm043.dox
@@ -0,0 +1,13 @@
+/** @page pcm043 Phytec's phyCORE-i.MX35
+
+This CPU card is based on a Freescale i.MX35 CPU. The card is shipped with:
+
+
+FIXME:
+- up to 64MiB NOR type Flash Memory
+- up to 2MiB static RAM
+- 64MiB NAND type Flash Memory
+- 128MiB synchronous dynamic RAM
+
+
+*/