add Support for Freescale MX35 3Stack Board

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

14 files changed, 889 insertions, 0 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 87250c7bf0..a6cbdd9f3a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -12,6 +12,7 @@ config ARCH_TEXT_BASE
 	default 0x87f00000 if MACH_PCM037
 	default 0x23f00000 if MACH_AT91SAM9260_EK
 	default 0x23f00000 if MACH_PM9263
+	default 0x80000000 if MACH_FREESCALE_MX35_3STACK
 
 config BOARDINFO
 	default "Synertronixx scb9328" if MACH_SCB9328
@@ -21,6 +22,7 @@ config BOARDINFO
 	default "Phytec phyCORE-i.MX31" if MACH_PCM037
 	default "Atmel 91SAM9260-EK" if MACH_AT91SAM9260_EK
 	default "Ronetix PM9263" if MACH_PM9263
+	default "Freescale MX35 3Stack" if MACH_FREESCALE_MX35_3STACK
 
 config BOARD_LINKER_SCRIPT
 	bool
@@ -132,6 +134,15 @@ config MACH_IMX27ADS
 	  Say Y here if you are using the Freescale i.MX27ads board equipped
 	  with a Freescale i.MX27 Processor
 
+config MACH_FREESCALE_MX35_3STACK
+	bool "Freescale MX35 3stack"
+	select HAS_CFI
+	select ARCH_IMX35
+	select MACH_HAS_LOWLEVEL_INIT
+	help
+	  Say Y here if you are using the Freescale MX35 3stack board equipped
+	  with a Freescale i.MX35 Processor
+
 config MACH_ECO920
 	bool "eco920"
 	select HAS_AT91_ETHER
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 15011f4b55..690558aa72 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -17,6 +17,7 @@ board-$(CONFIG_MACH_PCM037)	   := pcm037
 board-$(CONFIG_MACH_OMAP)	   := omap
 board-$(CONFIG_MACH_AT91SAM9260_EK):= at91sam9260ek
 board-$(CONFIG_MACH_PM9263)        := pm9263
+board-$(CONFIG_MACH_FREESCALE_MX35_3STACK) := freescale-mx35-3-stack
 
 # FIXME "cpu-y" never used on ARM!
 cpu-$(CONFIG_ARM920T)              := arm920t
diff --git a/board/freescale-mx35-3-stack/3stack.c b/board/freescale-mx35-3-stack/3stack.c
new file mode 100644
index 0000000000..5a3b102fcf
--- /dev/null
+++ b/board/freescale-mx35-3-stack/3stack.c
@@ -0,0 +1,217 @@
+/*
+ * Copyright (C) 2007 Sascha Hauer, Pengutronix 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <net.h>
+#include <cfi_flash.h>
+#include <init.h>
+#include <environment.h>
+#include <asm/arch/imx-regs.h>
+#include <fec.h>
+#include <asm/arch/gpio.h>
+#include <asm/armlinux.h>
+#include <asm/mach-types.h>
+#include <asm/arch/pmic.h>
+#include <partition.h>
+#include <fs.h>
+#include <fcntl.h>
+#include <nand.h>
+#include <spi/spi.h>
+#include <asm/io.h>
+#include <asm/arch/imx-nand.h>
+
+static struct device_d cfi_dev = {
+	.name     = "cfi_flash",
+	.id       = "nor0",
+
+	.map_base = 0xa0000000,
+	.size     = 64 * 1024 * 1024,
+};
+
+static struct device_d sdram_dev = {
+	.name     = "ram",
+	.id       = "ram0",
+
+	.map_base = 0x80000000,
+	.size     = 128 * 1024 * 1024,
+
+	.type     = DEVICE_TYPE_DRAM,
+};
+
+static struct fec_platform_data fec_info = {
+	.xcv_type = MII100,
+};
+
+static struct device_d fec_dev = {
+	.name     = "fec_imx27",
+	.id       = "eth0",
+	.map_base = 0x50038000,
+	.platform_data	= &fec_info,
+	.type     = DEVICE_TYPE_ETHER,
+};
+
+/*
+ * SMSC 9217 network controller
+ */
+static struct device_d smc911x_dev = {
+	.name     = "smc911x",
+	.id       = "eth0",
+	.map_base = IMX_CS5_BASE,
+	.size     = IMX_CS5_RANGE,	/* area size */
+	.type     = DEVICE_TYPE_ETHER,
+};
+
+static int f3s_devices_init(void)
+{
+	imx_gpio_mode(MUX_FEC_TX_CLK_FEC_TX_CLK);
+	imx_gpio_mode(MUX_FEC_RX_CLK_FEC_RX_CLK);
+	imx_gpio_mode(MUX_FEC_RX_DV_FEC_RX_DV);
+	imx_gpio_mode(MUX_FEC_COL_FEC_COL);
+	imx_gpio_mode(MUX_FEC_TX_EN_FEC_TX_EN);
+	imx_gpio_mode(MUX_FEC_MDC_FEC_MDC);
+	imx_gpio_mode(MUX_FEC_MDIO_FEC_MDIO);
+	imx_gpio_mode(MUX_FEC_TX_ERR_FEC_TX_ERR);
+	imx_gpio_mode(MUX_FEC_RX_ERR_FEC_RX_ERR);
+	imx_gpio_mode(MUX_FEC_CRS_FEC_CRS);
+	imx_gpio_mode(MUX_FEC_RDATA0_FEC_RDATA0);
+	imx_gpio_mode(MUX_FEC_TDATA0_FEC_TDATA0);
+	imx_gpio_mode(MUX_FEC_RDATA1_FEC_RDATA1);
+	imx_gpio_mode(MUX_FEC_TDATA1_FEC_TDATA1);
+	imx_gpio_mode(MUX_FEC_RDATA2_FEC_RDATA2);
+	imx_gpio_mode(MUX_FEC_TDATA2_FEC_TDATA2);
+	imx_gpio_mode(MUX_FEC_RDATA3_FEC_RDATA3);
+	imx_gpio_mode(MUX_FEC_TDATA3_FEC_TDATA3);
+
+	register_device(&cfi_dev);
+	register_device(&sdram_dev);
+	register_device(&smc911x_dev);
+	/* FEC is currently broken. It seems to work
+	 * shortly but after a few moments the board
+	 * goes to nirvana
+	 */
+//	register_device(&fec_dev);
+
+	/*
+	 * Create partitions that should be
+	 * not touched by any regular user
+	 */
+#ifdef CONFIG_PARTITION
+	dev_add_partition(&cfi_dev, 0x00000, 0x40000, PARTITION_FIXED, "self");	/* ourself */
+	dev_add_partition(&cfi_dev, 0x40000, 0x20000, PARTITION_FIXED, "env");	/* environment */
+#endif
+
+	armlinux_set_bootparams((void *)0x80000100);
+	armlinux_set_architecture(MACH_TYPE_PCM037); /* FIXME */
+
+	return 0;
+}
+
+device_initcall(f3s_devices_init);
+
+static struct device_d f3s_serial_device = {
+	.name     = "imx_serial",
+	.id       = "cs0",
+	.map_base = IMX_UART1_BASE,
+	.size     = 4096,
+	.type     = DEVICE_TYPE_CONSOLE,
+};
+
+static int f3s_console_init(void)
+{
+	register_device(&f3s_serial_device);
+	return 0;
+}
+
+console_initcall(f3s_console_init);
+
+static int f3s_core_setup(void)
+{
+	u32 tmp;
+
+	writel(0x0000D843, CSCR_U(5)); /* CS5: smc9117 */
+	writel(0x22252521, CSCR_L(5));
+	writel(0x22220A00, CSCR_A(5));
+
+	/* FIXME: The rest is currently done in Assembler. Remove assembler
+	 *        config once the board is running stable
+	 */
+	return 0;
+
+	/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
+	/*
+	 * Set all MPROTx to be non-bufferable, trusted for R/W,
+	 * not forced to user-mode.
+	 */
+	writel(0x77777777, IMX_AIPS1_BASE);
+	writel(0x77777777, IMX_AIPS1_BASE + 0x4);
+	writel(0x77777777, IMX_AIPS2_BASE);
+	writel(0x77777777, IMX_AIPS2_BASE + 0x4);
+
+	/*
+	 * Clear the on and off peripheral modules Supervisor Protect bit
+	 * for SDMA to access them. Did not change the AIPS control registers
+	 * (offset 0x20) access type
+	 */
+	writel(0x0, IMX_AIPS1_BASE + 0x40);
+	writel(0x0, IMX_AIPS1_BASE + 0x44);
+	writel(0x0, IMX_AIPS1_BASE + 0x48);
+	writel(0x0, IMX_AIPS1_BASE + 0x4C);
+	tmp = readl(IMX_AIPS1_BASE + 0x50);
+	tmp &= 0x00FFFFFF;
+	writel(tmp, IMX_AIPS1_BASE + 0x50);
+
+	writel(0x0, IMX_AIPS2_BASE + 0x40);
+	writel(0x0, IMX_AIPS2_BASE + 0x44);
+	writel(0x0, IMX_AIPS2_BASE + 0x48);
+	writel(0x0, IMX_AIPS2_BASE + 0x4C);
+	tmp = readl(IMX_AIPS2_BASE + 0x50);
+	tmp &= 0x00FFFFFF;
+	writel(tmp, IMX_AIPS2_BASE + 0x50);
+
+	/* MAX (Multi-Layer AHB Crossbar Switch) setup */
+
+	/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+#define MAX_PARAM1 0x00302154
+	writel(MAX_PARAM1, IMX_MAX_BASE + 0x0);   /* for S0 */
+	writel(MAX_PARAM1, IMX_MAX_BASE + 0x100); /* for S1 */
+	writel(MAX_PARAM1, IMX_MAX_BASE + 0x200); /* for S2 */
+	writel(MAX_PARAM1, IMX_MAX_BASE + 0x300); /* for S3 */
+	writel(MAX_PARAM1, IMX_MAX_BASE + 0x400); /* for S4 */
+
+	/* SGPCR - always park on last master */
+	writel(0x10, IMX_MAX_BASE + 0x10);	/* for S0 */
+	writel(0x10, IMX_MAX_BASE + 0x110);	/* for S1 */
+	writel(0x10, IMX_MAX_BASE + 0x210);	/* for S2 */
+	writel(0x10, IMX_MAX_BASE + 0x310);	/* for S3 */
+	writel(0x10, IMX_MAX_BASE + 0x410);	/* for S4 */
+
+	/* MGPCR - restore default values */
+	writel(0x0, IMX_MAX_BASE + 0x800);	/* for M0 */
+	writel(0x0, IMX_MAX_BASE + 0x900);	/* for M1 */
+	writel(0x0, IMX_MAX_BASE + 0xa00);	/* for M2 */
+	writel(0x0, IMX_MAX_BASE + 0xb00);	/* for M3 */
+	writel(0x0, IMX_MAX_BASE + 0xc00);	/* for M4 */
+	writel(0x0, IMX_MAX_BASE + 0xd00);	/* for M5 */
+
+	return 0;
+}
+
+core_initcall(f3s_core_setup);
+
diff --git a/board/freescale-mx35-3-stack/3stack.dox b/board/freescale-mx35-3-stack/3stack.dox
new file mode 100644
index 0000000000..73307219f6
--- /dev/null
+++ b/board/freescale-mx35-3-stack/3stack.dox
@@ -0,0 +1,4 @@
+/** @page 3stack Freescale MX35 3-Stack Board
+
+
+*/
diff --git a/board/freescale-mx35-3-stack/Makefile b/board/freescale-mx35-3-stack/Makefile
new file mode 100644
index 0000000000..1ad0ce984c
--- /dev/null
+++ b/board/freescale-mx35-3-stack/Makefile
@@ -0,0 +1,3 @@
+
+obj-y += lowlevel_init.o
+obj-y += 3stack.o
diff --git a/board/freescale-mx35-3-stack/config.h b/board/freescale-mx35-3-stack/config.h
new file mode 100644
index 0000000000..b3eed0bb3c
--- /dev/null
+++ b/board/freescale-mx35-3-stack/config.h
@@ -0,0 +1,24 @@
+/**
+ * @file
+ * @brief Global defintions for the ARM i.MX27 based pcm038
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#endif	/* __CONFIG_H */
diff --git a/board/freescale-mx35-3-stack/env/bin/_update b/board/freescale-mx35-3-stack/env/bin/_update
new file mode 100644
index 0000000000..fb7cbe8619
--- /dev/null
+++ b/board/freescale-mx35-3-stack/env/bin/_update
@@ -0,0 +1,36 @@
+#!/bin/sh
+
+if [ -z "$part" -o -z "$image" ]; then
+	echo "define \$part and \$image"
+	exit 1
+fi
+
+if [ \! -e "$part" ]; then
+	echo "Partition $part does not exist"
+	exit 1
+fi
+
+if [ $# = 1 ]; then
+	image=$1
+fi
+
+if [ x$ip = xdhcp ]; then
+	dhcp
+fi
+
+ping $eth0.serverip
+if [ $? -ne 0 ] ; then
+	echo "update aborted"
+	exit 1
+fi
+
+unprotect $part
+
+echo
+echo "erasing partition $part"
+erase $part
+
+echo
+echo "flashing $image to $part"
+echo
+tftp $image $part
diff --git a/board/freescale-mx35-3-stack/env/bin/boot b/board/freescale-mx35-3-stack/env/bin/boot
new file mode 100644
index 0000000000..dfb59aa692
--- /dev/null
+++ b/board/freescale-mx35-3-stack/env/bin/boot
@@ -0,0 +1,47 @@
+#!/bin/sh
+
+. /env/config
+
+if [ x$1 = xnand ]; then
+	root=nand
+	kernel=nand
+fi
+
+if [ x$1 = xnet ]; then
+	root=net
+	kernel=net
+fi
+
+if [ x$1 = xnor ]; then
+	root=nor
+	kernel=nor
+fi
+
+if [ x$ip = xdhcp ]; then
+	bootargs="$bootargs ip=dhcp"
+else
+	bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::"
+fi
+
+if [ x$root = xnand ]; then
+	bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2"
+elif [ x$root = xnor ]; then
+	bootargs="$bootargs root=$rootpart_nor rootfstype=jffs2"
+else
+	bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp"
+fi
+
+bootargs="$bootargs mtdparts=physmap-flash.0:$nor_parts;imx_nand:$nand_parts"
+
+if [ $kernel = net ]; then
+	if [ x$ip = xdhcp ]; then
+		dhcp
+	fi
+	tftp $uimage uImage || exit 1
+	bootm uImage
+elif [ $kernel = nor ]; then
+	bootm /dev/nor0.kernel
+else
+	bootm /dev/nand0.kernel.bb
+fi
+
diff --git a/board/freescale-mx35-3-stack/env/bin/hush_hack b/board/freescale-mx35-3-stack/env/bin/hush_hack
new file mode 100644
index 0000000000..5fffa92ecd
--- /dev/null
+++ b/board/freescale-mx35-3-stack/env/bin/hush_hack
@@ -0,0 +1 @@
+nand -a /dev/nand0.*
diff --git a/board/freescale-mx35-3-stack/env/bin/init b/board/freescale-mx35-3-stack/env/bin/init
new file mode 100644
index 0000000000..cdf0f6b8eb
--- /dev/null
+++ b/board/freescale-mx35-3-stack/env/bin/init
@@ -0,0 +1,37 @@
+#!/bin/sh
+
+PATH=/env/bin
+export PATH
+
+. /env/config
+if [ -e /dev/nor0 ]; then
+	addpart /dev/nor0 $nor_parts
+fi
+
+if [ -e /dev/nand0 ]; then
+	addpart /dev/nand0 $nand_parts
+
+	# Uh, oh, hush first expands wildcards and then starts executing
+	# commands. What a bug!
+	source /env/bin/hush_hack 
+fi
+
+#if [ -z $eth0.ethaddr ]; then
+#	while [ -z $eth0.ethaddr ]; do
+#		readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr
+#	done
+#	echo -a /env/config "eth0.ethaddr=$eth0.ethaddr"
+#fi
+
+echo
+echo -n "Hit any key to stop autoboot: "
+timeout -a $autoboot_timeout
+if [ $? != 0 ]; then
+	echo
+	echo "type update_kernel nand|nor [<imagename>] to update kernel into flash"
+	echo "type update_root nand|nor [<imagename>] to update rootfs into flash"
+	echo
+	exit
+fi
+
+boot
diff --git a/board/freescale-mx35-3-stack/env/bin/update_kernel b/board/freescale-mx35-3-stack/env/bin/update_kernel
new file mode 100644
index 0000000000..05c822d860
--- /dev/null
+++ b/board/freescale-mx35-3-stack/env/bin/update_kernel
@@ -0,0 +1,15 @@
+#!/bin/sh
+
+. /env/config
+
+image=$uimage
+if [ x$1 = xnand ]; then
+	part=/dev/nand0.kernel.bb
+elif [ x$1 = xnor ]; then
+	part=/dev/nor0.kernel
+else
+	echo "usage: $0 nor|nand [imagename]"
+	exit 1
+fi
+
+. /env/bin/_update $2
diff --git a/board/freescale-mx35-3-stack/env/bin/update_root b/board/freescale-mx35-3-stack/env/bin/update_root
new file mode 100644
index 0000000000..eaf36ebcea
--- /dev/null
+++ b/board/freescale-mx35-3-stack/env/bin/update_root
@@ -0,0 +1,16 @@
+#!/bin/sh
+
+. /env/config
+
+image=$uimage
+if [ x$1 = xnand ]; then
+	part=/dev/nand0.root.bb
+elif [ x$1 = xnor ]; then
+	part=/dev/nor0.root
+else
+	echo "usage: $0 nor|nand [imagename]"
+	exit 1
+fi
+
+. /env/bin/_update $2
+
diff --git a/board/freescale-mx35-3-stack/env/config b/board/freescale-mx35-3-stack/env/config
new file mode 100644
index 0000000000..d6afdfbeba
--- /dev/null
+++ b/board/freescale-mx35-3-stack/env/config
@@ -0,0 +1,28 @@
+#!/bin/sh
+
+# can be either 'net', 'nor' or 'nand''
+kernel=net
+root=net
+
+uimage=uImage-pcm038
+jffs2=root-pcm038.jffs2
+
+autoboot_timeout=3
+
+nfsroot="/ptx/work/octopus/rsc/svn/oselas/bsp/phytec/phyCORE-i.MX27/OSELAS.BSP-Phytec-phyCORE-i.MX27-trunk/root"
+bootargs="console=ttymxc0,115200"
+
+nor_parts="256k(uboot)ro,128k(ubootenv),1536k(kernel),-(root)"
+rootpart_nor="/dev/mtdblock3"
+
+nand_parts="256k(uboot)ro,128k(ubootenv),1536k(kernel),-(root)"
+rootpart_nand="/dev/mtdblock7"
+
+# use 'dhcp' to do dhcp in uboot and in kernel
+ip=dhcp
+
+# or set your networking parameters here
+#eth0.ipaddr=a.b.c.d
+#eth0.netmask=a.b.c.d
+#eth0.gateway=a.b.c.d
+#eth0.serverip=a.b.c.d
diff --git a/board/freescale-mx35-3-stack/lowlevel_init.S b/board/freescale-mx35-3-stack/lowlevel_init.S
new file mode 100644
index 0000000000..02b0326ca3
--- /dev/null
+++ b/board/freescale-mx35-3-stack/lowlevel_init.S
@@ -0,0 +1,449 @@
+/*
+ * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
+ * Applications Processor Reference Manual, Rev. 0.2".
+ *
+ */
+
+#include <config.h>
+#include <asm/arch/imx-regs.h>
+
+#define writel(val, reg) \
+	ldr		r0,	=reg;	\
+	ldr		r1,	=val;	\
+	str		r1,   [r0];
+#define IIM_BASE_ADDR           0x53FF0000
+#define SDRAM_BASE_ADDR             CSD0_BASE_ADDR
+#define CSD0_BASE_ADDR          0x80000000
+#define IIM_SREV_OFF            0x24
+#define AIPS1_CTRL_BASE_ADDR    AIPS1_BASE_ADDR
+#define AIPS1_BASE_ADDR         0x43F00000
+#define AIPS2_CTRL_BASE_ADDR    AIPS2_BASE_ADDR
+#define AIPS2_BASE_ADDR         0x53F00000
+#define MAX_BASE_ADDR           0x43F04000
+#define CLKCTL_BASE_ADDR        0x43F0C000
+#define ESDCTL_BASE             0xB8001000
+#define M3IF_BASE               0xB8003000
+#define IOMUXC_BASE_ADDR        0x43FAC000
+#define MPCTL_PARAM_399     (((1-1) << 26) + ((16-1) << 16) + (8  << 10) + (5 << 0))
+#define MPCTL_PARAM_532     ((1 << 31) + ((1-1) << 26) + ((12-1) << 16) + (11  << 10) + (1 << 0))
+#define PPCTL_PARAM_300     (((1-1) << 26) + ((4-1) << 16) + (6  << 10) + (1  << 0))
+#define SDRAM_SIZE                  0x08000000
+#define CCM_BASE_ADDR           0x53F80000
+#define IPU_CTRL_BASE_ADDR      0x53FC0000
+#define WEIM_CTRL_CS5           (WEIM_BASE_ADDR + 0x50)
+#define WEIM_BASE_ADDR          0xB8002000
+#define WEIM_CTRL_CS0           WEIM_BASE_ADDR
+
+ARM_PPMRR:              .word   0x40000015
+L2CACHE_PARAM:          .word   0x00030024
+IIM_SREV_REG_VAL:       .word   IIM_BASE_ADDR + IIM_SREV_OFF
+AIPS1_CTRL_BASE_ADDR_W: .word   AIPS1_CTRL_BASE_ADDR
+AIPS2_CTRL_BASE_ADDR_W: .word   AIPS2_CTRL_BASE_ADDR
+AIPS1_PARAM_W:          .word   0x77777777
+MAX_BASE_ADDR_W:        .word   MAX_BASE_ADDR
+MAX_PARAM1:             .word   0x00302154
+CLKCTL_BASE_ADDR_W:     .word   CLKCTL_BASE_ADDR
+ESDCTL_BASE_W:          .word   ESDCTL_BASE
+M3IF_BASE_W:            .word   M3IF_BASE
+RAM_PARAM1_MDDR:	.word	0x00000400
+RAM_PARAM2_MDDR:	.word	0x00000333
+RAM_PARAM3_MDDR:	.word	0x02000400
+			.word	0x02000000
+RAM_PARAM4_MDDR:	.word	0x04000000
+RAM_PARAM5_MDDR:	.word	0x06000000
+RAM_PARAM6_MDDR:	.word	0x00000233
+			.word	0x00000033
+RAM_PARAM7_MDDR:	.word	0x02000780
+ESDCTL_0x92220000:      .word   0x92220000
+ESDCTL_0xA2220000:      .word   0xA2220000
+ESDCTL_0xB2220000:      .word   0xB2220000
+ESDCTL_0x82226080:      .word   0x82226080
+ESDCTL_CONFIG:       	.word   0x007FFC3F	//DDR2
+			.word 	0x00295729	//MDDR
+ESDCTL_DELAY5:		.word   0x00F49F00
+IOMUXC_BASE_ADDR_W:     .word   IOMUXC_BASE_ADDR
+CCM_CCMR_W:             .word   0x003F4208
+//CCM_PDR0_W:             .word   0x00801000
+CCM_PDR0_W:             .word   0x00801c00
+MPCTL_PARAM_399_W:      .word   MPCTL_PARAM_399
+MPCTL_PARAM_532_W:      .word   MPCTL_PARAM_532
+PPCTL_PARAM_W:    	.word   PPCTL_PARAM_300
+MXC_REDBOOT_ROM_START:  .word   SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000
+CONST_0x0FFF:           .word   0x0FFF
+CCM_BASE_ADDR_W:        .word   CCM_BASE_ADDR
+IPU_CTRL_BASE_ADDR_W:   .word   IPU_CTRL_BASE_ADDR
+WEIM_CTRL_CS5_W:    .word   WEIM_CTRL_CS5
+WEIM_CTRL_CS0_W:    .word   WEIM_CTRL_CS0
+CS0_CSCRU_0x0000CC03:   .word   0x0000DCF6
+CS0_CSCRL_0xA0330D01:   .word   0x444A4541
+CS0_CSCRA_0x00220800:   .word   0x44443302
+CS5_CSCRU_0x0000D843:   .word   0x0000D843
+CS5_CSCRL_0x22252521:   .word   0x22252521
+CS5_CSCRA_0x22220A00:   .word   0x22220A00
+
+#define L2CC_BASE_ADDR          0x30000000
+#define L2_CACHE_CTL_REG                0x100
+#define L2_CACHE_AUX_CTL_REG            0x104
+#define L2_CACHE_DBG_CTL_REG      0xF40
+#define L2_CACHE_INV_WAY_REG            0x77C
+
+/* Assuming 24MHz input clock */
+/*                            PD             MFD              MFI          MFN */
+#define MPCTL_PARAM_399     (((1-1) << 26) + ((16-1) << 16) + (8  << 10) + (5 << 0))
+#define MPCTL_PARAM_532     ((1 << 31) + ((1-1) << 26) + ((12-1) << 16) + (11  << 10) + (1 << 0))
+#define MPCTL_PARAM_665     (((1-1) << 26) + ((48-1) << 16) + (13  << 10) + (41 << 0))
+#define PPCTL_PARAM_300     (((1-1) << 26) + ((4-1) << 16) + (6  << 10) + (1  << 0))
+
+#define M3IF_BASE               0xB8003000
+
+#define UNALIGNED_ACCESS_ENABLE
+#define LOW_INT_LATENCY_ENABLE
+#define BRANCH_PREDICTION_ENABLE
+
+.globl board_init_lowlevel
+board_init_lowlevel:
+	mov     r10, lr
+
+    mrc 15, 0, r1, c1, c0, 0
+    bic r1, r1, #(0x3<<21)
+    bic r1, r1, #(0x3<<11)
+    bic r1, r1, #0x5
+
+    bic r1, r1, #(1<<3)
+
+#ifndef BRANCH_PREDICTION_ENABLE
+    mrc 15, 0, r0, c1, c0, 1
+    bic r0, r0, #7
+    mcr 15, 0, r0, c1, c0, 1
+#else
+    mrc 15, 0, r0, c1, c0, 1
+    orr r0, r0, #7
+    mcr 15, 0, r0, c1, c0, 1
+    orr r1, r1, #(1<<11)
+#endif
+
+#ifdef UNALIGNED_ACCESS_ENABLE
+    orr r1, r1, #(1<<22)
+#endif
+
+#ifdef LOW_INT_LATENCY_ENABLE
+    orr r1, r1, #(1<<21)
+#endif
+    mcr 15, 0, r1, c1, c0, 0
+
+#ifdef BRANCH_PREDICTION_ENABLE
+    mov r0, #0
+    mcr 15, 0, r0, c15, c2, 4
+#endif
+
+    mov r0, #0
+    mcr 15, 0, r0, c7, c7, 0        /* invalidate I cache and D cache */
+    mcr 15, 0, r0, c8, c7, 0        /* invalidate TLBs */
+    mcr 15, 0, r0, c7, c10, 4       /* Drain the write buffer */
+
+    /* Also setup the Peripheral Port Remap register inside the core */
+    ldr r0, ARM_PPMRR        /* start from AIPS 2GB region */
+    mcr p15, 0, r0, c15, c2, 4
+
+    /*** L2 Cache setup/invalidation/disable ***/
+    /* Disable L2 cache first */
+    mov r0, #L2CC_BASE_ADDR
+    ldr r2, [r0, #L2_CACHE_CTL_REG]
+    bic r2, r2, #0x1
+    str r2, [r0, #L2_CACHE_CTL_REG]
+    /*
+     * Configure L2 Cache:
+     * - 128k size(16k way)
+     * - 8-way associativity
+     * - 0 ws TAG/VALID/DIRTY
+     * - 4 ws DATA R/W
+     */
+    ldr r1, [r0, #L2_CACHE_AUX_CTL_REG]
+    and r1, r1, #0xFE000000
+    ldr r2, L2CACHE_PARAM
+    orr r1, r1, r2
+    str r1, [r0, #L2_CACHE_AUX_CTL_REG]
+/* Workaournd for DDR issue:WT*/
+    ldr r1, [r0, #L2_CACHE_DBG_CTL_REG]
+    orr r1, r1, #2
+    str r1, [r0, #L2_CACHE_DBG_CTL_REG]
+
+    /* Invalidate L2 */
+    mov r1, #0x000000FF
+    str r1, [r0, #L2_CACHE_INV_WAY_REG]
+L2_loop:
+    /* Poll Invalidate By Way register */
+    ldr r2, [r0, #L2_CACHE_INV_WAY_REG]
+    cmp r2, #0
+    bne L2_loop
+    /*** End of L2 operations ***/
+
+/*
+ * End of ARM1136 init
+ */
+
+        /*
+         * Set all MPROTx to be non-bufferable, trusted for R/W,
+         * not forced to user-mode.
+         */
+        ldr r0, AIPS1_CTRL_BASE_ADDR_W
+        ldr r1, AIPS1_PARAM_W
+        str r1, [r0, #0x00]
+        str r1, [r0, #0x04]
+        ldr r0, AIPS2_CTRL_BASE_ADDR_W
+        str r1, [r0, #0x00]
+        str r1, [r0, #0x04]
+
+        /*
+         * Clear the on and off peripheral modules Supervisor Protect bit
+         * for SDMA to access them. Did not change the AIPS control registers
+         * (offset 0x20) access type
+         */
+        ldr r0, AIPS1_CTRL_BASE_ADDR_W
+        ldr r1, =0x0
+        str r1, [r0, #0x40]
+        str r1, [r0, #0x44]
+        str r1, [r0, #0x48]
+        str r1, [r0, #0x4C]
+        ldr r1, [r0, #0x50]
+        and r1, r1, #0x00FFFFFF
+        str r1, [r0, #0x50]
+
+        ldr r0, AIPS2_CTRL_BASE_ADDR_W
+        ldr r1, =0x0
+        str r1, [r0, #0x40]
+        str r1, [r0, #0x44]
+        str r1, [r0, #0x48]
+        str r1, [r0, #0x4C]
+        ldr r1, [r0, #0x50]
+        and r1, r1, #0x00FFFFFF
+        str r1, [r0, #0x50]
+
+        ldr r0, MAX_BASE_ADDR_W
+        /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+        ldr r1, MAX_PARAM1
+        str r1, [r0, #0x000]        /* for S0 */
+        str r1, [r0, #0x100]        /* for S1 */
+        str r1, [r0, #0x200]        /* for S2 */
+        str r1, [r0, #0x300]        /* for S3 */
+        str r1, [r0, #0x400]        /* for S4 */
+        /* SGPCR - always park on last master */
+        ldr r1, =0x10
+        str r1, [r0, #0x010]        /* for S0 */
+        str r1, [r0, #0x110]        /* for S1 */
+        str r1, [r0, #0x210]        /* for S2 */
+        str r1, [r0, #0x310]        /* for S3 */
+        str r1, [r0, #0x410]        /* for S4 */
+        /* MGPCR - restore default values */
+        ldr r1, =0x0
+        str r1, [r0, #0x800]        /* for M0 */
+        str r1, [r0, #0x900]        /* for M1 */
+        str r1, [r0, #0xA00]        /* for M2 */
+        str r1, [r0, #0xB00]        /* for M3 */
+        str r1, [r0, #0xC00]        /* for M4 */
+        str r1, [r0, #0xD00]        /* for M5 */
+
+	ldr r1, M3IF_BASE_W
+	/*
+	 * M3IF Control Register (M3IFCTL)
+	 * MRRP[0] = L2CC0 not on priority list (0 << 0)	= 0x00000000
+	 * MRRP[1] = MAX1 not on priority list (0 << 0)		= 0x00000000
+	 * MRRP[2] = L2CC1 not on priority list (0 << 0)	= 0x00000000
+	 * MRRP[3] = USB  not on priority list (0 << 0)		= 0x00000000
+	 * MRRP[4] = SDMA not on priority list (0 << 0)		= 0x00000000
+	 * MRRP[5] = GPU not on priority list (0 << 0)		= 0x00000000
+	 * MRRP[6] = IPU1 on priority list (1 << 6)		= 0x00000040
+	 * MRRP[7] = IPU2 not on priority list (0 << 0)		= 0x00000000
+	 *                                                       ------------
+	 *                                                        0x00000040
+	 */
+	ldr r0, =0x00000040
+	str r0, [r1]  /* M3IF control reg */
+
+#if 1
+	ldr r0, CCM_BASE_ADDR_W
+
+	/* default CLKO to 1/32 of the ARM core*/
+	ldr r1, [r0, #CCM_COSR]
+	bic r1, r1, #0x00000FF00
+	bic r1, r1, #0x0000000FF
+	mov r2, #0x00006C00
+	add r2, r2, #0x67
+	orr r1, r1, r2
+	str r1, [r0, #CCM_COSR]
+
+	ldr r2, CCM_CCMR_W
+	str r2, [r0, #CCM_CCMR]
+
+	/* check clock path */
+	ldr r2, [r0, #CCM_PDR0]
+	tst r2, #0x1
+	ldrne r3, MPCTL_PARAM_532_W  /* consumer path*/
+	ldreq r3, MPCTL_PARAM_399_W  /* auto path*/
+
+	/*Set MPLL , arm clock and ahb clock*/
+	str r3, [r0, #CCM_MPCTL]
+
+	ldr r1, PPCTL_PARAM_W
+	str r1, [r0, #CCM_PPCTL]
+
+	ldr r1, [r0, #CCM_PDR0]
+	orr r1, r1, #0x800000
+	str r1, [r0, #CCM_PDR0]
+
+	ldr r1, CCM_PDR0_W
+	str r1, [r0, #CCM_PDR0]
+
+	ldr r1, [r0, #CCM_CGR0]
+	orr r1, r1, #0x00300000
+	str r1, [r0, #CCM_CGR0]
+
+	ldr r1, [r0, #CCM_CGR1]
+	orr r1, r1, #0x00000C00
+	orr r1, r1, #0x00000003
+	str r1, [r0, #CCM_CGR1]
+#endif
+
+	/* Skip SDRAM initialization if we run from RAM */
+	cmp	pc, #0x80000000
+	bls	1f
+	cmp	pc, #0x90000000
+	bhi	1f
+
+	mov	pc, lr
+
+1:
+	ldr r0, ESDCTL_BASE_W
+	mov r3, #0x2000
+	str r3, [r0, #0x0]
+	str r3, [r0, #0x8]
+
+	mov r12, #0x00
+	mov r2, #0x00
+	mov r1, #IMX_SDRAM_CS0
+
+	ldr r0, ESDCTL_BASE_W
+	mov r3, #0x2000
+	str r3, [r0, #0x0]
+	str r3, [r0, #0x8]
+
+	mov r12, #0x00
+	mov r2, #0x00
+	mov r1, #IMX_SDRAM_CS0
+	bl setup_sdram_bank
+	cmp r3, #0x0
+	orreq r12, r12, #1
+	eorne r2, r2, #0x1
+	blne setup_sdram_bank
+
+	cmp r12, #0
+	movne r3, #L2CC_BASE_ADDR
+	ldrne r4, [r3, #L2_CACHE_AUX_CTL_REG]
+	orrne r4, r4, #0x1000
+	strne r4, [r3, #L2_CACHE_AUX_CTL_REG]
+
+	ldr r3, ESDCTL_DELAY5
+	str r3, [r0, #0x30]
+ret:
+	mov	pc,r10
+
+/*
+ * r0: control base, r1: ram bank base
+ * r2: ddr type(0:DDR2, 1:MDDR) r3, r4: working
+ */
+setup_sdram_bank:
+
+	mov r3, #0xE /*0xA + 0x4*/
+	tst r2, #0x1
+	orreq r3, r3, #0x300 /*DDR2*/
+	str r3, [r0, #0x10]
+	bic r3, r3, #0x00A
+	str r3, [r0, #0x10]
+	beq 2f
+
+	mov r3, #0x20000
+1:	subs r3, r3, #1
+	bne 1b
+
+2:      adr r4, ESDCTL_CONFIG
+	tst r2, #0x1
+	ldreq r3, [r4, #0x0]
+	ldrne r3, [r4, #0x4]
+	cmp r1, #IMX_SDRAM_CS1
+        strlo r3, [r0, #0x4]
+        strhs r3, [r0, #0xC]
+
+        ldr r3, ESDCTL_0x92220000
+        strlo r3, [r0, #0x0]
+        strhs r3, [r0, #0x8]
+	mov r3, #0xDA
+        ldr r4, RAM_PARAM1_MDDR
+        strb r3, [r1, r4]
+
+	tst r2, #0x1
+	bne skip_set_mode
+
+	cmp r1, #IMX_SDRAM_CS1
+	ldr r3, ESDCTL_0xB2220000
+        strlo r3, [r0, #0x0]
+        strhs r3, [r0, #0x8]
+	mov r3, #0xDA
+	ldr r4, RAM_PARAM4_MDDR
+        strb r3, [r1, r4]
+        ldr r4, RAM_PARAM5_MDDR
+        strb r3, [r1, r4]
+        ldr r4, RAM_PARAM3_MDDR
+        strb r3, [r1, r4]
+        ldr r4, RAM_PARAM2_MDDR
+        strb r3, [r1, r4]
+
+        ldr r3, ESDCTL_0x92220000
+        strlo r3, [r0, #0x0]
+        strhs r3, [r0, #0x8]
+	mov r3, #0xDA
+        ldr r4, RAM_PARAM1_MDDR
+        strb r3, [r1, r4]
+
+skip_set_mode:
+	cmp r1, #IMX_SDRAM_CS1
+        ldr r3, ESDCTL_0xA2220000
+        strlo r3, [r0, #0x0]
+        strhs r3, [r0, #0x8]
+        mov r3, #0xDA
+        strb r3, [r1]
+        strb r3, [r1]
+
+        ldr r3, ESDCTL_0xB2220000
+        strlo r3, [r0, #0x0]
+        strhs r3, [r0, #0x8]
+	adr r4, RAM_PARAM6_MDDR
+	tst r2, #0x1
+	ldreq r4, [r4, #0x0]
+	ldrne r4, [r4, #0x4]
+        mov r3, #0xDA
+        strb r3, [r1, r4]
+        ldreq r4, RAM_PARAM7_MDDR
+        streqb r3, [r1, r4]
+	adr r4, RAM_PARAM3_MDDR
+	ldreq r4, [r4, #0x0]
+	ldrne r4, [r4, #0x4]
+        strb r3, [r1, r4]
+
+	cmp r1, #IMX_SDRAM_CS1
+        ldr r3, ESDCTL_0x82226080
+        strlo r3, [r0, #0x0]
+        strhs r3, [r0, #0x8]
+
+	tst r2, #0x1
+	moveq r4, #0x20000
+	movne r4, #0x200
+1:	subs r4, r4, #1
+	bne 1b
+
+	str r3, [r1, #0x100]
+	ldr r4, [r1, #0x100]
+	cmp r3, r4
+	movne r3, #1
+	moveq r3, #0
+	mov pc, lr
+