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| author | Jan Weitzel <J.Weitzel@phytec.de> | 2009-05-18 10:35:28 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2009-05-18 12:32:02 +0200 |
| commit | a737211a01663c18ca3969b3d394bb7dd5e2567e (patch) | |
| tree | adde17135723c8909386ea1526f546294fe08a8b | |
| parent | 252f3bac8c2b7053b38f596960a4e7e4878648ce (diff) | |
| download | barebox-a737211a01663c18ca3969b3d394bb7dd5e2567e.tar.gz barebox-a737211a01663c18ca3969b3d394bb7dd5e2567e.tar.xz | |
mDDR drive strength v2
workarount for drive strength issue
v2: optimized settings after temperature tests
Signed-off-by: Jan Weitzel <J.Weitzel@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| -rw-r--r-- | board/pcm043/lowlevel_init.S | 18 |
1 files changed, 11 insertions, 7 deletions
diff --git a/board/pcm043/lowlevel_init.S b/board/pcm043/lowlevel_init.S index fd23a7c961..649bf387ed 100644 --- a/board/pcm043/lowlevel_init.S +++ b/board/pcm043/lowlevel_init.S @@ -123,19 +123,23 @@ board_init_lowlevel: mov pc, r10 1: - /* Set DDR Type to MDDR, drive strength workaround */ + /* Set DDR Type to SDRAM, drive strength workaround * + * 0x00000000 MDDR * + * 0x00000800 3,3V SDRAM */ - writel(0x00001800, IMX_IOMUXC_BASE + 0x794) - writel(0x00001800, IMX_IOMUXC_BASE + 0x798) - writel(0x00001800, IMX_IOMUXC_BASE + 0x79c) - writel(0x00001800, IMX_IOMUXC_BASE + 0x7a0) - writel(0x00001800, IMX_IOMUXC_BASE + 0x7a4) + #define DDRTYPE 0x00000800 + + writel(DDRTYPE, IMX_IOMUXC_BASE + 0x794) + writel(DDRTYPE, IMX_IOMUXC_BASE + 0x798) + writel(DDRTYPE, IMX_IOMUXC_BASE + 0x79c) + writel(DDRTYPE, IMX_IOMUXC_BASE + 0x7a0) + writel(DDRTYPE, IMX_IOMUXC_BASE + 0x7a4) /* MDDR init, enable mDDR*/ writel(0x00000304, ESDMISC) /* was 0x00000004 */ /* set timing paramters */ - writel(0x007ffc2f, ESDCFG0) /* was 0x007ffc3f */ + writel(0x00255417, ESDCFG0) /* select Prechare-All mode */ writel(0x92220000, ESDCTL0) /* Prechare-All */ |