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authorMarc Kleine-Budde <mkl@pengutronix.de>2010-01-28 23:07:50 +0100
committerMarc Kleine-Budde <mkl@pengutronix.de>2010-02-16 21:49:29 +0100
commit75478b15bfb2682aad88df990d50c63c3a4eb959 (patch)
tree94aa6982369592eb395bc790d3d38d9ce2b61753
parent1568957050274e47cd980c1450b8301720111d6d (diff)
downloadbarebox-75478b15bfb2682aad88df990d50c63c3a4eb959.tar.gz
barebox-75478b15bfb2682aad88df990d50c63c3a4eb959.tar.xz
start-arm: cleanup: proper indention
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
-rw-r--r--arch/arm/cpu/start-arm.S12
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/cpu/start-arm.S b/arch/arm/cpu/start-arm.S
index a30b281c93..4d61ceef42 100644
--- a/arch/arm/cpu/start-arm.S
+++ b/arch/arm/cpu/start-arm.S
@@ -127,16 +127,16 @@ reset:
msr cpsr,r0
#ifdef CONFIG_ARCH_HAS_LOWLEVEL_INIT
- bl arch_init_lowlevel
+ bl arch_init_lowlevel
#endif
#ifdef CONFIG_CPU_V7
/*
* Invalidate v7 I/D caches
*/
- mov r0, #0 /* set up for MCR */
- mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
- mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
+ mov r0, #0 /* set up for MCR */
+ mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
+ mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */
/* Invalidate all Dcaches */
#ifndef CONFIG_CPU_V7_DCACHE_SKIP
/* If Arch specific ROM code SMI handling does not exist */
@@ -212,8 +212,8 @@ finished_inval:
relocate: /* relocate barebox to RAM */
adr r0, _start /* r0 <- current position of code */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
- cmp r0, r1 /* don't reloc during debug */
- beq stack_setup
+ cmp r0, r1 /* don't reloc during debug */
+ beq stack_setup
ldr r2, _barebox_start
ldr r3, _bss_start