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| author | Enrik Berkhan <Enrik.Berkhan@ge.com> | 2008-03-14 17:01:25 +0100 |
|---|---|---|
| committer | Marc Kleine-Budde <mkl@pengutronix.de> | 2008-03-14 17:11:51 +0100 |
| commit | 03f8b48daa66a3a613dde735eebbeff222edba40 (patch) | |
| tree | ca62b7faefff8f04366c4ccc1da54b8e8fb0f45d | |
| parent | cccf87b621d8460d233dc51d45a9485aac354515 (diff) | |
| download | barebox-03f8b48daa66a3a613dde735eebbeff222edba40.tar.gz barebox-03f8b48daa66a3a613dde735eebbeff222edba40.tar.xz | |
Some Blackfin CPU revs don't handle the clock pre-divider correctly on reset
See anomaly 05000242.
Signed-Off-By: Enrik Berkhan <Enrik.Berkhan@ge.com>
| -rw-r--r-- | arch/blackfin/cpu-bf561/init_sdram.S | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/blackfin/cpu-bf561/init_sdram.S b/arch/blackfin/cpu-bf561/init_sdram.S index 84fda76bcd..88e592a574 100644 --- a/arch/blackfin/cpu-bf561/init_sdram.S +++ b/arch/blackfin/cpu-bf561/init_sdram.S @@ -92,6 +92,18 @@ init_sdram: * all other bits set to zero */ + /* first, explicitly enable DF, due to anomaly 05000242 */ + p0.h = hi(PLL_CTL); + p0.l = lo(PLL_CTL); /* Load the address */ + r0.l = w[p0]; + r1 = 1; + r0 = r0 | r1; + cli r2; + ssync; + w[p0] = r0.l; + idle; + sti r2; + r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */ r0 = r0 << 9; /* Shift it over, */ r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/ |