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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2010-12-03 16:25:32 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2010-12-03 16:25:32 +0100 |
| commit | e987040bc914e0677e62600d2b510389632a2605 (patch) | |
| tree | fe9062cb560f1fd5d46e97d2110800b758334b47 | |
| parent | ff3bea7fedd62a0c11b6b9468cf7e5c71b0f1a1a (diff) | |
| parent | 615076e1fc11a86efdc76c64ce65cd336684c742 (diff) | |
| download | barebox-e987040bc914e0677e62600d2b510389632a2605.tar.gz barebox-e987040bc914e0677e62600d2b510389632a2605.tar.xz | |
Merge branch 'next'
222 files changed, 7055 insertions, 19758 deletions
diff --git a/.gitignore b/.gitignore index 2c580c6b1f..4a4511394c 100644 --- a/.gitignore +++ b/.gitignore @@ -48,6 +48,9 @@ include/config include/linux/compile.h include/generated +# Generated files +Doxyfile.version + # stgit generated dirs patches-* diff --git a/Documentation/boards.dox b/Documentation/boards.dox index fa0f284a3b..c04e06b433 100644 --- a/Documentation/boards.dox +++ b/Documentation/boards.dox @@ -43,11 +43,6 @@ x86 type: @li @subpage generic_pc -coldfire/m68k type: - -@li @subpage phycore_mcf54xx -@li @subpage kp_ukd_r1 - */ /* TODO diff --git a/Documentation/commands.dox b/Documentation/commands.dox index 27eb511679..5ef7829aa8 100644 --- a/Documentation/commands.dox +++ b/Documentation/commands.dox @@ -15,34 +15,97 @@ available in @a Barebox: \todo Sort this by functionality? +@li @subpage _name @li @subpage addpart_command +@li @subpage alternate @li @subpage bmp_command @li @subpage bootm_command +@li @subpage bootu +@li @subpage bootz @li @subpage cat_command @li @subpage cd_command @li @subpage clear_command +@li @subpage clko @li @subpage cp_command +@li @subpage cpufreq +@li @subpage cpuinfo @li @subpage crc_command +@li @subpage crc32 @li @subpage delpart_command @li @subpage devinfo_command @li @subpage dfu_command +@li @subpage dhcp +@li @subpage dump_clocks @li @subpage echo_command @li @subpage edit_command @li @subpage erase_command +@li @subpage ethact +@li @subpage exec +@li @subpage exit @li @subpage export_command +@li @subpage false +@li @subpage getopt @li @subpage gpio_get_value_command @li @subpage gpio_set_value_command @li @subpage gpio_direction_input_command @li @subpage gpio_direction_output_command -@li @subpage tftp_command +@li @subpage go +@li @subpage help +@li @subpage host +@li @subpage i2c_probe +@li @subpage i2c_read +@li @subpage i2c_write +@li @subpage icache +@li @subpage iminfo +@li @subpage insmod +@li @subpage linux16_command @li @subpage loadenv_command +@li @subpage loadb +@li @subpage loady +@li @subpage loadxc +@li @subpage login @li @subpage ls_command +@li @subpage lsmod +@li @subpage md +@li @subpage memcmp +@li @subpage meminfo +@li @subpage memset +@li @subpage menu +@li @subpage mkdir @li @subpage mount_command +@li @subpage mtest +@li @subpage mw +@li @subpage mycdev +@li @subpage nand +@li @subpage nand_boot_test +@li @subpage nfs +@li @subpage passwd +@li @subpage ping @li @subpage printenv_command @li @subpage protect_command +@li @subpage pwd +@li @subpage readline +@li @subpage reset +@li @subpage rarpboot +@li @subpage reginfo +@li @subpage rm +@li @subpage rmdir @li @subpage saveenv_command @li @subpage setenv_command +@li @subpage sh +@li @subpage sleep +@li @subpage source +@li @subpage test +@li @subpage timeout +@li @subpage true +@li @subpage tftp_command +@li @subpage ubiattach +@li @subpage ubimkvol +@li @subpage ubirmvol +@li @subpage umount +@li @subpage unlzo @li @subpage unprotect_command -@li @subpage linux16_command +@li @subpage usb +@li @subpage version */ @@ -31,7 +31,7 @@ PROJECT_NAME = barebox # This could be handy for archiving the generated documentation or # if some version control system is used. -PROJECT_NUMBER = 1 +@INCLUDE = Doxyfile.version # The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) # base path where the generated documentation will be put. @@ -762,6 +762,9 @@ include/config/kernel.release: include/config/auto.conf FORCE $(Q)rm -f $@ $(Q)echo $(kernelrelease) > $@ +Doxyfile.version: include/config/auto.conf FORCE + $(Q)rm -f $@ + $(Q)echo "PROJECT_NUMBER = $(KERNELRELEASE)" > $@ # Things we need to do before we recursively start building the kernel # or the modules are listed in "prepare". @@ -973,7 +976,7 @@ endif # CONFIG_MODULES CLEAN_DIRS += $(MODVERDIR) CLEAN_FILES += barebox System.map include/generated/barebox_default_env.h \ .tmp_version .tmp_barebox* barebox.bin barebox.S \ - .tmp_kallsyms* barebox_default_env barebox.ldr + .tmp_kallsyms* barebox_default_env barebox.ldr Doxyfile.version # Directories & files removed with 'make mrproper' MRPROPER_DIRS += include/config include2 usr/include @@ -1098,7 +1101,7 @@ help: docs : htmldocs -htmldocs: +htmldocs: Doxyfile.version @echo 'Running doxygen with local Doxyfile' $(Q)doxygen Doxyfile diff --git a/arch/architecture.dox b/arch/architecture.dox index ea00dcdc89..67e2c38864 100644 --- a/arch/architecture.dox +++ b/arch/architecture.dox @@ -87,7 +87,6 @@ TODO @li @subpage dev_arm_mach @li @subpage dev_bf_mach @li @subpage dev_ppc_mach -@li @subpage dev_m68k_mach @li @subpage dev_x86_mach */ diff --git a/arch/arm/Makefile b/arch/arm/Makefile index c10d863633..9729c23572 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -52,8 +52,11 @@ machine-$(CONFIG_ARCH_S3C24xx) := s3c24xx board-$(CONFIG_MACH_A9M2410) := a9m2410 board-$(CONFIG_MACH_A9M2440) := a9m2440 board-$(CONFIG_MACH_AT91SAM9260EK) := at91sam9260ek +board-$(CONFIG_MACH_AT91SAM9261EK) := at91sam9261ek board-$(CONFIG_MACH_AT91SAM9263EK) := at91sam9263ek +board-$(CONFIG_MACH_AT91SAM9G10EK) := at91sam9261ek board-$(CONFIG_MACH_AT91SAM9G20EK) := at91sam9260ek +board-$(CONFIG_MACH_AT91SAM9M10G45EK) := at91sam9m10g45ek board-$(CONFIG_MACH_EDB9301) := edb93xx board-$(CONFIG_MACH_EDB9302) := edb93xx board-$(CONFIG_MACH_EDB9302A) := edb93xx @@ -78,7 +81,9 @@ board-$(CONFIG_MACH_PCA100) := phycard-i.MX27 board-$(CONFIG_MACH_PCM037) := pcm037 board-$(CONFIG_MACH_PCM038) := pcm038 board-$(CONFIG_MACH_PCM043) := pcm043 +board-$(CONFIG_MACH_PM9261) := pm9261 board-$(CONFIG_MACH_PM9263) := pm9263 +board-$(CONFIG_MACH_PM9G45) := pm9g45 board-$(CONFIG_MACH_SCB9328) := scb9328 board-$(CONFIG_MACH_NESO) := guf-neso board-$(CONFIG_MACH_MX23EVK) := freescale-mx23-evk diff --git a/arch/arm/boards/at91sam9261ek/Makefile b/arch/arm/boards/at91sam9261ek/Makefile new file mode 100644 index 0000000000..eb072c0161 --- /dev/null +++ b/arch/arm/boards/at91sam9261ek/Makefile @@ -0,0 +1 @@ +obj-y += init.o diff --git a/arch/arm/boards/at91sam9261ek/config.h b/arch/arm/boards/at91sam9261ek/config.h new file mode 100644 index 0000000000..006820cf21 --- /dev/null +++ b/arch/arm/boards/at91sam9261ek/config.h @@ -0,0 +1,6 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/at91sam9261ek/env/config b/arch/arm/boards/at91sam9261ek/env/config new file mode 100644 index 0000000000..3b922339fa --- /dev/null +++ b/arch/arm/boards/at91sam9261ek/env/config @@ -0,0 +1,41 @@ +#!/bin/sh + +# use 'dhcp' to do dhcp in barebox and in kernel +# use 'none' if you want to skip kernel ip autoconfiguration +ip=dhcp + +# or set your networking parameters here +#eth0.ipaddr=a.b.c.d +#eth0.netmask=a.b.c.d +#eth0.gateway=a.b.c.d +#eth0.serverip=a.b.c.d + +# can be either 'net' or 'nand' +kernel_loc=net +# can be either 'net', 'nand' or 'initrd' +rootfs_loc=net + +# can be either 'jffs2' or 'ubifs' +rootfs_type=ubifs +rootfsimage=root.$rootfs_type + +# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo +#kernelimage_type=zimage +#kernelimage=zImage +kernelimage_type=uimage +kernelimage=uImage +#kernelimage_type=raw +#kernelimage=Image +#kernelimage_type=raw_lzo +#kernelimage=Image.lzo + +nand_parts="256k(barebox)ro,64k(bareboxenv),1536k(kernel),-(root)" +rootfs_mtdblock_nand=3 + +autoboot_timeout=3 + +bootargs="console=ttyS0,115200" + +# set a fancy prompt (if support is compiled in) +PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " + diff --git a/arch/arm/boards/at91sam9261ek/init.c b/arch/arm/boards/at91sam9261ek/init.c new file mode 100644 index 0000000000..576a022434 --- /dev/null +++ b/arch/arm/boards/at91sam9261ek/init.c @@ -0,0 +1,174 @@ +/* + * Copyright (C) 2007 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <net.h> +#include <init.h> +#include <environment.h> +#include <asm/armlinux.h> +#include <generated/mach-types.h> +#include <partition.h> +#include <fs.h> +#include <fcntl.h> +#include <asm/io.h> +#include <asm/hardware.h> +#include <nand.h> +#include <linux/mtd/nand.h> +#include <mach/at91_pmc.h> +#include <mach/board.h> +#include <mach/gpio.h> +#include <mach/io.h> +#include <mach/at91sam9_smc.h> +#include <mach/sam9_smc.h> +#include <dm9000.h> + +static struct atmel_nand_data nand_pdata = { + .ale = 22, + .cle = 21, +/* .det_pin = ... not connected */ + .rdy_pin = AT91_PIN_PC15, + .enable_pin = AT91_PIN_PC14, +#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16) + .bus_width_16 = 1, +#else + .bus_width_16 = 0, +#endif +}; + +static struct sam9_smc_config ek_nand_smc_config = { + .ncs_read_setup = 0, + .nrd_setup = 1, + .ncs_write_setup = 0, + .nwe_setup = 1, + + .ncs_read_pulse = 3, + .nrd_pulse = 3, + .ncs_write_pulse = 3, + .nwe_pulse = 3, + + .read_cycle = 5, + .write_cycle = 5, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE, + .tdf_cycles = 2, +}; + +static void ek_add_device_nand(void) +{ + /* setup bus-width (8 or 16) */ + if (nand_pdata.bus_width_16) + ek_nand_smc_config.mode |= AT91_SMC_DBW_16; + else + ek_nand_smc_config.mode |= AT91_SMC_DBW_8; + + /* configure chip-select 3 (NAND) */ + sam9_smc_configure(3, &ek_nand_smc_config); + + at91_add_device_nand(&nand_pdata); +} + +/* + * DM9000 ethernet device + */ +#if defined(CONFIG_DRIVER_NET_DM9000) +static struct dm9000_platform_data dm9000_data = { + .iobase = AT91_CHIPSELECT_2, + .iodata = AT91_CHIPSELECT_2 + 4, + .buswidth = DM9000_WIDTH_16, + .srom = 0, +}; + +static struct device_d dm9000_dev = { + .id = 0, + .name = "dm9000", + .map_base = AT91_CHIPSELECT_2, + .size = 8, + .platform_data = &dm9000_data, +}; + +/* + * SMC timings for the DM9000. + * Note: These timings were calculated for MASTER_CLOCK = 100000000 according to the DM9000 timings. + */ +static struct sam9_smc_config __initdata dm9000_smc_config = { + .ncs_read_setup = 0, + .nrd_setup = 2, + .ncs_write_setup = 0, + .nwe_setup = 2, + + .ncs_read_pulse = 8, + .nrd_pulse = 4, + .ncs_write_pulse = 8, + .nwe_pulse = 4, + + .read_cycle = 16, + .write_cycle = 16, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16, + .tdf_cycles = 1, +}; + +static void __init ek_add_device_dm9000(void) +{ + /* Configure chip-select 2 (DM9000) */ + sam9_smc_configure(2, &dm9000_smc_config); + + /* Configure Reset signal as output */ + at91_set_gpio_output(AT91_PIN_PC10, 0); + + /* Configure Interrupt pin as input, no pull-up */ + at91_set_gpio_input(AT91_PIN_PC11, 0); + + register_device(&dm9000_dev); +} +#else +static void __init ek_add_device_dm9000(void) {} +#endif /* CONFIG_DRIVER_NET_DM9000 */ + +static int at91sam9261ek_devices_init(void) +{ + + at91_add_device_sdram(64 * 1024 * 1024); + ek_add_device_nand(); + ek_add_device_dm9000(); + + devfs_add_partition("nand0", 0x00000, 0x80000, PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + devfs_add_partition("nand0", 0x40000, 0x40000, PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); + + armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100)); + if (machine_is_at91sam9g10ek()) + armlinux_set_architecture(MACH_TYPE_AT91SAM9G10EK); + else + armlinux_set_architecture(MACH_TYPE_AT91SAM9261EK); + + return 0; +} + +device_initcall(at91sam9261ek_devices_init); + +static int at91sam9261ek_console_init(void) +{ + at91_register_uart(0, 0); + return 0; +} + +console_initcall(at91sam9261ek_console_init); diff --git a/arch/arm/boards/at91sam9m10g45ek/Makefile b/arch/arm/boards/at91sam9m10g45ek/Makefile new file mode 100644 index 0000000000..eb072c0161 --- /dev/null +++ b/arch/arm/boards/at91sam9m10g45ek/Makefile @@ -0,0 +1 @@ +obj-y += init.o diff --git a/arch/arm/boards/at91sam9m10g45ek/config.h b/arch/arm/boards/at91sam9m10g45ek/config.h new file mode 100644 index 0000000000..ac3114d865 --- /dev/null +++ b/arch/arm/boards/at91sam9m10g45ek/config.h @@ -0,0 +1,6 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/at91sam9m10g45ek/env/config b/arch/arm/boards/at91sam9m10g45ek/env/config new file mode 100644 index 0000000000..3b922339fa --- /dev/null +++ b/arch/arm/boards/at91sam9m10g45ek/env/config @@ -0,0 +1,41 @@ +#!/bin/sh + +# use 'dhcp' to do dhcp in barebox and in kernel +# use 'none' if you want to skip kernel ip autoconfiguration +ip=dhcp + +# or set your networking parameters here +#eth0.ipaddr=a.b.c.d +#eth0.netmask=a.b.c.d +#eth0.gateway=a.b.c.d +#eth0.serverip=a.b.c.d + +# can be either 'net' or 'nand' +kernel_loc=net +# can be either 'net', 'nand' or 'initrd' +rootfs_loc=net + +# can be either 'jffs2' or 'ubifs' +rootfs_type=ubifs +rootfsimage=root.$rootfs_type + +# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo +#kernelimage_type=zimage +#kernelimage=zImage +kernelimage_type=uimage +kernelimage=uImage +#kernelimage_type=raw +#kernelimage=Image +#kernelimage_type=raw_lzo +#kernelimage=Image.lzo + +nand_parts="256k(barebox)ro,64k(bareboxenv),1536k(kernel),-(root)" +rootfs_mtdblock_nand=3 + +autoboot_timeout=3 + +bootargs="console=ttyS0,115200" + +# set a fancy prompt (if support is compiled in) +PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " + diff --git a/arch/arm/boards/at91sam9m10g45ek/init.c b/arch/arm/boards/at91sam9m10g45ek/init.c new file mode 100644 index 0000000000..bb8b7bada6 --- /dev/null +++ b/arch/arm/boards/at91sam9m10g45ek/init.c @@ -0,0 +1,116 @@ +/* + * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> + * + * Copyright (C) 2007 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <net.h> +#include <init.h> +#include <environment.h> +#include <asm/armlinux.h> +#include <generated/mach-types.h> +#include <partition.h> +#include <fs.h> +#include <fcntl.h> +#include <asm/io.h> +#include <asm/hardware.h> +#include <nand.h> +#include <linux/mtd/nand.h> +#include <mach/at91_pmc.h> +#include <mach/board.h> +#include <mach/gpio.h> +#include <mach/io.h> +#include <mach/at91sam9_smc.h> +#include <mach/sam9_smc.h> + +static struct atmel_nand_data nand_pdata = { + .ale = 21, + .cle = 22, +/* .det_pin = ... not connected */ + .rdy_pin = AT91_PIN_PC8, + .enable_pin = AT91_PIN_PC14, +#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16) + .bus_width_16 = 1, +#else + .bus_width_16 = 0, +#endif +}; + +static struct sam9_smc_config ek_nand_smc_config = { + .ncs_read_setup = 0, + .nrd_setup = 2, + .ncs_write_setup = 0, + .nwe_setup = 2, + + .ncs_read_pulse = 4, + .nrd_pulse = 4, + .ncs_write_pulse = 4, + .nwe_pulse = 4, + + .read_cycle = 7, + .write_cycle = 7, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE, + .tdf_cycles = 3, +}; + +static void ek_add_device_nand(void) +{ + /* setup bus-width (8 or 16) */ + if (nand_pdata.bus_width_16) + ek_nand_smc_config.mode |= AT91_SMC_DBW_16; + else + ek_nand_smc_config.mode |= AT91_SMC_DBW_8; + + /* configure chip-select 3 (NAND) */ + sam9_smc_configure(3, &ek_nand_smc_config); + + at91_add_device_nand(&nand_pdata); +} + +static struct at91_ether_platform_data macb_pdata = { + .flags = AT91SAM_ETHER_RMII, + .phy_addr = 0, +}; + +static int at91sam9m10g45ek_devices_init(void) +{ + at91_add_device_sdram(128 * 1024 * 1024); + ek_add_device_nand(); + at91_add_device_eth(&macb_pdata); + + devfs_add_partition("nand0", 0x00000, 0x80000, PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + devfs_add_partition("nand0", 0x40000, 0x40000, PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); + + armlinux_set_bootparams((void *)(AT91_CHIPSELECT_6 + 0x100)); + armlinux_set_architecture(MACH_TYPE_AT91SAM9M10G45EK); + + return 0; +} +device_initcall(at91sam9m10g45ek_devices_init); + +static int at91sam9m10g45ek_console_init(void) +{ + at91_register_uart(0, 0); + return 0; +} +console_initcall(at91sam9m10g45ek_console_init); diff --git a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c index 805ffe2d10..3048c3fbcf 100644 --- a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c +++ b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c @@ -43,6 +43,7 @@ #include <i2c/i2c.h> #include <usb/fsl_usb2.h> #include <mach/usb.h> +#include <mach/devices-imx25.h> extern unsigned long _stext; extern void exception_vectors(void); @@ -88,13 +89,6 @@ static struct fec_platform_data fec_info = { .phy_addr = 1, }; -static struct device_d fec_dev = { - .id = -1, - .name = "fec_imx", - .map_base = IMX_FEC_BASE, - .platform_data = &fec_info, -}; - static struct memory_platform_data sdram_pdata = { .name = "ram0", .flags = DEVFS_RDWR, @@ -113,13 +107,6 @@ struct imx_nand_platform_data nand_info = { .hw_ecc = 1, }; -static struct device_d nand_dev = { - .id = -1, - .name = "imx_nand", - .map_base = IMX_NFC_BASE, - .platform_data = &nand_info, -}; - static struct imx_fb_videomode imxfb_mode = { .mode = { .name = "CMO-QVGA", @@ -145,26 +132,6 @@ static struct imx_fb_platform_data eukrea_cpuimx25_fb_data = { .dmacr = 0x80040060, }; - -static struct device_d imxfb_dev = { - .id = -1, - .name = "imxfb", - .map_base = 0x53fbc000, - .size = 0x1000, - .platform_data = &eukrea_cpuimx25_fb_data, -}; - -static struct device_d i2c_dev = { - .id = -1, - .name = "i2c-imx", - .map_base = IMX_I2C1_BASE, -}; - -static struct device_d esdhc_dev = { - .name = "imx-esdhc", - .map_base = 0x53fb4000, -}; - #ifdef CONFIG_USB static void imx25_usb_init(void) { @@ -285,10 +252,10 @@ static int eukrea_cpuimx25_devices_init(void) mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx25_pads, ARRAY_SIZE(eukrea_cpuimx25_pads)); - register_device(&fec_dev); + imx25_add_fec(&fec_info); nand_info.width = 1; - register_device(&nand_dev); + imx25_add_nand(&nand_info); devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw"); @@ -304,10 +271,10 @@ static int eukrea_cpuimx25_devices_init(void) gpio_direction_output(26, 1); gpio_set_value(26, 1); - register_device(&imxfb_dev); + imx25_add_fb(&eukrea_cpuimx25_fb_data); - register_device(&i2c_dev); - register_device(&esdhc_dev); + imx25_add_i2c0(NULL); + imx25_add_mmc0(NULL); #ifdef CONFIG_USB imx25_usb_init(); @@ -324,16 +291,9 @@ static int eukrea_cpuimx25_devices_init(void) device_initcall(eukrea_cpuimx25_devices_init); -static struct device_d eukrea_cpuimx25_serial_device = { - .id = -1, - .name = "imx_serial", - .map_base = IMX_UART1_BASE, - .size = 16 * 1024, -}; - static int eukrea_cpuimx25_console_init(void) { - register_device(&eukrea_cpuimx25_serial_device); + imx25_add_uart0(); return 0; } diff --git a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c index 62fc14e4ec..4567cba16b 100644 --- a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c +++ b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c @@ -46,6 +46,7 @@ #include <i2c/i2c.h> #include <mfd/lp3972.h> #include <mach/iomux-mx27.h> +#include <mach/devices-imx27.h> static struct device_d cfi_dev = { .id = -1, @@ -86,26 +87,12 @@ static struct fec_platform_data fec_info = { .phy_addr = 1, }; -static struct device_d fec_dev = { - .id = -1, - .name = "fec_imx", - .map_base = 0x1002b000, - .platform_data = &fec_info, -}; - struct imx_nand_platform_data nand_info = { .width = 1, .hw_ecc = 1, .flash_bbt = 1, }; -static struct device_d nand_dev = { - .id = -1, - .name = "imx_nand", - .map_base = 0xd8000000, - .platform_data = &nand_info, -}; - #ifdef CONFIG_DRIVER_SERIAL_NS16550 unsigned int quad_uart_read(unsigned long base, unsigned char reg_idx) { @@ -156,12 +143,6 @@ static struct i2c_board_info i2c_devices[] = { }, }; -static struct device_d i2c_dev = { - .id = -1, - .name = "i2c-imx", - .map_base = IMX_I2C1_BASE, -}; - #ifdef CONFIG_MMU static void eukrea_cpuimx27_mmu_init(void) { @@ -294,12 +275,12 @@ static int eukrea_cpuimx27_devices_init(void) #ifdef CONFIG_EUKREA_CPUIMX27_NOR_64MB register_device(&cfi_dev1); #endif - register_device(&nand_dev); + imx27_add_nand(&nand_info); register_device(&sdram_dev); PCCR0 |= PCCR0_I2C1_EN; i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); - register_device(&i2c_dev); + imx27_add_i2c0(NULL); devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0"); devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0"); @@ -359,7 +340,7 @@ static int eukrea_cpuimx27_late_init(void) u8 reg[1]; #endif console_flush(); - register_device(&fec_dev); + imx27_add_fec(&fec_info); #ifdef CONFIG_I2C_LP3972 client = lp3972_get_client(); diff --git a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c index dfe64d0174..07f320b367 100644 --- a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c +++ b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c @@ -54,19 +54,13 @@ #include <i2c/i2c.h> #include <usb/fsl_usb2.h> #include <mach/usb.h> +#include <mach/devices-imx35.h> static struct fec_platform_data fec_info = { .xcv_type = MII100, .phy_addr = 0x1F, }; -static struct device_d fec_dev = { - .id = -1, - .name = "fec_imx", - .map_base = IMX_FEC_BASE, - .platform_data = &fec_info, -}; - static struct memory_platform_data sdram_pdata = { .name = "ram0", .flags = DEVFS_RDWR, @@ -86,13 +80,6 @@ struct imx_nand_platform_data nand_info = { .flash_bbt = 1, }; -static struct device_d nand_dev = { - .id = -1, - .name = "imx_nand", - .map_base = IMX_NFC_BASE, - .platform_data = &nand_info, -}; - static struct fb_videomode imxfb_mode = { .name = "CMO_QVGA", .refresh = 60, @@ -121,25 +108,6 @@ static struct imx_ipu_fb_platform_data ipu_fb_data = { .enable = eukrea_cpuimx35_enable_display, }; -static struct device_d imxfb_dev = { - .id = -1, - .name = "imx-ipu-fb", - .map_base = 0x53fc0000, - .size = 0x1000, - .platform_data = &ipu_fb_data, -}; - -static struct device_d i2c_dev = { - .id = -1, - .name = "i2c-imx", - .map_base = IMX_I2C1_BASE, -}; - -static struct device_d esdhc_dev = { - .name = "imx-esdhc", - .map_base = IMX_SDHC1_BASE, -}; - #ifdef CONFIG_USB static void imx35_usb_init(void) { @@ -212,20 +180,20 @@ static int eukrea_cpuimx35_devices_init(void) { unsigned int tmp; - register_device(&nand_dev); + imx35_add_nand(&nand_info); devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw"); dev_add_bb_dev("self_raw", "self0"); devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw"); dev_add_bb_dev("env_raw", "env0"); - register_device(&fec_dev); + imx35_add_fec(&fec_info); register_device(&sdram_dev); - register_device(&imxfb_dev); + imx35_add_fb(&ipu_fb_data); - register_device(&i2c_dev); - register_device(&esdhc_dev); + imx35_add_i2c0(NULL); + imx35_add_mmc0(NULL); #ifdef CONFIG_USB imx35_usb_init(); @@ -245,13 +213,6 @@ static int eukrea_cpuimx35_devices_init(void) device_initcall(eukrea_cpuimx35_devices_init); -static struct device_d eukrea_cpuimx35_serial_device = { - .id = -1, - .name = "imx_serial", - .map_base = IMX_UART1_BASE, - .size = 4096, -}; - static struct pad_desc eukrea_cpuimx35_pads[] = { MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, @@ -306,7 +267,7 @@ static int eukrea_cpuimx35_console_init(void) /* led default off */ gpio_direction_output(32 * 2 + 29, 1); - register_device(&eukrea_cpuimx35_serial_device); + imx35_add_uart0(); return 0; } diff --git a/arch/arm/boards/freescale-mx25-3-stack/3stack.c b/arch/arm/boards/freescale-mx25-3-stack/3stack.c index 25945f13d8..49b7f5c2e5 100644 --- a/arch/arm/boards/freescale-mx25-3-stack/3stack.c +++ b/arch/arm/boards/freescale-mx25-3-stack/3stack.c @@ -40,6 +40,7 @@ #include <linux/err.h> #include <i2c/i2c.h> #include <mfd/mc34704.h> +#include <mach/devices-imx25.h> extern unsigned long _stext; extern void exception_vectors(void); @@ -112,13 +113,6 @@ static struct fec_platform_data fec_info = { .phy_addr = 1, }; -static struct device_d fec_dev = { - .id = -1, - .name = "fec_imx", - .map_base = IMX_FEC_BASE, - .platform_data = &fec_info, -}; - static struct memory_platform_data sdram_pdata = { .name = "ram0", .flags = DEVFS_RDWR, @@ -156,13 +150,6 @@ struct imx_nand_platform_data nand_info = { .hw_ecc = 1, }; -static struct device_d nand_dev = { - .id = -1, - .name = "imx_nand", - .map_base = IMX_NFC_BASE, - .platform_data = &nand_info, -}; - #ifdef CONFIG_USB static void imx25_usb_init(void) { @@ -197,12 +184,6 @@ static struct i2c_board_info i2c_devices[] = { }, }; -static struct device_d i2c_dev = { - .id = -1, - .name = "i2c-imx", - .map_base = IMX_I2C1_BASE, -}; - static int imx25_3ds_pmic_init(void) { struct mc34704 *pmic; @@ -259,12 +240,12 @@ static int imx25_devices_init(void) register_device(&usbh2_dev); #endif - register_device(&fec_dev); + imx25_add_fec(&fec_info); if (readl(IMX_CCM_BASE + CCM_RCSR) & (1 << 14)) nand_info.width = 2; - register_device(&nand_dev); + imx25_add_nand(&nand_info); devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw"); dev_add_bb_dev("self_raw", "self0"); @@ -276,7 +257,7 @@ static int imx25_devices_init(void) register_device(&sram0_dev); i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); - register_device(&i2c_dev); + imx25_add_i2c0(NULL); armlinux_add_dram(&sdram0_dev); armlinux_set_bootparams((void *)0x80000100); @@ -288,13 +269,6 @@ static int imx25_devices_init(void) device_initcall(imx25_devices_init); -static struct device_d imx25_serial_device = { - .id = -1, - .name = "imx_serial", - .map_base = IMX_UART1_BASE, - .size = 16 * 1024, -}; - static struct pad_desc imx25_pads[] = { MX25_PAD_FEC_MDC__MDC, MX25_PAD_FEC_MDIO__MDIO, @@ -339,7 +313,7 @@ static int imx25_console_init(void) writel(0x03010101, 0x53f80024); - register_device(&imx25_serial_device); + imx25_add_uart0(); return 0; } diff --git a/arch/arm/boards/freescale-mx35-3-stack/3stack.c b/arch/arm/boards/freescale-mx35-3-stack/3stack.c index d6699cdc93..127bfb4065 100644 --- a/arch/arm/boards/freescale-mx35-3-stack/3stack.c +++ b/arch/arm/boards/freescale-mx35-3-stack/3stack.c @@ -48,6 +48,7 @@ #include <mach/pmic.h> #include <mach/imx-ipu-fb.h> #include <mach/generic.h> +#include <mach/devices-imx35.h> #include <i2c/i2c.h> #include <mfd/mc13892.h> @@ -70,13 +71,6 @@ static struct fec_platform_data fec_info = { .phy_addr = 0x1F, }; -static struct device_d fec_dev = { - .id = -1, - .name = "fec_imx", - .map_base = IMX_FEC_BASE, - .platform_data = &fec_info, -}; - static struct memory_platform_data sdram_pdata = { .name = "ram0", .flags = DEVFS_RDWR, @@ -95,13 +89,6 @@ struct imx_nand_platform_data nand_info = { .flash_bbt = 1, }; -static struct device_d nand_dev = { - .id = -1, - .name = "imx_nand", - .map_base = IMX_NFC_BASE, - .platform_data = &nand_info, -}; - static struct device_d smc911x_dev = { .id = -1, .name = "smc911x", @@ -149,14 +136,6 @@ static struct imx_ipu_fb_platform_data ipu_fb_data = { .bpp = 16, }; -static struct device_d imxfb_dev = { - .id = -1, - .name = "imx-ipu-fb", - .map_base = 0x53fc0000, - .size = 0x1000, - .platform_data = &ipu_fb_data, -}; - /* * Revision to be passed to kernel. The kernel provided * by freescale relies on this. @@ -202,7 +181,7 @@ static int f3s_devices_init(void) /* * This platform supports NOR and NAND */ - register_device(&nand_dev); + imx35_add_nand(&nand_info); register_device(&cfi_dev); switch ((reg >> 25) & 0x3) { @@ -225,11 +204,11 @@ static int f3s_devices_init(void) i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); register_device(&i2c_dev); - register_device(&fec_dev); + imx35_add_fec(&fec_info); register_device(&smc911x_dev); register_device(&sdram_dev); - register_device(&imxfb_dev); + imx35_add_fb(&ipu_fb_data); armlinux_add_dram(&sdram_dev); armlinux_set_bootparams((void *)0x80000100); @@ -250,13 +229,6 @@ static int f3s_enable_display(void) late_initcall(f3s_enable_display); -static struct device_d f3s_serial_device = { - .id = -1, - .name = "imx_serial", - .map_base = IMX_UART1_BASE, - .size = 4096, -}; - static struct pad_desc f3s_pads[] = { MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, @@ -322,7 +294,7 @@ static int f3s_console_init(void) { mxc_iomux_v3_setup_multiple_pads(f3s_pads, ARRAY_SIZE(f3s_pads)); - register_device(&f3s_serial_device); + imx35_add_uart0(); return 0; } diff --git a/arch/arm/boards/freescale-mx51-pdk/board.c b/arch/arm/boards/freescale-mx51-pdk/board.c index 5197c55007..ff779ca026 100644 --- a/arch/arm/boards/freescale-mx51-pdk/board.c +++ b/arch/arm/boards/freescale-mx51-pdk/board.c @@ -39,6 +39,7 @@ #include <mach/spi.h> #include <mach/generic.h> #include <mach/iomux-mx51.h> +#include <mach/devices-imx51.h> static struct memory_platform_data ram_pdata = { .name = "ram0", @@ -57,17 +58,6 @@ static struct fec_platform_data fec_info = { .xcv_type = MII100, }; -static struct device_d fec_dev = { - .name = "fec_imx", - .map_base = 0x83fec000, - .platform_data = &fec_info, -}; - -static struct device_d esdhc_dev = { - .name = "imx-esdhc", - .map_base = 0x70004000, -}; - static struct pad_desc f3s_pads[] = { MX51_PAD_EIM_EB2__FEC_MDIO, MX51_PAD_EIM_EB3__FEC_RDATA1, @@ -130,13 +120,6 @@ static struct spi_imx_master spi_0_data = { .num_chipselect = ARRAY_SIZE(spi_0_cs), }; -static struct device_d spi_dev = { - .id = -1, - .name = "imx_spi", - .map_base = MX51_CSPI1_BASE_ADDR, - .platform_data = &spi_0_data, -}; - static const struct spi_board_info mx51_babbage_spi_board_info[] = { { .name = "mc13892-spi", @@ -268,12 +251,12 @@ static int f3s_devices_init(void) babbage_mmu_init(); register_device(&sdram_dev); - register_device(&fec_dev); - register_device(&esdhc_dev); + imx51_add_fec(&fec_info); + imx51_add_mmc0(NULL); spi_register_board_info(mx51_babbage_spi_board_info, ARRAY_SIZE(mx51_babbage_spi_board_info)); - register_device(&spi_dev); + imx51_add_spi0(&spi_0_data); babbage_power_init(); @@ -295,12 +278,6 @@ static int f3s_part_init(void) } late_initcall(f3s_part_init); -static struct device_d f3s_serial_device = { - .name = "imx_serial", - .map_base = 0x73fbc000, - .size = 4096, -}; - static int f3s_console_init(void) { mxc_iomux_v3_setup_multiple_pads(f3s_pads, ARRAY_SIZE(f3s_pads)); @@ -310,7 +287,7 @@ static int f3s_console_init(void) writel(0, 0x73fa8230); writel(0, 0x73fa8234); - register_device(&f3s_serial_device); + imx51_add_uart0(); return 0; } diff --git a/arch/arm/boards/guf-neso/board.c b/arch/arm/boards/guf-neso/board.c index 9c85c0869e..d371dd6a5a 100644 --- a/arch/arm/boards/guf-neso/board.c +++ b/arch/arm/boards/guf-neso/board.c @@ -44,6 +44,7 @@ #include <mach/imx-nand.h> #include <mach/imx-pll.h> #include <mach/imxfb.h> +#include <mach/devices-imx27.h> /* two pins are controlling the CS signals to the USB phys */ #define USBH2_PHY_CS_GPIO (GPIO_PORTF + 20) @@ -71,26 +72,12 @@ static struct fec_platform_data fec_info = { .phy_addr = 31, }; -static struct device_d fec_dev = { - .id = -1, - .name = "fec_imx", - .map_base = 0x1002b000, - .platform_data = &fec_info, -}; - static struct imx_nand_platform_data nand_info = { .width = 1, .hw_ecc = 1, .flash_bbt = 1, }; -static struct device_d nand_dev = { - .id = -1, - .name = "imx_nand", - .map_base = 0xd8000000, - .platform_data = &nand_info, -}; - static struct imx_fb_videomode imxfb_mode = { .mode = { .name = "CPT CLAA070LC0JCT", @@ -139,14 +126,6 @@ static struct imx_fb_platform_data neso_fb_data = { .framebuffer_ovl = (void *)0xa7f00000, }; -static struct device_d imxfb_dev = { - .id = -1, - .name = "imxfb", - .map_base = 0x10021000, - .size = 0x1000, - .platform_data = &neso_fb_data, -}; - #ifdef CONFIG_USB static struct device_d usbh2_dev = { @@ -334,16 +313,16 @@ static int neso_devices_init(void) for (i = 0; i < ARRAY_SIZE(mode); i++) imx_gpio_mode(mode[i]); - register_device(&nand_dev); + imx27_add_nand(&nand_info); register_device(&sdram_dev); - register_device(&imxfb_dev); + imx27_add_fb(&neso_fb_data); #ifdef CONFIG_USB neso_usbh_init(); register_device(&usbh2_dev); #endif - register_device(&fec_dev); + imx27_add_fec(&fec_info); devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw"); dev_add_bb_dev("self_raw", "self0"); @@ -360,16 +339,9 @@ static int neso_devices_init(void) device_initcall(neso_devices_init); -static struct device_d neso_serial_device = { - .id = -1, - .name = "imx_serial", - .map_base = IMX_UART1_BASE, - .size = 4096, -}; - static int neso_console_init(void) { - register_device(&neso_serial_device); + imx27_add_uart0(); return 0; } diff --git a/arch/arm/boards/imx21ads/imx21ads.c b/arch/arm/boards/imx21ads/imx21ads.c index 44d37aad4f..394258154d 100644 --- a/arch/arm/boards/imx21ads/imx21ads.c +++ b/arch/arm/boards/imx21ads/imx21ads.c @@ -36,6 +36,7 @@ #include <mach/imx-nand.h> #include <mach/imxfb.h> #include <mach/iomux-mx21.h> +#include <mach/devices-imx21.h> #define MX21ADS_IO_REG 0xCC800000 #define MX21ADS_IO_LCDON (1 << 9) @@ -65,13 +66,6 @@ struct imx_nand_platform_data nand_info = { .hw_ecc = 1, }; -static struct device_d nand_dev = { - .id = -1, - .name = "imx_nand", - .map_base = 0xDF003000, - .platform_data = &nand_info, -}; - static struct device_d cs8900_dev = { .id = -1, .name = "cs8900", @@ -111,14 +105,6 @@ static struct imx_fb_platform_data imx_fb_data = { .dmacr = 0x00020008, }; -static struct device_d imxfb_dev = { - .id = -1, - .name = "imxfb", - .map_base = 0x10021000, - .size = 0x1000, - .platform_data = &imx_fb_data, -}; - static int imx21ads_timing_init(void) { u32 temp; @@ -199,9 +185,9 @@ static int mx21ads_devices_init(void) register_device(&cfi_dev); register_device(&sdram_dev); - register_device(&nand_dev); + imx21_add_nand(&nand_info); register_device(&cs8900_dev); - register_device(&imxfb_dev); + imx21_add_fb(&imx_fb_data); armlinux_add_dram(&sdram_dev); armlinux_set_bootparams((void *)0xc0000100); @@ -224,16 +210,9 @@ static int mx21ads_enable_display(void) late_initcall(mx21ads_enable_display); -static struct device_d mx21ads_serial_device = { - .id = -1, - .name = "imx_serial", - .map_base = IMX_UART1_BASE, - .size = 4096, -}; - static int mx21ads_console_init(void) { - register_device(&mx21ads_serial_device); + imx21_add_uart0(); return 0; } diff --git a/arch/arm/boards/imx27ads/imx27ads.c b/arch/arm/boards/imx27ads/imx27ads.c index ae5da7fd63..0d433c12e8 100644 --- a/arch/arm/boards/imx27ads/imx27ads.c +++ b/arch/arm/boards/imx27ads/imx27ads.c @@ -32,6 +32,7 @@ #include <fcntl.h> #include <generated/mach-types.h> #include <mach/iomux-mx27.h> +#include <mach/devices-imx27.h> static struct device_d cfi_dev = { .id = -1, @@ -58,13 +59,6 @@ static struct fec_platform_data fec_info = { .phy_addr = 1, }; -static struct device_d fec_dev = { - .id = -1, - .name = "fec_imx", - .map_base = 0x1002b000, - .platform_data = &fec_info, -}; - static int imx27ads_timing_init(void) { /* configure cpld on cs4 */ @@ -134,7 +128,7 @@ static int mx27ads_devices_init(void) register_device(&cfi_dev); register_device(&sdram_dev); - register_device(&fec_dev); + imx27_add_fec(&fec_info); devfs_add_partition("nor0", 0x00000, 0x20000, PARTITION_FIXED, "self0"); devfs_add_partition("nor0", 0x20000, 0x20000, PARTITION_FIXED, "env0"); @@ -149,16 +143,9 @@ static int mx27ads_devices_init(void) device_initcall(mx27ads_devices_init); -static struct device_d mx27ads_serial_device = { - .id = -1, - .name = "imx_serial", - .map_base = IMX_UART1_BASE, - .size = 4096, -}; - static int mx27ads_console_init(void) { - register_device(&mx27ads_serial_device); + imx27_add_uart0(); return 0; } diff --git a/arch/arm/boards/pcm037/env/config b/arch/arm/boards/pcm037/env/config index bf15620057..df2f694c88 100644 --- a/arch/arm/boards/pcm037/env/config +++ b/arch/arm/boards/pcm037/env/config @@ -50,6 +50,7 @@ rootfs_mtdblock_nor=3 nand_parts="256k(barebox)ro,128k(bareboxenv),2M(kernel),-(root)" rootfs_mtdblock_nand=7 +nand_device="mxc_nand" # set a fancy prompt (if support is compiled in) PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " diff --git a/arch/arm/boards/pcm037/pcm037.c b/arch/arm/boards/pcm037/pcm037.c index 89e248190a..ffecec21da 100644 --- a/arch/arm/boards/pcm037/pcm037.c +++ b/arch/arm/boards/pcm037/pcm037.c @@ -37,7 +37,7 @@ #include <partition.h> #include <generated/mach-types.h> #include <mach/imx-nand.h> - +#include <mach/devices-imx31.h> /* * Up to 32MiB NOR type flash, connected to @@ -126,13 +126,6 @@ struct imx_nand_platform_data nand_info = { .flash_bbt = 1, }; -static struct device_d nand_dev = { - .id = -1, - .name = "imx_nand", - .map_base = 0xB8000000, - .platform_data = &nand_info, -}; - #ifdef CONFIG_USB static struct device_d usbotg_dev = { .id = -1, @@ -295,7 +288,7 @@ static int imx31_devices_init(void) protect_file("/dev/env0", 1); register_device(&sram_dev); - register_device(&nand_dev); + imx31_add_nand(&nand_info); register_device(&network_dev); register_device(&sdram0_dev); @@ -320,13 +313,6 @@ static int imx31_devices_init(void) device_initcall(imx31_devices_init); -static struct device_d imx31_serial_device = { - .id = -1, - .name = "imx_serial", - .map_base = IMX_UART1_BASE, - .size = 16 * 1024, -}; - static int imx31_console_init(void) { /* init gpios for serial port */ @@ -335,7 +321,7 @@ static int imx31_console_init(void) imx_iomux_mode(MX31_PIN_CTS1__CTS1); imx_iomux_mode(MX31_PIN_RTS1__RTS1); - register_device(&imx31_serial_device); + imx31_add_uart0(); return 0; } diff --git a/arch/arm/boards/pcm038/pcm038.c b/arch/arm/boards/pcm038/pcm038.c index 3a9b41352b..1dbc6b6e10 100644 --- a/arch/arm/boards/pcm038/pcm038.c +++ b/arch/arm/boards/pcm038/pcm038.c @@ -43,6 +43,7 @@ #include <usb/isp1504.h> #include <mach/spi.h> #include <mach/iomux-mx27.h> +#include <mach/devices-imx27.h> #include "pll.h" @@ -84,13 +85,6 @@ static struct fec_platform_data fec_info = { .phy_addr = 1, }; -static struct device_d fec_dev = { - .id = -1, - .name = "fec_imx", - .map_base = 0x1002b000, - .platform_data = &fec_info, -}; - static int pcm038_spi_cs[] = {GPIO_PORTD + 28}; static struct spi_imx_master pcm038_spi_0_data = { @@ -98,13 +92,6 @@ static struct spi_imx_master pcm038_spi_0_data = { .num_chipselect = ARRAY_SIZE(pcm038_spi_cs), }; -static struct device_d spi_dev = { - .id = -1, - .name = "imx_spi", - .map_base = 0x1000e000, - .platform_data = &pcm038_spi_0_data, -}; - static struct spi_board_info pcm038_spi_board_info[] = { { .name = "mc13783", @@ -120,13 +107,6 @@ static struct imx_nand_platform_data nand_info = { .flash_bbt = 1, }; -static struct device_d nand_dev = { - .id = -1, - .name = "imx_nand", - .map_base = 0xd8000000, - .platform_data = &nand_info, -}; - static struct imx_fb_videomode imxfb_mode = { .mode = { .name = "Sharp-LQ035Q7", @@ -161,14 +141,6 @@ static struct imx_fb_platform_data pcm038_fb_data = { .dmacr = 0x00020010, }; -static struct device_d imxfb_dev = { - .id = -1, - .name = "imxfb", - .map_base = 0x10021000, - .size = 0x1000, - .platform_data = &pcm038_fb_data, -}; - #ifdef CONFIG_USB static struct device_d usbh2_dev = { .id = -1, @@ -323,13 +295,13 @@ static int pcm038_devices_init(void) gpio_direction_output(GPIO_PORTD | 28, 0); gpio_set_value(GPIO_PORTD | 28, 0); spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info)); - register_device(&spi_dev); + imx27_add_spi0(&pcm038_spi_0_data); register_device(&cfi_dev); - register_device(&nand_dev); + imx27_add_nand(&nand_info); register_device(&sdram_dev); register_device(&sram_dev); - register_device(&imxfb_dev); + imx27_add_fb(&pcm038_fb_data); #ifdef CONFIG_USB pcm038_usbh_init(); @@ -339,7 +311,7 @@ static int pcm038_devices_init(void) /* Register the fec device after the PLL re-initialisation * as the fec depends on the (now higher) ipg clock */ - register_device(&fec_dev); + imx27_add_fec(&fec_info); switch ((GPCR & GPCR_BOOT_MASK) >> GPCR_BOOT_SHIFT) { case GPCR_BOOT_8BIT_NAND_2k: @@ -372,16 +344,9 @@ static int pcm038_devices_init(void) device_initcall(pcm038_devices_init); -static struct device_d pcm038_serial_device = { - .id = -1, - .name = "imx_serial", - .map_base = IMX_UART1_BASE, - .size = 4096, -}; - static int pcm038_console_init(void) { - register_device(&pcm038_serial_device); + imx27_add_uart0(); return 0; } diff --git a/arch/arm/boards/pcm043/pcm043.c b/arch/arm/boards/pcm043/pcm043.c index 5932f954c3..2191bc8f19 100644 --- a/arch/arm/boards/pcm043/pcm043.c +++ b/arch/arm/boards/pcm043/pcm043.c @@ -43,6 +43,7 @@ #include <mach/imx-ipu-fb.h> #include <mach/imx-pll.h> #include <mach/iomux-mx35.h> +#include <mach/devices-imx35.h> /* * Up to 32MiB NOR type flash, connected to @@ -59,13 +60,6 @@ static struct fec_platform_data fec_info = { .xcv_type = MII100, }; -static struct device_d fec_dev = { - .id = -1, - .name = "fec_imx", - .map_base = IMX_FEC_BASE, - .platform_data = &fec_info, -}; - static struct memory_platform_data ram_pdata = { .name = "ram0", .flags = DEVFS_RDWR, @@ -85,13 +79,6 @@ struct imx_nand_platform_data nand_info = { .flash_bbt = 1, }; -static struct device_d nand_dev = { - .id = -1, - .name = "imx_nand", - .map_base = IMX_NFC_BASE, - .platform_data = &nand_info, -}; - #ifdef CONFIG_PCM043_DISPLAY_SHARP static struct fb_videomode pcm043_fb_mode = { /* 240x320 @ 60 Hz */ @@ -135,14 +122,6 @@ static struct imx_ipu_fb_platform_data ipu_fb_data = { .bpp = 16, }; -static struct device_d imx_ipu_fb_dev = { - .id = -1, - .name = "imx-ipu-fb", - .map_base = 0x53fc0000, - .size = 0x1000, - .platform_data = &ipu_fb_data, -}; - #ifdef CONFIG_MMU static int pcm043_mmu_init(void) { @@ -185,11 +164,11 @@ static int imx35_devices_init(void) else nand_info.width = 1; /* 8 bit */ - register_device(&fec_dev); + imx35_add_fec(&fec_info); /* * This platform supports NOR and NAND */ - register_device(&nand_dev); + imx35_add_nand(&nand_info); register_device(&cfi_dev); if ((reg & 0xc00) == 0x800) { /* reset mode: external boot */ @@ -210,7 +189,7 @@ static int imx35_devices_init(void) } register_device(&sdram0_dev); - register_device(&imx_ipu_fb_dev); + imx35_add_fb(&ipu_fb_data); armlinux_add_dram(&sdram0_dev); armlinux_set_bootparams((void *)0x80000100); @@ -221,13 +200,6 @@ static int imx35_devices_init(void) device_initcall(imx35_devices_init); -static struct device_d imx35_serial_device = { - .id = -1, - .name = "imx_serial", - .map_base = IMX_UART1_BASE, - .size = 16 * 1024, -}; - static struct pad_desc pcm043_pads[] = { MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, @@ -261,7 +233,7 @@ static int imx35_console_init(void) { mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads)); - register_device(&imx35_serial_device); + imx35_add_uart0(); return 0; } diff --git a/arch/arm/boards/phycard-i.MX27/pca100.c b/arch/arm/boards/phycard-i.MX27/pca100.c index 3a96180814..32f7e74e43 100644 --- a/arch/arm/boards/phycard-i.MX27/pca100.c +++ b/arch/arm/boards/phycard-i.MX27/pca100.c @@ -1,4 +1,4 @@ - /* +/* * Copyright (C) 2007 Sascha Hauer, Pengutronix * * This program is free software; you can redistribute it and/or @@ -39,6 +39,7 @@ #include <asm/mmu.h> #include <usb/isp1504.h> #include <mach/iomux-mx27.h> +#include <mach/devices-imx27.h> static struct memory_platform_data ram_pdata = { .name = "ram0", @@ -58,26 +59,12 @@ static struct fec_platform_data fec_info = { .phy_addr = 1, }; -static struct device_d fec_dev = { - .id = -1, - .name = "fec_imx", - .map_base = 0x1002b000, - .platform_data = &fec_info, -}; - struct imx_nand_platform_data nand_info = { .width = 1, .hw_ecc = 1, .flash_bbt = 1, }; -static struct device_d nand_dev = { - .id = -1, - .name = "imx_nand", - .map_base = 0xd8000000, - .platform_data = &nand_info, -}; - #ifdef CONFIG_USB static struct device_d usbh2_dev = { .id = -1, @@ -110,11 +97,6 @@ static void pca100_usbh_init(void) } #endif -static struct device_d mmc_dev = { - .name = "imx-mmc", - .map_base = 0x10014000, -}; - #ifdef CONFIG_MMU static void pca100_mmu_init(void) { @@ -207,10 +189,10 @@ static int pca100_devices_init(void) for (i = 0; i < ARRAY_SIZE(mode); i++) imx_gpio_mode(mode[i]); - register_device(&nand_dev); + imx27_add_nand(&nand_info); register_device(&sdram_dev); - register_device(&fec_dev); - register_device(&mmc_dev); + imx27_add_fec(&fec_info); + imx27_add_mmc0(NULL); PCCR1 |= PCCR1_PERCLK2_EN; diff --git a/arch/arm/boards/pm9261/Makefile b/arch/arm/boards/pm9261/Makefile new file mode 100644 index 0000000000..eb072c0161 --- /dev/null +++ b/arch/arm/boards/pm9261/Makefile @@ -0,0 +1 @@ +obj-y += init.o diff --git a/arch/arm/boards/pm9261/config.h b/arch/arm/boards/pm9261/config.h new file mode 100644 index 0000000000..97f8efc0ca --- /dev/null +++ b/arch/arm/boards/pm9261/config.h @@ -0,0 +1,110 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ + +#define MASTER_PLL_DIV 15 +#define MASTER_PLL_MUL 162 +#define MAIN_PLL_DIV 2 + +/* clocks */ +#define CONFIG_SYS_MOR_VAL \ + (AT91_PMC_MOSCEN | \ + (255 << 8)) /* Main Oscillator Start-up Time */ +#define CONFIG_SYS_PLLAR_VAL \ + (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \ + AT91_PMC_OUT | \ + ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) + +/* PCK/2 = MCK Master Clock from PLLA */ +#define CONFIG_SYS_MCKR1_VAL \ + (AT91_PMC_CSS_SLOW | \ + AT91_PMC_PRES_1 | \ + AT91SAM9_PMC_MDIV_2 | \ + AT91_PMC_PDIV_1) + +/* PCK/2 = MCK Master Clock from PLLA */ +#define CONFIG_SYS_MCKR2_VAL \ + (AT91_PMC_CSS_PLLA | \ + AT91_PMC_PRES_1 | \ + AT91SAM9_PMC_MDIV_2 | \ + AT91_PMC_PDIV_1) + +/* define PDC[31:16] as DATA[31:16] */ +#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000 +/* no pull-up for D[31:16] */ +#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000 + +/* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */ +#define CONFIG_SYS_MATRIX_EBICSA_VAL \ + (AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC) + +/* SDRAM */ +/* SDRAMC_MR Mode register */ +#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL +/* SDRAMC_TR - Refresh Timer register */ +#define CONFIG_SYS_SDRC_TR_VAL1 0x13C +/* SDRAMC_CR - Configuration register*/ +#define CONFIG_SYS_SDRC_CR_VAL \ + (AT91_SDRAMC_NC_9 | \ + AT91_SDRAMC_NR_13 | \ + AT91_SDRAMC_NB_4 | \ + AT91_SDRAMC_CAS_3 | \ + AT91_SDRAMC_DBW_32 | \ + (1 << 8) | /* Write Recovery Delay */ \ + (7 << 12) | /* Row Cycle Delay */ \ + (3 << 16) | /* Row Precharge Delay */ \ + (2 << 20) | /* Row to Column Delay */ \ + (5 << 24) | /* Active to Precharge Delay */ \ + (1 << 28)) /* Exit Self Refresh to Active Delay */ + +/* Memory Device Register -> SDRAM */ +#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM +#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE +#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH +#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR +#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL +#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ +#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ + +/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ +#define CONFIG_SYS_SMC0_SETUP0_VAL \ + (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \ + AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10)) +#define CONFIG_SYS_SMC0_PULSE0_VAL \ + (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \ + AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11)) +#define CONFIG_SYS_SMC0_CYCLE0_VAL \ + (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22)) +#define CONFIG_SYS_SMC0_MODE0_VAL \ + (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ + AT91_SMC_DBW_16 | \ + AT91_SMC_TDFMODE | \ + AT91_SMC_TDF_(6)) + +/* user reset enable */ +#define CONFIG_SYS_RSTC_RMR_VAL \ + (AT91_RSTC_KEY | \ + AT91_RSTC_PROCRST | \ + AT91_RSTC_RSTTYP_WAKEUP | \ + AT91_RSTC_RSTTYP_WATCHDOG) + +/* Disable Watchdog */ +#define CONFIG_SYS_WDTC_WDMR_VAL \ + (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \ + AT91_WDT_WDV | \ + AT91_WDT_WDDIS | \ + AT91_WDT_WDD) + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/pm9261/env/config b/arch/arm/boards/pm9261/env/config new file mode 100644 index 0000000000..f7e133ecf9 --- /dev/null +++ b/arch/arm/boards/pm9261/env/config @@ -0,0 +1,41 @@ +#!/bin/sh + +# use 'dhcp' to do dhcp in barebox and in kernel +# use 'none' if you want to skip kernel ip autoconfiguration +ip=dhcp + +# or set your networking parameters here +#eth0.ipaddr=a.b.c.d +#eth0.netmask=a.b.c.d +#eth0.gateway=a.b.c.d +#eth0.serverip=a.b.c.d + +# can be either 'net' or 'nand' +kernel_loc=net +# can be either 'net', 'nand' or 'initrd' +rootfs_loc=net + +# can be either 'jffs2' or 'ubifs' +rootfs_type=ubifs +rootfsimage=root.$rootfs_type + +# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo +#kernelimage_type=zimage +#kernelimage=zImage +kernelimage_type=uimage +kernelimage=uImage +#kernelimage_type=raw +#kernelimage=Image +#kernelimage_type=raw_lzo +#kernelimage=Image.lzo + +nor_parts="256k(barebox)ro,64k(bareboxenv),1536k(kernel),-(root)" +rootfs_mtdblock_nor=3 + +autoboot_timeout=3 + +bootargs="console=ttyS0,115200" + +# set a fancy prompt (if support is compiled in) +PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " + diff --git a/arch/arm/boards/pm9261/init.c b/arch/arm/boards/pm9261/init.c new file mode 100644 index 0000000000..6fb14f7bce --- /dev/null +++ b/arch/arm/boards/pm9261/init.c @@ -0,0 +1,168 @@ +/* + * Copyright (C) 2007 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <net.h> +#include <init.h> +#include <environment.h> +#include <asm/armlinux.h> +#include <generated/mach-types.h> +#include <partition.h> +#include <fs.h> +#include <fcntl.h> +#include <asm/io.h> +#include <asm/hardware.h> +#include <nand.h> +#include <linux/mtd/nand.h> +#include <mach/at91_pmc.h> +#include <mach/board.h> +#include <mach/gpio.h> +#include <mach/io.h> +#include <mach/at91sam9_smc.h> +#include <mach/sam9_smc.h> +#include <dm9000.h> + +static struct atmel_nand_data nand_pdata = { + .ale = 22, + .cle = 21, +/* .det_pin = ... not connected */ + .rdy_pin = AT91_PIN_PA16, + .enable_pin = AT91_PIN_PC14, +#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16) + .bus_width_16 = 1, +#else + .bus_width_16 = 0, +#endif +}; + +static struct sam9_smc_config pm_nand_smc_config = { + .ncs_read_setup = 0, + .nrd_setup = 1, + .ncs_write_setup = 0, + .nwe_setup = 1, + + .ncs_read_pulse = 3, + .nrd_pulse = 3, + .ncs_write_pulse = 3, + .nwe_pulse = 3, + + .read_cycle = 5, + .write_cycle = 5, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE, + .tdf_cycles = 2, +}; + +static void pm_add_device_nand(void) +{ + /* setup bus-width (8 or 16) */ + if (nand_pdata.bus_width_16) + pm_nand_smc_config.mode |= AT91_SMC_DBW_16; + else + pm_nand_smc_config.mode |= AT91_SMC_DBW_8; + + /* configure chip-select 3 (NAND) */ + sam9_smc_configure(3, &pm_nand_smc_config); + + at91_add_device_nand(&nand_pdata); +} + +/* + * DM9000 ethernet device + */ +#if defined(CONFIG_DRIVER_NET_DM9000) +static struct dm9000_platform_data dm9000_data = { + .iobase = AT91_CHIPSELECT_2, + .iodata = AT91_CHIPSELECT_2 + 4, + .buswidth = DM9000_WIDTH_16, + .srom = 1, +}; + +static struct device_d dm9000_dev = { + .id = 0, + .name = "dm9000", + .map_base = AT91_CHIPSELECT_2, + .size = 8, + .platform_data = &dm9000_data, +}; + +/* + * SMC timings for the DM9000. + * Note: These timings were calculated for MASTER_CLOCK = 100000000 according to the DM9000 timings. + */ +static struct sam9_smc_config __initdata dm9000_smc_config = { + .ncs_read_setup = 0, + .nrd_setup = 2, + .ncs_write_setup = 0, + .nwe_setup = 2, + + .ncs_read_pulse = 8, + .nrd_pulse = 4, + .ncs_write_pulse = 8, + .nwe_pulse = 4, + + .read_cycle = 16, + .write_cycle = 16, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16, + .tdf_cycles = 1, +}; + +static void __init pm_add_device_dm9000(void) +{ + /* Configure chip-select 2 (DM9000) */ + sam9_smc_configure(2, &dm9000_smc_config); + + register_device(&dm9000_dev); +} +#else +static void __init ek_add_device_dm9000(void) {} +#endif /* CONFIG_DRIVER_NET_DM9000 */ + +static struct device_d cfi_dev = { + .id = 0, + .name = "cfi_flash", + .map_base = AT91_CHIPSELECT_0, + .size = 4 * 1024 * 1024, +}; + +static int pm9261_devices_init(void) +{ + at91_add_device_sdram(64 * 1024 * 1024); + pm_add_device_nand(); + register_device(&cfi_dev); + pm_add_device_dm9000(); + + devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self"); + devfs_add_partition("nor0", 0x40000, 0x10000, PARTITION_FIXED, "env0"); + + armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100)); + armlinux_set_architecture(MACH_TYPE_PM9261); + + return 0; +} +device_initcall(pm9261_devices_init); + +static int pm9261_console_init(void) +{ + at91_register_uart(0, 0); + return 0; +} +console_initcall(pm9261_console_init); diff --git a/arch/arm/boards/pm9g45/Makefile b/arch/arm/boards/pm9g45/Makefile new file mode 100644 index 0000000000..eb072c0161 --- /dev/null +++ b/arch/arm/boards/pm9g45/Makefile @@ -0,0 +1 @@ +obj-y += init.o diff --git a/arch/arm/boards/pm9g45/config.h b/arch/arm/boards/pm9g45/config.h new file mode 100644 index 0000000000..ac3114d865 --- /dev/null +++ b/arch/arm/boards/pm9g45/config.h @@ -0,0 +1,6 @@ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/pm9g45/env/config b/arch/arm/boards/pm9g45/env/config new file mode 100644 index 0000000000..3b922339fa --- /dev/null +++ b/arch/arm/boards/pm9g45/env/config @@ -0,0 +1,41 @@ +#!/bin/sh + +# use 'dhcp' to do dhcp in barebox and in kernel +# use 'none' if you want to skip kernel ip autoconfiguration +ip=dhcp + +# or set your networking parameters here +#eth0.ipaddr=a.b.c.d +#eth0.netmask=a.b.c.d +#eth0.gateway=a.b.c.d +#eth0.serverip=a.b.c.d + +# can be either 'net' or 'nand' +kernel_loc=net +# can be either 'net', 'nand' or 'initrd' +rootfs_loc=net + +# can be either 'jffs2' or 'ubifs' +rootfs_type=ubifs +rootfsimage=root.$rootfs_type + +# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo +#kernelimage_type=zimage +#kernelimage=zImage +kernelimage_type=uimage +kernelimage=uImage +#kernelimage_type=raw +#kernelimage=Image +#kernelimage_type=raw_lzo +#kernelimage=Image.lzo + +nand_parts="256k(barebox)ro,64k(bareboxenv),1536k(kernel),-(root)" +rootfs_mtdblock_nand=3 + +autoboot_timeout=3 + +bootargs="console=ttyS0,115200" + +# set a fancy prompt (if support is compiled in) +PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " + diff --git a/arch/arm/boards/pm9g45/init.c b/arch/arm/boards/pm9g45/init.c new file mode 100644 index 0000000000..8031ce5b64 --- /dev/null +++ b/arch/arm/boards/pm9g45/init.c @@ -0,0 +1,108 @@ +/* + * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> + * + * Copyright (C) 2007 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <net.h> +#include <init.h> +#include <environment.h> +#include <asm/armlinux.h> +#include <generated/mach-types.h> +#include <partition.h> +#include <fs.h> +#include <fcntl.h> +#include <asm/io.h> +#include <asm/hardware.h> +#include <nand.h> +#include <linux/mtd/nand.h> +#include <mach/at91_pmc.h> +#include <mach/board.h> +#include <mach/gpio.h> +#include <mach/io.h> +#include <mach/at91sam9_smc.h> +#include <mach/sam9_smc.h> + +static struct atmel_nand_data nand_pdata = { + .ale = 21, + .cle = 22, +/* .det_pin = ... not connected */ + .rdy_pin = AT91_PIN_PD3, + .enable_pin = AT91_PIN_PC14, + .bus_width_16 = 0, +}; + +static struct sam9_smc_config pm_nand_smc_config = { + .ncs_read_setup = 0, + .nrd_setup = 1, + .ncs_write_setup = 0, + .nwe_setup = 1, + + .ncs_read_pulse = 2, + .nrd_pulse = 3, + .ncs_write_pulse = 3, + .nwe_pulse = 4, + + .read_cycle = 4, + .write_cycle = 7, + + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE, + .tdf_cycles = 3, +}; + +static void pm_add_device_nand(void) +{ + pm_nand_smc_config.mode |= AT91_SMC_DBW_8; + + /* configure chip-select 3 (NAND) */ + sam9_smc_configure(3, &pm_nand_smc_config); + + at91_add_device_nand(&nand_pdata); +} + +static struct at91_ether_platform_data macb_pdata = { + .flags = AT91SAM_ETHER_RMII, + .phy_addr = 0, +}; + +static int pm9g45_devices_init(void) +{ + at91_add_device_sdram(128 * 1024 * 1024); + pm_add_device_nand(); + at91_add_device_eth(&macb_pdata); + + devfs_add_partition("nand0", 0x00000, 0x80000, PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + devfs_add_partition("nand0", 0x40000, 0x40000, PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); + + armlinux_set_bootparams((void *)(AT91_CHIPSELECT_6 + 0x100)); + armlinux_set_architecture(MACH_TYPE_PM9G45); + + return 0; +} +device_initcall(pm9g45_devices_init); + +static int pm9g45_console_init(void) +{ + at91_register_uart(0, 0); + return 0; +} +console_initcall(pm9g45_console_init); diff --git a/arch/arm/configs/at91sam9261ek_defconfig b/arch/arm/configs/at91sam9261ek_defconfig new file mode 100644 index 0000000000..c753eb38f2 --- /dev/null +++ b/arch/arm/configs/at91sam9261ek_defconfig @@ -0,0 +1,49 @@ +CONFIG_ARCH_AT91SAM9261=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_PROMPT="9261-EK:" +CONFIG_LONGHELP=y +CONFIG_GLOB=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +CONFIG_PARTITION=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/at91sam9261ek/env" +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_LOADENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_MENU=y +CONFIG_CMD_MENU_MANAGEMENT=y +CONFIG_CMD_PASSWD=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MTEST=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_BOOTM_ZLIB=y +CONFIG_CMD_BOOTM_BZLIB=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_UNLZO=y +CONFIG_NET=y +CONFIG_NET_DHCP=y +CONFIG_NET_NFS=y +CONFIG_NET_PING=y +CONFIG_NET_TFTP=y +CONFIG_NET_TFTP_PUSH=y +CONFIG_NET_RESOLV=y +CONFIG_DRIVER_NET_DM9000=y +# CONFIG_SPI is not set +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_NAND_ATMEL=y +CONFIG_UBI=y diff --git a/arch/m68k/configs/phycore_kpukdr1_5475num_defconfig b/arch/arm/configs/at91sam9g10ek_defconfig index 14c6d78f9f..d39639ae58 100644 --- a/arch/m68k/configs/phycore_kpukdr1_5475num_defconfig +++ b/arch/arm/configs/at91sam9g10ek_defconfig @@ -1,13 +1,13 @@ -CONFIG_MACH_KPUKDR1_NUM=y -CONFIG_INITRD_TAG=y -CONFIG_BROKEN=y -CONFIG_EXPERIMENTAL=y +CONFIG_ARCH_AT91SAM9G10=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_PROMPT="9G10-EK:" CONFIG_LONGHELP=y +CONFIG_GLOB=y CONFIG_CMDLINE_EDITING=y CONFIG_AUTO_COMPLETE=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/m68k/boards/kp_ukd_r1_num/env/" -CONFIG_DEBUG_INFO=y -CONFIG_ENABLE_DEVICE_NOISE=y +CONFIG_PARTITION=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/at91sam9261ek/env" CONFIG_CMD_EDIT=y CONFIG_CMD_SLEEP=y CONFIG_CMD_SAVEENV=y @@ -18,7 +18,6 @@ CONFIG_CMD_READLINE=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_CRC=y CONFIG_CMD_MTEST=y -CONFIG_CMD_MTEST_ALTERNATIVE=y CONFIG_CMD_FLASH=y CONFIG_CMD_BOOTM_ZLIB=y CONFIG_CMD_BOOTM_BZLIB=y @@ -27,10 +26,16 @@ CONFIG_CMD_RESET=y CONFIG_CMD_GO=y CONFIG_CMD_TIMEOUT=y CONFIG_CMD_PARTITION=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_UNLZO=y CONFIG_NET=y CONFIG_NET_DHCP=y +CONFIG_NET_NFS=y CONFIG_NET_PING=y CONFIG_NET_TFTP=y -CONFIG_DRIVER_CFI=y -CONFIG_CFI_BUFFER_WRITE=y -CONFIG_FS_CRAMFS=y +CONFIG_DRIVER_NET_DM9000=y +# CONFIG_SPI is not set +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_NAND_ATMEL=y +CONFIG_UBI=y diff --git a/arch/arm/configs/at91sam9m10g45ek_defconfig b/arch/arm/configs/at91sam9m10g45ek_defconfig new file mode 100644 index 0000000000..e1c6cef4da --- /dev/null +++ b/arch/arm/configs/at91sam9m10g45ek_defconfig @@ -0,0 +1,55 @@ +CONFIG_ARCH_AT91SAM9G45=y +CONFIG_MACH_AT91SAM9M10G45EK=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_PROMPT="9M10G45-EK:" +CONFIG_LONGHELP=y +CONFIG_GLOB=y +CONFIG_PROMPT_HUSH_PS2="y" +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +CONFIG_PASSWD_SUM_SHA1=y +CONFIG_PARTITION=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/at91sam9m10g45ek/env" +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_LOADENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_MENU=y +CONFIG_CMD_MENU_MANAGEMENT=y +CONFIG_CMD_PASSWD=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MTEST=y +CONFIG_CMD_MTEST_ALTERNATIVE=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_BOOTM_ZLIB=y +CONFIG_CMD_BOOTM_BZLIB=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_UNLZO=y +CONFIG_NET=y +CONFIG_NET_DHCP=y +CONFIG_NET_NFS=y +CONFIG_NET_PING=y +CONFIG_NET_TFTP=y +CONFIG_NET_TFTP_PUSH=y +CONFIG_NET_NETCONSOLE=y +CONFIG_NET_RESOLV=y +CONFIG_DRIVER_NET_MACB=y +# CONFIG_SPI is not set +CONFIG_DRIVER_CFI=y +CONFIG_CFI_BUFFER_WRITE=y +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_UBI=y diff --git a/arch/arm/configs/pcm037_defconfig b/arch/arm/configs/pcm037_defconfig index e12f690f26..b8ba53ce55 100644 --- a/arch/arm/configs/pcm037_defconfig +++ b/arch/arm/configs/pcm037_defconfig @@ -21,13 +21,13 @@ CONFIG_CMD_PRINTENV=y CONFIG_CMD_READLINE=y CONFIG_CMD_ECHO_E=y CONFIG_CMD_MEMINFO=y -CONFIG_CMD_CRC=y CONFIG_CMD_FLASH=y CONFIG_CMD_RESET=y CONFIG_CMD_GO=y CONFIG_CMD_TIMEOUT=y CONFIG_CMD_PARTITION=y CONFIG_CMD_GPIO=y +CONFIG_CMD_UNLZO=y CONFIG_NET=y CONFIG_NET_DHCP=y CONFIG_NET_PING=y @@ -39,5 +39,9 @@ CONFIG_NET_USB=y CONFIG_NET_USB_ASIX=y CONFIG_DRIVER_CFI=y CONFIG_CFI_BUFFER_WRITE=y +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_NAND_IMX=y +CONFIG_UBI=y CONFIG_USB=y CONFIG_USB_EHCI=y diff --git a/arch/arm/configs/pm9261_defconfig b/arch/arm/configs/pm9261_defconfig new file mode 100644 index 0000000000..0bd9483e75 --- /dev/null +++ b/arch/arm/configs/pm9261_defconfig @@ -0,0 +1,52 @@ +CONFIG_ARCH_AT91SAM9261=y +CONFIG_MACH_PM9261=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_PROMPT="PM9261:" +CONFIG_LONGHELP=y +CONFIG_GLOB=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +CONFIG_PARTITION=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/pm9261/env/" +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_LOADENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_MENU=y +CONFIG_CMD_MENU_MANAGEMENT=y +CONFIG_CMD_PASSWD=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MTEST=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_BOOTM_ZLIB=y +CONFIG_CMD_BOOTM_BZLIB=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_UNLZO=y +CONFIG_NET=y +CONFIG_NET_DHCP=y +CONFIG_NET_NFS=y +CONFIG_NET_PING=y +CONFIG_NET_TFTP=y +CONFIG_NET_TFTP_PUSH=y +CONFIG_NET_RESOLV=y +CONFIG_DRIVER_NET_DM9000=y +# CONFIG_SPI is not set +CONFIG_DRIVER_CFI=y +CONFIG_CFI_BUFFER_WRITE=y +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_NAND_ATMEL=y +CONFIG_UBI=y diff --git a/arch/arm/configs/pm9g45_defconfig b/arch/arm/configs/pm9g45_defconfig new file mode 100644 index 0000000000..20bfd718fe --- /dev/null +++ b/arch/arm/configs/pm9g45_defconfig @@ -0,0 +1,55 @@ +CONFIG_ARCH_AT91SAM9G45=y +CONFIG_MACH_PM9G45=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_PROMPT="pm9g45:" +CONFIG_LONGHELP=y +CONFIG_GLOB=y +CONFIG_PROMPT_HUSH_PS2="y" +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +CONFIG_PASSWD_SUM_SHA1=y +CONFIG_PARTITION=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/pm9g45/env" +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_LOADENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_MENU=y +CONFIG_CMD_MENU_MANAGEMENT=y +CONFIG_CMD_PASSWD=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MTEST=y +CONFIG_CMD_MTEST_ALTERNATIVE=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_BOOTM_ZLIB=y +CONFIG_CMD_BOOTM_BZLIB=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_UNLZO=y +CONFIG_NET=y +CONFIG_NET_DHCP=y +CONFIG_NET_NFS=y +CONFIG_NET_PING=y +CONFIG_NET_TFTP=y +CONFIG_NET_TFTP_PUSH=y +CONFIG_NET_NETCONSOLE=y +CONFIG_NET_RESOLV=y +CONFIG_DRIVER_NET_MACB=y +# CONFIG_SPI is not set +CONFIG_DRIVER_CFI=y +CONFIG_CFI_BUFFER_WRITE=y +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_UBI=y diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 1491161d6f..e5bd45e191 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -6,10 +6,15 @@ config ARCH_TEXT_BASE config BOARDINFO default "Atmel 91SAM9260-EK" if MACH_AT91SAM9260EK + default "Atmel at91sam9261-ek" if MACH_AT91SAM9261EK default "Atmel at91sam9263-ek" if MACH_AT91SAM9263EK + default "Atmel at91sam9g10-ek" if MACH_AT91SAM9G10EK default "Atmel at91sam9g20-ek" if MACH_AT91SAM9G20EK + default "Atmel at91sam9m10g45-ek" if MACH_AT91SAM9M10G45EK default "Bucyrus MMC-CPU" if MACH_MMCCPU + default "Ronetix PM9261" if MACH_PM9261 default "Ronetix PM9263" if MACH_PM9263 + default "Ronetix PM9G45" if MACH_PM9G45 config HAVE_NAND_ATMEL_BUSWIDTH_16 bool @@ -24,16 +29,29 @@ config ARCH_AT91SAM9260 select CPU_ARM926T select HAS_MACB +config ARCH_AT91SAM9261 + bool "AT91SAM9261" + select CPU_ARM926T + config ARCH_AT91SAM9263 bool "AT91SAM9263" select CPU_ARM926T select HAS_MACB +config ARCH_AT91SAM9G10 + bool "AT91SAM9G10" + select CPU_ARM926T + config ARCH_AT91SAM9G20 bool "AT91SAM9G20" select CPU_ARM926T select HAS_MACB +config ARCH_AT91SAM9G45 + bool "AT91SAM9G45 or AT91SAM9M10" + select CPU_ARM926T + select HAS_MACB + endchoice # ---------------------------------------------------------- @@ -56,6 +74,51 @@ endif # ---------------------------------------------------------- +if ARCH_AT91SAM9261 + +choice + prompt "AT91SAM9261 Board Type" + +config MACH_AT91SAM9261EK + bool "Atmel AT91SAM9261-EK Evaluation Kit" + select HAS_DM9000 + select HAVE_NAND_ATMEL_BUSWIDTH_16 + help + Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit. + <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820> + +config MACH_PM9261 + bool "Ronetix PM9261" + select HAS_DM9000 + select MACH_HAS_LOWLEVEL_INIT + help + Say y here if you are using the Ronetix PM9261 Board + +endchoice + +endif + +# ---------------------------------------------------------- + +if ARCH_AT91SAM9G10 + +choice + prompt "AT91SAM9G10 Board Type" + +config MACH_AT91SAM9G10EK + bool "Atmel AT91SAM9G10-EK Evaluation Kit" + select HAVE_NAND_ATMEL_BUSWIDTH_16 + select HAS_DM9000 + help + Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit. + <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588> + +endchoice + +endif + +# ---------------------------------------------------------- + if ARCH_AT91SAM9G20 choice @@ -102,6 +165,27 @@ endchoice endif +if ARCH_AT91SAM9G45 + +choice + prompt "AT91SAM9G45 or AT91SAM9M10 Board Type" + +config MACH_AT91SAM9M10G45EK + bool "Atmel AT91SAM9M10G45-EK Evaluation Kit" + select HAVE_NAND_ATMEL_BUSWIDTH_16 + help + Select this if you are using Atmel's AT91SAM9M10G45-EK Evaluation Kit. + <http://atmel.com/dyn/products/tools_card_v2.asp?tool_id=4735> + +config MACH_PM9G45 + bool "Ronetix PM9G45" + help + Say y here if you are using the Ronetix PM9G45 Board + +endchoice + +endif + # ---------------------------------------------------------- comment "AT91 Board Options" diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 1bedadbb66..d57c8f5e2d 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -4,5 +4,8 @@ obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o # CPU-specific support obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o +obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o +obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o +obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c index c6ddb13b54..fc8f82890e 100644 --- a/arch/arm/mach-at91/at91sam9260_devices.c +++ b/arch/arm/mach-at91/at91sam9260_devices.c @@ -120,7 +120,7 @@ void at91_add_device_nand(struct atmel_nand_data *data) {} #endif static struct device_d dbgu_serial_device = { - .id = -1, + .id = 0, .name = "atmel_serial", .map_base = AT91_BASE_SYS + AT91_DBGU, .size = 4096, @@ -133,7 +133,7 @@ static inline void configure_dbgu_pins(void) } static struct device_d uart0_serial_device = { - .id = -1, + .id = 1, .name = "atmel_serial", .map_base = AT91SAM9260_BASE_US0, .size = 4096, @@ -159,7 +159,7 @@ static inline void configure_usart0_pins(unsigned pins) } static struct device_d uart1_serial_device = { - .id = -1, + .id = 2, .name = "atmel_serial", .map_base = AT91SAM9260_BASE_US1, .size = 4096, @@ -177,7 +177,7 @@ static inline void configure_usart1_pins(unsigned pins) } static struct device_d uart2_serial_device = { - .id = -1, + .id = 3, .name = "atmel_serial", .map_base = AT91SAM9260_BASE_US2, .size = 4096, @@ -195,7 +195,7 @@ static inline void configure_usart2_pins(unsigned pins) } static struct device_d uart3_serial_device = { - .id = -1, + .id = 4, .name = "atmel_serial", .map_base = AT91SAM9260_BASE_US3, .size = 4096, @@ -213,7 +213,7 @@ static inline void configure_usart3_pins(unsigned pins) } static struct device_d uart4_serial_device = { - .id = -1, + .id = 5, .name = "atmel_serial", .map_base = AT91SAM9260_BASE_US4, .size = 4096, @@ -226,7 +226,7 @@ static inline void configure_usart4_pins(void) } static struct device_d uart5_serial_device = { - .id = -1, + .id = 6, .name = "atmel_serial", .map_base = AT91SAM9260_BASE_US5, .size = 4096, diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c new file mode 100644 index 0000000000..3d503aa201 --- /dev/null +++ b/arch/arm/mach-at91/at91sam9261.c @@ -0,0 +1,230 @@ +#include <common.h> +#include <gpio.h> +#include <init.h> +#include <asm/hardware.h> +#include <mach/at91_pmc.h> + +#include "generic.h" +#include "clock.h" + +/* -------------------------------------------------------------------- + * Clocks + * -------------------------------------------------------------------- */ + +/* + * The peripheral clocks. + */ +static struct clk pioA_clk = { + .name = "pioA_clk", + .pmc_mask = 1 << AT91SAM9261_ID_PIOA, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pioB_clk = { + .name = "pioB_clk", + .pmc_mask = 1 << AT91SAM9261_ID_PIOB, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pioC_clk = { + .name = "pioC_clk", + .pmc_mask = 1 << AT91SAM9261_ID_PIOC, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart0_clk = { + .name = "usart0_clk", + .pmc_mask = 1 << AT91SAM9261_ID_US0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart1_clk = { + .name = "usart1_clk", + .pmc_mask = 1 << AT91SAM9261_ID_US1, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart2_clk = { + .name = "usart2_clk", + .pmc_mask = 1 << AT91SAM9261_ID_US2, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk mmc_clk = { + .name = "mci_clk", + .pmc_mask = 1 << AT91SAM9261_ID_MCI, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk udc_clk = { + .name = "udc_clk", + .pmc_mask = 1 << AT91SAM9261_ID_UDP, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk twi_clk = { + .name = "twi_clk", + .pmc_mask = 1 << AT91SAM9261_ID_TWI, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk spi0_clk = { + .name = "spi0_clk", + .pmc_mask = 1 << AT91SAM9261_ID_SPI0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk spi1_clk = { + .name = "spi1_clk", + .pmc_mask = 1 << AT91SAM9261_ID_SPI1, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk ssc0_clk = { + .name = "ssc0_clk", + .pmc_mask = 1 << AT91SAM9261_ID_SSC0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk ssc1_clk = { + .name = "ssc1_clk", + .pmc_mask = 1 << AT91SAM9261_ID_SSC1, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk ssc2_clk = { + .name = "ssc2_clk", + .pmc_mask = 1 << AT91SAM9261_ID_SSC2, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk tc0_clk = { + .name = "tc0_clk", + .pmc_mask = 1 << AT91SAM9261_ID_TC0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk tc1_clk = { + .name = "tc1_clk", + .pmc_mask = 1 << AT91SAM9261_ID_TC1, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk tc2_clk = { + .name = "tc2_clk", + .pmc_mask = 1 << AT91SAM9261_ID_TC2, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk ohci_clk = { + .name = "ohci_clk", + .pmc_mask = 1 << AT91SAM9261_ID_UHP, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk lcdc_clk = { + .name = "lcdc_clk", + .pmc_mask = 1 << AT91SAM9261_ID_LCDC, + .type = CLK_TYPE_PERIPHERAL, +}; + +static struct clk *periph_clocks[] = { + &pioA_clk, + &pioB_clk, + &pioC_clk, + &usart0_clk, + &usart1_clk, + &usart2_clk, + &mmc_clk, + &udc_clk, + &twi_clk, + &spi0_clk, + &spi1_clk, + &ssc0_clk, + &ssc1_clk, + &ssc2_clk, + &tc0_clk, + &tc1_clk, + &tc2_clk, + &ohci_clk, + &lcdc_clk, + // irq0 .. irq2 +}; + +/* + * The four programmable clocks. + * You must configure pin multiplexing to bring these signals out. + */ +static struct clk pck0 = { + .name = "pck0", + .pmc_mask = AT91_PMC_PCK0, + .type = CLK_TYPE_PROGRAMMABLE, + .id = 0, +}; +static struct clk pck1 = { + .name = "pck1", + .pmc_mask = AT91_PMC_PCK1, + .type = CLK_TYPE_PROGRAMMABLE, + .id = 1, +}; +static struct clk pck2 = { + .name = "pck2", + .pmc_mask = AT91_PMC_PCK2, + .type = CLK_TYPE_PROGRAMMABLE, + .id = 2, +}; +static struct clk pck3 = { + .name = "pck3", + .pmc_mask = AT91_PMC_PCK3, + .type = CLK_TYPE_PROGRAMMABLE, + .id = 3, +}; + +/* HClocks */ +static struct clk hck0 = { + .name = "hck0", + .pmc_mask = AT91_PMC_HCK0, + .type = CLK_TYPE_SYSTEM, + .id = 0, +}; +static struct clk hck1 = { + .name = "hck1", + .pmc_mask = AT91_PMC_HCK1, + .type = CLK_TYPE_SYSTEM, + .id = 1, +}; + +static void at91sam9261_register_clocks(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) + clk_register(periph_clocks[i]); + + clk_register(&pck0); + clk_register(&pck1); + clk_register(&pck2); + clk_register(&pck3); + + clk_register(&hck0); + clk_register(&hck1); +} + + +/* -------------------------------------------------------------------- + * GPIO + * -------------------------------------------------------------------- */ + +static struct at91_gpio_bank at91sam9261_gpio[] = { + { + .id = AT91SAM9261_ID_PIOA, + .offset = AT91_PIOA, + .clock = &pioA_clk, + }, { + .id = AT91SAM9261_ID_PIOB, + .offset = AT91_PIOB, + .clock = &pioB_clk, + }, { + .id = AT91SAM9261_ID_PIOC, + .offset = AT91_PIOC, + .clock = &pioC_clk, + } +}; + + +static int at91sam9261_initialize(void) +{ + /* Init clock subsystem */ + at91_clock_init(AT91_MAIN_CLOCK); + + /* Register the processor-specific clocks */ + at91sam9261_register_clocks(); + + /* Register GPIO subsystem */ + at91_gpio_init(at91sam9261_gpio, 3); + return 0; +} + +core_initcall(at91sam9261_initialize); diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c new file mode 100644 index 0000000000..45bfb23ed1 --- /dev/null +++ b/arch/arm/mach-at91/at91sam9261_devices.c @@ -0,0 +1,175 @@ +/* + * arch/arm/mach-at91/at91sam9261_devices.c + * + * Copyright (C) 2006 Atmel + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ +#include <common.h> +#include <asm/armlinux.h> +#include <asm/hardware.h> +#include <mach/at91_pmc.h> +#include <mach/at91sam9261_matrix.h> +#include <mach/board.h> +#include <mach/gpio.h> +#include <mach/io.h> + +#include "generic.h" + +static struct memory_platform_data ram_pdata = { + .name = "ram0", + .flags = DEVFS_RDWR, +}; + +static struct device_d sdram_dev = { + .id = 0, + .name = "mem", + .map_base = AT91_CHIPSELECT_1, + .platform_data = &ram_pdata, +}; + +void at91_add_device_sdram(u32 size) +{ + sdram_dev.size = size; + register_device(&sdram_dev); + armlinux_add_dram(&sdram_dev); +} + +#if defined(CONFIG_NAND_ATMEL) +static struct device_d nand_dev = { + .id = 0, + .name = "atmel_nand", + .map_base = AT91_CHIPSELECT_3, + .size = 0x10, +}; + +void at91_add_device_nand(struct atmel_nand_data *data) +{ + unsigned long csa; + + if (!data) + return; + + csa = at91_sys_read(AT91_MATRIX_EBICSA); + at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); + + /* enable pin */ + if (data->enable_pin) + at91_set_gpio_output(data->enable_pin, 1); + + /* ready/busy pin */ + if (data->rdy_pin) + at91_set_gpio_input(data->rdy_pin, 1); + + /* card detect pin */ + if (data->det_pin) + at91_set_gpio_input(data->det_pin, 1); + + at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */ + at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */ + + nand_dev.platform_data = data; + register_device(&nand_dev); +} +#else +void at91_add_device_nand(struct atmel_nand_data *data) {} +#endif + +static struct device_d dbgu_serial_device = { + .id = 0, + .name = "atmel_serial", + .map_base = (AT91_BASE_SYS + AT91_DBGU), + .size = 4096, +}; + +static inline void configure_dbgu_pins(void) +{ + at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */ + at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */ +} + +static struct device_d uart0_serial_device = { + .id = 1, + .name = "atmel_serial", + .map_base = AT91SAM9261_BASE_US0, + .size = 4096, +}; + +static inline void configure_usart0_pins(unsigned pins) +{ + at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */ + at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */ + + if (pins & ATMEL_UART_RTS) + at91_set_A_periph(AT91_PIN_PC10, 0); /* RTS0 */ + if (pins & ATMEL_UART_CTS) + at91_set_A_periph(AT91_PIN_PC11, 0); /* CTS0 */ +} + +static struct device_d uart1_serial_device = { + .id = 2, + .name = "atmel_serial", + .map_base = AT91SAM9261_BASE_US1, + .size = 4096, +}; + +static inline void configure_usart1_pins(unsigned pins) +{ + at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */ + at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */ + + if (pins & ATMEL_UART_RTS) + at91_set_B_periph(AT91_PIN_PA12, 0); /* RTS1 */ + if (pins & ATMEL_UART_CTS) + at91_set_B_periph(AT91_PIN_PA13, 0); /* CTS1 */ +} + +static struct device_d uart2_serial_device = { + .id = 3, + .name = "atmel_serial", + .map_base = AT91SAM9261_BASE_US2, + .size = 4096, +}; + +static inline void configure_usart2_pins(unsigned pins) +{ + at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */ + at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */ + + if (pins & ATMEL_UART_RTS) + at91_set_B_periph(AT91_PIN_PA15, 0); /* RTS2*/ + if (pins & ATMEL_UART_CTS) + at91_set_B_periph(AT91_PIN_PA16, 0); /* CTS2 */ +} + +void at91_register_uart(unsigned id, unsigned pins) +{ + switch (id) { + case 0: /* DBGU */ + configure_dbgu_pins(); + at91_clock_associate("mck", &dbgu_serial_device, "usart"); + register_device(&dbgu_serial_device); + break; + case AT91SAM9261_ID_US0: + configure_usart0_pins(pins); + at91_clock_associate("usart0_clk", &uart0_serial_device, "usart"); + register_device(&uart0_serial_device); + break; + case AT91SAM9261_ID_US1: + configure_usart1_pins(pins); + at91_clock_associate("usart1_clk", &uart1_serial_device, "usart"); + register_device(&uart1_serial_device); + break; + case AT91SAM9261_ID_US2: + configure_usart2_pins(pins); + at91_clock_associate("usart2_clk", &uart2_serial_device, "usart"); + register_device(&uart2_serial_device); + break; + default: + return; + } +} diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c index 807a6a769d..346426cb00 100644 --- a/arch/arm/mach-at91/at91sam9263_devices.c +++ b/arch/arm/mach-at91/at91sam9263_devices.c @@ -119,7 +119,7 @@ void at91_add_device_nand(struct atmel_nand_data *data) {} #endif static struct device_d dbgu_serial_device = { - .id = -1, + .id = 0, .name = "atmel_serial", .map_base = (AT91_BASE_SYS + AT91_DBGU), .size = 4096, @@ -132,7 +132,7 @@ static inline void configure_dbgu_pins(void) } static struct device_d uart0_serial_device = { - .id = -1, + .id = 1, .name = "atmel_serial", .map_base = AT91SAM9263_BASE_US0, .size = 4096, @@ -150,7 +150,7 @@ static inline void configure_usart0_pins(unsigned pins) } static struct device_d uart1_serial_device = { - .id = -1, + .id = 2, .name = "atmel_serial", .map_base = AT91SAM9263_BASE_US1, .size = 4096, @@ -168,7 +168,7 @@ static inline void configure_usart1_pins(unsigned pins) } static struct device_d uart2_serial_device = { - .id = -1, + .id = 3, .name = "atmel_serial", .map_base = AT91SAM9263_BASE_US2, .size = 4096, diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c index c1b42f92c9..7a1d6dd2f4 100644 --- a/arch/arm/mach-at91/at91sam926x_time.c +++ b/arch/arm/mach-at91/at91sam926x_time.c @@ -46,7 +46,7 @@ uint64_t at91sam9_clocksource_read(void) static struct clocksource cs = { .read = at91sam9_clocksource_read, - .mask = 0xffffffff, + .mask = CLOCKSOURCE_MASK(32), .shift = 10, }; diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c new file mode 100644 index 0000000000..2eaae58e18 --- /dev/null +++ b/arch/arm/mach-at91/at91sam9g45.c @@ -0,0 +1,277 @@ +#include <common.h> +#include <gpio.h> +#include <init.h> +#include <mach/io.h> +#include <mach/hardware.h> +#include <mach/at91_pmc.h> +#include <mach/cpu.h> + +#include "generic.h" +#include "clock.h" + +/* -------------------------------------------------------------------- + * Clocks + * -------------------------------------------------------------------- */ + +/* + * The peripheral clocks. + */ +static struct clk pioA_clk = { + .name = "pioA_clk", + .pmc_mask = 1 << AT91SAM9G45_ID_PIOA, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pioB_clk = { + .name = "pioB_clk", + .pmc_mask = 1 << AT91SAM9G45_ID_PIOB, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pioC_clk = { + .name = "pioC_clk", + .pmc_mask = 1 << AT91SAM9G45_ID_PIOC, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pioDE_clk = { + .name = "pioDE_clk", + .pmc_mask = 1 << AT91SAM9G45_ID_PIODE, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart0_clk = { + .name = "usart0_clk", + .pmc_mask = 1 << AT91SAM9G45_ID_US0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart1_clk = { + .name = "usart1_clk", + .pmc_mask = 1 << AT91SAM9G45_ID_US1, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart2_clk = { + .name = "usart2_clk", + .pmc_mask = 1 << AT91SAM9G45_ID_US2, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart3_clk = { + .name = "usart3_clk", + .pmc_mask = 1 << AT91SAM9G45_ID_US3, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk mmc0_clk = { + .name = "mci0_clk", + .pmc_mask = 1 << AT91SAM9G45_ID_MCI0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk twi0_clk = { + .name = "twi0_clk", + .pmc_mask = 1 << AT91SAM9G45_ID_TWI0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk twi1_clk = { + .name = "twi1_clk", + .pmc_mask = 1 << AT91SAM9G45_ID_TWI1, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk spi0_clk = { + .name = "spi0_clk", + .pmc_mask = 1 << AT91SAM9G45_ID_SPI0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk spi1_clk = { + .name = "spi1_clk", + .pmc_mask = 1 << AT91SAM9G45_ID_SPI1, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk ssc0_clk = { + .name = "ssc0_clk", + .pmc_mask = 1 << AT91SAM9G45_ID_SSC0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk ssc1_clk = { + .name = "ssc1_clk", + .pmc_mask = 1 << AT91SAM9G45_ID_SSC1, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk tcb0_clk = { + .name = "tcb0_clk", + .pmc_mask = 1 << AT91SAM9G45_ID_TCB, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pwm_clk = { + .name = "pwm_clk", + .pmc_mask = 1 << AT91SAM9G45_ID_PWMC, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk tsc_clk = { + .name = "tsc_clk", + .pmc_mask = 1 << AT91SAM9G45_ID_TSC, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk dma_clk = { + .name = "dma_clk", + .pmc_mask = 1 << AT91SAM9G45_ID_DMA, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk uhphs_clk = { + .name = "uhphs_clk", + .pmc_mask = 1 << AT91SAM9G45_ID_UHPHS, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk lcdc_clk = { + .name = "lcdc_clk", + .pmc_mask = 1 << AT91SAM9G45_ID_LCDC, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk ac97_clk = { + .name = "ac97_clk", + .pmc_mask = 1 << AT91SAM9G45_ID_AC97C, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk macb_clk = { + .name = "macb_clk", + .pmc_mask = 1 << AT91SAM9G45_ID_EMAC, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk isi_clk = { + .name = "isi_clk", + .pmc_mask = 1 << AT91SAM9G45_ID_ISI, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk udphs_clk = { + .name = "udphs_clk", + .pmc_mask = 1 << AT91SAM9G45_ID_UDPHS, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk mmc1_clk = { + .name = "mci1_clk", + .pmc_mask = 1 << AT91SAM9G45_ID_MCI1, + .type = CLK_TYPE_PERIPHERAL, +}; + +/* Video decoder clock - Only for sam9m10/sam9m11 */ +static struct clk vdec_clk = { + .name = "vdec_clk", + .pmc_mask = 1 << AT91SAM9G45_ID_VDEC, + .type = CLK_TYPE_PERIPHERAL, +}; + +/* One additional fake clock for ohci */ +static struct clk ohci_clk = { + .name = "ohci_clk", + .pmc_mask = 0, + .type = CLK_TYPE_PERIPHERAL, + .parent = &uhphs_clk, +}; + +/* One additional fake clock for second TC block */ +static struct clk tcb1_clk = { + .name = "tcb1_clk", + .pmc_mask = 0, + .type = CLK_TYPE_PERIPHERAL, + .parent = &tcb0_clk, +}; + +static struct clk *periph_clocks[] __initdata = { + &pioA_clk, + &pioB_clk, + &pioC_clk, + &pioDE_clk, + &usart0_clk, + &usart1_clk, + &usart2_clk, + &usart3_clk, + &mmc0_clk, + &twi0_clk, + &twi1_clk, + &spi0_clk, + &spi1_clk, + &ssc0_clk, + &ssc1_clk, + &tcb0_clk, + &pwm_clk, + &tsc_clk, + &dma_clk, + &uhphs_clk, + &lcdc_clk, + &ac97_clk, + &macb_clk, + &isi_clk, + &udphs_clk, + &mmc1_clk, + // irq0 + &ohci_clk, + &tcb1_clk, +}; + +/* + * The two programmable clocks. + * You must configure pin multiplexing to bring these signals out. + */ +static struct clk pck0 = { + .name = "pck0", + .pmc_mask = AT91_PMC_PCK0, + .type = CLK_TYPE_PROGRAMMABLE, + .id = 0, +}; +static struct clk pck1 = { + .name = "pck1", + .pmc_mask = AT91_PMC_PCK1, + .type = CLK_TYPE_PROGRAMMABLE, + .id = 1, +}; + +static void __init at91sam9g45_register_clocks(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) + clk_register(periph_clocks[i]); + + if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11()) + clk_register(&vdec_clk); + + clk_register(&pck0); + clk_register(&pck1); +} + +/* -------------------------------------------------------------------- + * GPIO + * -------------------------------------------------------------------- */ + +static struct at91_gpio_bank at91sam9g45_gpio[] = { + { + .id = AT91SAM9G45_ID_PIOA, + .offset = AT91_PIOA, + .clock = &pioA_clk, + }, { + .id = AT91SAM9G45_ID_PIOB, + .offset = AT91_PIOB, + .clock = &pioB_clk, + }, { + .id = AT91SAM9G45_ID_PIOC, + .offset = AT91_PIOC, + .clock = &pioC_clk, + }, { + .id = AT91SAM9G45_ID_PIODE, + .offset = AT91_PIOD, + .clock = &pioDE_clk, + }, { + .id = AT91SAM9G45_ID_PIODE, + .offset = AT91_PIOE, + .clock = &pioDE_clk, + } +}; + +static int at91sam9g45_initialize(void) +{ + /* Init clock subsystem */ + at91_clock_init(AT91_MAIN_CLOCK); + + /* Register the processor-specific clocks */ + at91sam9g45_register_clocks(); + + /* Register GPIO subsystem */ + at91_gpio_init(at91sam9g45_gpio, 5); + return 0; +} + +core_initcall(at91sam9g45_initialize); diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c new file mode 100644 index 0000000000..ddb005a89b --- /dev/null +++ b/arch/arm/mach-at91/at91sam9g45_devices.c @@ -0,0 +1,242 @@ +/* + * arch/arm/mach-at91/at91sam9263_devices.c + * + * Copyright (C) 2006 Atmel + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ +#include <common.h> +#include <asm/armlinux.h> +#include <asm/hardware.h> +#include <mach/at91_pmc.h> +#include <mach/at91sam9g45_matrix.h> +#include <mach/board.h> +#include <mach/gpio.h> +#include <mach/io.h> + +#include "generic.h" + +static struct memory_platform_data ram_pdata = { + .name = "ram0", + .flags = DEVFS_RDWR, +}; + +static struct device_d sdram_dev = { + .id = -1, + .name = "mem", + .map_base = AT91_CHIPSELECT_6, + .platform_data = &ram_pdata, +}; + +void at91_add_device_sdram(u32 size) +{ + sdram_dev.size = size; + register_device(&sdram_dev); + armlinux_add_dram(&sdram_dev); +} + +#if defined(CONFIG_DRIVER_NET_MACB) +static struct device_d macb_dev = { + .id = 0, + .name = "macb", + .map_base = AT91SAM9G45_BASE_EMAC, + .size = 0x1000, +}; + +void at91_add_device_eth(struct at91_ether_platform_data *data) +{ + if (!data) + return; + + /* Pins used for MII and RMII */ + at91_set_A_periph(AT91_PIN_PA17, 0); /* ETXCK_EREFCK */ + at91_set_A_periph(AT91_PIN_PA15, 0); /* ERXDV */ + at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */ + at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */ + at91_set_A_periph(AT91_PIN_PA16, 0); /* ERXER */ + at91_set_A_periph(AT91_PIN_PA14, 0); /* ETXEN */ + at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX0 */ + at91_set_A_periph(AT91_PIN_PA11, 0); /* ETX1 */ + at91_set_A_periph(AT91_PIN_PA19, 0); /* EMDIO */ + at91_set_A_periph(AT91_PIN_PA18, 0); /* EMDC */ + + if (!(data->flags & AT91SAM_ETHER_RMII)) { + at91_set_B_periph(AT91_PIN_PA29, 0); /* ECRS */ + at91_set_B_periph(AT91_PIN_PA30, 0); /* ECOL */ + at91_set_B_periph(AT91_PIN_PA8, 0); /* ERX2 */ + at91_set_B_periph(AT91_PIN_PA9, 0); /* ERX3 */ + at91_set_B_periph(AT91_PIN_PA28, 0); /* ERXCK */ + at91_set_B_periph(AT91_PIN_PA6, 0); /* ETX2 */ + at91_set_B_periph(AT91_PIN_PA7, 0); /* ETX3 */ + at91_set_B_periph(AT91_PIN_PA27, 0); /* ETXER */ + } + + macb_dev.platform_data = data; + register_device(&macb_dev); +} +#else +void at91_add_device_eth(struct at91_ether_platform_data *data) {} +#endif + +#if defined(CONFIG_NAND_ATMEL) +static struct device_d nand_dev = { + .id = -1, + .name = "atmel_nand", + .map_base = AT91_CHIPSELECT_3, + .size = 0x10, +}; + +void at91_add_device_nand(struct atmel_nand_data *data) +{ + unsigned long csa; + + if (!data) + return; + + data->ecc_base = (void __iomem *)(AT91_BASE_SYS + AT91_ECC); + data->ecc_mode = NAND_ECC_HW; + + csa = at91_sys_read(AT91_MATRIX_EBICSA); + at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA); + + /* enable pin */ + if (data->enable_pin) + at91_set_gpio_output(data->enable_pin, 1); + + /* ready/busy pin */ + if (data->rdy_pin) + at91_set_gpio_input(data->rdy_pin, 1); + + /* card detect pin */ + if (data->det_pin) + at91_set_gpio_input(data->det_pin, 1); + + nand_dev.platform_data = data; + register_device(&nand_dev); +} +#else +void at91_add_device_nand(struct atmel_nand_data *data) {} +#endif + +static struct device_d dbgu_serial_device = { + .id = -1, + .name = "atmel_serial", + .map_base = (AT91_BASE_SYS + AT91_DBGU), + .size = 4096, +}; + +static inline void configure_dbgu_pins(void) +{ + at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */ + at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */ +} + +static struct device_d uart0_serial_device = { + .id = -1, + .name = "atmel_serial", + .map_base = AT91SAM9G45_BASE_US0, + .size = 4096, +}; + +static inline void configure_usart0_pins(unsigned pins) +{ + at91_set_A_periph(AT91_PIN_PB19, 1); /* TXD0 */ + at91_set_A_periph(AT91_PIN_PB18, 0); /* RXD0 */ + + if (pins & ATMEL_UART_RTS) + at91_set_B_periph(AT91_PIN_PB17, 0); /* RTS0 */ + if (pins & ATMEL_UART_CTS) + at91_set_B_periph(AT91_PIN_PB15, 0); /* CTS0 */ +} + +static struct device_d uart1_serial_device = { + .id = -1, + .name = "atmel_serial", + .map_base = AT91SAM9G45_BASE_US1, + .size = 4096, +}; + +static inline void configure_usart1_pins(unsigned pins) +{ + at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD1 */ + at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD1 */ + + if (pins & ATMEL_UART_RTS) + at91_set_A_periph(AT91_PIN_PD16, 0); /* RTS1 */ + if (pins & ATMEL_UART_CTS) + at91_set_A_periph(AT91_PIN_PD17, 0); /* CTS1 */ +} + +static struct device_d uart2_serial_device = { + .id = -1, + .name = "atmel_serial", + .map_base = AT91SAM9G45_BASE_US2, + .size = 4096, +}; + +static inline void configure_usart2_pins(unsigned pins) +{ + at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD2 */ + at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD2 */ + + if (pins & ATMEL_UART_RTS) + at91_set_B_periph(AT91_PIN_PC9, 0); /* RTS2 */ + if (pins & ATMEL_UART_CTS) + at91_set_B_periph(AT91_PIN_PC11, 0); /* CTS2 */ +} + +static struct device_d uart3_serial_device = { + .id = -1, + .name = "atmel_serial", + .map_base = AT91SAM9G45_ID_US3, + .size = 4096, +}; + +static inline void configure_usart3_pins(unsigned pins) +{ + at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD3 */ + at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD3 */ + + if (pins & ATMEL_UART_RTS) + at91_set_B_periph(AT91_PIN_PA23, 0); /* RTS3 */ + if (pins & ATMEL_UART_CTS) + at91_set_B_periph(AT91_PIN_PA24, 0); /* CTS3 */ +} + +void at91_register_uart(unsigned id, unsigned pins) +{ + switch (id) { + case 0: /* DBGU */ + configure_dbgu_pins(); + at91_clock_associate("mck", &dbgu_serial_device, "usart"); + register_device(&dbgu_serial_device); + break; + case AT91SAM9G45_ID_US0: + configure_usart0_pins(pins); + at91_clock_associate("usart0_clk", &uart0_serial_device, "usart"); + register_device(&uart0_serial_device); + break; + case AT91SAM9G45_ID_US1: + configure_usart1_pins(pins); + at91_clock_associate("usart1_clk", &uart1_serial_device, "usart"); + register_device(&uart1_serial_device); + break; + case AT91SAM9G45_ID_US2: + configure_usart2_pins(pins); + at91_clock_associate("usart2_clk", &uart2_serial_device, "usart"); + register_device(&uart2_serial_device); + break; + case AT91SAM9G45_ID_US3: + configure_usart3_pins(pins); + at91_clock_associate("usart3_clk", &uart2_serial_device, "usart"); + register_device(&uart3_serial_device); + break; + default: + return; + } + +} diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h new file mode 100644 index 0000000000..b303e07bbc --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91sam9261.h @@ -0,0 +1,109 @@ +/* + * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261.h] + * + * Copyright (C) SAN People + * + * Common definitions. + * Based on AT91SAM9261 datasheet revision E. (Preliminary) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91SAM9261_H +#define AT91SAM9261_H + +/* + * Peripheral identifiers/interrupts. + */ +#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define AT91_ID_SYS 1 /* System Peripherals */ +#define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */ +#define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */ +#define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */ +#define AT91SAM9261_ID_US0 6 /* USART 0 */ +#define AT91SAM9261_ID_US1 7 /* USART 1 */ +#define AT91SAM9261_ID_US2 8 /* USART 2 */ +#define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */ +#define AT91SAM9261_ID_UDP 10 /* USB Device Port */ +#define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */ +#define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */ +#define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */ +#define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */ +#define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */ +#define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */ +#define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */ +#define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */ +#define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */ +#define AT91SAM9261_ID_UHP 20 /* USB Host port */ +#define AT91SAM9261_ID_LCDC 21 /* LDC Controller */ +#define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ +#define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ +#define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ + + +/* + * User Peripheral physical base addresses. + */ +#define AT91SAM9261_BASE_TCB0 0xfffa0000 +#define AT91SAM9261_BASE_TC0 0xfffa0000 +#define AT91SAM9261_BASE_TC1 0xfffa0040 +#define AT91SAM9261_BASE_TC2 0xfffa0080 +#define AT91SAM9261_BASE_UDP 0xfffa4000 +#define AT91SAM9261_BASE_MCI 0xfffa8000 +#define AT91SAM9261_BASE_TWI 0xfffac000 +#define AT91SAM9261_BASE_US0 0xfffb0000 +#define AT91SAM9261_BASE_US1 0xfffb4000 +#define AT91SAM9261_BASE_US2 0xfffb8000 +#define AT91SAM9261_BASE_SSC0 0xfffbc000 +#define AT91SAM9261_BASE_SSC1 0xfffc0000 +#define AT91SAM9261_BASE_SSC2 0xfffc4000 +#define AT91SAM9261_BASE_SPI0 0xfffc8000 +#define AT91SAM9261_BASE_SPI1 0xfffcc000 +#define AT91_BASE_SYS 0xffffea00 + + +/* + * System Peripherals (offset from AT91_BASE_SYS) + */ +#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) +#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) +#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) +#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) +#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) +#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) +#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) +#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) +#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) +#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) +#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) +#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) +#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) +#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) +#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) + +#define AT91_USART0 AT91SAM9261_BASE_US0 +#define AT91_USART1 AT91SAM9261_BASE_US1 +#define AT91_USART2 AT91SAM9261_BASE_US2 + + +/* + * Internal Memory. + */ +#define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */ +#define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */ + +#define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */ +#define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ + +#define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */ +#define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */ + +/* + * Cpu Name + */ +#define AT91_CPU_NAME "AT91SAM9261" + +#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h new file mode 100644 index 0000000000..7de01573a3 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h @@ -0,0 +1,64 @@ +/* + * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261_matrix.h] + * + * Copyright (C) 2007 Atmel Corporation. + * + * Memory Controllers (MATRIX, EBI) - System peripherals registers. + * Based on AT91SAM9261 datasheet revision D. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91SAM9261_MATRIX_H +#define AT91SAM9261_MATRIX_H + +#define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00) /* Master Configuration Register */ +#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ +#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ + +#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04) /* Slave Configuration Register 0 */ +#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08) /* Slave Configuration Register 1 */ +#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x0C) /* Slave Configuration Register 2 */ +#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x10) /* Slave Configuration Register 3 */ +#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x14) /* Slave Configuration Register 4 */ +#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ +#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ +#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) +#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ + +#define AT91_MATRIX_TCR (AT91_MATRIX + 0x24) /* TCM Configuration Register */ +#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ +#define AT91_MATRIX_ITCM_0 (0 << 0) +#define AT91_MATRIX_ITCM_16 (5 << 0) +#define AT91_MATRIX_ITCM_32 (6 << 0) +#define AT91_MATRIX_ITCM_64 (7 << 0) +#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ +#define AT91_MATRIX_DTCM_0 (0 << 4) +#define AT91_MATRIX_DTCM_16 (5 << 4) +#define AT91_MATRIX_DTCM_32 (6 << 4) +#define AT91_MATRIX_DTCM_64 (7 << 4) + +#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30) /* EBI Chip Select Assignment Register */ +#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ +#define AT91_MATRIX_CS1A_SMC (0 << 1) +#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) +#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ +#define AT91_MATRIX_CS3A_SMC (0 << 3) +#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) +#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ +#define AT91_MATRIX_CS4A_SMC (0 << 4) +#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) +#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ +#define AT91_MATRIX_CS5A_SMC (0 << 5) +#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) +#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ + +#define AT91_MATRIX_USBPUCR (AT91_MATRIX + 0x34) /* USB Pad Pull-Up Control Register */ +#define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */ + +#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9_matrix.h index 58cafd8527..1d1d9059a5 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9_matrix.h +++ b/arch/arm/mach-at91/include/mach/at91sam9_matrix.h @@ -13,7 +13,7 @@ #if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20) #include <mach/at91sam9260_matrix.h> -#elif defined(CONFIG_ARCH_AT91SAM9261) +#elif defined(CONFIG_ARCH_AT91SAM9261) || defined(CONFIG_ARCH_AT91SAM9G10) #include <mach/at91sam9261_matrix.h> #elif defined(CONFIG_ARCH_AT91SAM9263) #include <mach/at91sam9263_matrix.h> diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h new file mode 100644 index 0000000000..c5c7f497d4 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h @@ -0,0 +1,160 @@ +/* + * Chip-specific header file for the AT91SAM9G45 family + * + * Copyright (C) 2008-2009 Atmel Corporation. + * + * Common definitions. + * Based on AT91SAM9G45 preliminary datasheet. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91SAM9G45_H +#define AT91SAM9G45_H + +/* + * Peripheral identifiers/interrupts. + */ +#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define AT91_ID_SYS 1 /* System Controller Interrupt */ +#define AT91SAM9G45_ID_PIOA 2 /* Parallel I/O Controller A */ +#define AT91SAM9G45_ID_PIOB 3 /* Parallel I/O Controller B */ +#define AT91SAM9G45_ID_PIOC 4 /* Parallel I/O Controller C */ +#define AT91SAM9G45_ID_PIODE 5 /* Parallel I/O Controller D and E */ +#define AT91SAM9G45_ID_TRNG 6 /* True Random Number Generator */ +#define AT91SAM9G45_ID_US0 7 /* USART 0 */ +#define AT91SAM9G45_ID_US1 8 /* USART 1 */ +#define AT91SAM9G45_ID_US2 9 /* USART 2 */ +#define AT91SAM9G45_ID_US3 10 /* USART 3 */ +#define AT91SAM9G45_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */ +#define AT91SAM9G45_ID_TWI0 12 /* Two-Wire Interface 0 */ +#define AT91SAM9G45_ID_TWI1 13 /* Two-Wire Interface 1 */ +#define AT91SAM9G45_ID_SPI0 14 /* Serial Peripheral Interface 0 */ +#define AT91SAM9G45_ID_SPI1 15 /* Serial Peripheral Interface 1 */ +#define AT91SAM9G45_ID_SSC0 16 /* Synchronous Serial Controller 0 */ +#define AT91SAM9G45_ID_SSC1 17 /* Synchronous Serial Controller 1 */ +#define AT91SAM9G45_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ +#define AT91SAM9G45_ID_PWMC 19 /* Pulse Width Modulation Controller */ +#define AT91SAM9G45_ID_TSC 20 /* Touch Screen ADC Controller */ +#define AT91SAM9G45_ID_DMA 21 /* DMA Controller */ +#define AT91SAM9G45_ID_UHPHS 22 /* USB Host High Speed */ +#define AT91SAM9G45_ID_LCDC 23 /* LCD Controller */ +#define AT91SAM9G45_ID_AC97C 24 /* AC97 Controller */ +#define AT91SAM9G45_ID_EMAC 25 /* Ethernet MAC */ +#define AT91SAM9G45_ID_ISI 26 /* Image Sensor Interface */ +#define AT91SAM9G45_ID_UDPHS 27 /* USB Device High Speed */ +#define AT91SAM9G45_ID_AESTDESSHA 28 /* AES + T-DES + SHA */ +#define AT91SAM9G45_ID_MCI1 29 /* High Speed Multimedia Card Interface 1 */ +#define AT91SAM9G45_ID_VDEC 30 /* Video Decoder */ +#define AT91SAM9G45_ID_IRQ0 31 /* Advanced Interrupt Controller */ + +/* + * User Peripheral physical base addresses. + */ +#define AT91SAM9G45_BASE_UDPHS 0xfff78000 +#define AT91SAM9G45_BASE_TCB0 0xfff7c000 +#define AT91SAM9G45_BASE_TC0 0xfff7c000 +#define AT91SAM9G45_BASE_TC1 0xfff7c040 +#define AT91SAM9G45_BASE_TC2 0xfff7c080 +#define AT91SAM9G45_BASE_MCI0 0xfff80000 +#define AT91SAM9G45_BASE_TWI0 0xfff84000 +#define AT91SAM9G45_BASE_TWI1 0xfff88000 +#define AT91SAM9G45_BASE_US0 0xfff8c000 +#define AT91SAM9G45_BASE_US1 0xfff90000 +#define AT91SAM9G45_BASE_US2 0xfff94000 +#define AT91SAM9G45_BASE_US3 0xfff98000 +#define AT91SAM9G45_BASE_SSC0 0xfff9c000 +#define AT91SAM9G45_BASE_SSC1 0xfffa0000 +#define AT91SAM9G45_BASE_SPI0 0xfffa4000 +#define AT91SAM9G45_BASE_SPI1 0xfffa8000 +#define AT91SAM9G45_BASE_AC97C 0xfffac000 +#define AT91SAM9G45_BASE_TSC 0xfffb0000 +#define AT91SAM9G45_BASE_ISI 0xfffb4000 +#define AT91SAM9G45_BASE_PWMC 0xfffb8000 +#define AT91SAM9G45_BASE_EMAC 0xfffbc000 +#define AT91SAM9G45_BASE_AES 0xfffc0000 +#define AT91SAM9G45_BASE_TDES 0xfffc4000 +#define AT91SAM9G45_BASE_SHA 0xfffc8000 +#define AT91SAM9G45_BASE_TRNG 0xfffcc000 +#define AT91SAM9G45_BASE_MCI1 0xfffd0000 +#define AT91SAM9G45_BASE_TCB1 0xfffd4000 +#define AT91SAM9G45_BASE_TC3 0xfffd4000 +#define AT91SAM9G45_BASE_TC4 0xfffd4040 +#define AT91SAM9G45_BASE_TC5 0xfffd4080 +#define AT91_BASE_SYS 0xffffe200 + +/* + * System Peripherals (offset from AT91_BASE_SYS) + */ +#define AT91_ECC (0xffffe200 - AT91_BASE_SYS) +#define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS) +#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) +#define AT91_SMC (0xffffe800 - AT91_BASE_SYS) +#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) +#define AT91_DMA (0xffffec00 - AT91_BASE_SYS) +#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) +#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) +#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS) +#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS) +#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS) +#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS) +#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS) +#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) +#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) +#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) +#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) +#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) +#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) +#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) +#define AT91_RTC (0xfffffdb0 - AT91_BASE_SYS) + +#define AT91_USART0 AT91SAM9G45_BASE_US0 +#define AT91_USART1 AT91SAM9G45_BASE_US1 +#define AT91_USART2 AT91SAM9G45_BASE_US2 +#define AT91_USART3 AT91SAM9G45_BASE_US3 + +/* + * Internal Memory. + */ +#define AT91SAM9G45_SRAM_BASE 0x00300000 /* Internal SRAM base address */ +#define AT91SAM9G45_SRAM_SIZE SZ_64K /* Internal SRAM size (64Kb) */ + +#define AT91SAM9G45_ROM_BASE 0x00400000 /* Internal ROM base address */ +#define AT91SAM9G45_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */ + +#define AT91SAM9G45_LCDC_BASE 0x00500000 /* LCD Controller */ +#define AT91SAM9G45_UDPHS_FIFO 0x00600000 /* USB Device HS controller */ +#define AT91SAM9G45_OHCI_BASE 0x00700000 /* USB Host controller (OHCI) */ +#define AT91SAM9G45_EHCI_BASE 0x00800000 /* USB Host controller (EHCI) */ +#define AT91SAM9G45_VDEC_BASE 0x00900000 /* Video Decoder Controller */ + +#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6 + +#define CONSISTENT_DMA_SIZE SZ_4M + +/* + * DMA peripheral identifiers + * for hardware handshaking interface + */ +#define AT_DMA_ID_MCI0 0 +#define AT_DMA_ID_SPI0_TX 1 +#define AT_DMA_ID_SPI0_RX 2 +#define AT_DMA_ID_SPI1_TX 3 +#define AT_DMA_ID_SPI1_RX 4 +#define AT_DMA_ID_SSC0_TX 5 +#define AT_DMA_ID_SSC0_RX 6 +#define AT_DMA_ID_SSC1_TX 7 +#define AT_DMA_ID_SSC1_RX 8 +#define AT_DMA_ID_AC97_TX 9 +#define AT_DMA_ID_AC97_RX 10 +#define AT_DMA_ID_MCI1 13 + +/* + * Cpu Name + */ +#define AT91_CPU_NAME "AT91SAM9G45" + +#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h new file mode 100644 index 0000000000..c972d60e0a --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h @@ -0,0 +1,153 @@ +/* + * Matrix-centric header file for the AT91SAM9G45 family + * + * Copyright (C) 2008-2009 Atmel Corporation. + * + * Memory Controllers (MATRIX, EBI) - System peripherals registers. + * Based on AT91SAM9G45 preliminary datasheet. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91SAM9G45_MATRIX_H +#define AT91SAM9G45_MATRIX_H + +#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ +#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ +#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ +#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ +#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ +#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ +#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */ +#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */ +#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */ +#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */ +#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */ +#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */ +#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ +#define AT91_MATRIX_ULBT_INFINITE (0 << 0) +#define AT91_MATRIX_ULBT_SINGLE (1 << 0) +#define AT91_MATRIX_ULBT_FOUR (2 << 0) +#define AT91_MATRIX_ULBT_EIGHT (3 << 0) +#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) +#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0) +#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0) +#define AT91_MATRIX_ULBT_128 (7 << 0) + +#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ +#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ +#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ +#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ +#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ +#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ +#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */ +#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */ +#define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */ +#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ +#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) +#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ + +#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ +#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */ +#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ +#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */ +#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ +#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */ +#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ +#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */ +#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ +#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */ +#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ +#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */ +#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */ +#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */ +#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */ +#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */ +#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ +#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ +#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ +#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ +#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ +#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ +#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */ +#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ +#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ +#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */ +#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */ +#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */ + +#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ +#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ +#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ +#define AT91_MATRIX_RCB2 (1 << 2) +#define AT91_MATRIX_RCB3 (1 << 3) +#define AT91_MATRIX_RCB4 (1 << 4) +#define AT91_MATRIX_RCB5 (1 << 5) +#define AT91_MATRIX_RCB6 (1 << 6) +#define AT91_MATRIX_RCB7 (1 << 7) +#define AT91_MATRIX_RCB8 (1 << 8) +#define AT91_MATRIX_RCB9 (1 << 9) +#define AT91_MATRIX_RCB10 (1 << 10) +#define AT91_MATRIX_RCB11 (1 << 11) + +#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x110) /* TCM Configuration Register */ +#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ +#define AT91_MATRIX_ITCM_0 (0 << 0) +#define AT91_MATRIX_ITCM_32 (6 << 0) +#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ +#define AT91_MATRIX_DTCM_0 (0 << 4) +#define AT91_MATRIX_DTCM_32 (6 << 4) +#define AT91_MATRIX_DTCM_64 (7 << 4) +#define AT91_MATRIX_TCM_NWS (0x1 << 11) /* Wait state TCM register */ +#define AT91_MATRIX_TCM_NO_WS (0x0 << 11) +#define AT91_MATRIX_TCM_ONE_WS (0x1 << 11) + +#define AT91_MATRIX_VIDEO (AT91_MATRIX + 0x118) /* Video Mode Configuration Register */ +#define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */ +#define AT91C_VDEC_SEL_OFF (0 << 0) +#define AT91C_VDEC_SEL_ON (1 << 0) + +#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x128) /* EBI Chip Select Assignment Register */ +#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ +#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) +#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) +#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */ +#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3) +#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) +#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */ +#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4) +#define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4) +#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */ +#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5) +#define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5) +#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ +#define AT91_MATRIX_EBI_DBPU_ON (0 << 8) +#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8) +#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */ +#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) +#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) +#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */ +#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17) +#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17) +#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */ +#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18) +#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18) + +#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */ +#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */ +#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0) +#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0) +#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */ + +#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */ +#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */ +#define AT91_MATRIX_WPSR_NO_WPV (0 << 0) +#define AT91_MATRIX_WPSR_WPV (1 << 0) +#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */ + +#endif diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h index 833659d120..3bef931d0b 100644 --- a/arch/arm/mach-at91/include/mach/cpu.h +++ b/arch/arm/mach-at91/include/mach/cpu.h @@ -52,6 +52,7 @@ static inline unsigned long at91_cpu_fully_identify(void) #define ARCH_EXID_AT91SAM9M11 0x00000001 #define ARCH_EXID_AT91SAM9M10 0x00000002 +#define ARCH_EXID_AT91SAM9G46 0x00000003 #define ARCH_EXID_AT91SAM9G45 0x00000004 static inline unsigned long at91_exid_identify(void) @@ -128,9 +129,18 @@ static inline unsigned long at91cap9_rev_identify(void) #ifdef CONFIG_ARCH_AT91SAM9G45 #define cpu_is_at91sam9g45() (at91_cpu_identify() == ARCH_ID_AT91SAM9G45) #define cpu_is_at91sam9g45es() (at91_cpu_fully_identify() == ARCH_ID_AT91SAM9G45ES) +#define cpu_is_at91sam9m10() (cpu_is_at91sam9g45() && \ + (at91_exid_identify() == ARCH_EXID_AT91SAM9M10)) +#define cpu_is_at91sam9m46() (cpu_is_at91sam9g45() && \ + (at91_exid_identify() == ARCH_EXID_AT91SAM9G46)) +#define cpu_is_at91sam9m11() (cpu_is_at91sam9g45() && \ + (at91_exid_identify() == ARCH_EXID_AT91SAM9M11)) #else #define cpu_is_at91sam9g45() (0) #define cpu_is_at91sam9g45es() (0) +#define cpu_is_at91sam9m10() (0) +#define cpu_is_at91sam9g46() (0) +#define cpu_is_at91sam9m11() (0) #endif #ifdef CONFIG_ARCH_AT91CAP9 diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h index 82b574eb0a..fcb1bd4e67 100644 --- a/arch/arm/mach-at91/include/mach/hardware.h +++ b/arch/arm/mach-at91/include/mach/hardware.h @@ -24,7 +24,7 @@ #include <mach/at91sam9263.h> #elif defined(CONFIG_ARCH_AT91SAM9RL) #include <mach/at91sam9rl.h> -#elif defined(CONFIG_ARCH_AT91SAM9G45) || defined(CONFIG_ARCH_AT91SAM9M10G45) +#elif defined(CONFIG_ARCH_AT91SAM9G45) #include <mach/at91sam9g45.h> #elif defined(CONFIG_ARCH_AT91CAP9) #include <mach/at91cap9.h> diff --git a/arch/arm/mach-at91/lowlevel_init.S b/arch/arm/mach-at91/lowlevel_init.S index 8a0ae02a6a..805b201bf7 100644 --- a/arch/arm/mach-at91/lowlevel_init.S +++ b/arch/arm/mach-at91/lowlevel_init.S @@ -194,7 +194,7 @@ SMRDATA: .word (AT91_BASE_SYS + AT91_PIOD + PIO_ASR) .word CONFIG_SYS_PIOD_PPUDR_VAL #elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9261) \ - || defined(CONFIG_ARCH_AT91SAM9G20) + || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91SAM9G10) .word (AT91_BASE_SYS + AT91_PIOC + PIO_PDR) .word CONFIG_SYS_PIOC_PDR_VAL1 .word (AT91_BASE_SYS + AT91_PIOC + PIO_PUDR) diff --git a/arch/arm/mach-ep93xx/clocksource.c b/arch/arm/mach-ep93xx/clocksource.c index a1e315dca6..b500948968 100644 --- a/arch/arm/mach-ep93xx/clocksource.c +++ b/arch/arm/mach-ep93xx/clocksource.c @@ -41,7 +41,7 @@ static uint64_t ep93xx_clocksource_read(void) static struct clocksource cs = { .read = ep93xx_clocksource_read, - .mask = 0xffffffff, + .mask = CLOCKSOURCE_MASK(32), .shift = 10, }; diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index ce38566502..d000683863 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -10,4 +10,4 @@ obj-$(CONFIG_IMX_CLKO) += clko.o obj-$(CONFIG_IMX_IIM) += iim.o obj-$(CONFIG_NAND_IMX) += nand.o obj-y += speed.o - +obj-y += devices.o diff --git a/arch/arm/mach-imx/clocksource.c b/arch/arm/mach-imx/clocksource.c index 5b1bad52f8..5397da03d7 100644 --- a/arch/arm/mach-imx/clocksource.c +++ b/arch/arm/mach-imx/clocksource.c @@ -47,7 +47,7 @@ static uint64_t imx_clocksource_read(void) static struct clocksource cs = { .read = imx_clocksource_read, - .mask = 0xffffffff, + .mask = CLOCKSOURCE_MASK(32), .shift = 10, }; diff --git a/arch/arm/mach-imx/devices.c b/arch/arm/mach-imx/devices.c new file mode 100644 index 0000000000..0395b0e572 --- /dev/null +++ b/arch/arm/mach-imx/devices.c @@ -0,0 +1,64 @@ +#include <common.h> +#include <driver.h> +#include <mach/devices.h> + +static struct device_d *imx_add_device(char *name, int id, void *base, int size, void *pdata) +{ + struct device_d *dev; + + dev = xzalloc(sizeof(*dev)); + strcpy(dev->name,name); + dev->id = id; + dev->map_base = (unsigned long)base; + dev->size = size; + dev->platform_data = pdata; + + register_device(dev); + + return 0; +} + +struct device_d *imx_add_fec(void *base, struct fec_platform_data *pdata) +{ + return imx_add_device("fec_imx", -1, base, 0x1000, pdata); +} + +struct device_d *imx_add_spi(void *base, int id, struct spi_imx_master *pdata) +{ + return imx_add_device("imx_spi", id, base, 0x1000, pdata); +} + +struct device_d *imx_add_i2c(void *base, int id, struct i2c_platform_data *pdata) +{ + return imx_add_device("i2c-imx", id, base, 0x1000, pdata); +} + +struct device_d *imx_add_uart(void *base, int id) +{ + return imx_add_device("imx_serial", id, base, 0x1000, NULL); +} + +struct device_d *imx_add_nand(void *base, struct imx_nand_platform_data *pdata) +{ + return imx_add_device("imx_nand", -1, base, 0x1000, pdata); +} + +struct device_d *imx_add_fb(void *base, struct imx_fb_platform_data *pdata) +{ + return imx_add_device("imxfb", -1, base, 0x1000, pdata); +} + +struct device_d *imx_add_ipufb(void *base, struct imx_ipu_fb_platform_data *pdata) +{ + return imx_add_device("imx-ipu-fb", -1, base, 0x1000, pdata); +} + +struct device_d *imx_add_mmc(void *base, int id, void *pdata) +{ + return imx_add_device("imx-mmc", id, base, 0x1000, pdata); +} + +struct device_d *imx_add_esdhc(void *base, int id, void *pdata) +{ + return imx_add_device("imx-esdhc", id, base, 0x1000, pdata); +} diff --git a/arch/arm/mach-imx/include/mach/devices-imx21.h b/arch/arm/mach-imx/include/mach/devices-imx21.h new file mode 100644 index 0000000000..1e1fbbdf4c --- /dev/null +++ b/arch/arm/mach-imx/include/mach/devices-imx21.h @@ -0,0 +1,33 @@ + +#include <mach/devices.h> + +static inline struct device_d *imx21_add_uart0(void) +{ + return imx_add_uart((void *)IMX_UART1_BASE, 0); +} + +static inline struct device_d *imx21_add_uart1(void) +{ + return imx_add_uart((void *)IMX_UART2_BASE, 1); +} + +static inline struct device_d *imx21_add_uart2(void) +{ + return imx_add_uart((void *)IMX_UART3_BASE, 2); +} + +static inline struct device_d *imx21_add_uart3(void) +{ + return imx_add_uart((void *)IMX_UART4_BASE, 3); +} + +static inline struct device_d *imx21_add_nand(struct imx_nand_platform_data *pdata) +{ + return imx_add_nand((void *)0xDF003000, pdata); +} + +static inline struct device_d *imx21_add_fb(struct imx_fb_platform_data *pdata) +{ + return imx_add_fb((void *)0x10021000, pdata); +} + diff --git a/arch/arm/mach-imx/include/mach/devices-imx25.h b/arch/arm/mach-imx/include/mach/devices-imx25.h new file mode 100644 index 0000000000..87f5ba0e5e --- /dev/null +++ b/arch/arm/mach-imx/include/mach/devices-imx25.h @@ -0,0 +1,38 @@ + +#include <mach/devices.h> + +static inline struct device_d *imx25_add_i2c0(struct i2c_platform_data *pdata) +{ + return imx_add_i2c((void *)IMX_I2C1_BASE, 0, pdata); +} + +static inline struct device_d *imx25_add_uart0(void) +{ + return imx_add_uart((void *)IMX_UART1_BASE, 0); +} + +static inline struct device_d *imx25_add_uart1(void) +{ + return imx_add_uart((void *)IMX_UART2_BASE, 1); +} + +static inline struct device_d *imx25_add_nand(struct imx_nand_platform_data *pdata) +{ + return imx_add_nand((void *)IMX_NFC_BASE, pdata); +} + +static inline struct device_d *imx25_add_fb(struct imx_fb_platform_data *pdata) +{ + return imx_add_fb((void *)0x53fbc000, pdata); +} + +static inline struct device_d *imx25_add_fec(struct fec_platform_data *pdata) +{ + return imx_add_fec((void *)IMX_FEC_BASE, pdata); +} + +static inline struct device_d *imx25_add_mmc0(void *pdata) +{ + return imx_add_esdhc((void *)0x53fb4000, 0, pdata); +} + diff --git a/arch/arm/mach-imx/include/mach/devices-imx27.h b/arch/arm/mach-imx/include/mach/devices-imx27.h new file mode 100644 index 0000000000..0511eb5d21 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/devices-imx27.h @@ -0,0 +1,54 @@ + +#include <mach/devices.h> + +static inline struct device_d *imx27_add_spi0(struct spi_imx_master *pdata) +{ + return imx_add_spi((void *)IMX_SPI1_BASE, 0, pdata); +} + +static inline struct device_d *imx27_add_i2c0(struct i2c_platform_data *pdata) +{ + return imx_add_i2c((void *)IMX_I2C1_BASE, 0, pdata); +} + +static inline struct device_d *imx27_add_uart0(void) +{ + return imx_add_uart((void *)IMX_UART1_BASE, 0); +} + +static inline struct device_d *imx27_add_uart1(void) +{ + return imx_add_uart((void *)IMX_UART2_BASE, 1); +} + +static inline struct device_d *imx27_add_uart2(void) +{ + return imx_add_uart((void *)IMX_UART3_BASE, 2); +} + +static inline struct device_d *imx27_add_uart3(void) +{ + return imx_add_uart((void *)IMX_UART4_BASE, 3); +} + +static inline struct device_d *imx27_add_nand(struct imx_nand_platform_data *pdata) +{ + return imx_add_nand((void *)IMX_NFC_BASE, pdata); +} + +static inline struct device_d *imx27_add_fb(struct imx_fb_platform_data *pdata) +{ + return imx_add_fb((void *)0x10021000, pdata); +} + +static inline struct device_d *imx27_add_fec(struct fec_platform_data *pdata) +{ + return imx_add_fec((void *)IMX_FEC_BASE, pdata); +} + +static inline struct device_d *imx27_add_mmc0(void *pdata) +{ + return imx_add_mmc((void *)0x10014000, 0, pdata); +} + + diff --git a/arch/arm/mach-imx/include/mach/devices-imx31.h b/arch/arm/mach-imx/include/mach/devices-imx31.h new file mode 100644 index 0000000000..5dcea82fb0 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/devices-imx31.h @@ -0,0 +1,35 @@ + +#include <mach/imx-regs.h> +#include <mach/devices.h> + +#if 0 +static inline struct device_d *imx31_add_spi0(struct spi_imx_master *pdata) +{ + return imx_add_spi((void *)IMX_SPI1_BASE, 0, pdata); +} + +static inline struct device_d *imx31_add_spi1(struct spi_imx_master *pdata) +{ + return imx_add_spi((void *)IMX_SPI2_BASE, 1, pdata); +} +#endif + +static inline struct device_d *imx31_add_uart0(void) +{ + return imx_add_uart((void *)IMX_UART1_BASE, 0); +} + +static inline struct device_d *imx31_add_uart1(void) +{ + return imx_add_uart((void *)IMX_UART2_BASE, 1); +} + +static inline struct device_d *imx31_add_nand(struct imx_nand_platform_data *pdata) +{ + return imx_add_nand((void *)0xb8000000, pdata); +} + +static inline struct device_d *imx31_add_fb(struct imx_ipu_fb_platform_data *pdata) +{ + return imx_add_ipufb((void *)IPU_BASE, pdata); +} diff --git a/arch/arm/mach-imx/include/mach/devices-imx35.h b/arch/arm/mach-imx/include/mach/devices-imx35.h new file mode 100644 index 0000000000..69f4b36709 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/devices-imx35.h @@ -0,0 +1,57 @@ + +#include <mach/devices.h> + +static inline struct device_d *imx35_add_i2c0(struct i2c_platform_data *pdata) +{ + return imx_add_i2c((void *)IMX_I2C1_BASE, 0, pdata); +} + +static inline struct device_d *imx35_add_i2c1(struct i2c_platform_data *pdata) +{ + return imx_add_i2c((void *)IMX_I2C2_BASE, 1, pdata); +} + +static inline struct device_d *imx35_add_i2c2(struct i2c_platform_data *pdata) +{ + return imx_add_i2c((void *)IMX_I2C3_BASE, 2, pdata); +} + +static inline struct device_d *imx35_add_uart0(void) +{ + return imx_add_uart((void *)IMX_UART1_BASE, 0); +} + +static inline struct device_d *imx35_add_uart1(void) +{ + return imx_add_uart((void *)IMX_UART2_BASE, 1); +} + +static inline struct device_d *imx35_add_nand(struct imx_nand_platform_data *pdata) +{ + return imx_add_nand((void *)IMX_NFC_BASE, pdata); +} + +static inline struct device_d *imx35_add_fb(struct imx_ipu_fb_platform_data *pdata) +{ + return imx_add_ipufb((void *)IMX_IPU_BASE, pdata); +} + +static inline struct device_d *imx35_add_fec(struct fec_platform_data *pdata) +{ + return imx_add_fec((void *)IMX_FEC_BASE, pdata); +} + +static inline struct device_d *imx35_add_mmc0(void *pdata) +{ + return imx_add_esdhc((void *)IMX_SDHC1_BASE, 0, pdata); +} + +static inline struct device_d *imx35_add_mmc1(void *pdata) +{ + return imx_add_esdhc((void *)IMX_SDHC2_BASE, 1, pdata); +} + +static inline struct device_d *imx35_add_mmc2(void *pdata) +{ + return imx_add_esdhc((void *)IMX_SDHC3_BASE, 2, pdata); +} diff --git a/arch/arm/mach-imx/include/mach/devices-imx51.h b/arch/arm/mach-imx/include/mach/devices-imx51.h new file mode 100644 index 0000000000..a5deb5c863 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/devices-imx51.h @@ -0,0 +1,58 @@ + +#include <mach/devices.h> + +static inline struct device_d *imx51_add_spi0(struct spi_imx_master *pdata) +{ + return imx_add_spi((void *)MX51_CSPI1_BASE_ADDR, 0, pdata); +} + +static inline struct device_d *imx51_add_spi1(struct spi_imx_master *pdata) +{ + return imx_add_spi((void *)MX51_CSPI2_BASE_ADDR, 1, pdata); +} + +static inline struct device_d *imx51_add_spi2(struct spi_imx_master *pdata) +{ + return imx_add_spi((void *)MX51_CSPI3_BASE_ADDR, 2, pdata); +} + +static inline struct device_d *imx51_add_i2c0(struct i2c_platform_data *pdata) +{ + return imx_add_i2c((void *)MX51_I2C1_BASE_ADDR, 0, pdata); +} + +static inline struct device_d *imx51_add_i2c1(struct i2c_platform_data *pdata) +{ + return imx_add_i2c((void *)MX51_I2C2_BASE_ADDR, 1, pdata); +} + +static inline struct device_d *imx51_add_uart0(void) +{ + return imx_add_uart((void *)MX51_UART1_BASE_ADDR, 0); +} + +static inline struct device_d *imx51_add_uart1(void) +{ + return imx_add_uart((void *)MX51_UART2_BASE_ADDR, 1); +} + +static inline struct device_d *imx51_add_fec(struct fec_platform_data *pdata) +{ + return imx_add_fec((void *)MX51_MXC_FEC_BASE_ADDR, pdata); +} + +static inline struct device_d *imx51_add_mmc0(void *pdata) +{ + return imx_add_esdhc((void *)MX51_MMC_SDHC1_BASE_ADDR, 0, pdata); +} + +static inline struct device_d *imx51_add_mmc1(void *pdata) +{ + return imx_add_esdhc((void *)MX51_MMC_SDHC2_BASE_ADDR, 0, pdata); +} + +static inline struct device_d *imx51_add_nand(struct imx_nand_platform_data *pdata) +{ + return imx_add_nand((void *)MX51_NFC_AXI_BASE_ADDR, pdata); +} + diff --git a/arch/arm/mach-imx/include/mach/devices.h b/arch/arm/mach-imx/include/mach/devices.h new file mode 100644 index 0000000000..7338ac56ed --- /dev/null +++ b/arch/arm/mach-imx/include/mach/devices.h @@ -0,0 +1,18 @@ + +#include <fec.h> +#include <i2c/i2c.h> +#include <mach/spi.h> +#include <mach/imx-nand.h> +#include <mach/imxfb.h> +#include <mach/imx-ipu-fb.h> + +struct device_d *imx_add_fec(void *base, struct fec_platform_data *pdata); +struct device_d *imx_add_spi(void *base, int id, struct spi_imx_master *pdata); +struct device_d *imx_add_i2c(void *base, int id, struct i2c_platform_data *pdata); +struct device_d *imx_add_uart(void *base, int id); +struct device_d *imx_add_nand(void *base, struct imx_nand_platform_data *pdata); +struct device_d *imx_add_fb(void *base, struct imx_fb_platform_data *pdata); +struct device_d *imx_add_ipufb(void *base, struct imx_ipu_fb_platform_data *pdata); +struct device_d *imx_add_mmc(void *base, int id, void *pdata); +struct device_d *imx_add_esdhc(void *base, int id, void *pdata); + diff --git a/arch/arm/mach-imx/include/mach/imx35-regs.h b/arch/arm/mach-imx/include/mach/imx35-regs.h index 89ca7eafcd..75825e50df 100644 --- a/arch/arm/mach-imx/include/mach/imx35-regs.h +++ b/arch/arm/mach-imx/include/mach/imx35-regs.h @@ -51,6 +51,7 @@ #define IMX_SDHC1_BASE 0x53FB4000 #define IMX_SDHC2_BASE 0x53FB8000 #define IMX_SDHC3_BASE 0x53FBC000 +#define IMX_IPU_BASE 0x53FC0000 #define IMX_OTG_BASE 0x53FF4000 #define IMX_WDOG_BASE 0x53fdc000 diff --git a/arch/arm/mach-imx/include/mach/imx51-regs.h b/arch/arm/mach-imx/include/mach/imx51-regs.h index 1719a787c5..2e6cacb5bf 100644 --- a/arch/arm/mach-imx/include/mach/imx51-regs.h +++ b/arch/arm/mach-imx/include/mach/imx51-regs.h @@ -91,7 +91,20 @@ #define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F8000) #define MX51_SPBA0_BASE_ADDR 0x70000000 -#define MX51_CSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00010000) +#define MX51_MMC_SDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00004000) +#define MX51_MMC_SDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00008000) +#define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0000C000) +#define MX51_CSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00010000) +#define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00014000) +#define MX51_MMC_SDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00020000) +#define MX51_MMC_SDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00024000) +#define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00028000) +#define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00030000) +#define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00034000) +#define MX51_HSI2C_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00038000) +#define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0003C000) + +#define MX51_NFC_AXI_BASE_ADDR 0xcfff0000 /* * Memory regions and CS diff --git a/arch/arm/mach-imx/include/mach/imxfb.h b/arch/arm/mach-imx/include/mach/imxfb.h index 16b43ea4c0..b71b7f4594 100644 --- a/arch/arm/mach-imx/include/mach/imxfb.h +++ b/arch/arm/mach-imx/include/mach/imxfb.h @@ -1,3 +1,6 @@ +#ifndef __MACH_IMXFB_H +#define __MACH_IMXFB_H + /* * This structure describes the machine which we are running on. */ @@ -80,6 +83,8 @@ struct imx_fb_platform_data { void set_imx_fb_info(struct imx_fb_platform_data *); +#endif /* __MACH_IMXFB_H */ + /** * @file * @brief i.MX related framebuffer declarations diff --git a/arch/arm/mach-imx/nand.c b/arch/arm/mach-imx/nand.c index c228f963d0..c52b8b06c2 100644 --- a/arch/arm/mach-imx/nand.c +++ b/arch/arm/mach-imx/nand.c @@ -95,6 +95,15 @@ void imx_nand_set_layout(int writesize, int datawidth) FMCR = fmcr; } +#elif defined CONFIG_ARCH_IMX51 + +void imx_nand_set_layout(int writesize, int datawidth) +{ + /* Just silence the compiler warning below. On i.MX51 we don't + * have external boot. + */ +} + #else #warning using empty imx_nand_set_layout(). NAND flash will not work properly if not booting from it diff --git a/arch/arm/mach-netx/clocksource.c b/arch/arm/mach-netx/clocksource.c index 818709df47..853eab71fa 100644 --- a/arch/arm/mach-netx/clocksource.c +++ b/arch/arm/mach-netx/clocksource.c @@ -34,7 +34,7 @@ uint64_t netx_clocksource_read(void) static struct clocksource cs = { .read = netx_clocksource_read, - .mask = 0xffffffff, + .mask = CLOCKSOURCE_MASK(32), .shift = 10, }; diff --git a/arch/arm/mach-nomadik/timer.c b/arch/arm/mach-nomadik/timer.c index 12e56f05e3..7de1f391a6 100644 --- a/arch/arm/mach-nomadik/timer.c +++ b/arch/arm/mach-nomadik/timer.c @@ -35,7 +35,7 @@ static uint64_t nmdk_read_timer(void) static struct clocksource nmdk_clksrc = { .read = nmdk_read_timer, .shift = 20, - .mask = 0xffffffff, + .mask = CLOCKSOURCE_MASK(32), }; static void nmdk_timer_reset(void) diff --git a/arch/arm/mach-omap/s32k_clksource.c b/arch/arm/mach-omap/s32k_clksource.c index 353670c583..094b76d6b7 100644 --- a/arch/arm/mach-omap/s32k_clksource.c +++ b/arch/arm/mach-omap/s32k_clksource.c @@ -56,7 +56,7 @@ static uint64_t s32k_clocksource_read(void) /* A bit obvious isn't it? */ static struct clocksource s32k_cs = { .read = s32k_clocksource_read, - .mask = 0xffffffff, + .mask = CLOCKSOURCE_MASK(32), .shift = 10, }; diff --git a/arch/arm/mach-s3c24xx/generic.c b/arch/arm/mach-s3c24xx/generic.c index 46b5c50d5b..c04e0b653e 100644 --- a/arch/arm/mach-s3c24xx/generic.c +++ b/arch/arm/mach-s3c24xx/generic.c @@ -196,7 +196,7 @@ static uint64_t s3c24xx_clocksource_read(void) static struct clocksource cs = { .read = s3c24xx_clocksource_read, - .mask = 0x0000ffff, + .mask = CLOCKSOURCE_MASK(16), .shift = 10, }; diff --git a/arch/arm/mach-stm/clocksource-imx23.c b/arch/arm/mach-stm/clocksource-imx23.c index 7c0268c1fb..f7c94c1d75 100644 --- a/arch/arm/mach-stm/clocksource-imx23.c +++ b/arch/arm/mach-stm/clocksource-imx23.c @@ -48,7 +48,7 @@ static uint64_t imx23_clocksource_read(void) static struct clocksource cs = { .read = imx23_clocksource_read, - .mask = 0x0000ffff, + .mask = CLOCKSOURCE_MASK(16), .shift = 10, }; diff --git a/arch/blackfin/lib/clock.c b/arch/blackfin/lib/clock.c index dc2ab5f555..7a5673f2ce 100644 --- a/arch/blackfin/lib/clock.c +++ b/arch/blackfin/lib/clock.c @@ -55,7 +55,7 @@ static uint64_t blackfin_clocksource_read(void) static struct clocksource cs = { .read = blackfin_clocksource_read, - .mask = 0xffffffff, + .mask = CLOCKSOURCE_MASK(32), .shift = 10, }; diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig deleted file mode 100644 index c9608da5cb..0000000000 --- a/arch/m68k/Kconfig +++ /dev/null @@ -1,182 +0,0 @@ -# -# Default location of link barebox Image on M68k/Coldfire -# -config ARCH_TEXT_BASE - hex - default 0x07f00000 if MACH_MCF54xx - default 0x07f00000 if MACH_MCF5445x - help - Vector table for M68k and barebox Link Address - - On M68k/Coldfire cores all exceptions and interrupts are routed through - a vector array. This vector is by default at address 0x0000_0000, but - can be moved to any other 1MB aligned address. - - We take advantage of this to move barebox out of low memory. Some BDM - debuggers won't like a moved vector base and might need tweaking to - work. - - Note: Respect alignment restrictions for TEXT_BASE, which must be - 1MB aligned (VBR register constrain). - -# -# Internal configurations -# -config BOARDINFO - default "konzeptpark UKD Prototype with Phycore MCF5485" if MACH_KPUKDR1 - default "konzeptpark UKD Prototype with Phycore MCF5475 NUM" if MACH_KPUKDR1_NUM - default "konzeptpark UKD Revision 2 with Phycore MCF5485" if MACH_KPUKDR2 - default "konzeptpark UKD Revision 2 with Phycore MCF5475 NUM" if MACH_KPUKDR2_NUM - default "Phytec Baseboard with Phycore MCF5485" if MACH_PCM982_5485 - default "Phytec Baseboard with Phycore MCF5475" if MACH_PCM982_5475 - default "Phytec Baseboard with Phycore MCF5475 NUM" if MACH_PCM982_5475_NUM - default "Phytec Baseboard with Phycore MCF54455" if MACH_PCM982_54455 - default "!No boardinfo string set!" - -config HAS_EARLY_INIT - bool - default n - -config BOARD_LINKER_SCRIPT - bool - default n - -config GENERIC_LINKER_SCRIPT - bool - default y - depends on !BOARD_LINKER_SCRIPT - -config M68K - bool - select HAS_KALLSYMS - select HAS_MODULES - default y - -config MCFV4E - bool - -config MCFV4M - bool - -config ARCH_MCF54xx - bool - select MCFV4E - -config ARCH_MCF5445x - bool - select MCFV4M - -# -# Board selection -# -choice - prompt "Select your board" - -config MACH_KPUKDR1 - bool "konzeptpark UKD R1 + phyCore MCF5485" - select HAS_CFI - select ARCH_MCF54xx - help - Say Y here if you are using the konzeptpark UKD R1 with a - Phytec Phycore PCM-024 equipped with a Freescale MC5485 Processor - -config MACH_KPUKDR1_NUM - bool "konzeptpark UKD R1 + phyCore MCF5475 NUM" - select HAS_CFI - select ARCH_MCF54xx - select MACH_HAS_LOWLEVEL_INIT - help - Say Y here if you are using the konzeptpark UKD R1 with a - Phytec Phycore PCM-024-NUM equipped with a Freescale MC5475 Processor - -config MACH_KPUKDR2 - bool "konzeptpark UKD R2 + phyCore MCF5485" - select HAS_CFI - select ARCH_MCF54xx - help - Say Y here if you are using the konzeptpark UKD R2 with a - Phytec Phycore PCM-024 equipped with a Freescale MC5485 Processor - -config MACH_KPUKDR2_NUM - bool "konzeptpark UKD R2 + phyCore MCF5475 NUM" - select HAS_CFI - select ARCH_MCF54xx - help - Say Y here if you are using the konzeptpark UKD R2 with a - Phytec Phycore PCM-024-NUM equipped with a Freescale MC5475 Processor - -config MACH_PCM982_5485 - bool "Phytec pcm982 + phyCore MCF5485" - select HAS_CFI - select ARCH_MCF54xx - select MACH_HAS_LOWLEVEL_INIT - help - Say Y here if you are using the Phytec Phycore PCM-024 equipped - with a Freescale MC5485 Processor - -config MACH_PCM982_5475 - bool "Phytec pcm982 + phyCore MCF5475" - select HAS_CFI - select ARCH_MCF54xx - select MACH_HAS_LOWLEVEL_INIT - help - Say Y here if you are using the Phytec Phycore PCM-024 equipped - with a Freescale MC5475 Processor - -config MACH_PCM982_5475_NUM - bool "Phytec pcm982 + phyCore MCF5475 NUM" - select HAS_CFI - select ARCH_MCF54xx - select MACH_HAS_LOWLEVEL_INIT - help - Say Y here if you are using the Phytec Phycore PCM-024 equipped - with a Freescale MC5475 Processor (NUM Variant) - -config MACH_PCM982_54455 - bool "Phytec pcm982 + phyCore MCF54455 (experimental)" - select HAS_CFI - select ARCH_MCF5445x - help - Say Y here if you are using the Phytec Phycore PCM-mcf54455 equipped - with a Freescale MC54455 Processor (experimental) - -endchoice - -# -# M68k/Coldfire Subarch Configuration -# -source arch/m68k/mach-mcfv4e/Kconfig - -menu "M68k/Coldfire specific Linux boot settings" - -config CMDLINE_TAG - bool "Send commandline to kernel" - default y - help - If you want to start a 2.6 kernel say y here. - -config SETUP_MEMORY_TAGS - bool "send memory definition to kernel" - default y - help - If you want to start a 2.6 kernel say y here. - -config INITRD_TAG - bool "send initrd params to kernel" - default n - help - If you want to start a 2.6 kernel and use an - initrd image say y here. - -endmenu - -# -# Common barebox options -# - -source common/Kconfig -source commands/Kconfig -source net/Kconfig -source drivers/Kconfig -source fs/Kconfig -source lib/Kconfig diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile deleted file mode 100644 index 86afb24732..0000000000 --- a/arch/m68k/Makefile +++ /dev/null @@ -1,82 +0,0 @@ -# -# (C) Copyright 2007 Carsten Schlote <schlote@vahanus.net> -# See file CREDITS for list of people who contributed to this project. -# -# This file is part of barebox. -# -# barebox is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# barebox is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with barebox. If not, see <http://www.gnu.org/licenses/>. -# - -CPPFLAGS += -isystem $(gccincdir) -fno-strict-aliasing - - -machine-$(CONFIG_ARCH_MCF54xx) := mcfv4e -board-$(CONFIG_MACH_KPUKDR1) := kp_ukd_r1 -board-$(CONFIG_MACH_KPUKDR1_NUM) := kp_ukd_r1_num -board-$(CONFIG_MACH_KPUKDR2) := kp_ukd_r2 -board-$(CONFIG_MACH_KPUKDR2_NUM) := kp_ukd_r2_num -board-$(CONFIG_MACH_PCM982_5485) := phycore_mcf54xx -board-$(CONFIG_MACH_PCM982_5475) := phycore_mcf54xx -board-$(CONFIG_MACH_PCM982_5475_NUM) := phycore_mcf54xx_num -board-$(CONFIG_MACH_PCM982_54455) := phycore_mcf5445x - -cpu-$(CONFIG_MCFV4E) := mcfv4e -cpu-$(CONFIG_MCFV4M) := mcfv4m - -TEXT_BASE = $(CONFIG_TEXT_BASE) - -CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -P -AFLAGS += -gdwarf-2 -save-temps -# FIXME - remove overide -CFLAGS += -msoft-float -mcfv4e -gdwarf-2 -feliminate-unused-debug-types \ - -fmerge-all-constants -# Incompatible code in barebox for -std=c99 -LDFLAGS_barebox :=-L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc -# --verbose --stats - -machdirs := $(patsubst %,arch/m68k/mach-%/,$(machine-y)) - -ifeq ($(KBUILD_SRC),) -CPPFLAGS += $(patsubst %,-I%include,$(machdirs)) -else -CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs)) -endif - - -all: $(KBUILD_IMAGE) - -archprepare: maketools - -PHONY += maketools - - -ifneq ($(board-y),) -BOARD := arch/m68k/boards/$(board-y)/ -else -BOARD := -endif - -ifneq ($(machine-y),) -MACH := arch/m68k/mach-$(machine-y)/ -else -MACH := -endif - -common-y += $(BOARD) $(MACH) -common-y += arch/m68k/lib/ arch/m68k/cpu/ - -lds-$(CONFIG_GENERIC_LINKER_SCRIPT) := arch/m68k/lib/barebox.lds -lds-$(CONFIG_BOARD_LINKER_SCRIPT) := $(BOARD)/barebox.lds - -CLEAN_FILES += arch/m68k/lib/barebox.lds diff --git a/arch/m68k/boards/kp_ukd_r1_num/Makefile b/arch/m68k/boards/kp_ukd_r1_num/Makefile deleted file mode 100644 index 65f2a02fca..0000000000 --- a/arch/m68k/boards/kp_ukd_r1_num/Makefile +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2007 Carsten Schlote <schlote@vahanus.net> -# See file CREDITS for list of people who contributed to this project. -# -# This file is part of barebox. -# -# barebox is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# barebox is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with barebox. If not, see <http://www.gnu.org/licenses/>. -# - -# The build system allows to split everything into distinct files covering an -# separate issue. Use that! - -# Board specific callbacks and initialisations - -obj-y += lowlevel_init.o -obj-y += highlevel_init.o -obj-y += kp_ukd_r1_num.o - -obj-y += pci-stubs.o - diff --git a/arch/m68k/boards/kp_ukd_r1_num/env/bin/_update b/arch/m68k/boards/kp_ukd_r1_num/env/bin/_update deleted file mode 100644 index 014bce3512..0000000000 --- a/arch/m68k/boards/kp_ukd_r1_num/env/bin/_update +++ /dev/null @@ -1,36 +0,0 @@ -#!/bin/sh - -if [ -z "$part" -o -z "$image" ]; then - echo "define \$part and \$image" - exit 1 -fi - -if [ ! -e "$part" ]; then - echo "Partition $part does not exist" - exit 1 -fi - -if [ $# = 1 ]; then - image=$1 -fi - -if [ x$ip = xdhcp ]; then - dhcp -fi - -ping $eth0.serverip -if [ $? -ne 0 ] ; then - echo "update aborted" - exit 1 -fi - -unprotect $part - -echo -echo "erasing partition $part" -erase $part - -echo -echo "flashing $image to $part" -echo -tftp $image $part diff --git a/arch/m68k/boards/kp_ukd_r1_num/env/bin/boot b/arch/m68k/boards/kp_ukd_r1_num/env/bin/boot deleted file mode 100644 index c9fcbac620..0000000000 --- a/arch/m68k/boards/kp_ukd_r1_num/env/bin/boot +++ /dev/null @@ -1,38 +0,0 @@ -#!/bin/sh - -. /env/config - -if [ x$1 = xflash ]; then - root=flash - kernel=flash -fi - -if [ x$1 = xnet ]; then - root=net - kernel=net -fi - -if [ x$ip = xdhcp ]; then - bootargs="$bootargs ip=dhcp" -else - bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" -fi - -if [ x$root = xflash ]; then - bootargs="$bootargs root=$rootpart rootfstype=jffs2" -else - bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot" -fi - -bootargs="$bootargs mtdparts=physmap-flash.0:$mtdparts" - -if [ $kernel = net ]; then - if [ x$ip = xdhcp ]; then - dhcp - fi - tftp $uimage uImage || exit 1 - bootm uImage -else - bootm /dev/nor0.kernel -fi - diff --git a/arch/m68k/boards/kp_ukd_r1_num/env/bin/init b/arch/m68k/boards/kp_ukd_r1_num/env/bin/init deleted file mode 100644 index 48e2139f7d..0000000000 --- a/arch/m68k/boards/kp_ukd_r1_num/env/bin/init +++ /dev/null @@ -1,20 +0,0 @@ -#!/bin/sh - -PATH=/env/bin -export PATH - -. /env/config -addpart /dev/nor0 $mtdparts - -echo -echo -n "Hit any key to stop autoboot: " -timeout -a $autoboot_timeout -if [ $? != 0 ]; then - echo - echo "type update_kernel [<imagename>] to update kernel into flash" - echo "type udate_root [<imagename>] to update rootfs into flash" - echo - exit -fi - -boot
\ No newline at end of file diff --git a/arch/m68k/boards/kp_ukd_r1_num/env/bin/pcidmaloop b/arch/m68k/boards/kp_ukd_r1_num/env/bin/pcidmaloop deleted file mode 100644 index 24e76cbed7..0000000000 --- a/arch/m68k/boards/kp_ukd_r1_num/env/bin/pcidmaloop +++ /dev/null @@ -1,14 +0,0 @@ -pci stat -pci stat -c -while true; do - pci readm 32 0xA1000000 32 -s - pci readm 32 0xA2000000 256 -s - pci dmatx 2000 a2000100 128 -s - pci writem 32 0xa2000100 0x12345678 4 -s - pci readm 32 0xA3000000 256 -s - pci dmatx 2000 a3000040 128 -s - pci writem 32 0xa3000100 0x12345678 4 -s - pci readm 32 0xA4000000 16 -s - pci dmatx 2000 a4000080 4 -s - pci writem 32 0xa4000080 0x12345678 4 -s -done diff --git a/arch/m68k/boards/kp_ukd_r1_num/env/bin/pciloop b/arch/m68k/boards/kp_ukd_r1_num/env/bin/pciloop deleted file mode 100644 index 4a804f9f31..0000000000 --- a/arch/m68k/boards/kp_ukd_r1_num/env/bin/pciloop +++ /dev/null @@ -1,13 +0,0 @@ -pci stat -pci stat -c -while true; do - pci readm 32 0xA1000000 32 -s - pci readm 32 0xA2000000 256 -s - pci writem 32 0xa2000100 0x12345678 4 -s - pci readm 32 0xA3000000 256 -s - pci writem 32 0xa3000100 0x12345678 4 -s - pci readm 32 0xA4000000 16 -s - pci writem 32 0xa4000080 0x12345678 4 -s - -# pci dmatx 2000 a3000040 128 -s -done diff --git a/arch/m68k/boards/kp_ukd_r1_num/env/bin/update_kernel b/arch/m68k/boards/kp_ukd_r1_num/env/bin/update_kernel deleted file mode 100644 index 1ad95fc5d6..0000000000 --- a/arch/m68k/boards/kp_ukd_r1_num/env/bin/update_kernel +++ /dev/null @@ -1,8 +0,0 @@ -#!/bin/sh - -. /env/config - -image=$uimage -part=/dev/nor0.kernel - -. /env/bin/_update $1 diff --git a/arch/m68k/boards/kp_ukd_r1_num/env/bin/update_root b/arch/m68k/boards/kp_ukd_r1_num/env/bin/update_root deleted file mode 100644 index b757a5b922..0000000000 --- a/arch/m68k/boards/kp_ukd_r1_num/env/bin/update_root +++ /dev/null @@ -1,8 +0,0 @@ -#!/bin/sh - -. /env/config - -image=$jffs2 -part=/dev/nor0.root - -. /env/bin/_update $1 diff --git a/arch/m68k/boards/kp_ukd_r1_num/env/config b/arch/m68k/boards/kp_ukd_r1_num/env/config deleted file mode 100644 index 14958ba1df..0000000000 --- a/arch/m68k/boards/kp_ukd_r1_num/env/config +++ /dev/null @@ -1,32 +0,0 @@ -#!/bin/sh - -# can be either 'net' or 'flash' -kernel=net -root=net - -# use 'dhcp' todo dhcp in barebox and in kernel -ip=dhcp - -# -# setup default ethernet address -# -eth0.ipaddr=192.168.0.99 -eth0.netmask=255.255.255.0 -eth0.gateway=192.168.0.110 -eth0.serverip=192.168.0.110 - -uimage=uImage-mcf5475 -jffs2=root-mcf5475-ptx.jffs2 - -autoboot_timeout=3 - -#nfsroot="/home/cschlote/src/bitshrine/ltib/rootfs" -nfsroot="/home/cschlote/src/pengutronics/ptxdist-project-KP-UKD/root-debug,v3" -bootargs="console=ttyS0 rw initcall_debug debug" - -# -# setup the partitions in the main flash -# -mtdparts=512k(self),256k(env),3M(kernel),-(root) -rootpart="/dev/mtdblock3" - diff --git a/arch/m68k/boards/kp_ukd_r1_num/highlevel_init.c b/arch/m68k/boards/kp_ukd_r1_num/highlevel_init.c deleted file mode 100644 index 3a88cd68c7..0000000000 --- a/arch/m68k/boards/kp_ukd_r1_num/highlevel_init.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * (C) 2007,2008 konzeptpark, Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * @brief This file contains high-level init functions. - * - */ -#include <common.h> -#include <reloc.h> -#include <config.h> -#include <mach/mcf54xx-regs.h> - -static void board_gpio_init(void) -{ - /* - * Enable Ethernet signals so that, if a cable is plugged into - * the ports, the lines won't be floating and potentially cause - * erroneous transmissions - */ - MCF_GPIO_PAR_FECI2CIRQ = 0 - | MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC - | MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO - | MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MII - | MCF_GPIO_PAR_FECI2CIRQ_PAR_E17 - | MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDC - | MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO - | MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MII - | MCF_GPIO_PAR_FECI2CIRQ_PAR_E07; -} - - -static void board_psc_init(void) -{ -#if (CFG_EARLY_UART_PORT == 0) - MCF_GPIO_PAR_PSC0 = (0 -#ifdef HARDWARE_FLOW_CONTROL - | MCF_GPIO_PAR_PSC0_PAR_CTS0_CTS - | MCF_GPIO_PAR_PSC0_PAR_RTS0_RTS -#endif - | MCF_GPIO_PAR_PSC0_PAR_TXD0 - | MCF_GPIO_PAR_PSC0_PAR_RXD0); -#elif (CFG_EARLY_UART_PORT == 1) - MCF_GPIO_PAR_PSC1 = (0 -#ifdef HARDWARE_FLOW_CONTROL - | MCF_GPIO_PAR_PSC1_PAR_CTS1_CTS - | MCF_GPIO_PAR_PSC1_PAR_RTS1_RTS -#endif - | MCF_GPIO_PAR_PSC1_PAR_TXD1 - | MCF_GPIO_PAR_PSC1_PAR_RXD1); -#elif (CFG_EARLY_UART_PORT == 2) - MCF_GPIO_PAR_PSC2 = (0 -#ifdef HARDWARE_FLOW_CONTROL - | MCF_GPIO_PAR_PSC2_PAR_CTS2_CTS - | MCF_GPIO_PAR_PSC2_PAR_RTS2_RTS -#endif - | MCF_GPIO_PAR_PSC2_PAR_TXD2 - | MCF_GPIO_PAR_PSC2_PAR_RXD2); -#elif (CFG_EARLY_UART_PORT == 3) - MCF_GPIO_PAR_PSC3 = (0 -#ifdef HARDWARE_FLOW_CONTROL - | MCF_GPIO_PAR_PSC3_PAR_CTS3_CTS - | MCF_GPIO_PAR_PSC3_PAR_RTS3_RTS -#endif - | MCF_GPIO_PAR_PSC3_PAR_TXD3 - | MCF_GPIO_PAR_PSC3_PAR_RXD3); -#else -#error "Invalid CFG_EARLY_UART_PORT setting" -#endif - - /* Put PSC in UART mode */ - MCF_PSC_SICR(CFG_EARLY_UART_PORT) = MCF_PSC_SICR_SIM_UART; - - /* Call generic UART initialization */ -// mcf5xxx_uart_init(DBUG_UART_PORT, board_get_baud()); -} - - -/** Do board specific early init - * - * @note We run at link address now, you can now call other code - */ -void board_init_highlevel(void) -{ - /* Initialize platform specific GPIOs */ - board_gpio_init(); - - /* Init UART GPIOs and Modes */ - board_psc_init(); - - /* Setup the early init data */ -#ifdef CONFIG_HAS_EARLY_INIT - early_init(); -#endif - /* Configure the early debug output facility */ -#ifdef CONFIG_DEBUG_LL - early_debug_init(); -#endif -} - -/** Provide address of early debug low-level output - * - * @todo Should return real address for UART register map. - */ -void *get_early_console_base(const char *name) -{ - return (void*)1 + CFG_EARLY_UART_PORT; -} diff --git a/arch/m68k/boards/kp_ukd_r1_num/kp_ukd_r1_num.c b/arch/m68k/boards/kp_ukd_r1_num/kp_ukd_r1_num.c deleted file mode 100644 index 7475ab326b..0000000000 --- a/arch/m68k/boards/kp_ukd_r1_num/kp_ukd_r1_num.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * (C) 2007 konzeptpark, Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - - -#include <common.h> -#include <init.h> -#include <driver.h> -#include <fec.h> -#include <environment.h> -#include <mach/mcf54xx-regs.h> -//#include <mach/gpio.h> -#include <mach/clocks.h> -#include <asm/io.h> -#include <partition.h> - -/* - * Return board clock in MHz FIXME move to clocks file - */ -ulong mcfv4e_get_bus_clk(void) -{ - return CFG_SYSTEM_CORE_CLOCK; -} -/* - * Up to 64MiB NOR type flash, connected to - * CS line 0, data width is 32 bit - */ -static struct device_d cfi_dev = { - .id = -1, - .name = "cfi_flash", - .map_base = CFG_FLASH_ADDRESS, - .size = CFG_FLASH_SIZE, -}; - -/* - * up to 2MiB static RAM type memory, connected - * to CS4, data width is 16 bit - */ -//static struct device_d sram_dev = { -// .id = -1, -// .name = "sram", -//FIXME .map_base = IMX_CS4_BASE, -//FIXME .size = IMX_CS4_RANGE, /* area size */ -//}; - -/* - * ?MiB NAND type flash, data width 8 bit - */ -//static struct device_d nand_dev = { -// .id = -1, -// .name = "cfi_flash_nand", -// .map_base = 0xfc000000, /* FIXME */ -// .size = 32 * 1024 * 1024, /* FIXME */ -//}; - - -/* - * Build in FastEthernetControllers (FECs) - */ -static struct fec_platform_data fec_info = { - .xcv_type = MII100, -}; - -static struct device_d network_dev0 = { - .id = -1, - .name = "fec_mcf54xx", - .map_base = MCF_FEC_ADDR(0), - .size = MCF_FEC_SIZE(0), /* area size */ - .platform_data = &fec_info, -}; -static struct device_d network_dev1 = { - .id = -1, - .name = "fec_mcf54xx", - .map_base = MCF_FEC_ADDR(1), - .size = MCF_FEC_SIZE(1), /* area size */ - .platform_data = &fec_info, -}; - -/* - * 128MiB of SDRAM, data width is 32 bit - */ -static struct memory_platform_data ram_pdata = { - .name = "ram0", - .flags = DEVFS_RDWR, -}; - -static struct device_d sdram_dev = { - .id = -1, - .name = "mem", - .map_base = CFG_SDRAM_ADDRESS, - .size = CFG_SDRAM_SIZE, - .platform_data = &ram_pdata, -}; - -static int mcfv4e_devices_init(void) -{ - printf("Setting up board devices...\n"); - - /* setup pins for I2C2 (for EEPROM, RTC) */ -//FIXME imx_gpio_mode(MUX_CSPI2_MOSI_I2C2_SCL); -//FIXME imx_gpio_mode(MUX_CSPI2_MISO_I2C2_SCL); - - register_device(&cfi_dev); - - /* - * Create partitions that should be - * not touched by any regular user - */ - devfs_add_partition("nor0", 0x00000, 0x80000, PARTITION_FIXED, "self0"); /* ourself */ - devfs_add_partition("nor0", 0x80000, 0x40000, PARTITION_FIXED, "env0"); /* environment */ - protect_file("/dev/env0", 1); - - //register_device(&sram_dev); - //register_device(&nand_dev); - - register_device(&network_dev0); - //register_device(&network_dev1); - - register_device(&sdram_dev); - - return 0; -} - -device_initcall(mcfv4e_devices_init); - -static struct device_d mcfv4e_serial_device = { - .id = -1, - .name = "mcfv4e_serial", - .map_base = 1+CFG_EARLY_UART_PORT, - .size = 16 * 1024, -}; - -static int mcfv4e_console_init(void) -{ - /* init gpios for serial port */ - - /* Already set in lowlevel_init.c */ - - register_device(&mcfv4e_serial_device); - return 0; -} - -console_initcall(mcfv4e_console_init); - diff --git a/arch/m68k/boards/kp_ukd_r1_num/kp_ukd_r1_num.dox b/arch/m68k/boards/kp_ukd_r1_num/kp_ukd_r1_num.dox deleted file mode 100644 index ca0fcbcf39..0000000000 --- a/arch/m68k/boards/kp_ukd_r1_num/kp_ukd_r1_num.dox +++ /dev/null @@ -1,13 +0,0 @@ -/** @page kp_ukd_r1 konzeptpark MCB2 Prototype Board - -This target is based on a PhyTec PhyCore MCF54x5 NUM CPU. The card is shipped with: - -- up to 64MiB NOR type Flash Memory -- 128MiB synchronous dynamic RAM -- PCI USB 2.0 Host -- PCCard Controller -- MiniPCI Parallel -- MiniPCIe (USB lane only) -- ... - -*/ diff --git a/arch/m68k/boards/kp_ukd_r1_num/lowlevel_init.c b/arch/m68k/boards/kp_ukd_r1_num/lowlevel_init.c deleted file mode 100644 index b3de505c24..0000000000 --- a/arch/m68k/boards/kp_ukd_r1_num/lowlevel_init.c +++ /dev/null @@ -1,183 +0,0 @@ -/* - * (C) 2007 konzeptpark, Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * @brief This file contains ... - * - */ -#include <common.h> -#include <config.h> -#include <mach/mcf54xx-regs.h> - -/** Initialize board specific very early inits - * - * @note This code is not allowed to call other code - just init - * your Chipselects and SDRAM stuff here! - */ -void board_init_lowlevel(void) -{ - /* - * The phyCORE-MCF548x has a 32MB or 64MB boot flash. - * The is a CF Card and ControlRegs on CS1 and CS2 - */ - - /* Setup SysGlue Chip-Select */ - MCF_FBCS_CSAR5 = MCF_FBCS_CSAR_BA(CFG_SYSGLUE_ADDRESS); - - MCF_FBCS_CSCR5 = (MCF_FBCS_CSCR_PS_32 - | MCF_FBCS_CSCR_AA - | MCF_FBCS_CSCR_ASET(1) - | MCF_FBCS_CSCR_WS(CFG_SYSGLUE_WAIT_STATES)); - - MCF_FBCS_CSMR5 = (MCF_FBCS_CSMR_BAM_16M - | MCF_FBCS_CSMR_V); - - /* Setup boot flash chip-select */ - MCF_FBCS_CSAR0 = MCF_FBCS_CSAR_BA(CFG_FLASH_ADDRESS); - - MCF_FBCS_CSCR0 = (MCF_FBCS_CSCR_PS_32 - | MCF_FBCS_CSCR_AA - | MCF_FBCS_CSCR_ASET(1) - | MCF_FBCS_CSCR_WS(CFG_FLASH_WAIT_STATES)); - - MCF_FBCS_CSMR0 = (MCF_FBCS_CSMR_BAM_32M - | MCF_FBCS_CSMR_V); - - /* - * Check to see if the SDRAM has already been initialized - * by a run control tool - */ - if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)) - { - /* - * Basic configuration and initialization - */ - // 0x000002AA - MCF_SDRAMC_SDRAMDS = (0 - | MCF_SDRAMC_SDRAMDS_SB_E(MCF_SDRAMC_SDRAMDS_DRIVE_8MA) - | MCF_SDRAMC_SDRAMDS_SB_C(MCF_SDRAMC_SDRAMDS_DRIVE_8MA) - | MCF_SDRAMC_SDRAMDS_SB_A(MCF_SDRAMC_SDRAMDS_DRIVE_8MA) - | MCF_SDRAMC_SDRAMDS_SB_S(MCF_SDRAMC_SDRAMDS_DRIVE_8MA) - | MCF_SDRAMC_SDRAMDS_SB_D(MCF_SDRAMC_SDRAMDS_DRIVE_8MA) - ); - - // 0x0000001A - MCF_SDRAMC_CS0CFG = (0 - | MCF_SDRAMC_CSnCFG_CSBA(CFG_SDRAM_ADDRESS) - | MCF_SDRAMC_CSnCFG_CSSZ(MCF_SDRAMC_CSnCFG_CSSZ_128MBYTE) - ); - - MCF_SDRAMC_CS1CFG = 0; - MCF_SDRAMC_CS2CFG = 0; - MCF_SDRAMC_CS3CFG = 0; - - // 0x73611730 - MCF_SDRAMC_SDCFG1 = (0 - | MCF_SDRAMC_SDCFG1_SRD2RW((unsigned int)((CFG_SDRAM_CASL + CFG_SDRAM_BL / 2 + 1) + 0.5)) - | MCF_SDRAMC_SDCFG1_SWT2RD((unsigned int) (CFG_SDRAM_TWR + 1)) - | MCF_SDRAMC_SDCFG1_RDLAT((unsigned int)((CFG_SDRAM_CASL * 2) + 2)) - | MCF_SDRAMC_SDCFG1_ACT2RW((unsigned int)(((CFG_SDRAM_TRCD / CFG_SYSTEM_CORE_PERIOD) - 1) + 0.5)) - | MCF_SDRAMC_SDCFG1_PRE2ACT((unsigned int)(((CFG_SDRAM_TRP / CFG_SYSTEM_CORE_PERIOD) - 1) + 0.5)) - | MCF_SDRAMC_SDCFG1_REF2ACT((unsigned int)(((CFG_SDRAM_TRFC / CFG_SYSTEM_CORE_PERIOD) - 1) + 0.5)) - | MCF_SDRAMC_SDCFG1_WTLAT(3) - ); - - // 0x46770000 - MCF_SDRAMC_SDCFG2 = (0 - | MCF_SDRAMC_SDCFG2_BRD2PRE(CFG_SDRAM_BL / 2) - | MCF_SDRAMC_SDCFG2_BWT2RW(CFG_SDRAM_BL / 2 + CFG_SDRAM_TWR) - | MCF_SDRAMC_SDCFG2_BRD2WT(7) - | MCF_SDRAMC_SDCFG2_BL(CFG_SDRAM_BL - 1) - ); - - /* - * Precharge and enable write to SDMR - */ - // 0xE10B0002 - MCF_SDRAMC_SDCR = (0 - | MCF_SDRAMC_SDCR_MODE_EN - | MCF_SDRAMC_SDCR_CKE - | MCF_SDRAMC_SDCR_DDR - | MCF_SDRAMC_SDCR_MUX(1) // 13 x 10 x 2 ==> MUX=1 - | MCF_SDRAMC_SDCR_RCNT((int)(((CFG_SDRAM_TREFI / (CFG_SYSTEM_CORE_PERIOD * 64)) - 1) + 0.5)) - | MCF_SDRAMC_SDCR_IPALL - ); - - /* - * Write extended mode register - */ - // 0x40010000 - MCF_SDRAMC_SDMR = (0 - | MCF_SDRAMC_SDMR_BNKAD_LEMR - | MCF_SDRAMC_SDMR_AD(0x0) - | MCF_SDRAMC_SDMR_CMD - ); - - /* - * Write mode register and reset DLL - */ - // 0x048d0000 - MCF_SDRAMC_SDMR = (0 - | MCF_SDRAMC_SDMR_BNKAD_LMR - | MCF_SDRAMC_SDMR_AD(CFG_SDRAM_RESET_DLL | CFG_SDRAM_MOD) - | MCF_SDRAMC_SDMR_CMD - ); - - /* - * Execute a PALL command - */ - // 0xE10B0002 - MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL; - - /* - * Perform two REF cycles - */ - // 0xE10B0004 - MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF; - MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF; - - /* - * Write mode register and clear reset DLL - */ - // 0x008D0000 - MCF_SDRAMC_SDMR = (0 - | MCF_SDRAMC_SDMR_BNKAD_LMR - | MCF_SDRAMC_SDMR_AD(CFG_SDRAM_MOD) - | MCF_SDRAMC_SDMR_CMD - ); - - /* - * Enable auto refresh and lock SDMR - */ - // 0x610B0000 - MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN; - - // 0x710B0F00 - MCF_SDRAMC_SDCR |= (0 - | MCF_SDRAMC_SDCR_REF - | MCF_SDRAMC_SDCR_DQS_OE(0xF) - ); - } -} - -/** @file - * - * Target specific early chipselect and SDRAM init. - */ diff --git a/arch/m68k/boards/kp_ukd_r1_num/pci-stubs.c b/arch/m68k/boards/kp_ukd_r1_num/pci-stubs.c deleted file mode 100644 index b7ab7c7d72..0000000000 --- a/arch/m68k/boards/kp_ukd_r1_num/pci-stubs.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * (C) 2007,2008 Carsten Schlote <schlote@vahanus.net> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * @brief This file contains callbacks for the PCI subsystem - * - */ -#include <common.h> -#include <config.h> - - -/** Returns mapping from PCI slot to CPU irq for the target board - * @return Coldfire IRQ vector number, or -1 for no irq - */ -int mcfv4e_pci_gethostirq(uint8_t slot, uint8_t irqpin) -{ - int rc = -1; - switch (slot) - { - case 16 : break; - case 17 ... 21 : rc = 64 + 7; break; // Eport IRQ7 - } - return rc; -} diff --git a/arch/m68k/boards/phycore_mcf54xx/Makefile b/arch/m68k/boards/phycore_mcf54xx/Makefile deleted file mode 100644 index 054123fe75..0000000000 --- a/arch/m68k/boards/phycore_mcf54xx/Makefile +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2007 Carsten Schlote <schlote@vahanus.net> -# See file CREDITS for list of people who contributed to this project. -# -# This file is part of barebox. -# -# barebox is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# barebox is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with barebox. If not, see <http://www.gnu.org/licenses/>. -# - -# The build system allows to split everything into distinct files covering an -# separate issue. Use that! - -# Board specific callbacks and initialisations - -obj-y += lowlevel_init.o -obj-y += highlevel_init.o -obj-y += phyCore_MCF54xx.o - -obj-y += pci-stubs.o - diff --git a/arch/m68k/boards/phycore_mcf54xx/env/bin/_update b/arch/m68k/boards/phycore_mcf54xx/env/bin/_update deleted file mode 100644 index 014bce3512..0000000000 --- a/arch/m68k/boards/phycore_mcf54xx/env/bin/_update +++ /dev/null @@ -1,36 +0,0 @@ -#!/bin/sh - -if [ -z "$part" -o -z "$image" ]; then - echo "define \$part and \$image" - exit 1 -fi - -if [ ! -e "$part" ]; then - echo "Partition $part does not exist" - exit 1 -fi - -if [ $# = 1 ]; then - image=$1 -fi - -if [ x$ip = xdhcp ]; then - dhcp -fi - -ping $eth0.serverip -if [ $? -ne 0 ] ; then - echo "update aborted" - exit 1 -fi - -unprotect $part - -echo -echo "erasing partition $part" -erase $part - -echo -echo "flashing $image to $part" -echo -tftp $image $part diff --git a/arch/m68k/boards/phycore_mcf54xx/env/bin/boot b/arch/m68k/boards/phycore_mcf54xx/env/bin/boot deleted file mode 100644 index c9fcbac620..0000000000 --- a/arch/m68k/boards/phycore_mcf54xx/env/bin/boot +++ /dev/null @@ -1,38 +0,0 @@ -#!/bin/sh - -. /env/config - -if [ x$1 = xflash ]; then - root=flash - kernel=flash -fi - -if [ x$1 = xnet ]; then - root=net - kernel=net -fi - -if [ x$ip = xdhcp ]; then - bootargs="$bootargs ip=dhcp" -else - bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" -fi - -if [ x$root = xflash ]; then - bootargs="$bootargs root=$rootpart rootfstype=jffs2" -else - bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot" -fi - -bootargs="$bootargs mtdparts=physmap-flash.0:$mtdparts" - -if [ $kernel = net ]; then - if [ x$ip = xdhcp ]; then - dhcp - fi - tftp $uimage uImage || exit 1 - bootm uImage -else - bootm /dev/nor0.kernel -fi - diff --git a/arch/m68k/boards/phycore_mcf54xx/env/bin/init b/arch/m68k/boards/phycore_mcf54xx/env/bin/init deleted file mode 100644 index 48e2139f7d..0000000000 --- a/arch/m68k/boards/phycore_mcf54xx/env/bin/init +++ /dev/null @@ -1,20 +0,0 @@ -#!/bin/sh - -PATH=/env/bin -export PATH - -. /env/config -addpart /dev/nor0 $mtdparts - -echo -echo -n "Hit any key to stop autoboot: " -timeout -a $autoboot_timeout -if [ $? != 0 ]; then - echo - echo "type update_kernel [<imagename>] to update kernel into flash" - echo "type udate_root [<imagename>] to update rootfs into flash" - echo - exit -fi - -boot
\ No newline at end of file diff --git a/arch/m68k/boards/phycore_mcf54xx/env/bin/pcidmaloop b/arch/m68k/boards/phycore_mcf54xx/env/bin/pcidmaloop deleted file mode 100644 index 24e76cbed7..0000000000 --- a/arch/m68k/boards/phycore_mcf54xx/env/bin/pcidmaloop +++ /dev/null @@ -1,14 +0,0 @@ -pci stat -pci stat -c -while true; do - pci readm 32 0xA1000000 32 -s - pci readm 32 0xA2000000 256 -s - pci dmatx 2000 a2000100 128 -s - pci writem 32 0xa2000100 0x12345678 4 -s - pci readm 32 0xA3000000 256 -s - pci dmatx 2000 a3000040 128 -s - pci writem 32 0xa3000100 0x12345678 4 -s - pci readm 32 0xA4000000 16 -s - pci dmatx 2000 a4000080 4 -s - pci writem 32 0xa4000080 0x12345678 4 -s -done diff --git a/arch/m68k/boards/phycore_mcf54xx/env/bin/pciloop b/arch/m68k/boards/phycore_mcf54xx/env/bin/pciloop deleted file mode 100644 index 4a804f9f31..0000000000 --- a/arch/m68k/boards/phycore_mcf54xx/env/bin/pciloop +++ /dev/null @@ -1,13 +0,0 @@ -pci stat -pci stat -c -while true; do - pci readm 32 0xA1000000 32 -s - pci readm 32 0xA2000000 256 -s - pci writem 32 0xa2000100 0x12345678 4 -s - pci readm 32 0xA3000000 256 -s - pci writem 32 0xa3000100 0x12345678 4 -s - pci readm 32 0xA4000000 16 -s - pci writem 32 0xa4000080 0x12345678 4 -s - -# pci dmatx 2000 a3000040 128 -s -done diff --git a/arch/m68k/boards/phycore_mcf54xx/env/bin/update_kernel b/arch/m68k/boards/phycore_mcf54xx/env/bin/update_kernel deleted file mode 100644 index 1ad95fc5d6..0000000000 --- a/arch/m68k/boards/phycore_mcf54xx/env/bin/update_kernel +++ /dev/null @@ -1,8 +0,0 @@ -#!/bin/sh - -. /env/config - -image=$uimage -part=/dev/nor0.kernel - -. /env/bin/_update $1 diff --git a/arch/m68k/boards/phycore_mcf54xx/env/bin/update_root b/arch/m68k/boards/phycore_mcf54xx/env/bin/update_root deleted file mode 100644 index b757a5b922..0000000000 --- a/arch/m68k/boards/phycore_mcf54xx/env/bin/update_root +++ /dev/null @@ -1,8 +0,0 @@ -#!/bin/sh - -. /env/config - -image=$jffs2 -part=/dev/nor0.root - -. /env/bin/_update $1 diff --git a/arch/m68k/boards/phycore_mcf54xx/env/config b/arch/m68k/boards/phycore_mcf54xx/env/config deleted file mode 100644 index 58550625d2..0000000000 --- a/arch/m68k/boards/phycore_mcf54xx/env/config +++ /dev/null @@ -1,32 +0,0 @@ -#!/bin/sh - -# can be either 'net' or 'flash' -kernel=net -root=net - -# use 'dhcp' todo dhcp in barebox and in kernel -ip=dhcp - -# -# setup default ethernet address -# -eth0.ipaddr=192.168.0.99 -eth0.netmask=255.255.255.0 -eth0.gateway=192.168.0.110 -eth0.serverip=192.168.0.110 - -uimage=uImage-mcf5485 -jffs2=root-mcf5485-ptx.jffs2 - -autoboot_timeout=3 - -#nfsroot="/home/cschlote/src/bitshrine/ltib/rootfs" -nfsroot="/home/cschlote/src/pengutronics/ptxdist-project-KP-UKD/root-debug,v3" -bootargs="console=ttyS0 rw initcall_debug debug" - -# -# setup the partitions in the main flash -# -mtdparts=512k(self),256k(env),3M(kernel),-(root) -rootpart="/dev/mtdblock3" - diff --git a/arch/m68k/boards/phycore_mcf54xx/highlevel_init.c b/arch/m68k/boards/phycore_mcf54xx/highlevel_init.c deleted file mode 100644 index 3a88cd68c7..0000000000 --- a/arch/m68k/boards/phycore_mcf54xx/highlevel_init.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * (C) 2007,2008 konzeptpark, Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * @brief This file contains high-level init functions. - * - */ -#include <common.h> -#include <reloc.h> -#include <config.h> -#include <mach/mcf54xx-regs.h> - -static void board_gpio_init(void) -{ - /* - * Enable Ethernet signals so that, if a cable is plugged into - * the ports, the lines won't be floating and potentially cause - * erroneous transmissions - */ - MCF_GPIO_PAR_FECI2CIRQ = 0 - | MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC - | MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO - | MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MII - | MCF_GPIO_PAR_FECI2CIRQ_PAR_E17 - | MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDC - | MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO - | MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MII - | MCF_GPIO_PAR_FECI2CIRQ_PAR_E07; -} - - -static void board_psc_init(void) -{ -#if (CFG_EARLY_UART_PORT == 0) - MCF_GPIO_PAR_PSC0 = (0 -#ifdef HARDWARE_FLOW_CONTROL - | MCF_GPIO_PAR_PSC0_PAR_CTS0_CTS - | MCF_GPIO_PAR_PSC0_PAR_RTS0_RTS -#endif - | MCF_GPIO_PAR_PSC0_PAR_TXD0 - | MCF_GPIO_PAR_PSC0_PAR_RXD0); -#elif (CFG_EARLY_UART_PORT == 1) - MCF_GPIO_PAR_PSC1 = (0 -#ifdef HARDWARE_FLOW_CONTROL - | MCF_GPIO_PAR_PSC1_PAR_CTS1_CTS - | MCF_GPIO_PAR_PSC1_PAR_RTS1_RTS -#endif - | MCF_GPIO_PAR_PSC1_PAR_TXD1 - | MCF_GPIO_PAR_PSC1_PAR_RXD1); -#elif (CFG_EARLY_UART_PORT == 2) - MCF_GPIO_PAR_PSC2 = (0 -#ifdef HARDWARE_FLOW_CONTROL - | MCF_GPIO_PAR_PSC2_PAR_CTS2_CTS - | MCF_GPIO_PAR_PSC2_PAR_RTS2_RTS -#endif - | MCF_GPIO_PAR_PSC2_PAR_TXD2 - | MCF_GPIO_PAR_PSC2_PAR_RXD2); -#elif (CFG_EARLY_UART_PORT == 3) - MCF_GPIO_PAR_PSC3 = (0 -#ifdef HARDWARE_FLOW_CONTROL - | MCF_GPIO_PAR_PSC3_PAR_CTS3_CTS - | MCF_GPIO_PAR_PSC3_PAR_RTS3_RTS -#endif - | MCF_GPIO_PAR_PSC3_PAR_TXD3 - | MCF_GPIO_PAR_PSC3_PAR_RXD3); -#else -#error "Invalid CFG_EARLY_UART_PORT setting" -#endif - - /* Put PSC in UART mode */ - MCF_PSC_SICR(CFG_EARLY_UART_PORT) = MCF_PSC_SICR_SIM_UART; - - /* Call generic UART initialization */ -// mcf5xxx_uart_init(DBUG_UART_PORT, board_get_baud()); -} - - -/** Do board specific early init - * - * @note We run at link address now, you can now call other code - */ -void board_init_highlevel(void) -{ - /* Initialize platform specific GPIOs */ - board_gpio_init(); - - /* Init UART GPIOs and Modes */ - board_psc_init(); - - /* Setup the early init data */ -#ifdef CONFIG_HAS_EARLY_INIT - early_init(); -#endif - /* Configure the early debug output facility */ -#ifdef CONFIG_DEBUG_LL - early_debug_init(); -#endif -} - -/** Provide address of early debug low-level output - * - * @todo Should return real address for UART register map. - */ -void *get_early_console_base(const char *name) -{ - return (void*)1 + CFG_EARLY_UART_PORT; -} diff --git a/arch/m68k/boards/phycore_mcf54xx/lowlevel_init.c b/arch/m68k/boards/phycore_mcf54xx/lowlevel_init.c deleted file mode 100644 index 2837e3ed67..0000000000 --- a/arch/m68k/boards/phycore_mcf54xx/lowlevel_init.c +++ /dev/null @@ -1,194 +0,0 @@ -/* - * (C) 2007 konzeptpark, Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * @brief This file contains ... - * - */ -#include <common.h> -#include <config.h> -#include <mach/mcf54xx-regs.h> - -/** Initialize board specific very early inits - * - * @note This code is not allowed to call other code - just init - * your Chipselects and SDRAM stuff here! - */ -void board_init_lowlevel(void) -{ - /* - * The phyCORE-MCF548x has a 32MB or 64MB boot flash. - * The is a CF Card and ControlRegs on CS1 and CS2 - */ - - /* Setup SysGlue Chip-Select for user IOs */ - MCF_FBCS_CSAR2 = MCF_FBCS_CSAR_BA(CFG_XPLD_ADDRESS); - - MCF_FBCS_CSCR2 = (MCF_FBCS_CSCR_PS_16 - | MCF_FBCS_CSCR_AA - | MCF_FBCS_CSCR_ASET(1) - | MCF_FBCS_CSCR_WS(CFG_XPLD_WAIT_STATES)); - - MCF_FBCS_CSMR2 = (MCF_FBCS_CSMR_BAM_16M - | MCF_FBCS_CSMR_V); - - /* Setup SysGlue Chip-Select for CFCARD */ - MCF_FBCS_CSAR1 = MCF_FBCS_CSAR_BA(CFG_CFCARD_ADDRESS); - - MCF_FBCS_CSCR1 = (MCF_FBCS_CSCR_PS_16 - | MCF_FBCS_CSCR_AA - | MCF_FBCS_CSCR_ASET(1) - | MCF_FBCS_CSCR_WS(CFG_CFCARD_WAIT_STATES)); - - MCF_FBCS_CSMR1 = (MCF_FBCS_CSMR_BAM_16M - | MCF_FBCS_CSMR_V); - - /* Setup boot flash chip-select */ - MCF_FBCS_CSAR0 = MCF_FBCS_CSAR_BA(CFG_FLASH_ADDRESS); - - MCF_FBCS_CSCR0 = (MCF_FBCS_CSCR_PS_32 - | MCF_FBCS_CSCR_AA - | MCF_FBCS_CSCR_ASET(1) - | MCF_FBCS_CSCR_WS(CFG_FLASH_WAIT_STATES)); - - MCF_FBCS_CSMR0 = (MCF_FBCS_CSMR_BAM_32M - | MCF_FBCS_CSMR_V); - - /* - * Check to see if the SDRAM has already been initialized - * by a run control tool - */ - if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)) - { - /* - * Basic configuration and initialization - */ - // 0x000002AA - MCF_SDRAMC_SDRAMDS = (0 - | MCF_SDRAMC_SDRAMDS_SB_E(MCF_SDRAMC_SDRAMDS_DRIVE_8MA) - | MCF_SDRAMC_SDRAMDS_SB_C(MCF_SDRAMC_SDRAMDS_DRIVE_8MA) - | MCF_SDRAMC_SDRAMDS_SB_A(MCF_SDRAMC_SDRAMDS_DRIVE_8MA) - | MCF_SDRAMC_SDRAMDS_SB_S(MCF_SDRAMC_SDRAMDS_DRIVE_8MA) - | MCF_SDRAMC_SDRAMDS_SB_D(MCF_SDRAMC_SDRAMDS_DRIVE_8MA) - ); - - // 0x0000001A - MCF_SDRAMC_CS0CFG = (0 - | MCF_SDRAMC_CSnCFG_CSBA(CFG_SDRAM_ADDRESS) - | MCF_SDRAMC_CSnCFG_CSSZ(MCF_SDRAMC_CSnCFG_CSSZ_128MBYTE) - ); - - MCF_SDRAMC_CS1CFG = 0; - MCF_SDRAMC_CS2CFG = 0; - MCF_SDRAMC_CS3CFG = 0; - - // 0x73611730 - MCF_SDRAMC_SDCFG1 = (0 - | MCF_SDRAMC_SDCFG1_SRD2RW((unsigned int)((CFG_SDRAM_CASL + CFG_SDRAM_BL / 2 + 1) + 0.5)) - | MCF_SDRAMC_SDCFG1_SWT2RD((unsigned int) (CFG_SDRAM_TWR + 1)) - | MCF_SDRAMC_SDCFG1_RDLAT((unsigned int)((CFG_SDRAM_CASL * 2) + 2)) - | MCF_SDRAMC_SDCFG1_ACT2RW((unsigned int)(((CFG_SDRAM_TRCD / CFG_SYSTEM_CORE_PERIOD) - 1) + 0.5)) - | MCF_SDRAMC_SDCFG1_PRE2ACT((unsigned int)(((CFG_SDRAM_TRP / CFG_SYSTEM_CORE_PERIOD) - 1) + 0.5)) - | MCF_SDRAMC_SDCFG1_REF2ACT((unsigned int)(((CFG_SDRAM_TRFC / CFG_SYSTEM_CORE_PERIOD) - 1) + 0.5)) - | MCF_SDRAMC_SDCFG1_WTLAT(3) - ); - - // 0x46770000 - MCF_SDRAMC_SDCFG2 = (0 - | MCF_SDRAMC_SDCFG2_BRD2PRE(CFG_SDRAM_BL / 2) - | MCF_SDRAMC_SDCFG2_BWT2RW(CFG_SDRAM_BL / 2 + CFG_SDRAM_TWR) - | MCF_SDRAMC_SDCFG2_BRD2WT(7) - | MCF_SDRAMC_SDCFG2_BL(CFG_SDRAM_BL - 1) - ); - - /* - * Precharge and enable write to SDMR - */ - // 0xE10B0002 - MCF_SDRAMC_SDCR = (0 - | MCF_SDRAMC_SDCR_MODE_EN - | MCF_SDRAMC_SDCR_CKE - | MCF_SDRAMC_SDCR_DDR - | MCF_SDRAMC_SDCR_MUX(1) // 13 x 10 x 2 ==> MUX=1 - | MCF_SDRAMC_SDCR_RCNT((int)(((CFG_SDRAM_TREFI / (CFG_SYSTEM_CORE_PERIOD * 64)) - 1) + 0.5)) - | MCF_SDRAMC_SDCR_IPALL - ); - - /* - * Write extended mode register - */ - // 0x40010000 - MCF_SDRAMC_SDMR = (0 - | MCF_SDRAMC_SDMR_BNKAD_LEMR - | MCF_SDRAMC_SDMR_AD(0x0) - | MCF_SDRAMC_SDMR_CMD - ); - - /* - * Write mode register and reset DLL - */ - // 0x048d0000 - MCF_SDRAMC_SDMR = (0 - | MCF_SDRAMC_SDMR_BNKAD_LMR - | MCF_SDRAMC_SDMR_AD(CFG_SDRAM_RESET_DLL | CFG_SDRAM_MOD) - | MCF_SDRAMC_SDMR_CMD - ); - - /* - * Execute a PALL command - */ - // 0xE10B0002 - MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL; - - /* - * Perform two REF cycles - */ - // 0xE10B0004 - MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF; - MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF; - - /* - * Write mode register and clear reset DLL - */ - // 0x008D0000 - MCF_SDRAMC_SDMR = (0 - | MCF_SDRAMC_SDMR_BNKAD_LMR - | MCF_SDRAMC_SDMR_AD(CFG_SDRAM_MOD) - | MCF_SDRAMC_SDMR_CMD - ); - - /* - * Enable auto refresh and lock SDMR - */ - // 0x610B0000 - MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN; - - // 0x710B0F00 - MCF_SDRAMC_SDCR |= (0 - | MCF_SDRAMC_SDCR_REF - | MCF_SDRAMC_SDCR_DQS_OE(0xF) - ); - } -} - -/** @file - * - * Target specific early chipselect and SDRAM init. - */
\ No newline at end of file diff --git a/arch/m68k/boards/phycore_mcf54xx/pci-stubs.c b/arch/m68k/boards/phycore_mcf54xx/pci-stubs.c deleted file mode 100644 index b7ab7c7d72..0000000000 --- a/arch/m68k/boards/phycore_mcf54xx/pci-stubs.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * (C) 2007,2008 Carsten Schlote <schlote@vahanus.net> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * @brief This file contains callbacks for the PCI subsystem - * - */ -#include <common.h> -#include <config.h> - - -/** Returns mapping from PCI slot to CPU irq for the target board - * @return Coldfire IRQ vector number, or -1 for no irq - */ -int mcfv4e_pci_gethostirq(uint8_t slot, uint8_t irqpin) -{ - int rc = -1; - switch (slot) - { - case 16 : break; - case 17 ... 21 : rc = 64 + 7; break; // Eport IRQ7 - } - return rc; -} diff --git a/arch/m68k/boards/phycore_mcf54xx/phyCore_MCF54xx.c b/arch/m68k/boards/phycore_mcf54xx/phyCore_MCF54xx.c deleted file mode 100644 index 3744950699..0000000000 --- a/arch/m68k/boards/phycore_mcf54xx/phyCore_MCF54xx.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * (C) 2007 konzeptpark, Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * @brief This file contains ... - * - */ -#include <common.h> -#include <init.h> -#include <driver.h> -#include <fec.h> -#include <environment.h> -#include <mach/mcf54xx-regs.h> -#include <mach/clocks.h> -#include <asm/io.h> -#include <partition.h> - -/* - * Return board clock in MHz FIXME move to clocks file - */ -ulong mcfv4e_get_bus_clk(void) -{ - return CFG_SYSTEM_CORE_CLOCK; -} - -/* - * Up to 64MiB NOR type flash, connected to - * CS line 0, data width is 32 bit - */ -static struct device_d cfi_dev = -{ - .id = -1, - .name = "cfi_flash", - .map_base = CFG_FLASH_ADDRESS, - .size = CFG_FLASH_SIZE, -}; - -/* - * Build in FastEthernetControllers (FECs) - */ -static struct fec_platform_data fec_info = -{ - .xcv_type = MII100, -}; - -static struct device_d network_dev0 = -{ - .id = -1, - .name = "fec_mcf54xx", - .map_base = MCF_FEC_ADDR(0), - .size = MCF_FEC_SIZE(0), /* area size */ - .platform_data = &fec_info, -}; -static struct device_d network_dev1 = -{ - .id = -1, - .name = "fec_mcf54xx", - .map_base = MCF_FEC_ADDR(1), - .size = MCF_FEC_SIZE(1), /* area size */ - .platform_data = &fec_info, -}; - -/* - * 128MiB of SDRAM, data width is 32 bit - */ -static struct memory_platform_data ram_pdata = { - .name = "ram0", - .flags = DEVFS_RDWR, -}; - -static struct device_d sdram_dev = -{ - .id = -1, - .name = "mem", - .map_base = CFG_SDRAM_ADDRESS, - .size = CFG_SDRAM_SIZE, - .platform_data = &ram_pdata, -}; - -static int mcfv4e_devices_init(void) -{ - printf("FIXME - setup board devices...\n"); - - register_device(&cfi_dev); - - /* - * Create partitions that should be - * not touched by any regular user - */ - devfs_add_partition("nor0", 0x00000, 0x80000, PARTITION_FIXED, "self0"); /* ourself */ - devfs_add_partition("nor0", 0x80000, 0x40000, PARTITION_FIXED, "env0"); /* environment */ - protect_file("/dev/env0", 1); - - register_device(&network_dev0); - //register_device(&network_dev1); - - register_device(&sdram_dev); - - return 0; -} - -device_initcall(mcfv4e_devices_init); - -static struct device_d mcfv4e_serial_device = -{ - .id = -1, - .name = "mcfv4e_serial", - .map_base = 1 + CFG_EARLY_UART_PORT, - .size = 16 * 1024, -}; - -static int mcfv4e_console_init(void) -{ - /* init gpios for serial port */ - - /* Already set in lowlevel_init.c */ - - register_device(&mcfv4e_serial_device); - return 0; -} - -console_initcall(mcfv4e_console_init); diff --git a/arch/m68k/boards/phycore_mcf54xx/phyCore_MCF54xx.dox b/arch/m68k/boards/phycore_mcf54xx/phyCore_MCF54xx.dox deleted file mode 100644 index 36dd0ad195..0000000000 --- a/arch/m68k/boards/phycore_mcf54xx/phyCore_MCF54xx.dox +++ /dev/null @@ -1,14 +0,0 @@ - -/** @page phycore_mcf54xx Phytec's phyCORE-MCF54x5 - -This target is based on a PhyTec PhyCore MCF54x5 CPU module. The card is shipped with: - -- up to 64MiB NOR type Flash Memory -- 128MiB synchronous dynamic RAM -- PCI USB 2.0 Host -- PCCard Controller -- MiniPCI Parallel -- MiniPCIe (USB lane only) -- ... - -*/ diff --git a/arch/m68k/configs/phycore_mcf54xx_defconfig b/arch/m68k/configs/phycore_mcf54xx_defconfig deleted file mode 100644 index f0d9fc2845..0000000000 --- a/arch/m68k/configs/phycore_mcf54xx_defconfig +++ /dev/null @@ -1,36 +0,0 @@ -CONFIG_MACH_PCM982_5485=y -CONFIG_INITRD_TAG=y -CONFIG_BROKEN=y -CONFIG_EXPERIMENTAL=y -CONFIG_LONGHELP=y -CONFIG_CMDLINE_EDITING=y -CONFIG_AUTO_COMPLETE=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/m68k/boards/phycore_mcf54xx/env" -CONFIG_DEBUG_INFO=y -CONFIG_ENABLE_DEVICE_NOISE=y -CONFIG_CMD_EDIT=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_LOADENV=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_CRC=y -CONFIG_CMD_MTEST=y -CONFIG_CMD_MTEST_ALTERNATIVE=y -CONFIG_CMD_FLASH=y -CONFIG_CMD_BOOTM_ZLIB=y -CONFIG_CMD_BOOTM_BZLIB=y -CONFIG_CMD_BOOTM_SHOW_TYPE=y -CONFIG_CMD_RESET=y -CONFIG_CMD_GO=y -CONFIG_CMD_TIMEOUT=y -CONFIG_CMD_PARTITION=y -CONFIG_NET=y -CONFIG_NET_DHCP=y -CONFIG_NET_PING=y -CONFIG_NET_TFTP=y -CONFIG_DRIVER_CFI=y -CONFIG_CFI_BUFFER_WRITE=y -CONFIG_FS_CRAMFS=y diff --git a/arch/m68k/cpu/Makefile b/arch/m68k/cpu/Makefile deleted file mode 100644 index 2e434af4e1..0000000000 --- a/arch/m68k/cpu/Makefile +++ /dev/null @@ -1,41 +0,0 @@ -# -# (C) Copyright 2007 Carsten Schlote <schlote@vahanus.net> -# See file CREDITS for list of people who contributed to this project. -# -# This file is part of barebox. -# -# barebox is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# barebox is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with barebox. If not, see <http://www.gnu.org/licenses/>. -# - -obj-y += cpu.o -obj-y += interrupts.o - -# -# Support code for early IO over BDM wigglers -# - -# obj-y += early_init_support.o - -# -# Support for relocated early initdata -# -obj-$(CONFIG_HAS_EARLY_INIT) += early_init_support.o - -# -# Startup codes - try to merge them into single file! -# -obj-$(CONFIG_ARCH_MCF54xx) += start-mcfv4e.o -obj-$(CONFIG_ARCH_MCF5445x) += start-mcfv4m.o - -start-mcfv4e.o : start-mcfv4e.s
\ No newline at end of file diff --git a/arch/m68k/cpu/cpu.c b/arch/m68k/cpu/cpu.c deleted file mode 100644 index 9268785a4c..0000000000 --- a/arch/m68k/cpu/cpu.c +++ /dev/null @@ -1,185 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * A few helper functions for M6kK/Coldfire - */ -#include <common.h> -#include <command.h> -#include <init.h> -#include <proc/processor.h> // FIXME -stup place -#include <mach/mcf54xx-regs.h> - -static uint32_t CACR_shadow = MCF5XXX_CACR_BEC; - -/* - * Reset init value := 0x010C0100 - * MCF5XXX_CACR_DCINVA - * MCF5XXX_CACR_BEC - * MCF5XXX_CACR_BCINVA - * MCF5XXX_CACR_ICINVA - */ - -/** - * Enable processor's instruction cache - */ -void icache_enable (void) -{ - CACR_shadow |= MCF5XXX_CACR_IEC; - mcf5xxx_wr_cacr( CACR_shadow ); -} - -/** - * Disable processor's instruction cache - */ -void icache_disable (void) -{ - CACR_shadow &= ~MCF5XXX_CACR_IEC; - mcf5xxx_wr_cacr( CACR_shadow ); -} - -/** - * Detect processor's current instruction cache status - * @return 0=disabled, 1=enabled - */ -int icache_status (void) -{ - return (CACR_shadow & MCF5XXX_CACR_IEC)?1:0; -} - -/** - * Enable processor's data cache - */ -void dcache_enable (void) -{ - CACR_shadow |= MCF5XXX_CACR_DEC; - mcf5xxx_wr_cacr( CACR_shadow ); -} - -/** - * Disable processor's data cache - */ -void dcache_disable (void) -{ - CACR_shadow &= ~MCF5XXX_CACR_DEC; - mcf5xxx_wr_cacr( CACR_shadow ); -} - -/** - * Detect processor's current instruction cache status - * @return 0=disabled, 1=enabled - */ -int dcache_status (void) -{ - return (CACR_shadow & MCF5XXX_CACR_DEC)?1:0; -} - -/** - * Flush CPU caches to memory - */ -void cpu_cache_flush(void) -{ - uint32_t way, set; - void *addr; - - for ( way=0; way < 4; way++ ) { - addr = (void*)way; - for ( set=0; set < 512; set++ ) { - mcf5xxx_cpushl_bc ( addr ); - addr += 0x10; - } - } -} - -/** - * Flush CPU caches to memory and disable them. - */ -void cpu_cache_disable(void) -{ - uint32_t lastipl; - - lastipl = asm_set_ipl( 7 ); - - cpu_cache_flush(); - mcf5xxx_wr_acr0( 0 ); - mcf5xxx_wr_acr1( 0 ); - mcf5xxx_wr_acr2( 0 ); - mcf5xxx_wr_acr3( 0 ); - - CACR_shadow &= ~MCF5XXX_CACR_IEC; - CACR_shadow &= ~MCF5XXX_CACR_DEC; - mcf5xxx_wr_cacr( CACR_shadow | (MCF5XXX_CACR_DCINVA|MCF5XXX_CACR_ICINVA)); - - lastipl = asm_set_ipl( lastipl ); -} - -/** - * Prepare a "clean" CPU for Linux to run - * @return 0 (always) - * - * This function is called by the generic barebox part just before we call - * Linux. It prepares the processor for Linux. - */ -int cleanup_before_linux (void) -{ - /* - * we never enable dcache so we do not need to disable - * it. Linux can be called with icache enabled, so just - * do nothing here - */ - - /* flush I/D-cache */ - cpu_cache_disable(); - - /* reenable icache */ - icache_enable(); - return (0); -} -/** @page m68k_boot_preparation Linux Preparation on M68k/Coldfire - * - * For M68K we never enable data cache so we do not need to disable it again. - * - * Linux can be called with instruction cache enabled. As this is the - * default setting we are running in barebox, there's no special preparation - * required. - */ - - -/** Early init of Coldfire V4E CPU - */ -static int cpu_init (void) -{ - /* Enable ICache - branch cache is already on */ - icache_enable(); - - /* - * setup up stacks if necessary - * setup other CPU specifics here to prepare - * handling of exceptions and interrupts - */ -#ifdef CONFIG_USE_IRQ - printf("Prepare CPU interrupts for handlers\n"); - mcf_interrupts_initialize(); -#endif - - return 0; -} - -core_initcall(cpu_init); diff --git a/arch/m68k/cpu/cw_console_io.c b/arch/m68k/cpu/cw_console_io.c deleted file mode 100644 index 417a1b48b6..0000000000 --- a/arch/m68k/cpu/cw_console_io.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Debug output stubs over BDM for Codewarrior - */ -#include <common.h> -#include <command.h> -#include <console.h> -#include <reloc.h> -#include <init.h> - -#ifdef CONFIG_HAS_EARLY_INIT - - -#if 0 // FIXME - make a CW debug port serial driver for barebox - -/* - * The result of an I/O command can be any one of the following. - */ -typedef enum DSIOResult -{ - kDSIONoError = 0x00, - kDSIOError = 0x01, - kDSIOEOF = 0x02 -} DSIOResult; - -/* - * MessageCommandID - */ -typedef enum MessageCommandID -{ - /* - * target->host support commands - */ - - kDSWriteFile = 0xD0, /* L2 L3 */ - kDSReadFile = 0xD1 /* L2 L3 */ - -} MessageCommandID; - - -enum DSIOResult TransferData( - MessageCommandID msg, - unsigned char *buffer, int size, - int * txsize -) -{ - enum DSIOResult iores = kDSIOError; - unsigned long sized2=0; - - /* -- Call codewarrior stub -- */ - __asm__ __volatile__ ( -" move.l %[cmd],%%d0 \n" -" move.l #0,%%d1 \n" -" move.l %[size],%%d2 \n" -" move.l %[buffer],%%d3 \n" -" trap #14 \n" -" move.l %%d1,%[txsize] \n" -" move.l %%d0,%[res] \n" - : [res] "=r" (iores), [txsize] "=g" (sized2) - : [cmd] "g" (msg), [size] "g" (size), [buffer] "g" (buffer) - : "d2","d3" ); - - if (txsize!=NULL) *txsize=sized2; - return iores; -} - -void *get_early_console_base(const char *name) -{ - return (void*)0xdeadbeef; -} - -static unsigned char early_iobuffer[80]; -static int early_iobuffer_cnt; - -void early_console_putc(void *base, char c) -{ - early_iobuffer[early_iobuffer_cnt++] = c; - if ( ( early_iobuffer_cnt >= sizeof(early_iobuffer)) || - (c == '\n') ) - { - TransferData(kDSWriteFile,early_iobuffer,early_iobuffer_cnt, NULL); - early_iobuffer_cnt = 0; - } -} - -void early_console_init(void *base, int baudrate) -{ - early_iobuffer_cnt = 0; -} - -//void early_console_start(const char *name, int baudrate) -//{ -//} - -#endif - -#endif diff --git a/arch/m68k/cpu/early_init_support.c b/arch/m68k/cpu/early_init_support.c deleted file mode 100644 index be4a9e4cb6..0000000000 --- a/arch/m68k/cpu/early_init_support.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Early InitData support routines - */ -#include <common.h> -#include <command.h> -#include <console.h> -#include <reloc.h> -#include <init.h> - -#ifdef CONFIG_HAS_EARLY_INIT - -/** Returns relocation offset to early init data - */ -unsigned long reloc_offset(void) -{ - //extern char __early_init_data_begin[]; - //FIXME: return (unsigned long)init_data_ptr - (unsigned long)__early_init_data_begin; - return 0; -} - -#endif diff --git a/arch/m68k/cpu/interrupts.c b/arch/m68k/cpu/interrupts.c deleted file mode 100644 index 4e1ff12733..0000000000 --- a/arch/m68k/cpu/interrupts.c +++ /dev/null @@ -1,246 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Interrupt routines and supporting code for Coldfire V4E - */ -#include <common.h> -#include <asm/ptrace.h> -#include <mach/mcf54xx-regs.h> - -#ifdef CONFIG_USE_IRQ -void enable_interrupts(void) -{ - asm_set_ipl(0); -} - -int disable_interrupts(void) -{ - return asm_set_ipl(7) ? 1 : 0; -} -#endif - -/** - */ -static void mcf_bad_mode (void) -{ - panic ("Resetting CPU ...\n"); - mdelay(3000); - reset_cpu (0); -} - -/** - */ -static void mcf_show_regs (struct pt_regs *regs) -{ - unsigned long flags; - flags = condition_codes (regs); - - printf ("pc : [<%08lx>]\n" - "sp : %08lx fp : %08lx\n", - instruction_pointer (regs), - regs->M68K_sp, regs->M68K_a6); - - printf ("d0-d3 : %08lx %08lx %08lx %08lx\n", - regs->M68K_d0, regs->M68K_d1, regs->M68K_d2, regs->M68K_d3); - printf ("d3-d7 : %08lx %08lx %08lx %08lx\n", - regs->M68K_d3, regs->M68K_d4, regs->M68K_d5, regs->M68K_d6); - - printf ("a0-d3 : %08lx %08lx %08lx %08lx\n", - regs->M68K_a0, regs->M68K_a1, regs->M68K_a2, regs->M68K_a3); - printf ("a3-d7 : %08lx %08lx %08lx %08lx\n", - regs->M68K_a3, regs->M68K_a4, regs->M68K_a5, regs->M68K_a6); - - printf ("fp0 : %08lx%08lx fp1 : %08lx%08lx\n", - regs->M68K_fp0+1, regs->M68K_fp0, regs->M68K_fp1+1, regs->M68K_fp1); - printf ("fp2 : %08lx%08lx fp3 : %08lx%08lx\n", - regs->M68K_fp2+1, regs->M68K_fp2, regs->M68K_fp3+1, regs->M68K_fp3); - printf ("fp4 : %08lx%08lx fp5 : %08lx%08lx\n", - regs->M68K_fp4+1, regs->M68K_fp4, regs->M68K_fp5+1, regs->M68K_fp5); - printf ("fp6 : %08lx%08lx fp7 : %08lx%08lx\n", - regs->M68K_fp6+1, regs->M68K_fp6, regs->M68K_fp7+1, regs->M68K_fp7); - - printf ("Flags: %c%c%c%c", - flags & CC_X_BIT ? 'X' : 'x', - flags & CC_N_BIT ? 'N' : 'n', - flags & CC_Z_BIT ? 'Z' : 'z', - flags & CC_V_BIT ? 'V' : 'v', - flags & CC_C_BIT ? 'C' : 'c' ); - - printf (" IRQs %s (%0x) Mode %s\n", - interrupts_enabled (regs) ? "on" : "off", interrupts_enabled (regs), - user_mode (regs) ? "user" : "supervisor"); -} - -void mcf_execute_exception_handler (struct pt_regs *pt_regs) -{ - printf ("unhandled exception\n"); - mcf_show_regs (pt_regs); - mcf_bad_mode (); -} - -#ifndef CONFIG_USE_IRQ - -void mcf_execute_irq_handler (struct pt_regs *pt_regs, int vector) -{ - printf ("interrupt request\n"); - mcf_show_regs (pt_regs); - mcf_bad_mode (); -} - -#else - -#ifndef CONFIG_MAX_ISR_HANDLERS -#define CONFIG_MAX_ISR_HANDLERS (20) -#endif - -typedef struct -{ - int vector; - int (*handler)(void *, void *); - void *hdev; - void *harg; -} -mcfv4e_irq_handler_s; - -mcfv4e_irq_handler_s irq_handler_table[CONFIG_MAX_ISR_HANDLERS]; - -/** Initialize an empty interrupt handler list - */ -void mcf_interrupts_initialize (void) -{ - int index; - for (index = 0; index < CONFIG_MAX_ISR_HANDLERS; index++) - { - irq_handler_table[index].vector = 0; - irq_handler_table[index].handler = 0; - irq_handler_table[index].hdev = 0; - irq_handler_table[index].harg = 0; - } -} - -/** Add an interrupt handler to the handler list - * - * @param vector : M68k exception/interrupt vector number - * @param handler : Pointer to handler function - * @param hdev : Handler specific data - * @param harg : Handler specific arg - */ -int mcf_interrupts_register_handler( - int vector, - int (*handler)(void *, void *), void *hdev, void *harg) -{ - /* - * This function places an interrupt handler in the ISR table, - * thereby registering it so that the low-level handler may call it. - * - * The two parameters are intended for the first arg to be a - * pointer to the device itself, and the second a pointer to a data - * structure used by the device driver for that particular device. - */ - int index; - - if ((vector == 0) || (handler == NULL)) - { - return 0; - } - - for (index = 0; index < CONFIG_MAX_ISR_HANDLERS; index++) - { - if (irq_handler_table[index].vector == vector) - { - /* only one entry of each type per vector */ - return 0; - } - - if (irq_handler_table[index].vector == 0) - { - irq_handler_table[index].vector = vector; - irq_handler_table[index].handler = handler; - irq_handler_table[index].hdev = hdev; - irq_handler_table[index].harg = harg; - return 1; - } - } - return 0; /* no available slots */ -} - -/** Remove an interrupt handler from the handler list - * - * @param type : FIXME - * @param handler : Pointer of handler function to remove. - */ -void mcf_interrupts_remove_handler (int type ,int (*handler)(void *, void *)) -{ - /* - * This routine removes from the ISR table all - * entries that matches 'handler'. - */ - int index; - - for (index = 0; index < CONFIG_MAX_ISR_HANDLERS; index++) - { - if (irq_handler_table[index].handler == handler) - { - irq_handler_table[index].vector = 0; - irq_handler_table[index].handler = 0; - irq_handler_table[index].hdev = 0; - irq_handler_table[index].harg = 0; - } - } -} - -/** Traverse list of registered interrupts and call matching handlers. - * - * @param pt_regs : Pointer to saved register context - * @param vector : M68k exception/interrupt vector number - */ -int mcf_execute_irq_handler (struct pt_regs *pt_regs, int vector) -{ - /* - * This routine searches the ISR table for an entry that matches - * 'vector'. If one is found, then 'handler' is executed. - */ - int index, retval = 0; - - /* - * Try to locate a user-registered Interrupt Service Routine handler. - */ - for (index = 0; index < CONFIG_MAX_ISR_HANDLERS; index++) - { - if (irq_handler_table[index].handler == NULL) - { - printf("\nFault: No handler for IRQ vector %ld found.\n", vector); - break; - } - if (irq_handler_table[index].vector == vector) - { - if (irq_handler_table[index].handler(irq_handler_table[index].hdev,irq_handler_table[index].harg)) - { - retval = 1; - break; - } - } - } - - return retval; -} - -#endif diff --git a/arch/m68k/cpu/start-mcfv4e.S b/arch/m68k/cpu/start-mcfv4e.S deleted file mode 100644 index df9ee4d4bb..0000000000 --- a/arch/m68k/cpu/start-mcfv4e.S +++ /dev/null @@ -1,677 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Resetcode and exception/interrupt shells for Coldfire V4E - * - * This file contains the common startup code for use on at least Coldfire - * V4E cores: - * - MCF547x - * - MCF548x - */ -#include <config.h> - - .section ".vectors","a" - -/* - * Define some addresses from your board configuration file - */ - .equ __MBAR,CFG_MBAR_ADDRESS - .globl __MBAR - - .equ __CORE_SRAM0,CFG_CORE0_SRAM_ADDRESS - .equ __CORE_SRAM0_SIZE,CFG_CORE0_SRAM_SIZE - - .equ __CORE_SRAM1,CFG_CORE1_SRAM_ADDRESS - .equ __CORE_SRAM1_SIZE,CFG_CORE1_SRAM_SIZE - - /* - * Preload stack pointer with end of Core SRAM - useable _after_ you have - * setup the MBR register in reset code! - * - * The upper 4 LW of the Core SRAM are left spare - it can be used as - * fixed address temporay storage in the code below (ok, well also to - * fix up stack traces in the debugger) - * - * So we have a stack usable for C code, before we even started SDRAM! - */ - .equ ___SP_INIT,__CORE_SRAM1+__CORE_SRAM1_SIZE-16 - -/* - * Vector table for M68k and barebox Link Address - * - * On M68k/Coldfire cores all exceptions and interrupts are routed through - * a vector array. This vector is by default at address 0x0000_0000, but - * can be moved to any other 1MB aligned address. - * - * We take advantage of this to move barebox out of low memory. Some BDM - * debuggers won't like a moved vector base and might need tweaking to - * work. - * - * Note: Respect alignment restrictions for TEXT_BASE, which must be - * 1MB aligned. - */ - - .globl _barebox_start -_barebox_start: - -VECTOR_TABLE: -_VECTOR_TABLE: -INITSP: .long ___SP_INIT /* Initial SP */ -INITPC: .long 0x410 /* Initial PC */ -vector02: .long _asm_exception_handler /* Access Error */ -vector03: .long _asm_exception_handler /* Address Error */ -vector04: .long _asm_exception_handler /* Illegal Instruction */ -vector05: .long _asm_exception_handler /* Divide by Zero */ -vector06: .long _asm_exception_handler /* Reserved */ -vector07: .long _asm_exception_handler /* Reserved */ -vector08: .long _asm_exception_handler /* Privilege Violation */ -vector09: .long _asm_exception_handler /* Trace */ -vector0A: .long _asm_exception_handler /* Unimplemented A-Line */ -vector0B: .long _asm_exception_handler /* Unimplemented F-Line */ -vector0C: .long _asm_exception_handler /* Non-PC Brkpt Debug Int */ -vector0D: .long _asm_exception_handler /* PC Brkpt Debug Int */ -vector0E: .long _asm_exception_handler /* Format Error */ -vector0F: .long _asm_exception_handler /* Unitialized Int */ -vector10: .long _asm_exception_handler /* Reserved */ -vector11: .long _asm_exception_handler /* Reserved */ -vector12: .long _asm_exception_handler /* Reserved */ -vector13: .long _asm_exception_handler /* Reserved */ -vector14: .long _asm_exception_handler /* Reserved */ -vector15: .long _asm_exception_handler /* Reserved */ -vector16: .long _asm_exception_handler /* Reserved */ -vector17: .long _asm_exception_handler /* Reserved */ -vector18: .long _asm_exception_handler /* Spurious Interrupt */ -vector19: .long _asm_isr_handler /* Autovector Level 1 */ -vector1A: .long _asm_isr_handler /* Autovector Level 2 */ -vector1B: .long _asm_isr_handler /* Autovector Level 3 */ -vector1C: .long _asm_isr_handler /* Autovector Level 4 */ -vector1D: .long _asm_isr_handler /* Autovector Level 5 */ -vector1E: .long _asm_isr_handler /* Autovector Level 6 */ -vector1F: .long _asm_isr_handler /* Autovector Level 7 */ -vector20: .long _asm_exception_handler /* TRAP #0 */ -vector21: .long _asm_exception_handler /* TRAP #1 */ -vector22: .long _asm_exception_handler /* TRAP #2 */ -vector23: .long _asm_exception_handler /* TRAP #3 */ -vector24: .long _asm_exception_handler /* TRAP #4 */ -vector25: .long _asm_exception_handler /* TRAP #5 */ -vector26: .long _asm_exception_handler /* TRAP #6 */ -vector27: .long _asm_exception_handler /* TRAP #7 */ -vector28: .long _asm_exception_handler /* TRAP #8 */ -vector29: .long _asm_exception_handler /* TRAP #9 */ -vector2A: .long _asm_exception_handler /* TRAP #10 */ -vector2B: .long _asm_exception_handler /* TRAP #11 */ -vector2C: .long _asm_exception_handler /* TRAP #12 */ -vector2D: .long _asm_exception_handler /* TRAP #13 */ -vector2E: .long _asm_exception_handler /* TRAP #14 */ -vector2F: .long _dbug_sc_handler /* TRAP #15 - System Call */ -vector30: .long _asm_exception_handler /* Reserved */ -vector31: .long _asm_exception_handler /* Reserved */ -vector32: .long _asm_exception_handler /* Reserved */ -vector33: .long _asm_exception_handler /* Reserved */ -vector34: .long _asm_exception_handler /* Reserved */ -vector35: .long _asm_exception_handler /* Reserved */ -vector36: .long _asm_exception_handler /* Reserved */ -vector37: .long _asm_exception_handler /* Reserved */ -vector38: .long _asm_exception_handler /* Reserved */ -vector39: .long _asm_exception_handler /* Reserved */ -vector3A: .long _asm_exception_handler /* Reserved */ -vector3B: .long _asm_exception_handler /* Reserved */ -vector3C: .long _asm_exception_handler /* Reserved */ -vector3D: .long _asm_exception_handler /* Unsupported Instruction */ -vector3E: .long _asm_exception_handler /* Reserved */ -vector3F: .long _asm_exception_handler /* Reserved */ -vector40: .long _asm_isr_handler /* User Defined Interrupts */ -vector41: .long _asm_isr_handler -vector42: .long _asm_isr_handler -vector43: .long _asm_isr_handler -vector44: .long _asm_isr_handler -vector45: .long _asm_isr_handler -vector46: .long _asm_isr_handler -vector47: .long _asm_isr_handler -vector48: .long _asm_isr_handler -vector49: .long _asm_isr_handler -vector4A: .long _asm_isr_handler -vector4B: .long _asm_isr_handler -vector4C: .long _asm_isr_handler -vector4D: .long _asm_isr_handler -vector4E: .long _asm_isr_handler -vector4F: .long _asm_isr_handler -vector50: .long _asm_isr_handler -vector51: .long _asm_isr_handler -vector52: .long _asm_isr_handler -vector53: .long _asm_isr_handler -vector54: .long _asm_isr_handler -vector55: .long _asm_isr_handler -vector56: .long _asm_isr_handler -vector57: .long _asm_isr_handler -vector58: .long _asm_isr_handler -vector59: .long _asm_isr_handler -vector5A: .long _asm_isr_handler -vector5B: .long _asm_isr_handler -vector5C: .long _asm_isr_handler -vector5D: .long _asm_isr_handler -vector5E: .long _asm_isr_handler -vector5F: .long _asm_isr_handler -vector60: .long _asm_isr_handler -vector61: .long _asm_isr_handler -vector62: .long _asm_isr_handler -vector63: .long _asm_isr_handler -vector64: .long _asm_isr_handler -vector65: .long _asm_isr_handler -vector66: .long _asm_isr_handler -vector67: .long _asm_isr_handler -vector68: .long _asm_isr_handler -vector69: .long _asm_isr_handler -vector6A: .long _asm_isr_handler -vector6B: .long _asm_isr_handler -vector6C: .long _asm_isr_handler -vector6D: .long _asm_isr_handler -vector6E: .long _asm_isr_handler -vector6F: .long _asm_isr_handler -vector70: .long _asm_isr_handler -vector71: .long _asm_isr_handler -vector72: .long _asm_isr_handler -vector73: .long _asm_isr_handler -vector74: .long _asm_isr_handler -vector75: .long _asm_isr_handler -vector76: .long _asm_isr_handler -vector77: .long _asm_isr_handler -vector78: .long _asm_isr_handler -vector79: .long _asm_isr_handler -vector7A: .long _asm_isr_handler -vector7B: .long _asm_isr_handler -vector7C: .long _asm_isr_handler -vector7D: .long _asm_isr_handler -vector7E: .long _asm_isr_handler -vector7F: .long _asm_isr_handler -vector80: .long _asm_isr_handler -vector81: .long _asm_isr_handler -vector82: .long _asm_isr_handler -vector83: .long _asm_isr_handler -vector84: .long _asm_isr_handler -vector85: .long _asm_isr_handler -vector86: .long _asm_isr_handler -vector87: .long _asm_isr_handler -vector88: .long _asm_isr_handler -vector89: .long _asm_isr_handler -vector8A: .long _asm_isr_handler -vector8B: .long _asm_isr_handler -vector8C: .long _asm_isr_handler -vector8D: .long _asm_isr_handler -vector8E: .long _asm_isr_handler -vector8F: .long _asm_isr_handler -vector90: .long _asm_isr_handler -vector91: .long _asm_isr_handler -vector92: .long _asm_isr_handler -vector93: .long _asm_isr_handler -vector94: .long _asm_isr_handler -vector95: .long _asm_isr_handler -vector96: .long _asm_isr_handler -vector97: .long _asm_isr_handler -vector98: .long _asm_isr_handler -vector99: .long _asm_isr_handler -vector9A: .long _asm_isr_handler -vector9B: .long _asm_isr_handler -vector9C: .long _asm_isr_handler -vector9D: .long _asm_isr_handler -vector9E: .long _asm_isr_handler -vector9F: .long _asm_isr_handler -vectorA0: .long _asm_isr_handler -vectorA1: .long _asm_isr_handler -vectorA2: .long _asm_isr_handler -vectorA3: .long _asm_isr_handler -vectorA4: .long _asm_isr_handler -vectorA5: .long _asm_isr_handler -vectorA6: .long _asm_isr_handler -vectorA7: .long _asm_isr_handler -vectorA8: .long _asm_isr_handler -vectorA9: .long _asm_isr_handler -vectorAA: .long _asm_isr_handler -vectorAB: .long _asm_isr_handler -vectorAC: .long _asm_isr_handler -vectorAD: .long _asm_isr_handler -vectorAE: .long _asm_isr_handler -vectorAF: .long _asm_isr_handler -vectorB0: .long _asm_isr_handler -vectorB1: .long _asm_isr_handler -vectorB2: .long _asm_isr_handler -vectorB3: .long _asm_isr_handler -vectorB4: .long _asm_isr_handler -vectorB5: .long _asm_isr_handler -vectorB6: .long _asm_isr_handler -vectorB7: .long _asm_isr_handler -vectorB8: .long _asm_isr_handler -vectorB9: .long _asm_isr_handler -vectorBA: .long _asm_isr_handler -vectorBB: .long _asm_isr_handler -vectorBC: .long _asm_isr_handler -vectorBD: .long _asm_isr_handler -vectorBE: .long _asm_isr_handler -vectorBF: .long _asm_isr_handler -vectorC0: .long _asm_isr_handler -vectorC1: .long _asm_isr_handler -vectorC2: .long _asm_isr_handler -vectorC3: .long _asm_isr_handler -vectorC4: .long _asm_isr_handler -vectorC5: .long _asm_isr_handler -vectorC6: .long _asm_isr_handler -vectorC7: .long _asm_isr_handler -vectorC8: .long _asm_isr_handler -vectorC9: .long _asm_isr_handler -vectorCA: .long _asm_isr_handler -vectorCB: .long _asm_isr_handler -vectorCC: .long _asm_isr_handler -vectorCD: .long _asm_isr_handler -vectorCE: .long _asm_isr_handler -vectorCF: .long _asm_isr_handler -vectorD0: .long _asm_isr_handler -vectorD1: .long _asm_isr_handler -vectorD2: .long _asm_isr_handler -vectorD3: .long _asm_isr_handler -vectorD4: .long _asm_isr_handler -vectorD5: .long _asm_isr_handler -vectorD6: .long _asm_isr_handler -vectorD7: .long _asm_isr_handler -vectorD8: .long _asm_isr_handler -vectorD9: .long _asm_isr_handler -vectorDA: .long _asm_isr_handler -vectorDB: .long _asm_isr_handler -vectorDC: .long _asm_isr_handler -vectorDD: .long _asm_isr_handler -vectorDE: .long _asm_isr_handler -vectorDF: .long _asm_isr_handler -vectorE0: .long _asm_isr_handler -vectorE1: .long _asm_isr_handler -vectorE2: .long _asm_isr_handler -vectorE3: .long _asm_isr_handler -vectorE4: .long _asm_isr_handler -vectorE5: .long _asm_isr_handler -vectorE6: .long _asm_isr_handler -vectorE7: .long _asm_isr_handler -vectorE8: .long _asm_isr_handler -vectorE9: .long _asm_isr_handler -vectorEA: .long _asm_isr_handler -vectorEB: .long _asm_isr_handler -vectorEC: .long _asm_isr_handler -vectorED: .long _asm_isr_handler -vectorEE: .long _asm_isr_handler -vectorEF: .long _asm_isr_handler -vectorF0: .long _asm_isr_handler -vectorF1: .long _asm_isr_handler -vectorF2: .long _asm_isr_handler -vectorF3: .long _asm_isr_handler -vectorF4: .long _asm_isr_handler -vectorF5: .long _asm_isr_handler -vectorF6: .long _asm_isr_handler -vectorF7: .long _asm_isr_handler -vectorF8: .long _asm_isr_handler -vectorF9: .long _asm_isr_handler -vectorFA: .long _asm_isr_handler -vectorFB: .long _asm_isr_handler -vectorFC: .long _asm_isr_handler -vectorFD: .long _asm_isr_handler -vectorFE: .long _asm_isr_handler -vectorFF: .long _asm_isr_handler - -/* - * Leave some bytes spare here for CW debugger (console IO stuff) - */ - .rept 4 - .long 0xdeadbeef - .endr - -/** @func reset Startup Code (reset vector) - * - * The vector array is mapped to address 0 at reset and SP and PC are - * fetched from adress 0 and 4. - * - * For debugger uploads this image will reside in the middle of RAM, leaving - * as much memory for other stuff in low memory available, e.g. Linux and - * an init ramdisk. - * - * For real system resets, the boot rom is mapped to all addresses in - * system, as long as somebody sets up the CS. Now the trick part until - * relocation to RAM is that we must code at the start of your bootrom - * - all link addresses are wrong, so we need the reloc.h stuff to find the - * right address. - * - * The following things happen here: - * * do important init, like SDRAM, only if we don't start from memory! - * * setup Memory and board specific bits prior to relocation. - * * Setup stack - * * relocate barebox to ram - * - */ - .globl _start -_start: - .global reset -reset: - /* Mask all IRQs */ - move.w #0x2700,%sr - - /* Initialize MBAR - keep D0/D1 registers */ - move.l #__MBAR,%d2 - movec %d2,%MBAR - nop - - /* Initialize RAMBAR0 - locate it on the data bus */ - move.l #__CORE_SRAM0,%d2 - add.l #0x21,%d2 - movec %d2,%RAMBAR0 - nop - - /* Initialize RAMBAR1 - locate it on the data bus */ - move.l #__CORE_SRAM1,%d2 - add.l #0x21,%d2 - movec %d2,%RAMBAR1 - nop - - /* Point Stack Pointer into Core SRAM temporarily */ - move.l #___SP_INIT,%d2 - move.l %d2,%sp - nop - - /* Invalidate the data, instruction, and branch caches */ - /* Turn on the branch cache */ - move.l #0x010C0100,%d2 - movec %d2,%cacr - nop - - /* Prepare stack top */ - clr.l %sp@(0) - move.l %d0,%sp@(4) - move.l %d1,%sp@(8) - clr.l %sp@(12) - - /* - * This call is intended to give all developers a chance to use a - * standard reset vector file, but also do some special things - * required only on their specific CPU. - */ -#ifdef CONFIG_ARCH_HAS_LOWLEVEL_INIT - bsr.l arch_init_lowlevel - nop -#endif - /* - * If the code vector table is not at TEXT_BASE and so this code - * as well, jump to the address mirror at FLASH ROM start address - * - * So load your image to TEXT_BASE for debugging or flash a binary - * image to your bootflash - code below will take proper action. - */ - lea.l %pc@(VECTOR_TABLE),%a0 - move.l #TEXT_BASE,%a1 - cmp.l %a0,%a1 - beq.s saveland - - /* - * Execution is not at TEXT_BASE. We assume entry to this code by - * a hardware reset and change execution to address of _FLASH_ rom. - */ - lea.l %pc@(saveland),%a0 // Effective ! Address of label below - move.l %a0,%d0 - and.l #0x00ffffff,%d0 // Cut away address high byte - move.l #CFG_FLASH_ADDRESS,%d1 // Get flash address - and.l #0xff000000,%d1 // and just take base for CS0 - or.l %d1,%d0 // Compose new address - move.l %d0,%a0 - jmp %a0@ // Jump to flash rom address! - nop - - /* We now either in SDRAM or FLASH START addresses, save to - change chip selects */ -saveland: - nop - - /* - * Before relocating, we have to setup RAM timing - * because memory timing is board-dependend, you will - * find a lowlevel_init.[c|S] in your board directory. - * - * Do not jump/call other barebox code here! - */ -#ifdef CONFIG_MACH_DO_LOWLEVEL_INIT - bsr.l board_init_lowlevel - nop -#endif - - /* - * relocate barebox Code to RAM (including copy of vectors) - */ -relocate: - lea.l %pc@(VECTOR_TABLE),%a0 - move.l #TEXT_BASE,%a1 - move.l #__bss_start,%a3 - cmp.l %a0,%a1 - beq.s skip_relocate - - /* - * Calculate number of long words, and copy them to RAM - */ - move.l %a3,%d2 - sub.l %a1,%d2 - asr.l #2,%d2 -copy_loop: - move.l %a0@+,%a1@+ - subq.l #1,%d2 - bne.s copy_loop - -skip_relocate: - - /* Clear BSS segment in RAM */ -clear_bss: - move.l #__bss_end,%a4 - moveq.l #0,%d2 -clear_loop: - move.l %d2,%a3@+ - cmp.l %a4,%a3 - ble.s clear_loop - - /* - * Relocate Vectors to memory start (address 0) - * - * NOTE: It could be at other places, but debuggers expect - * this table to be at address 0. - */ -#ifdef CONFIG_COPY_LOWMEM_VECTORS -reloc_vectors: - lea.l %pc@(VECTOR_TABLE),%a0 - move.l #0,%a1 - cmp.l %a0,%a1 - beq.s skip_copy_vectors - - move.l #0x100,%d2 -copy_loop_vectors: - move.l %a0@+,%a1@+ - subq.l #1,%d2 - bne.s copy_loop_vectors -skip_copy_vectors: -#endif - -#ifndef CONFIG_USE_LOWMEM_VECTORS - move.l #TEXT_BASE,%d0 - movec %d0,%vbr - nop -#endif - -#ifdef CONFIG_MACH_DO_LOWLEVEL_INIT - /* - * Call other half of initcode in relocated code - * - * You allowed to call other barebox code from here - */ - jsr.l board_init_highlevel - nop -#endif - /* - * Now jump to real link address and barebox entry point - */ - nop - jmp.l start_barebox - nop - nop - -/* - * Interrupt handling - */ - -/* - * IRQ stack frame. - */ -#define S_FRAME_SIZE 148 - -#define S_SP S_A7 -#define S_SR 144 -#define S_PC 140 - -#define S_FPIAR 136 -#define S_FPSR 132 -#define S_FPCR 128 - -#define S_FP7 120 -#define S_FP6 112 -#define S_FP5 104 -#define S_FP4 96 -#define S_FP3 88 -#define S_FP2 80 -#define S_FP1 72 -#define S_FP0 64 - -#define S_A7 60 -#define S_A6 56 -#define S_A5 52 -#define S_A4 48 -#define S_A3 44 -#define S_A2 40 -#define S_A1 36 -#define S_A0 32 - -#define S_D7 28 -#define S_D6 24 -#define S_D5 20 -#define S_D4 16 -#define S_D3 12 -#define S_D2 8 -#define S_D1 4 -#define S_D0 0 - - -/* - * exception handlers - */ -#ifdef CONFIG_USE_IRQ - .global _dbug_sc_handler -_dbug_sc_handler: - .global _asm_exception_handler -_asm_exception_handler: - move.w #0x2700,%sr /* Disable IRQs */ - - move.l %sp,___SP_INIT /* Remember on top of stack */ - move.l #___SP_INIT,%sp /* Set stack to known area */ - - move.l %a0,%sp@- - lea _asm_context,%a0 - - movem.l %d0-%d7/%a0-%a7,%a0@ - - fmovem %fp0-%fp7,%a0@(S_FP0) - fmove.l %fpcr,%a0@(S_FPCR) - fmove.l %fpsr,%a0@(S_FPSR) - fmove.l %fpiar,%a0@(S_FPIAR) - - move.l %sp@+,%a0@(S_A0) - move.l %sp@,%a1 - move.l %a1,%a0@(S_SP) - move.l %a1@(4),%a0@(S_PC) - move.w %a1@(2),%a0@(S_SR) - - jsr cpu_cache_flush - nop - - move.l %a1,%sp@- - jsr mcf_execute_exception_handler - - - lea _asm_context,%a0 - move.l %a0@(S_SP),%sp - - move.l %a0@(S_D1),%d1 - move.l %a0@(S_D0),%d0 - move.l %a0@(S_A1),%a1 - move.l %a0@(S_A0),%a0 - - rte - nop - nop - - .global _asm_isr_handler -_asm_isr_handler: - link %a6,#-16 - movem.l %d0-%d1/%a0-%a1,%sp@ - - move.w %a6@(4),%d0 - lsr.l #2,%d0 - andi.l #0x0000FF,%d0 - move.l %d0,%sp@- - move.l #0,%a0 - move.l %a0,%sp@- - jsr mcf_execute_irq_handler - lea %sp@(8),%sp - cmpi.l #1,%d0 - beq handled - -nothandled: - movem.l %sp@,%d0-%d1/%a0-%a1 - unlk %a6 - jmp _asm_exception_handler - nop - -handled: - movem.l %sp@,%d0-%d1/%a0-%a1 - unlk %a6 - rte - nop - nop - -#else - - .global _dbug_sc_handler -_dbug_sc_handler: - .global _asm_exception_handler -_asm_exception_handler: - nop - // FIXME - do something useful here - rte - - .global _asm_isr_handler -_asm_isr_handler: - nop - // FIXME - do something useful here - rte - -#endif - - .data -_asm_context: - .space S_FRAME_SIZE,0x55 - - - .end diff --git a/arch/m68k/include/asm/atomic.h b/arch/m68k/include/asm/atomic.h deleted file mode 100644 index efbe2b88bf..0000000000 --- a/arch/m68k/include/asm/atomic.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Declaration for atomic operations - */ - -/* Empty dummy FIXME */ diff --git a/arch/m68k/include/asm/barebox-m68k.h b/arch/m68k/include/asm/barebox-m68k.h deleted file mode 100644 index c1ee75ed33..0000000000 --- a/arch/m68k/include/asm/barebox-m68k.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Arch dependant barebox defines - */ -#ifndef _BAREBOX_M68K_H_ -#define _BAREBOX_M68K_H_ 1 - -/* for the following variables, see start.S */ -//extern ulong _armboot_start; /* code start */ -//extern ulong _bss_start; /* code + data end == BSS start */ -//extern ulong _bss_end; /* BSS end */ -//extern ulong IRQ_STACK_START; /* top of IRQ stack */ - -/* cpu/.../cpu.c */ -int cleanup_before_linux(void); - -/* board/.../... */ -//int board_init(void); -//int dram_init (void); - -#endif /* _BAREBOX_M68K_H_ */ diff --git a/arch/m68k/include/asm/barebox.h b/arch/m68k/include/asm/barebox.h deleted file mode 100644 index 568b2883b9..0000000000 --- a/arch/m68k/include/asm/barebox.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * @note This header file defines an interface to barebox. Including - * this (unmodified) header file in another file is considered normal - * use of barebox, and does *not* fall under the heading of "derived - * work". - */ - -#ifndef _BAREBOX_H_ -#define _BAREBOX_H_ 1 - -//typedef struct bd_info {} bd_t; - -#endif /* _BAREBOX_H_ */ diff --git a/arch/m68k/include/asm/bitops.h b/arch/m68k/include/asm/bitops.h deleted file mode 100644 index fee64a425c..0000000000 --- a/arch/m68k/include/asm/bitops.h +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Bitops helper functions and defines for M68k - * - * bit 0 is the LSB of addr; bit 32 is the HSB. - * - * Please note that the code in this file should never be included - * from user space. Many of these are not implemented in assembler - * since they would be too costly. Also, they require priviledged - * instructions (which are not available from user mode) to ensure - * that they are atomic. - */ - -#ifndef __ASM_M68K_BITOPS_H -#define __ASM_M68K_BITOPS_H - -/* - * Function prototypes to keep gcc -Wall happy. - */ -extern void set_bit(int nr, volatile void * addr); - -static inline void __set_bit(int nr, volatile void *addr) -{ - ((unsigned char *) addr)[nr >> 3] |= (1U << (nr & 7)); -} - -extern void clear_bit(int nr, volatile void * addr); - -static inline void __clear_bit(int nr, volatile void *addr) -{ - ((unsigned char *) addr)[nr >> 3] &= ~(1U << (nr & 7)); -} - -extern void change_bit(int nr, volatile void * addr); - -static inline void __change_bit(int nr, volatile void *addr) -{ - ((unsigned char *) addr)[nr >> 3] ^= (1U << (nr & 7)); -} - -extern int test_and_set_bit(int nr, volatile void * addr); - -static inline int __test_and_set_bit(int nr, volatile void *addr) -{ - unsigned int mask = 1 << (nr & 7); - unsigned int oldval; - - oldval = ((unsigned char *) addr)[nr >> 3]; - ((unsigned char *) addr)[nr >> 3] = oldval | mask; - return oldval & mask; -} - -extern int test_and_clear_bit(int nr, volatile void * addr); - -static inline int __test_and_clear_bit(int nr, volatile void *addr) -{ - unsigned int mask = 1 << (nr & 7); - unsigned int oldval; - - oldval = ((unsigned char *) addr)[nr >> 3]; - ((unsigned char *) addr)[nr >> 3] = oldval & ~mask; - return oldval & mask; -} - -extern int test_and_change_bit(int nr, volatile void * addr); - -static inline int __test_and_change_bit(int nr, volatile void *addr) -{ - unsigned int mask = 1 << (nr & 7); - unsigned int oldval; - - oldval = ((unsigned char *) addr)[nr >> 3]; - ((unsigned char *) addr)[nr >> 3] = oldval ^ mask; - return oldval & mask; -} - -extern int find_first_zero_bit(void * addr, unsigned size); -extern int find_next_zero_bit(void * addr, int size, int offset); - -/* - * This routine doesn't need to be atomic. - */ -static inline int test_bit(int nr, const void * addr) -{ - return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7)); -} - -/* - * ffz = Find First Zero in word. Undefined if no zero exists, - * so code should check against ~0UL first.. - */ -static inline unsigned long ffz(unsigned long word) -{ - int k; - - word = ~word; - k = 31; - if (word & 0x0000ffff) { k -= 16; word <<= 16; } - if (word & 0x00ff0000) { k -= 8; word <<= 8; } - if (word & 0x0f000000) { k -= 4; word <<= 4; } - if (word & 0x30000000) { k -= 2; word <<= 2; } - if (word & 0x40000000) { k -= 1; } - return k; -} - -#include <asm-generic/bitops/ffs.h> -#include <asm-generic/bitops/hweight.h> - -#define ext2_set_bit test_and_set_bit -#define ext2_clear_bit test_and_clear_bit -#define ext2_test_bit test_bit -#define ext2_find_first_zero_bit find_first_zero_bit -#define ext2_find_next_zero_bit find_next_zero_bit - -/* Bitmap functions for the minix filesystem. */ -#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr) -#define minix_set_bit(nr,addr) set_bit(nr,addr) -#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr) -#define minix_test_bit(nr,addr) test_bit(nr,addr) -#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size) - -#endif /* __ASM_M68K_BITOPS_H */ diff --git a/arch/m68k/include/asm/bootinfo.h b/arch/m68k/include/asm/bootinfo.h deleted file mode 100644 index a0bd27b317..0000000000 --- a/arch/m68k/include/asm/bootinfo.h +++ /dev/null @@ -1,381 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Definition of the Linux/m68k boot information structure. - * - * Taken from Linux includes. See there for latest version, and update - * if needed - */ -#ifndef _M68K_BOOTINFO_H -#define _M68K_BOOTINFO_H - - -/* - * Bootinfo definitions - * - * This is an easily parsable and extendable structure containing all - * information to be passed from the bootstrap to the kernel. - * - * This way I hope to keep all future changes back/forewards compatible. - * Thus, keep your fingers crossed... - * - * This structure is copied right after the kernel bss by the bootstrap - * routine. - */ - -#ifndef __ASSEMBLY__ - -struct bi_record { - unsigned short tag; /* tag ID */ - unsigned short size; /* size of record (in bytes) */ - unsigned long data[0]; /* data */ -}; - -#endif /* __ASSEMBLY__ */ - - -/* - * Tag Definitions - * - * Machine independent tags start counting from 0x0000 - * Machine dependent tags start counting from 0x8000 - */ - -#define BI_LAST 0x0000 /* last record (sentinel) */ -#define BI_MACHTYPE 0x0001 /* machine type (u_long) */ -#define BI_CPUTYPE 0x0002 /* cpu type (u_long) */ -#define BI_FPUTYPE 0x0003 /* fpu type (u_long) */ -#define BI_MMUTYPE 0x0004 /* mmu type (u_long) */ -#define BI_MEMCHUNK 0x0005 /* memory chunk address and size */ - /* (struct mem_info) */ -#define BI_RAMDISK 0x0006 /* ramdisk address and size */ - /* (struct mem_info) */ -#define BI_COMMAND_LINE 0x0007 /* kernel command line parameters */ - /* (string) */ - -/* - * Amiga-specific tags - */ - -#define BI_AMIGA_MODEL 0x8000 /* model (u_long) */ -#define BI_AMIGA_AUTOCON 0x8001 /* AutoConfig device */ - /* (struct ConfigDev) */ -#define BI_AMIGA_CHIP_SIZE 0x8002 /* size of Chip RAM (u_long) */ -#define BI_AMIGA_VBLANK 0x8003 /* VBLANK frequency (u_char) */ -#define BI_AMIGA_PSFREQ 0x8004 /* power supply frequency (u_char) */ -#define BI_AMIGA_ECLOCK 0x8005 /* EClock frequency (u_long) */ -#define BI_AMIGA_CHIPSET 0x8006 /* native chipset present (u_long) */ -#define BI_AMIGA_SERPER 0x8007 /* serial port period (u_short) */ - -/* - * Atari-specific tags - */ - -#define BI_ATARI_MCH_COOKIE 0x8000 /* _MCH cookie from TOS (u_long) */ -#define BI_ATARI_MCH_TYPE 0x8001 /* special machine type (u_long) */ - /* (values are ATARI_MACH_* defines */ - -/* mch_cookie values (upper word) */ -#define ATARI_MCH_ST 0 -#define ATARI_MCH_STE 1 -#define ATARI_MCH_TT 2 -#define ATARI_MCH_FALCON 3 - -/* mch_type values */ -#define ATARI_MACH_NORMAL 0 /* no special machine type */ -#define ATARI_MACH_MEDUSA 1 /* Medusa 040 */ -#define ATARI_MACH_HADES 2 /* Hades 040 or 060 */ -#define ATARI_MACH_AB40 3 /* Afterburner040 on Falcon */ - -/* - * VME-specific tags - */ - -#define BI_VME_TYPE 0x8000 /* VME sub-architecture (u_long) */ -#define BI_VME_BRDINFO 0x8001 /* VME board information (struct) */ - -/* BI_VME_TYPE codes */ -#define VME_TYPE_TP34V 0x0034 /* Tadpole TP34V */ -#define VME_TYPE_MVME147 0x0147 /* Motorola MVME147 */ -#define VME_TYPE_MVME162 0x0162 /* Motorola MVME162 */ -#define VME_TYPE_MVME166 0x0166 /* Motorola MVME166 */ -#define VME_TYPE_MVME167 0x0167 /* Motorola MVME167 */ -#define VME_TYPE_MVME172 0x0172 /* Motorola MVME172 */ -#define VME_TYPE_MVME177 0x0177 /* Motorola MVME177 */ -#define VME_TYPE_BVME4000 0x4000 /* BVM Ltd. BVME4000 */ -#define VME_TYPE_BVME6000 0x6000 /* BVM Ltd. BVME6000 */ - -/* BI_VME_BRDINFO is a 32 byte struct as returned by the Bug code on - * Motorola VME boards. Contains board number, Bug version, board - * configuration options, etc. See include/asm/mvme16xhw.h for details. - */ - - -/* - * Macintosh-specific tags (all u_long) - */ - -#define BI_MAC_MODEL 0x8000 /* Mac Gestalt ID (model type) */ -#define BI_MAC_VADDR 0x8001 /* Mac video base address */ -#define BI_MAC_VDEPTH 0x8002 /* Mac video depth */ -#define BI_MAC_VROW 0x8003 /* Mac video rowbytes */ -#define BI_MAC_VDIM 0x8004 /* Mac video dimensions */ -#define BI_MAC_VLOGICAL 0x8005 /* Mac video logical base */ -#define BI_MAC_SCCBASE 0x8006 /* Mac SCC base address */ -#define BI_MAC_BTIME 0x8007 /* Mac boot time */ -#define BI_MAC_GMTBIAS 0x8008 /* Mac GMT timezone offset */ -#define BI_MAC_MEMSIZE 0x8009 /* Mac RAM size (sanity check) */ -#define BI_MAC_CPUID 0x800a /* Mac CPU type (sanity check) */ -#define BI_MAC_ROMBASE 0x800b /* Mac system ROM base address */ - -/* - * Macintosh hardware profile data - unused, see macintosh.h for - * resonable type values - */ - -#define BI_MAC_VIA1BASE 0x8010 /* Mac VIA1 base address (always present) */ -#define BI_MAC_VIA2BASE 0x8011 /* Mac VIA2 base address (type varies) */ -#define BI_MAC_VIA2TYPE 0x8012 /* Mac VIA2 type (VIA, RBV, OSS) */ -#define BI_MAC_ADBTYPE 0x8013 /* Mac ADB interface type */ -#define BI_MAC_ASCBASE 0x8014 /* Mac Apple Sound Chip base address */ -#define BI_MAC_SCSI5380 0x8015 /* Mac NCR 5380 SCSI (base address, multi) */ -#define BI_MAC_SCSIDMA 0x8016 /* Mac SCSI DMA (base address) */ -#define BI_MAC_SCSI5396 0x8017 /* Mac NCR 53C96 SCSI (base address, multi) */ -#define BI_MAC_IDETYPE 0x8018 /* Mac IDE interface type */ -#define BI_MAC_IDEBASE 0x8019 /* Mac IDE interface base address */ -#define BI_MAC_NUBUS 0x801a /* Mac Nubus type (none, regular, pseudo) */ -#define BI_MAC_SLOTMASK 0x801b /* Mac Nubus slots present */ -#define BI_MAC_SCCTYPE 0x801c /* Mac SCC serial type (normal, IOP) */ -#define BI_MAC_ETHTYPE 0x801d /* Mac builtin ethernet type (Sonic, MACE */ -#define BI_MAC_ETHBASE 0x801e /* Mac builtin ethernet base address */ -#define BI_MAC_PMU 0x801f /* Mac power management / poweroff hardware */ -#define BI_MAC_IOP_SWIM 0x8020 /* Mac SWIM floppy IOP */ -#define BI_MAC_IOP_ADB 0x8021 /* Mac ADB IOP */ - -/* - * Mac: compatibility with old booter data format (temporarily) - * Fields unused with the new bootinfo can be deleted now; instead of - * adding new fields the struct might be splitted into a hardware address - * part and a hardware type part - */ - -#ifndef __ASSEMBLY__ - -struct mac_booter_data -{ - unsigned long videoaddr; - unsigned long videorow; - unsigned long videodepth; - unsigned long dimensions; - unsigned long args; - unsigned long boottime; - unsigned long gmtbias; - unsigned long bootver; - unsigned long videological; - unsigned long sccbase; - unsigned long id; - unsigned long memsize; - unsigned long serialmf; - unsigned long serialhsk; - unsigned long serialgpi; - unsigned long printmf; - unsigned long printhsk; - unsigned long printgpi; - unsigned long cpuid; - unsigned long rombase; - unsigned long adbdelay; - unsigned long timedbra; -}; - -extern struct mac_booter_data - mac_bi_data; - -#endif - -/* - * Apollo-specific tags - */ - -#define BI_APOLLO_MODEL 0x8000 /* model (u_long) */ - -/* - * HP300-specific tags - */ - -#define BI_HP300_MODEL 0x8000 /* model (u_long) */ -#define BI_HP300_UART_SCODE 0x8001 /* UART select code (u_long) */ -#define BI_HP300_UART_ADDR 0x8002 /* phys. addr of UART (u_long) */ - -/* - * Stuff for bootinfo interface versioning - * - * At the start of kernel code, a 'struct bootversion' is located. - * bootstrap checks for a matching version of the interface before booting - * a kernel, to avoid user confusion if kernel and bootstrap don't work - * together :-) - * - * If incompatible changes are made to the bootinfo interface, the major - * number below should be stepped (and the minor reset to 0) for the - * appropriate machine. If a change is backward-compatible, the minor - * should be stepped. "Backwards-compatible" means that booting will work, - * but certain features may not. - */ - -#define BOOTINFOV_MAGIC 0x4249561A /* 'BIV^Z' */ -#define MK_BI_VERSION(major,minor) (((major)<<16)+(minor)) -#define BI_VERSION_MAJOR(v) (((v) >> 16) & 0xffff) -#define BI_VERSION_MINOR(v) ((v) & 0xffff) - -#ifndef __ASSEMBLY__ - -struct bootversion { - unsigned short branch; - unsigned long magic; - struct { - unsigned long machtype; - unsigned long version; - } machversions[0]; -}; - -#endif /* __ASSEMBLY__ */ - -#define AMIGA_BOOTI_VERSION MK_BI_VERSION( 2, 0 ) -#define ATARI_BOOTI_VERSION MK_BI_VERSION( 2, 1 ) -#define MAC_BOOTI_VERSION MK_BI_VERSION( 2, 0 ) -#define MVME147_BOOTI_VERSION MK_BI_VERSION( 2, 0 ) -#define MVME16x_BOOTI_VERSION MK_BI_VERSION( 2, 0 ) -#define BVME6000_BOOTI_VERSION MK_BI_VERSION( 2, 0 ) -#define Q40_BOOTI_VERSION MK_BI_VERSION( 2, 0 ) -#define HP300_BOOTI_VERSION MK_BI_VERSION( 2, 0 ) - -#ifdef BOOTINFO_COMPAT_1_0 - -/* - * Backwards compatibility with bootinfo interface version 1.0 - */ - -#define COMPAT_AMIGA_BOOTI_VERSION MK_BI_VERSION( 1, 0 ) -#define COMPAT_ATARI_BOOTI_VERSION MK_BI_VERSION( 1, 0 ) -#define COMPAT_MAC_BOOTI_VERSION MK_BI_VERSION( 1, 0 ) - -#include <linux/zorro.h> - -#define COMPAT_NUM_AUTO 16 - -struct compat_bi_Amiga { - int model; - int num_autocon; - struct ConfigDev autocon[COMPAT_NUM_AUTO]; - unsigned long chip_size; - unsigned char vblank; - unsigned char psfreq; - unsigned long eclock; - unsigned long chipset; - unsigned long hw_present; -}; - -struct compat_bi_Atari { - unsigned long hw_present; - unsigned long mch_cookie; -}; - -#ifndef __ASSEMBLY__ - -struct compat_bi_Macintosh -{ - unsigned long videoaddr; - unsigned long videorow; - unsigned long videodepth; - unsigned long dimensions; - unsigned long args; - unsigned long boottime; - unsigned long gmtbias; - unsigned long bootver; - unsigned long videological; - unsigned long sccbase; - unsigned long id; - unsigned long memsize; - unsigned long serialmf; - unsigned long serialhsk; - unsigned long serialgpi; - unsigned long printmf; - unsigned long printhsk; - unsigned long printgpi; - unsigned long cpuid; - unsigned long rombase; - unsigned long adbdelay; - unsigned long timedbra; -}; - -#endif - -struct compat_mem_info { - unsigned long addr; - unsigned long size; -}; - -#define COMPAT_NUM_MEMINFO 4 - -#define COMPAT_CPUB_68020 0 -#define COMPAT_CPUB_68030 1 -#define COMPAT_CPUB_68040 2 -#define COMPAT_CPUB_68060 3 -#define COMPAT_FPUB_68881 5 -#define COMPAT_FPUB_68882 6 -#define COMPAT_FPUB_68040 7 -#define COMPAT_FPUB_68060 8 - -#define COMPAT_CPU_68020 (1<<COMPAT_CPUB_68020) -#define COMPAT_CPU_68030 (1<<COMPAT_CPUB_68030) -#define COMPAT_CPU_68040 (1<<COMPAT_CPUB_68040) -#define COMPAT_CPU_68060 (1<<COMPAT_CPUB_68060) -#define COMPAT_CPU_MASK (31) -#define COMPAT_FPU_68881 (1<<COMPAT_FPUB_68881) -#define COMPAT_FPU_68882 (1<<COMPAT_FPUB_68882) -#define COMPAT_FPU_68040 (1<<COMPAT_FPUB_68040) -#define COMPAT_FPU_68060 (1<<COMPAT_FPUB_68060) -#define COMPAT_FPU_MASK (0xfe0) - -#define COMPAT_CL_SIZE (256) - -struct compat_bootinfo { - unsigned long machtype; - unsigned long cputype; - struct compat_mem_info memory[COMPAT_NUM_MEMINFO]; - int num_memory; - unsigned long ramdisk_size; - unsigned long ramdisk_addr; - char command_line[COMPAT_CL_SIZE]; - union { - struct compat_bi_Amiga bi_ami; - struct compat_bi_Atari bi_ata; - struct compat_bi_Macintosh bi_mac; - } bi_un; -}; - -#define bi_amiga bi_un.bi_ami -#define bi_atari bi_un.bi_ata -#define bi_mac bi_un.bi_mac - -#endif /* BOOTINFO_COMPAT_1_0 */ - - -#endif /* _M68K_BOOTINFO_H */ diff --git a/arch/m68k/include/asm/byteorder.h b/arch/m68k/include/asm/byteorder.h deleted file mode 100644 index 7a5fb6188c..0000000000 --- a/arch/m68k/include/asm/byteorder.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Define byte order of target - * - * M68K is always big-endian mode. - * - * When in big endian mode, byte accesses appear as: - * 0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7 - * and word accesses (data or instruction) appear as: - * d0...d31 - */ -#ifndef __ASM_M68K_BYTEORDER_H -#define __ASM_M68K_BYTEORDER_H - - -#include <asm/types.h> - -#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) -# define __BYTEORDER_HAS_U64__ -# define __SWAB_64_THRU_32__ -#endif -#include <linux/byteorder/big_endian.h> - -#endif diff --git a/arch/m68k/include/asm/coldfire/mcf548x.h b/arch/m68k/include/asm/coldfire/mcf548x.h deleted file mode 100644 index 4bde42a57d..0000000000 --- a/arch/m68k/include/asm/coldfire/mcf548x.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF547X and MCF548X processors - */ -#ifndef __MCF548X_H__ -#define __MCF548X_H__ - -/* - * useful padding structure for register maps - */ -typedef struct -{ - vuint8_t a; - vuint16_t b; -} __attribute ((packed)) vuint24_t; - -/* - * Include all internal hardware register macros and defines for this CPU. - */ -#include "asm/coldfire/mcf548x/mcf548x_fec.h" -#include "asm/coldfire/mcf548x/mcf548x_siu.h" -#include "asm/coldfire/mcf548x/mcf548x_ctm.h" -#include "asm/coldfire/mcf548x/mcf548x_dspi.h" -#include "asm/coldfire/mcf548x/mcf548x_eport.h" -#include "asm/coldfire/mcf548x/mcf548x_fbcs.h" -#include "asm/coldfire/mcf548x/mcf548x_gpio.h" -#include "asm/coldfire/mcf548x/mcf548x_gpt.h" -#include "asm/coldfire/mcf548x/mcf548x_i2c.h" -#include "asm/coldfire/mcf548x/mcf548x_intc.h" -#include "asm/coldfire/mcf548x/mcf548x_sdramc.h" -#include "asm/coldfire/mcf548x/mcf548x_sec.h" -#include "asm/coldfire/mcf548x/mcf548x_slt.h" -#include "asm/coldfire/mcf548x/mcf548x_usb.h" -#include "asm/coldfire/mcf548x/mcf548x_psc.h" -#include "asm/coldfire/mcf548x/mcf548x_uart.h" -#include "asm/coldfire/mcf548x/mcf548x_sram.h" -#include "asm/coldfire/mcf548x/mcf548x_pci.h" -#include "asm/coldfire/mcf548x/mcf548x_pciarb.h" -#include "asm/coldfire/mcf548x/mcf548x_dma.h" -#include "asm/coldfire/mcf548x/mcf548x_dma_ereq.h" -#include "asm/coldfire/mcf548x/mcf548x_can.h" -#include "asm/coldfire/mcf548x/mcf548x_xlbarb.h" - -#endif /* __MCF548X_H__ */ diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_can.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_can.h deleted file mode 100644 index bb53eaa03a..0000000000 --- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_can.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * CAN controllers - */ -#ifndef __MCF548X_CAN_H__ -#define __MCF548X_CAN_H__ - -/* - * FlexCAN Module (CAN) - */ - -/* Register read/write macros */ -#define MCF_CAN_CANMCR0 (*(vuint32_t*)(&__MBAR[0x00A000])) -#define MCF_CAN_CANCTRL0 (*(vuint32_t*)(&__MBAR[0x00A004])) -#define MCF_CAN_TIMER0 (*(vuint32_t*)(&__MBAR[0x00A008])) -#define MCF_CAN_RXGMASK0 (*(vuint32_t*)(&__MBAR[0x00A010])) -#define MCF_CAN_RX14MASK0 (*(vuint32_t*)(&__MBAR[0x00A014])) -#define MCF_CAN_RX15MASK0 (*(vuint32_t*)(&__MBAR[0x00A018])) -#define MCF_CAN_ERRCNT0 (*(vuint32_t*)(&__MBAR[0x00A01C])) -#define MCF_CAN_ERRSTAT0 (*(vuint32_t*)(&__MBAR[0x00A020])) -#define MCF_CAN_IMASK0 (*(vuint16_t*)(&__MBAR[0x00A02A])) -#define MCF_CAN_IFLAG0 (*(vuint16_t*)(&__MBAR[0x00A032])) -#define MCF_CAN_CANMCR1 (*(vuint32_t*)(&__MBAR[0x00A800])) -#define MCF_CAN_CANCTRL1 (*(vuint32_t*)(&__MBAR[0x00A804])) -#define MCF_CAN_TIMER1 (*(vuint32_t*)(&__MBAR[0x00A808])) -#define MCF_CAN_RXGMASK1 (*(vuint32_t*)(&__MBAR[0x00A810])) -#define MCF_CAN_RX14MASK1 (*(vuint32_t*)(&__MBAR[0x00A814])) -#define MCF_CAN_RX15MASK1 (*(vuint32_t*)(&__MBAR[0x00A818])) -#define MCF_CAN_ERRCNT1 (*(vuint32_t*)(&__MBAR[0x00A81C])) -#define MCF_CAN_ERRSTAT1 (*(vuint32_t*)(&__MBAR[0x00A820])) -#define MCF_CAN_IMASK1 (*(vuint16_t*)(&__MBAR[0x00A82A])) -#define MCF_CAN_IFLAG1 (*(vuint16_t*)(&__MBAR[0x00A832])) -#define MCF_CAN_CANMCR(x) (*(vuint32_t*)(&__MBAR[0x00A000+((x)*0x800)])) -#define MCF_CAN_CANCTRL(x) (*(vuint32_t*)(&__MBAR[0x00A004+((x)*0x800)])) -#define MCF_CAN_TIMER(x) (*(vuint32_t*)(&__MBAR[0x00A008+((x)*0x800)])) -#define MCF_CAN_RXGMASK(x) (*(vuint32_t*)(&__MBAR[0x00A010+((x)*0x800)])) -#define MCF_CAN_RX14MASK(x) (*(vuint32_t*)(&__MBAR[0x00A014+((x)*0x800)])) -#define MCF_CAN_RX15MASK(x) (*(vuint32_t*)(&__MBAR[0x00A018+((x)*0x800)])) -#define MCF_CAN_ERRCNT(x) (*(vuint32_t*)(&__MBAR[0x00A01C+((x)*0x800)])) -#define MCF_CAN_ERRSTAT(x) (*(vuint32_t*)(&__MBAR[0x00A020+((x)*0x800)])) -#define MCF_CAN_IMASK(x) (*(vuint16_t*)(&__MBAR[0x00A02A+((x)*0x800)])) -#define MCF_CAN_IFLAG(x) (*(vuint16_t*)(&__MBAR[0x00A032+((x)*0x800)])) - -/* Bit definitions and macros for MCF_CAN_CANMCR */ -#define MCF_CAN_CANMCR_MAXMB(x) (((x)&0x0000000F)<<0) -#define MCF_CAN_CANMCR_SUPV (0x00800000) -#define MCF_CAN_CANMCR_FRZACK (0x01000000) -#define MCF_CAN_CANMCR_SOFTRST (0x02000000) -#define MCF_CAN_CANMCR_HALT (0x10000000) -#define MCF_CAN_CANMCR_FRZ (0x40000000) -#define MCF_CAN_CANMCR_MDIS (0x80000000) - -/* Bit definitions and macros for MCF_CAN_CANCTRL */ -#define MCF_CAN_CANCTRL_PROPSEG(x) (((x)&0x00000007)<<0) -#define MCF_CAN_CANCTRL_LOM (0x00000008) -#define MCF_CAN_CANCTRL_LBUF (0x00000010) -#define MCF_CAN_CANCTRL_TSYNC (0x00000020) -#define MCF_CAN_CANCTRL_BOFFREC (0x00000040) -#define MCF_CAN_CANCTRL_SAMP (0x00000080) -#define MCF_CAN_CANCTRL_LPB (0x00001000) -#define MCF_CAN_CANCTRL_CLKSRC (0x00002000) -#define MCF_CAN_CANCTRL_ERRMSK (0x00004000) -#define MCF_CAN_CANCTRL_BOFFMSK (0x00008000) -#define MCF_CAN_CANCTRL_PSEG2(x) (((x)&0x00000007)<<16) -#define MCF_CAN_CANCTRL_PSEG1(x) (((x)&0x00000007)<<19) -#define MCF_CAN_CANCTRL_RJW(x) (((x)&0x00000003)<<22) -#define MCF_CAN_CANCTRL_PRESDIV(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_CAN_TIMER */ -#define MCF_CAN_TIMER_TIMER(x) (((x)&0x0000FFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_RXGMASK */ -#define MCF_CAN_RXGMASK_MI(x) (((x)&0x1FFFFFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_RX14MASK */ -#define MCF_CAN_RX14MASK_MI(x) (((x)&0x1FFFFFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_RX15MASK */ -#define MCF_CAN_RX15MASK_MI(x) (((x)&0x1FFFFFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_ERRCNT */ -#define MCF_CAN_ERRCNT_TXECTR(x) (((x)&0x000000FF)<<0) -#define MCF_CAN_ERRCNT_RXECTR(x) (((x)&0x000000FF)<<8) - -/* Bit definitions and macros for MCF_CAN_ERRSTAT */ -#define MCF_CAN_ERRSTAT_WAKINT (0x00000001) -#define MCF_CAN_ERRSTAT_ERRINT (0x00000002) -#define MCF_CAN_ERRSTAT_BOFFINT (0x00000004) -#define MCF_CAN_ERRSTAT_FLTCONF(x) (((x)&0x00000003)<<4) -#define MCF_CAN_ERRSTAT_TXRX (0x00000040) -#define MCF_CAN_ERRSTAT_IDLE (0x00000080) -#define MCF_CAN_ERRSTAT_RXWRN (0x00000100) -#define MCF_CAN_ERRSTAT_TXWRN (0x00000200) -#define MCF_CAN_ERRSTAT_STFERR (0x00000400) -#define MCF_CAN_ERRSTAT_FRMERR (0x00000800) -#define MCF_CAN_ERRSTAT_CRCERR (0x00001000) -#define MCF_CAN_ERRSTAT_ACKERR (0x00002000) -#define MCF_CAN_ERRSTAT_BITERR(x) (((x)&0x00000003)<<14) -#define MCF_CAN_ERRSTAT_FLTCONF_ACTIVE (0x00000000) -#define MCF_CAN_ERRSTAT_FLTCONF_PASSIVE (0x00000010) -#define MCF_CAN_ERRSTAT_FLTCONF_BUSOFF (0x00000020) - -/* Bit definitions and macros for MCF_CAN_IMASK */ -#define MCF_CAN_IMASK_BUF0M (0x0001) -#define MCF_CAN_IMASK_BUF1M (0x0002) -#define MCF_CAN_IMASK_BUF2M (0x0004) -#define MCF_CAN_IMASK_BUF3M (0x0008) -#define MCF_CAN_IMASK_BUF4M (0x0010) -#define MCF_CAN_IMASK_BUF5M (0x0020) -#define MCF_CAN_IMASK_BUF6M (0x0040) -#define MCF_CAN_IMASK_BUF7M (0x0080) -#define MCF_CAN_IMASK_BUF8M (0x0100) -#define MCF_CAN_IMASK_BUF9M (0x0200) -#define MCF_CAN_IMASK_BUF10M (0x0400) -#define MCF_CAN_IMASK_BUF11M (0x0800) -#define MCF_CAN_IMASK_BUF12M (0x1000) -#define MCF_CAN_IMASK_BUF13M (0x2000) -#define MCF_CAN_IMASK_BUF14M (0x4000) -#define MCF_CAN_IMASK_BUF15M (0x8000) - -/* Bit definitions and macros for MCF_CAN_IFLAG */ -#define MCF_CAN_IFLAG_BUF0I (0x0001) -#define MCF_CAN_IFLAG_BUF1I (0x0002) -#define MCF_CAN_IFLAG_BUF2I (0x0004) -#define MCF_CAN_IFLAG_BUF3I (0x0008) -#define MCF_CAN_IFLAG_BUF4I (0x0010) -#define MCF_CAN_IFLAG_BUF5I (0x0020) -#define MCF_CAN_IFLAG_BUF6I (0x0040) -#define MCF_CAN_IFLAG_BUF7I (0x0080) -#define MCF_CAN_IFLAG_BUF8I (0x0100) -#define MCF_CAN_IFLAG_BUF9I (0x0200) -#define MCF_CAN_IFLAG_BUF10I (0x0400) -#define MCF_CAN_IFLAG_BUF11I (0x0800) -#define MCF_CAN_IFLAG_BUF12I (0x1000) -#define MCF_CAN_IFLAG_BUF13I (0x2000) -#define MCF_CAN_IFLAG_BUF14I (0x4000) -#define MCF_CAN_IFLAG_BUF15I (0x8000) - -#endif /* __MCF548X_CAN_H__ */ diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_ctm.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_ctm.h deleted file mode 100644 index 6c779ec739..0000000000 --- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_ctm.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * Common Timer Module - */ -#ifndef __MCF548X_CTM_H__ -#define __MCF548X_CTM_H__ - -/* - * Comm Timer Module (CTM) - */ - -/* Register read/write macros */ -#define MCF_CTM_CTCRF0 (*(vuint32_t*)(&__MBAR[0x007F00])) -#define MCF_CTM_CTCRF1 (*(vuint32_t*)(&__MBAR[0x007F04])) -#define MCF_CTM_CTCRF2 (*(vuint32_t*)(&__MBAR[0x007F08])) -#define MCF_CTM_CTCRF3 (*(vuint32_t*)(&__MBAR[0x007F0C])) -#define MCF_CTM_CTCRFn(x) (*(vuint32_t*)(&__MBAR[0x007F00+((x)*0x004)])) -#define MCF_CTM_CTCRV4 (*(vuint32_t*)(&__MBAR[0x007F10])) -#define MCF_CTM_CTCRV5 (*(vuint32_t*)(&__MBAR[0x007F14])) -#define MCF_CTM_CTCRV6 (*(vuint32_t*)(&__MBAR[0x007F18])) -#define MCF_CTM_CTCRV7 (*(vuint32_t*)(&__MBAR[0x007F1C])) -#define MCF_CTM_CTCRVn(x) (*(vuint32_t*)(&__MBAR[0x007F10+((x)*0x004)])) - -/* Bit definitions and macros for MCF_CTM_CTCRFn */ -#define MCF_CTM_CTCRFn_CRV(x) (((x)&0x0000FFFF)<<0) -#define MCF_CTM_CTCRFn_S(x) (((x)&0x0000000F)<<16) -#define MCF_CTM_CTCRFn_PCT(x) (((x)&0x00000007)<<20) -#define MCF_CTM_CTCRFn_M (0x00800000) -#define MCF_CTM_CTCRFn_IM (0x01000000) -#define MCF_CTM_CTCRFn_I (0x80000000) -#define MCF_CTM_CTCRFn_PCT_100 (0x00000000) -#define MCF_CTM_CTCRFn_PCT_50 (0x00100000) -#define MCF_CTM_CTCRFn_PCT_25 (0x00200000) -#define MCF_CTM_CTCRFn_PCT_12p5 (0x00300000) -#define MCF_CTM_CTCRFn_PCT_6p25 (0x00400000) -#define MCF_CTM_CTCRFn_PCT_OFF (0x00500000) -#define MCF_CTM_CTCRFn_S_CLK_1 (0x00000000) -#define MCF_CTM_CTCRFn_S_CLK_2 (0x00010000) -#define MCF_CTM_CTCRFn_S_CLK_4 (0x00020000) -#define MCF_CTM_CTCRFn_S_CLK_8 (0x00030000) -#define MCF_CTM_CTCRFn_S_CLK_16 (0x00040000) -#define MCF_CTM_CTCRFn_S_CLK_32 (0x00050000) -#define MCF_CTM_CTCRFn_S_CLK_64 (0x00060000) -#define MCF_CTM_CTCRFn_S_CLK_128 (0x00070000) -#define MCF_CTM_CTCRFn_S_CLK_256 (0x00080000) - -/* Bit definitions and macros for MCF_CTM_CTCRVn */ -#define MCF_CTM_CTCRVn_CRV(x) (((x)&0x00FFFFFF)<<0) -#define MCF_CTM_CTCRVn_PCT(x) (((x)&0x00000007)<<24) -#define MCF_CTM_CTCRVn_M (0x08000000) -#define MCF_CTM_CTCRVn_S(x) (((x)&0x0000000F)<<28) -#define MCF_CTM_CTCRVn_S_CLK_1 (0x00000000) -#define MCF_CTM_CTCRVn_S_CLK_2 (0x10000000) -#define MCF_CTM_CTCRVn_S_CLK_4 (0x20000000) -#define MCF_CTM_CTCRVn_S_CLK_8 (0x30000000) -#define MCF_CTM_CTCRVn_S_CLK_16 (0x40000000) -#define MCF_CTM_CTCRVn_S_CLK_32 (0x50000000) -#define MCF_CTM_CTCRVn_S_CLK_64 (0x60000000) -#define MCF_CTM_CTCRVn_S_CLK_128 (0x70000000) -#define MCF_CTM_CTCRVn_S_CLK_256 (0x80000000) -#define MCF_CTM_CTCRVn_PCT_100 (0x00000000) -#define MCF_CTM_CTCRVn_PCT_50 (0x01000000) -#define MCF_CTM_CTCRVn_PCT_25 (0x02000000) -#define MCF_CTM_CTCRVn_PCT_12p5 (0x03000000) -#define MCF_CTM_CTCRVn_PCT_6p25 (0x04000000) -#define MCF_CTM_CTCRVn_PCT_OFF (0x05000000) - -#endif /* __MCF548X_CTM_H__ */ diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_dma.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_dma.h deleted file mode 100644 index 4229c36758..0000000000 --- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_dma.h +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * Multichannel DMA - */ -#ifndef __MCF548X_DMA_H__ -#define __MCF548X_DMA_H__ - -/* - * Multi-Channel DMA (DMA) - */ - -/* Register read/write macros */ -#define MCF_DMA_DIPR (*(vuint32_t*)(&__MBAR[0x008014])) -#define MCF_DMA_DIMR (*(vuint32_t*)(&__MBAR[0x008018])) -#define MCF_DMA_IMCR (*(vuint32_t*)(&__MBAR[0x00805C])) - -/* Bit definitions and macros for MCF_DMA_DIPR */ -#define MCF_DMA_DIPR_TASK0 (0x00000001) -#define MCF_DMA_DIPR_TASK1 (0x00000002) -#define MCF_DMA_DIPR_TASK2 (0x00000004) -#define MCF_DMA_DIPR_TASK3 (0x00000008) -#define MCF_DMA_DIPR_TASK4 (0x00000010) -#define MCF_DMA_DIPR_TASK5 (0x00000020) -#define MCF_DMA_DIPR_TASK6 (0x00000040) -#define MCF_DMA_DIPR_TASK7 (0x00000080) -#define MCF_DMA_DIPR_TASK8 (0x00000100) -#define MCF_DMA_DIPR_TASK9 (0x00000200) -#define MCF_DMA_DIPR_TASK10 (0x00000400) -#define MCF_DMA_DIPR_TASK11 (0x00000800) -#define MCF_DMA_DIPR_TASK12 (0x00001000) -#define MCF_DMA_DIPR_TASK13 (0x00002000) -#define MCF_DMA_DIPR_TASK14 (0x00004000) -#define MCF_DMA_DIPR_TASK15 (0x00008000) - -/* Bit definitions and macros for MCF_DMA_DIMR */ -#define MCF_DMA_DIMR_TASK0 (0x00000001) -#define MCF_DMA_DIMR_TASK1 (0x00000002) -#define MCF_DMA_DIMR_TASK2 (0x00000004) -#define MCF_DMA_DIMR_TASK3 (0x00000008) -#define MCF_DMA_DIMR_TASK4 (0x00000010) -#define MCF_DMA_DIMR_TASK5 (0x00000020) -#define MCF_DMA_DIMR_TASK6 (0x00000040) -#define MCF_DMA_DIMR_TASK7 (0x00000080) -#define MCF_DMA_DIMR_TASK8 (0x00000100) -#define MCF_DMA_DIMR_TASK9 (0x00000200) -#define MCF_DMA_DIMR_TASK10 (0x00000400) -#define MCF_DMA_DIMR_TASK11 (0x00000800) -#define MCF_DMA_DIMR_TASK12 (0x00001000) -#define MCF_DMA_DIMR_TASK13 (0x00002000) -#define MCF_DMA_DIMR_TASK14 (0x00004000) -#define MCF_DMA_DIMR_TASK15 (0x00008000) - -/* Bit definitions and macros for MCF_DMA_IMCR */ -#define MCF_DMA_IMCR_SRC16(x) (((x)&0x00000003)<<0) -#define MCF_DMA_IMCR_SRC17(x) (((x)&0x00000003)<<2) -#define MCF_DMA_IMCR_SRC18(x) (((x)&0x00000003)<<4) -#define MCF_DMA_IMCR_SRC19(x) (((x)&0x00000003)<<6) -#define MCF_DMA_IMCR_SRC20(x) (((x)&0x00000003)<<8) -#define MCF_DMA_IMCR_SRC21(x) (((x)&0x00000003)<<10) -#define MCF_DMA_IMCR_SRC22(x) (((x)&0x00000003)<<12) -#define MCF_DMA_IMCR_SRC23(x) (((x)&0x00000003)<<14) -#define MCF_DMA_IMCR_SRC24(x) (((x)&0x00000003)<<16) -#define MCF_DMA_IMCR_SRC25(x) (((x)&0x00000003)<<18) -#define MCF_DMA_IMCR_SRC26(x) (((x)&0x00000003)<<20) -#define MCF_DMA_IMCR_SRC27(x) (((x)&0x00000003)<<22) -#define MCF_DMA_IMCR_SRC28(x) (((x)&0x00000003)<<24) -#define MCF_DMA_IMCR_SRC29(x) (((x)&0x00000003)<<26) -#define MCF_DMA_IMCR_SRC30(x) (((x)&0x00000003)<<28) -#define MCF_DMA_IMCR_SRC31(x) (((x)&0x00000003)<<30) -#define MCF_DMA_IMCR_SRC16_FEC0RX (0x00000000) -#define MCF_DMA_IMCR_SRC17_FEC0TX (0x00000000) -#define MCF_DMA_IMCR_SRC18_FEC0RX (0x00000020) -#define MCF_DMA_IMCR_SRC19_FEC0TX (0x00000080) -#define MCF_DMA_IMCR_SRC20_FEC1RX (0x00000100) -#define MCF_DMA_IMCR_SRC21_DREQ1 (0x00000000) -#define MCF_DMA_IMCR_SRC21_FEC1TX (0x00000400) -#define MCF_DMA_IMCR_SRC22_FEC0RX (0x00001000) -#define MCF_DMA_IMCR_SRC23_FEC0TX (0x00004000) -#define MCF_DMA_IMCR_SRC24_CTM0 (0x00010000) -#define MCF_DMA_IMCR_SRC24_FEC1RX (0x00020000) -#define MCF_DMA_IMCR_SRC25_CTM1 (0x00040000) -#define MCF_DMA_IMCR_SRC25_FEC1TX (0x00080000) -#define MCF_DMA_IMCR_SRC26_USBEP4 (0x00000000) -#define MCF_DMA_IMCR_SRC26_CTM2 (0x00200000) -#define MCF_DMA_IMCR_SRC27_USBEP5 (0x00000000) -#define MCF_DMA_IMCR_SRC27_CTM3 (0x00800000) -#define MCF_DMA_IMCR_SRC28_USBEP6 (0x00000000) -#define MCF_DMA_IMCR_SRC28_CTM4 (0x01000000) -#define MCF_DMA_IMCR_SRC28_DREQ1 (0x02000000) -#define MCF_DMA_IMCR_SRC28_PSC2RX (0x03000000) -#define MCF_DMA_IMCR_SRC29_DREQ1 (0x04000000) -#define MCF_DMA_IMCR_SRC29_CTM5 (0x08000000) -#define MCF_DMA_IMCR_SRC29_PSC2TX (0x0C000000) -#define MCF_DMA_IMCR_SRC30_FEC1RX (0x00000000) -#define MCF_DMA_IMCR_SRC30_CTM6 (0x10000000) -#define MCF_DMA_IMCR_SRC30_PSC3RX (0x30000000) -#define MCF_DMA_IMCR_SRC31_FEC1TX (0x00000000) -#define MCF_DMA_IMCR_SRC31_CTM7 (0x80000000) -#define MCF_DMA_IMCR_SRC31_PSC3TX (0xC0000000) - -#endif /* __MCF548X_DMA_H__ */ diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_dma_ereq.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_dma_ereq.h deleted file mode 100644 index 8eac58bfe0..0000000000 --- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_dma_ereq.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * Multi-Channel DMA External Requests (DMA_EREQ) - */ -#ifndef __MCF548X_DMA_EREQ_H__ -#define __MCF548X_DMA_EREQ_H__ - -/* - * Multi-Channel DMA External Requests (DMA_EREQ) - */ - -/* Register read/write macros */ -#define MCF_DMA_EREQ_EREQBAR0 (*(vuint32_t*)(&__MBAR[0x000D00])) -#define MCF_DMA_EREQ_EREQMASK0 (*(vuint32_t*)(&__MBAR[0x000D04])) -#define MCF_DMA_EREQ_EREQCTRL0 (*(vuint32_t*)(&__MBAR[0x000D08])) -#define MCF_DMA_EREQ_EREQBAR1 (*(vuint32_t*)(&__MBAR[0x000D10])) -#define MCF_DMA_EREQ_EREQMASK1 (*(vuint32_t*)(&__MBAR[0x000D14])) -#define MCF_DMA_EREQ_EREQCTRL1 (*(vuint32_t*)(&__MBAR[0x000D18])) -#define MCF_DMA_EREQ_EREQBAR(x) (*(vuint32_t*)(&__MBAR[0x000D00+((x)*0x010)])) -#define MCF_DMA_EREQ_EREQMASK(x) (*(vuint32_t*)(&__MBAR[0x000D04+((x)*0x010)])) -#define MCF_DMA_EREQ_EREQCTRL(x) (*(vuint32_t*)(&__MBAR[0x000D08+((x)*0x010)])) - -/* Bit definitions and macros for MCF_DMA_EREQ_EREQCTRL */ -#define MCF_DMA_EREQ_EREQCTRL_EN (0x00000001) -#define MCF_DMA_EREQ_EREQCTRL_SYNC (0x00000002) -#define MCF_DMA_EREQ_EREQCTRL_DACKWID(x) (((x)&0x00000003)<<2) -#define MCF_DMA_EREQ_EREQCTRL_BSEL(x) (((x)&0x00000003)<<4) -#define MCF_DMA_EREQ_EREQCTRL_MD(x) (((x)&0x00000003)<<6) -#define MCF_DMA_EREQ_EREQCTRL_MD_IDLE (0x00000000) -#define MCF_DMA_EREQ_EREQCTRL_MD_LEVEL (0x00000040) -#define MCF_DMA_EREQ_EREQCTRL_MD_EDGE (0x00000080) -#define MCF_DMA_EREQ_EREQCTRL_MD_PIPED (0x000000C0) -#define MCF_DMA_EREQ_EREQCTRL_BSEL_MEM_WRITE (0x00000000) -#define MCF_DMA_EREQ_EREQCTRL_BSEL_MEM_READ (0x00000010) -#define MCF_DMA_EREQ_EREQCTRL_BSEL_PERIPH_WRITE (0x00000020) -#define MCF_DMA_EREQ_EREQCTRL_BSEL_PERIPH_READ (0x00000030) -#define MCF_DMA_EREQ_EREQCTRL_DACKWID_ONE (0x00000000) -#define MCF_DMA_EREQ_EREQCTRL_DACKWID_TWO (0x00000004) -#define MCF_DMA_EREQ_EREQCTRL_DACKWID_THREE (0x00000008) -#define MCF_DMA_EREQ_EREQCTRL_DACKWID_FOUR (0x0000000C) - -#endif /* __MCF548X_DMA_EREQ_H__ */ diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_dspi.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_dspi.h deleted file mode 100644 index 889e75bc1d..0000000000 --- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_dspi.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * DMA Serial Peripheral Interface (DSPI) - */ -#ifndef __MCF548X_DSPI_H__ -#define __MCF548X_DSPI_H__ - -/* - * DMA Serial Peripheral Interface (DSPI) - */ - -/* Register read/write macros */ -#define MCF_DSPI_DMCR (*(vuint32_t*)(&__MBAR[0x008A00])) -#define MCF_DSPI_DTCR (*(vuint32_t*)(&__MBAR[0x008A08])) -#define MCF_DSPI_DCTAR0 (*(vuint32_t*)(&__MBAR[0x008A0C])) -#define MCF_DSPI_DCTAR1 (*(vuint32_t*)(&__MBAR[0x008A10])) -#define MCF_DSPI_DCTAR2 (*(vuint32_t*)(&__MBAR[0x008A14])) -#define MCF_DSPI_DCTAR3 (*(vuint32_t*)(&__MBAR[0x008A18])) -#define MCF_DSPI_DCTAR4 (*(vuint32_t*)(&__MBAR[0x008A1C])) -#define MCF_DSPI_DCTAR5 (*(vuint32_t*)(&__MBAR[0x008A20])) -#define MCF_DSPI_DCTAR6 (*(vuint32_t*)(&__MBAR[0x008A24])) -#define MCF_DSPI_DCTAR7 (*(vuint32_t*)(&__MBAR[0x008A28])) -#define MCF_DSPI_DCTARn(x) (*(vuint32_t*)(&__MBAR[0x008A0C+((x)*0x004)])) -#define MCF_DSPI_DSR (*(vuint32_t*)(&__MBAR[0x008A2C])) -#define MCF_DSPI_DIRSR (*(vuint32_t*)(&__MBAR[0x008A30])) -#define MCF_DSPI_DTFR (*(vuint32_t*)(&__MBAR[0x008A34])) -#define MCF_DSPI_DRFR (*(vuint32_t*)(&__MBAR[0x008A38])) -#define MCF_DSPI_DTFDR0 (*(vuint32_t*)(&__MBAR[0x008A3C])) -#define MCF_DSPI_DTFDR1 (*(vuint32_t*)(&__MBAR[0x008A40])) -#define MCF_DSPI_DTFDR2 (*(vuint32_t*)(&__MBAR[0x008A44])) -#define MCF_DSPI_DTFDR3 (*(vuint32_t*)(&__MBAR[0x008A48])) -#define MCF_DSPI_DTFDRn(x) (*(vuint32_t*)(&__MBAR[0x008A3C+((x)*0x004)])) -#define MCF_DSPI_DRFDR0 (*(vuint32_t*)(&__MBAR[0x008A7C])) -#define MCF_DSPI_DRFDR1 (*(vuint32_t*)(&__MBAR[0x008A80])) -#define MCF_DSPI_DRFDR2 (*(vuint32_t*)(&__MBAR[0x008A84])) -#define MCF_DSPI_DRFDR3 (*(vuint32_t*)(&__MBAR[0x008A88])) -#define MCF_DSPI_DRFDRn(x) (*(vuint32_t*)(&__MBAR[0x008A7C+((x)*0x004)])) - -/* Bit definitions and macros for MCF_DSPI_DMCR */ -#define MCF_DSPI_DMCR_HALT (0x00000001) -#define MCF_DSPI_DMCR_SMPL_PT(x) (((x)&0x00000003)<<8) -#define MCF_DSPI_DMCR_CRXF (0x00000400) -#define MCF_DSPI_DMCR_CTXF (0x00000800) -#define MCF_DSPI_DMCR_DRXF (0x00001000) -#define MCF_DSPI_DMCR_DTXF (0x00002000) -#define MCF_DSPI_DMCR_CSIS0 (0x00010000) -#define MCF_DSPI_DMCR_CSIS2 (0x00040000) -#define MCF_DSPI_DMCR_CSIS3 (0x00080000) -#define MCF_DSPI_DMCR_CSIS5 (0x00200000) -#define MCF_DSPI_DMCR_ROOE (0x01000000) -#define MCF_DSPI_DMCR_PCSSE (0x02000000) -#define MCF_DSPI_DMCR_MTFE (0x04000000) -#define MCF_DSPI_DMCR_FRZ (0x08000000) -#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28) -#define MCF_DSPI_DMCR_CSCK (0x40000000) -#define MCF_DSPI_DMCR_MSTR (0x80000000) - -/* Bit definitions and macros for MCF_DSPI_DTCR */ -#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_DSPI_DCTARn */ -#define MCF_DSPI_DCTARn_BR(x) (((x)&0x0000000F)<<0) -#define MCF_DSPI_DCTARn_DT(x) (((x)&0x0000000F)<<4) -#define MCF_DSPI_DCTARn_ASC(x) (((x)&0x0000000F)<<8) -#define MCF_DSPI_DCTARn_CSSCK(x) (((x)&0x0000000F)<<12) -#define MCF_DSPI_DCTARn_PBR(x) (((x)&0x00000003)<<16) -#define MCF_DSPI_DCTARn_PDT(x) (((x)&0x00000003)<<18) -#define MCF_DSPI_DCTARn_PASC(x) (((x)&0x00000003)<<20) -#define MCF_DSPI_DCTARn_PCSSCK(x) (((x)&0x00000003)<<22) -#define MCF_DSPI_DCTARn_LSBFE (0x01000000) -#define MCF_DSPI_DCTARn_CPHA (0x02000000) -#define MCF_DSPI_DCTARn_CPOL (0x04000000) -#define MCF_DSPI_DCTARn_TRSZ(x) (((x)&0x0000000F)<<27) -#define MCF_DSPI_DCTARn_PCSSCK_1CLK (0x00000000) -#define MCF_DSPI_DCTARn_PCSSCK_3CLK (0x00400000) -#define MCF_DSPI_DCTARn_PCSSCK_5CLK (0x00800000) -#define MCF_DSPI_DCTARn_PCSSCK_7CLK (0x00A00000) -#define MCF_DSPI_DCTARn_PASC_1CLK (0x00000000) -#define MCF_DSPI_DCTARn_PASC_3CLK (0x00100000) -#define MCF_DSPI_DCTARn_PASC_5CLK (0x00200000) -#define MCF_DSPI_DCTARn_PASC_7CLK (0x00300000) -#define MCF_DSPI_DCTARn_PDT_1CLK (0x00000000) -#define MCF_DSPI_DCTARn_PDT_3CLK (0x00040000) -#define MCF_DSPI_DCTARn_PDT_5CLK (0x00080000) -#define MCF_DSPI_DCTARn_PDT_7CLK (0x000A0000) -#define MCF_DSPI_DCTARn_PBR_1CLK (0x00000000) -#define MCF_DSPI_DCTARn_PBR_3CLK (0x00010000) -#define MCF_DSPI_DCTARn_PBR_5CLK (0x00020000) -#define MCF_DSPI_DCTARn_PBR_7CLK (0x00030000) - -/* Bit definitions and macros for MCF_DSPI_DSR */ -#define MCF_DSPI_DSR_RXPTR(x) (((x)&0x0000000F)<<0) -#define MCF_DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4) -#define MCF_DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8) -#define MCF_DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12) -#define MCF_DSPI_DSR_RFDF (0x00020000) -#define MCF_DSPI_DSR_RFOF (0x00080000) -#define MCF_DSPI_DSR_TFFF (0x02000000) -#define MCF_DSPI_DSR_TFUF (0x08000000) -#define MCF_DSPI_DSR_EOQF (0x10000000) -#define MCF_DSPI_DSR_TXRXS (0x40000000) -#define MCF_DSPI_DSR_TCF (0x80000000) - -/* Bit definitions and macros for MCF_DSPI_DIRSR */ -#define MCF_DSPI_DIRSR_RFDFS (0x00010000) -#define MCF_DSPI_DIRSR_RFDFE (0x00020000) -#define MCF_DSPI_DIRSR_RFOFE (0x00080000) -#define MCF_DSPI_DIRSR_TFFFS (0x01000000) -#define MCF_DSPI_DIRSR_TFFFE (0x02000000) -#define MCF_DSPI_DIRSR_TFUFE (0x08000000) -#define MCF_DSPI_DIRSR_EOQFE (0x10000000) -#define MCF_DSPI_DIRSR_TCFE (0x80000000) - -/* Bit definitions and macros for MCF_DSPI_DTFR */ -#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF)<<0) -#define MCF_DSPI_DTFR_CS0 (0x00010000) -#define MCF_DSPI_DTFR_CS2 (0x00040000) -#define MCF_DSPI_DTFR_CS3 (0x00080000) -#define MCF_DSPI_DTFR_CS5 (0x00200000) -#define MCF_DSPI_DTFR_CTCNT (0x04000000) -#define MCF_DSPI_DTFR_EOQ (0x08000000) -#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28) -#define MCF_DSPI_DTFR_CONT (0x80000000) - -/* Bit definitions and macros for MCF_DSPI_DRFR */ -#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF)<<0) - -/* Bit definitions and macros for MCF_DSPI_DTFDRn */ -#define MCF_DSPI_DTFDRn_TXDATA(x) (((x)&0x0000FFFF)<<0) -#define MCF_DSPI_DTFDRn_TXCMD(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_DSPI_DRFDRn */ -#define MCF_DSPI_DRFDRn_RXDATA(x) (((x)&0x0000FFFF)<<0) - -#endif /* __MCF548X_DSPI_H__ */ diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_eport.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_eport.h deleted file mode 100644 index 94f724fa28..0000000000 --- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_eport.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * Edge Port Module (EPORT) - */ -#ifndef __MCF548X_EPORT_H__ -#define __MCF548X_EPORT_H__ - -/* - * Edge Port Module (EPORT) - */ - -/* Register read/write macros */ -#define MCF_EPORT_EPPAR (*(vuint16_t*)(&__MBAR[0x000F00])) -#define MCF_EPORT_EPDDR (*(vuint8_t *)(&__MBAR[0x000F04])) -#define MCF_EPORT_EPIER (*(vuint8_t *)(&__MBAR[0x000F05])) -#define MCF_EPORT_EPDR (*(vuint8_t *)(&__MBAR[0x000F08])) -#define MCF_EPORT_EPPDR (*(vuint8_t *)(&__MBAR[0x000F09])) -#define MCF_EPORT_EPFR (*(vuint8_t *)(&__MBAR[0x000F0C])) - -/* Bit definitions and macros for MCF_EPORT_EPPAR */ -#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) -#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4) -#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6) -#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8) -#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10) -#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12) -#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14) -#define MCF_EPORT_EPPAR_EPPAx_LEVEL (0) -#define MCF_EPORT_EPPAR_EPPAx_RISING (1) -#define MCF_EPORT_EPPAR_EPPAx_FALLING (2) -#define MCF_EPORT_EPPAR_EPPAx_BOTH (3) - -/* Bit definitions and macros for MCF_EPORT_EPDDR */ -#define MCF_EPORT_EPDDR_EPDD1 (0x02) -#define MCF_EPORT_EPDDR_EPDD2 (0x04) -#define MCF_EPORT_EPDDR_EPDD3 (0x08) -#define MCF_EPORT_EPDDR_EPDD4 (0x10) -#define MCF_EPORT_EPDDR_EPDD5 (0x20) -#define MCF_EPORT_EPDDR_EPDD6 (0x40) -#define MCF_EPORT_EPDDR_EPDD7 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPIER */ -#define MCF_EPORT_EPIER_EPIE1 (0x02) -#define MCF_EPORT_EPIER_EPIE2 (0x04) -#define MCF_EPORT_EPIER_EPIE3 (0x08) -#define MCF_EPORT_EPIER_EPIE4 (0x10) -#define MCF_EPORT_EPIER_EPIE5 (0x20) -#define MCF_EPORT_EPIER_EPIE6 (0x40) -#define MCF_EPORT_EPIER_EPIE7 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPDR */ -#define MCF_EPORT_EPDR_EPD1 (0x02) -#define MCF_EPORT_EPDR_EPD2 (0x04) -#define MCF_EPORT_EPDR_EPD3 (0x08) -#define MCF_EPORT_EPDR_EPD4 (0x10) -#define MCF_EPORT_EPDR_EPD5 (0x20) -#define MCF_EPORT_EPDR_EPD6 (0x40) -#define MCF_EPORT_EPDR_EPD7 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPPDR */ -#define MCF_EPORT_EPPDR_EPPD1 (0x02) -#define MCF_EPORT_EPPDR_EPPD2 (0x04) -#define MCF_EPORT_EPPDR_EPPD3 (0x08) -#define MCF_EPORT_EPPDR_EPPD4 (0x10) -#define MCF_EPORT_EPPDR_EPPD5 (0x20) -#define MCF_EPORT_EPPDR_EPPD6 (0x40) -#define MCF_EPORT_EPPDR_EPPD7 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPFR */ -#define MCF_EPORT_EPFR_EPF1 (0x02) -#define MCF_EPORT_EPFR_EPF2 (0x04) -#define MCF_EPORT_EPFR_EPF3 (0x08) -#define MCF_EPORT_EPFR_EPF4 (0x10) -#define MCF_EPORT_EPFR_EPF5 (0x20) -#define MCF_EPORT_EPFR_EPF6 (0x40) -#define MCF_EPORT_EPFR_EPF7 (0x80) - -#endif /* __MCF548X_EPORT_H__ */ diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_fbcs.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_fbcs.h deleted file mode 100644 index 1e11944c46..0000000000 --- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_fbcs.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * FlexBus Chip Selects (FBCS) - */ -#ifndef __MCF548X_FBCS_H__ -#define __MCF548X_FBCS_H__ - -/* - * FlexBus Chip Selects (FBCS) - */ - -/* Register read/write macros */ -#define MCF_FBCS_CSAR0 (*(vuint32_t*)(&__MBAR[0x000500])) -#define MCF_FBCS_CSMR0 (*(vuint32_t*)(&__MBAR[0x000504])) -#define MCF_FBCS_CSCR0 (*(vuint32_t*)(&__MBAR[0x000508])) -#define MCF_FBCS_CSAR1 (*(vuint32_t*)(&__MBAR[0x00050C])) -#define MCF_FBCS_CSMR1 (*(vuint32_t*)(&__MBAR[0x000510])) -#define MCF_FBCS_CSCR1 (*(vuint32_t*)(&__MBAR[0x000514])) -#define MCF_FBCS_CSAR2 (*(vuint32_t*)(&__MBAR[0x000518])) -#define MCF_FBCS_CSMR2 (*(vuint32_t*)(&__MBAR[0x00051C])) -#define MCF_FBCS_CSCR2 (*(vuint32_t*)(&__MBAR[0x000520])) -#define MCF_FBCS_CSAR3 (*(vuint32_t*)(&__MBAR[0x000524])) -#define MCF_FBCS_CSMR3 (*(vuint32_t*)(&__MBAR[0x000528])) -#define MCF_FBCS_CSCR3 (*(vuint32_t*)(&__MBAR[0x00052C])) -#define MCF_FBCS_CSAR4 (*(vuint32_t*)(&__MBAR[0x000530])) -#define MCF_FBCS_CSMR4 (*(vuint32_t*)(&__MBAR[0x000534])) -#define MCF_FBCS_CSCR4 (*(vuint32_t*)(&__MBAR[0x000538])) -#define MCF_FBCS_CSAR5 (*(vuint32_t*)(&__MBAR[0x00053C])) -#define MCF_FBCS_CSMR5 (*(vuint32_t*)(&__MBAR[0x000540])) -#define MCF_FBCS_CSCR5 (*(vuint32_t*)(&__MBAR[0x000544])) -#define MCF_FBCS_CSAR(x) (*(vuint32_t*)(&__MBAR[0x000500+((x)*0x00C)])) -#define MCF_FBCS_CSMR(x) (*(vuint32_t*)(&__MBAR[0x000504+((x)*0x00C)])) -#define MCF_FBCS_CSCR(x) (*(vuint32_t*)(&__MBAR[0x000508+((x)*0x00C)])) - -/* Bit definitions and macros for MCF_FBCS_CSAR */ -#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000) - -/* Bit definitions and macros for MCF_FBCS_CSMR */ -#define MCF_FBCS_CSMR_V (0x00000001) -#define MCF_FBCS_CSMR_WP (0x00000100) -#define MCF_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) -#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000) -#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000) -#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000) -#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000) -#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000) -#define MCF_FBCS_CSMR_BAM_256M (0x0FFF0000) -#define MCF_FBCS_CSMR_BAM_128M (0x07FF0000) -#define MCF_FBCS_CSMR_BAM_64M (0x03FF0000) -#define MCF_FBCS_CSMR_BAM_32M (0x01FF0000) -#define MCF_FBCS_CSMR_BAM_16M (0x00FF0000) -#define MCF_FBCS_CSMR_BAM_8M (0x007F0000) -#define MCF_FBCS_CSMR_BAM_4M (0x003F0000) -#define MCF_FBCS_CSMR_BAM_2M (0x001F0000) -#define MCF_FBCS_CSMR_BAM_1M (0x000F0000) -#define MCF_FBCS_CSMR_BAM_1024K (0x000F0000) -#define MCF_FBCS_CSMR_BAM_512K (0x00070000) -#define MCF_FBCS_CSMR_BAM_256K (0x00030000) -#define MCF_FBCS_CSMR_BAM_128K (0x00010000) -#define MCF_FBCS_CSMR_BAM_64K (0x00000000) - -/* Bit definitions and macros for MCF_FBCS_CSCR */ -#define MCF_FBCS_CSCR_BSTW (0x00000008) -#define MCF_FBCS_CSCR_BSTR (0x00000010) -#define MCF_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) -#define MCF_FBCS_CSCR_AA (0x00000100) -#define MCF_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) -#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) -#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) -#define MCF_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) -#define MCF_FBCS_CSCR_SWSEN (0x00800000) -#define MCF_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) -#define MCF_FBCS_CSCR_PS_8 (0x0040) -#define MCF_FBCS_CSCR_PS_16 (0x0080) -#define MCF_FBCS_CSCR_PS_32 (0x0000) - -#endif /* __MCF548X_FBCS_H__ */ diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_fec.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_fec.h deleted file mode 100644 index 738abd80a7..0000000000 --- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_fec.h +++ /dev/null @@ -1,623 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * Fast Ethernet Controller (FEC) - */ -#ifndef __MCF548X_FEC_H__ -#define __MCF548X_FEC_H__ - -/* - * Fast Ethernet Controller (FEC) - */ - -/* Register read/write macros */ -#define MCF_FEC_EIR0 (*(vuint32_t*)(&__MBAR[0x009004])) -#define MCF_FEC_EIMR0 (*(vuint32_t*)(&__MBAR[0x009008])) -#define MCF_FEC_ECR0 (*(vuint32_t*)(&__MBAR[0x009024])) -#define MCF_FEC_MMFR0 (*(vuint32_t*)(&__MBAR[0x009040])) -#define MCF_FEC_MSCR0 (*(vuint32_t*)(&__MBAR[0x009044])) -#define MCF_FEC_MIBC0 (*(vuint32_t*)(&__MBAR[0x009064])) -#define MCF_FEC_RCR0 (*(vuint32_t*)(&__MBAR[0x009084])) -#define MCF_FEC_R_HASH0 (*(vuint32_t*)(&__MBAR[0x009088])) -#define MCF_FEC_TCR0 (*(vuint32_t*)(&__MBAR[0x0090C4])) -#define MCF_FEC_PALR0 (*(vuint32_t*)(&__MBAR[0x0090E4])) -#define MCF_FEC_PAUR0 (*(vuint32_t*)(&__MBAR[0x0090E8])) -#define MCF_FEC_OPD0 (*(vuint32_t*)(&__MBAR[0x0090EC])) -#define MCF_FEC_IAUR0 (*(vuint32_t*)(&__MBAR[0x009118])) -#define MCF_FEC_IALR0 (*(vuint32_t*)(&__MBAR[0x00911C])) -#define MCF_FEC_GAUR0 (*(vuint32_t*)(&__MBAR[0x009120])) -#define MCF_FEC_GALR0 (*(vuint32_t*)(&__MBAR[0x009124])) -#define MCF_FEC_FECTFWR0 (*(vuint32_t*)(&__MBAR[0x009144])) -#define MCF_FEC_FECRFDR0 (*(vuint32_t*)(&__MBAR[0x009184])) -#define MCF_FEC_FECRFSR0 (*(vuint32_t*)(&__MBAR[0x009188])) -#define MCF_FEC_FECRFCR0 (*(vuint32_t*)(&__MBAR[0x00918C])) -#define MCF_FEC_FECRLRFP0 (*(vuint32_t*)(&__MBAR[0x009190])) -#define MCF_FEC_FECRLWFP0 (*(vuint32_t*)(&__MBAR[0x009194])) -#define MCF_FEC_FECRFAR0 (*(vuint32_t*)(&__MBAR[0x009198])) -#define MCF_FEC_FECRFRP0 (*(vuint32_t*)(&__MBAR[0x00919C])) -#define MCF_FEC_FECRFWP0 (*(vuint32_t*)(&__MBAR[0x0091A0])) -#define MCF_FEC_FECTFDR0 (*(vuint32_t*)(&__MBAR[0x0091A4])) -#define MCF_FEC_FECTFSR0 (*(vuint32_t*)(&__MBAR[0x0091A8])) -#define MCF_FEC_FECTFCR0 (*(vuint32_t*)(&__MBAR[0x0091AC])) -#define MCF_FEC_FECTLRFP0 (*(vuint32_t*)(&__MBAR[0x0091B0])) -#define MCF_FEC_FECTLWFP0 (*(vuint32_t*)(&__MBAR[0x0091B4])) -#define MCF_FEC_FECTFAR0 (*(vuint32_t*)(&__MBAR[0x0091B8])) -#define MCF_FEC_FECTFRP0 (*(vuint32_t*)(&__MBAR[0x0091BC])) -#define MCF_FEC_FECTFWP0 (*(vuint32_t*)(&__MBAR[0x0091C0])) -#define MCF_FEC_FRST0 (*(vuint32_t*)(&__MBAR[0x0091C4])) -#define MCF_FEC_CTCWR0 (*(vuint32_t*)(&__MBAR[0x0091C8])) -#define MCF_FEC_RMON_T_DROP0 (*(vuint32_t*)(&__MBAR[0x009200])) -#define MCF_FEC_RMON_T_PACKETS0 (*(vuint32_t*)(&__MBAR[0x009204])) -#define MCF_FEC_RMON_T_BC_PKT0 (*(vuint32_t*)(&__MBAR[0x009208])) -#define MCF_FEC_RMON_T_MC_PKT0 (*(vuint32_t*)(&__MBAR[0x00920C])) -#define MCF_FEC_RMON_T_CRC_ALIGN0 (*(vuint32_t*)(&__MBAR[0x009210])) -#define MCF_FEC_RMON_T_UNDERSIZE0 (*(vuint32_t*)(&__MBAR[0x009214])) -#define MCF_FEC_RMON_T_OVERSIZE0 (*(vuint32_t*)(&__MBAR[0x009218])) -#define MCF_FEC_RMON_T_FRAG0 (*(vuint32_t*)(&__MBAR[0x00921C])) -#define MCF_FEC_RMON_T_JAB0 (*(vuint32_t*)(&__MBAR[0x009220])) -#define MCF_FEC_RMON_T_COL0 (*(vuint32_t*)(&__MBAR[0x009224])) -#define MCF_FEC_RMON_T_P640 (*(vuint32_t*)(&__MBAR[0x009228])) -#define MCF_FEC_RMON_T_P65TO1270 (*(vuint32_t*)(&__MBAR[0x00922C])) -#define MCF_FEC_RMON_T_P128TO2550 (*(vuint32_t*)(&__MBAR[0x009230])) -#define MCF_FEC_RMON_T_P256TO5110 (*(vuint32_t*)(&__MBAR[0x009234])) -#define MCF_FEC_RMON_T_P512TO10230 (*(vuint32_t*)(&__MBAR[0x009238])) -#define MCF_FEC_RMON_T_P1024TO20470 (*(vuint32_t*)(&__MBAR[0x00923C])) -#define MCF_FEC_RMON_T_P_GTE20480 (*(vuint32_t*)(&__MBAR[0x009240])) -#define MCF_FEC_RMON_T_OCTETS0 (*(vuint32_t*)(&__MBAR[0x009244])) -#define MCF_FEC_IEEE_T_DROP0 (*(vuint32_t*)(&__MBAR[0x009248])) -#define MCF_FEC_IEEE_T_FRAME_OK0 (*(vuint32_t*)(&__MBAR[0x00924C])) -#define MCF_FEC_IEEE_T_1COL0 (*(vuint32_t*)(&__MBAR[0x009250])) -#define MCF_FEC_IEEE_T_MCOL0 (*(vuint32_t*)(&__MBAR[0x009254])) -#define MCF_FEC_IEEE_T_DEF0 (*(vuint32_t*)(&__MBAR[0x009258])) -#define MCF_FEC_IEEE_T_LCOL0 (*(vuint32_t*)(&__MBAR[0x00925C])) -#define MCF_FEC_IEEE_T_EXCOL0 (*(vuint32_t*)(&__MBAR[0x009260])) -#define MCF_FEC_IEEE_T_MACERR0 (*(vuint32_t*)(&__MBAR[0x009264])) -#define MCF_FEC_IEEE_T_CSERR0 (*(vuint32_t*)(&__MBAR[0x009268])) -#define MCF_FEC_IEEE_T_SQE0 (*(vuint32_t*)(&__MBAR[0x00926C])) -#define MCF_FEC_IEEE_T_FDXFC0 (*(vuint32_t*)(&__MBAR[0x009270])) -#define MCF_FEC_IEEE_T_OCTETS_OK0 (*(vuint32_t*)(&__MBAR[0x009274])) -#define MCF_FEC_RMON_R_DROP0 (*(vuint32_t*)(&__MBAR[0x009280])) -#define MCF_FEC_RMON_R_PACKETS0 (*(vuint32_t*)(&__MBAR[0x009284])) -#define MCF_FEC_RMON_R_BC_PKT0 (*(vuint32_t*)(&__MBAR[0x009288])) -#define MCF_FEC_RMON_R_MC_PKT0 (*(vuint32_t*)(&__MBAR[0x00928C])) -#define MCF_FEC_RMON_R_CRC_ALIGN0 (*(vuint32_t*)(&__MBAR[0x009290])) -#define MCF_FEC_RMON_R_UNDERSIZE0 (*(vuint32_t*)(&__MBAR[0x009294])) -#define MCF_FEC_RMON_R_OVERSIZE0 (*(vuint32_t*)(&__MBAR[0x009298])) -#define MCF_FEC_RMON_R_FRAG0 (*(vuint32_t*)(&__MBAR[0x00929C])) -#define MCF_FEC_RMON_R_JAB0 (*(vuint32_t*)(&__MBAR[0x0092A0])) -#define MCF_FEC_RMON_R_RESVD_00 (*(vuint32_t*)(&__MBAR[0x0092A4])) -#define MCF_FEC_RMON_R_P640 (*(vuint32_t*)(&__MBAR[0x0092A8])) -#define MCF_FEC_RMON_R_P65TO1270 (*(vuint32_t*)(&__MBAR[0x0092AC])) -#define MCF_FEC_RMON_R_P128TO2550 (*(vuint32_t*)(&__MBAR[0x0092B0])) -#define MCF_FEC_RMON_R_P256TO5110 (*(vuint32_t*)(&__MBAR[0x0092B4])) -#define MCF_FEC_RMON_R_512TO10230 (*(vuint32_t*)(&__MBAR[0x0092B8])) -#define MCF_FEC_RMON_R_1024TO20470 (*(vuint32_t*)(&__MBAR[0x0092BC])) -#define MCF_FEC_RMON_R_P_GTE20480 (*(vuint32_t*)(&__MBAR[0x0092C0])) -#define MCF_FEC_RMON_R_OCTETS0 (*(vuint32_t*)(&__MBAR[0x0092C4])) -#define MCF_FEC_IEEE_R_DROP0 (*(vuint32_t*)(&__MBAR[0x0092C8])) -#define MCF_FEC_IEEE_R_FRAME_OK0 (*(vuint32_t*)(&__MBAR[0x0092CC])) -#define MCF_FEC_IEEE_R_CRC0 (*(vuint32_t*)(&__MBAR[0x0092D0])) -#define MCF_FEC_IEEE_R_ALIGN0 (*(vuint32_t*)(&__MBAR[0x0092D4])) -#define MCF_FEC_IEEE_R_MACERR0 (*(vuint32_t*)(&__MBAR[0x0092D8])) -#define MCF_FEC_IEEE_R_FDXFC0 (*(vuint32_t*)(&__MBAR[0x0092DC])) -#define MCF_FEC_IEEE_R_OCTETS_OK0 (*(vuint32_t*)(&__MBAR[0x0092E0])) -#define MCF_FEC_EIR1 (*(vuint32_t*)(&__MBAR[0x009804])) -#define MCF_FEC_EIMR1 (*(vuint32_t*)(&__MBAR[0x009808])) -#define MCF_FEC_ECR1 (*(vuint32_t*)(&__MBAR[0x009824])) -#define MCF_FEC_MMFR1 (*(vuint32_t*)(&__MBAR[0x009840])) -#define MCF_FEC_MSCR1 (*(vuint32_t*)(&__MBAR[0x009844])) -#define MCF_FEC_MIBC1 (*(vuint32_t*)(&__MBAR[0x009864])) -#define MCF_FEC_RCR1 (*(vuint32_t*)(&__MBAR[0x009884])) -#define MCF_FEC_R_HASH1 (*(vuint32_t*)(&__MBAR[0x009888])) -#define MCF_FEC_TCR1 (*(vuint32_t*)(&__MBAR[0x0098C4])) -#define MCF_FEC_PALR1 (*(vuint32_t*)(&__MBAR[0x0098E4])) -#define MCF_FEC_PAUR1 (*(vuint32_t*)(&__MBAR[0x0098E8])) -#define MCF_FEC_OPD1 (*(vuint32_t*)(&__MBAR[0x0098EC])) -#define MCF_FEC_IAUR1 (*(vuint32_t*)(&__MBAR[0x009918])) -#define MCF_FEC_IALR1 (*(vuint32_t*)(&__MBAR[0x00991C])) -#define MCF_FEC_GAUR1 (*(vuint32_t*)(&__MBAR[0x009920])) -#define MCF_FEC_GALR1 (*(vuint32_t*)(&__MBAR[0x009924])) -#define MCF_FEC_FECTFWR1 (*(vuint32_t*)(&__MBAR[0x009944])) -#define MCF_FEC_FECRFDR1 (*(vuint32_t*)(&__MBAR[0x009984])) -#define MCF_FEC_FECRFSR1 (*(vuint32_t*)(&__MBAR[0x009988])) -#define MCF_FEC_FECRFCR1 (*(vuint32_t*)(&__MBAR[0x00998C])) -#define MCF_FEC_FECRLRFP1 (*(vuint32_t*)(&__MBAR[0x009990])) -#define MCF_FEC_FECRLWFP1 (*(vuint32_t*)(&__MBAR[0x009994])) -#define MCF_FEC_FECRFAR1 (*(vuint32_t*)(&__MBAR[0x009998])) -#define MCF_FEC_FECRFRP1 (*(vuint32_t*)(&__MBAR[0x00999C])) -#define MCF_FEC_FECRFWP1 (*(vuint32_t*)(&__MBAR[0x0099A0])) -#define MCF_FEC_FECTFDR1 (*(vuint32_t*)(&__MBAR[0x0099A4])) -#define MCF_FEC_FECTFSR1 (*(vuint32_t*)(&__MBAR[0x0099A8])) -#define MCF_FEC_FECTFCR1 (*(vuint32_t*)(&__MBAR[0x0099AC])) -#define MCF_FEC_FECTLRFP1 (*(vuint32_t*)(&__MBAR[0x0099B0])) -#define MCF_FEC_FECTLWFP1 (*(vuint32_t*)(&__MBAR[0x0099B4])) -#define MCF_FEC_FECTFAR1 (*(vuint32_t*)(&__MBAR[0x0099B8])) -#define MCF_FEC_FECTFRP1 (*(vuint32_t*)(&__MBAR[0x0099BC])) -#define MCF_FEC_FECTFWP1 (*(vuint32_t*)(&__MBAR[0x0099C0])) -#define MCF_FEC_FRST1 (*(vuint32_t*)(&__MBAR[0x0099C4])) -#define MCF_FEC_CTCWR1 (*(vuint32_t*)(&__MBAR[0x0099C8])) -#define MCF_FEC_RMON_T_DROP1 (*(vuint32_t*)(&__MBAR[0x009A00])) -#define MCF_FEC_RMON_T_PACKETS1 (*(vuint32_t*)(&__MBAR[0x009A04])) -#define MCF_FEC_RMON_T_BC_PKT1 (*(vuint32_t*)(&__MBAR[0x009A08])) -#define MCF_FEC_RMON_T_MC_PKT1 (*(vuint32_t*)(&__MBAR[0x009A0C])) -#define MCF_FEC_RMON_T_CRC_ALIGN1 (*(vuint32_t*)(&__MBAR[0x009A10])) -#define MCF_FEC_RMON_T_UNDERSIZE1 (*(vuint32_t*)(&__MBAR[0x009A14])) -#define MCF_FEC_RMON_T_OVERSIZE1 (*(vuint32_t*)(&__MBAR[0x009A18])) -#define MCF_FEC_RMON_T_FRAG1 (*(vuint32_t*)(&__MBAR[0x009A1C])) -#define MCF_FEC_RMON_T_JAB1 (*(vuint32_t*)(&__MBAR[0x009A20])) -#define MCF_FEC_RMON_T_COL1 (*(vuint32_t*)(&__MBAR[0x009A24])) -#define MCF_FEC_RMON_T_P641 (*(vuint32_t*)(&__MBAR[0x009A28])) -#define MCF_FEC_RMON_T_P65TO1271 (*(vuint32_t*)(&__MBAR[0x009A2C])) -#define MCF_FEC_RMON_T_P128TO2551 (*(vuint32_t*)(&__MBAR[0x009A30])) -#define MCF_FEC_RMON_T_P256TO5111 (*(vuint32_t*)(&__MBAR[0x009A34])) -#define MCF_FEC_RMON_T_P512TO10231 (*(vuint32_t*)(&__MBAR[0x009A38])) -#define MCF_FEC_RMON_T_P1024TO20471 (*(vuint32_t*)(&__MBAR[0x009A3C])) -#define MCF_FEC_RMON_T_P_GTE20481 (*(vuint32_t*)(&__MBAR[0x009A40])) -#define MCF_FEC_RMON_T_OCTETS1 (*(vuint32_t*)(&__MBAR[0x009A44])) -#define MCF_FEC_IEEE_T_DROP1 (*(vuint32_t*)(&__MBAR[0x009A48])) -#define MCF_FEC_IEEE_T_FRAME_OK1 (*(vuint32_t*)(&__MBAR[0x009A4C])) -#define MCF_FEC_IEEE_T_1COL1 (*(vuint32_t*)(&__MBAR[0x009A50])) -#define MCF_FEC_IEEE_T_MCOL1 (*(vuint32_t*)(&__MBAR[0x009A54])) -#define MCF_FEC_IEEE_T_DEF1 (*(vuint32_t*)(&__MBAR[0x009A58])) -#define MCF_FEC_IEEE_T_LCOL1 (*(vuint32_t*)(&__MBAR[0x009A5C])) -#define MCF_FEC_IEEE_T_EXCOL1 (*(vuint32_t*)(&__MBAR[0x009A60])) -#define MCF_FEC_IEEE_T_MACERR1 (*(vuint32_t*)(&__MBAR[0x009A64])) -#define MCF_FEC_IEEE_T_CSERR1 (*(vuint32_t*)(&__MBAR[0x009A68])) -#define MCF_FEC_IEEE_T_SQE1 (*(vuint32_t*)(&__MBAR[0x009A6C])) -#define MCF_FEC_IEEE_T_FDXFC1 (*(vuint32_t*)(&__MBAR[0x009A70])) -#define MCF_FEC_IEEE_T_OCTETS_OK1 (*(vuint32_t*)(&__MBAR[0x009A74])) -#define MCF_FEC_RMON_R_DROP1 (*(vuint32_t*)(&__MBAR[0x009A80])) -#define MCF_FEC_RMON_R_PACKETS1 (*(vuint32_t*)(&__MBAR[0x009A84])) -#define MCF_FEC_RMON_R_BC_PKT1 (*(vuint32_t*)(&__MBAR[0x009A88])) -#define MCF_FEC_RMON_R_MC_PKT1 (*(vuint32_t*)(&__MBAR[0x009A8C])) -#define MCF_FEC_RMON_R_CRC_ALIGN1 (*(vuint32_t*)(&__MBAR[0x009A90])) -#define MCF_FEC_RMON_R_UNDERSIZE1 (*(vuint32_t*)(&__MBAR[0x009A94])) -#define MCF_FEC_RMON_R_OVERSIZE1 (*(vuint32_t*)(&__MBAR[0x009A98])) -#define MCF_FEC_RMON_R_FRAG1 (*(vuint32_t*)(&__MBAR[0x009A9C])) -#define MCF_FEC_RMON_R_JAB1 (*(vuint32_t*)(&__MBAR[0x009AA0])) -#define MCF_FEC_RMON_R_RESVD_01 (*(vuint32_t*)(&__MBAR[0x009AA4])) -#define MCF_FEC_RMON_R_P641 (*(vuint32_t*)(&__MBAR[0x009AA8])) -#define MCF_FEC_RMON_R_P65TO1271 (*(vuint32_t*)(&__MBAR[0x009AAC])) -#define MCF_FEC_RMON_R_P128TO2551 (*(vuint32_t*)(&__MBAR[0x009AB0])) -#define MCF_FEC_RMON_R_P256TO5111 (*(vuint32_t*)(&__MBAR[0x009AB4])) -#define MCF_FEC_RMON_R_512TO10231 (*(vuint32_t*)(&__MBAR[0x009AB8])) -#define MCF_FEC_RMON_R_1024TO20471 (*(vuint32_t*)(&__MBAR[0x009ABC])) -#define MCF_FEC_RMON_R_P_GTE20481 (*(vuint32_t*)(&__MBAR[0x009AC0])) -#define MCF_FEC_RMON_R_OCTETS1 (*(vuint32_t*)(&__MBAR[0x009AC4])) -#define MCF_FEC_IEEE_R_DROP1 (*(vuint32_t*)(&__MBAR[0x009AC8])) -#define MCF_FEC_IEEE_R_FRAME_OK1 (*(vuint32_t*)(&__MBAR[0x009ACC])) -#define MCF_FEC_IEEE_R_CRC1 (*(vuint32_t*)(&__MBAR[0x009AD0])) -#define MCF_FEC_IEEE_R_ALIGN1 (*(vuint32_t*)(&__MBAR[0x009AD4])) -#define MCF_FEC_IEEE_R_MACERR1 (*(vuint32_t*)(&__MBAR[0x009AD8])) -#define MCF_FEC_IEEE_R_FDXFC1 (*(vuint32_t*)(&__MBAR[0x009ADC])) -#define MCF_FEC_IEEE_R_OCTETS_OK1 (*(vuint32_t*)(&__MBAR[0x009AE0])) -#define MCF_FEC_EIR(x) (*(vuint32_t*)(&__MBAR[0x009004+((x)*0x800)])) -#define MCF_FEC_EIMR(x) (*(vuint32_t*)(&__MBAR[0x009008+((x)*0x800)])) -#define MCF_FEC_ECR(x) (*(vuint32_t*)(&__MBAR[0x009024+((x)*0x800)])) -#define MCF_FEC_MMFR(x) (*(vuint32_t*)(&__MBAR[0x009040+((x)*0x800)])) -#define MCF_FEC_MSCR(x) (*(vuint32_t*)(&__MBAR[0x009044+((x)*0x800)])) -#define MCF_FEC_MIBC(x) (*(vuint32_t*)(&__MBAR[0x009064+((x)*0x800)])) -#define MCF_FEC_RCR(x) (*(vuint32_t*)(&__MBAR[0x009084+((x)*0x800)])) -#define MCF_FEC_R_HASH(x) (*(vuint32_t*)(&__MBAR[0x009088+((x)*0x800)])) -#define MCF_FEC_TCR(x) (*(vuint32_t*)(&__MBAR[0x0090C4+((x)*0x800)])) -#define MCF_FEC_PALR(x) (*(vuint32_t*)(&__MBAR[0x0090E4+((x)*0x800)])) -#define MCF_FEC_PAUR(x) (*(vuint32_t*)(&__MBAR[0x0090E8+((x)*0x800)])) -#define MCF_FEC_OPD(x) (*(vuint32_t*)(&__MBAR[0x0090EC+((x)*0x800)])) -#define MCF_FEC_IAUR(x) (*(vuint32_t*)(&__MBAR[0x009118+((x)*0x800)])) -#define MCF_FEC_IALR(x) (*(vuint32_t*)(&__MBAR[0x00911C+((x)*0x800)])) -#define MCF_FEC_GAUR(x) (*(vuint32_t*)(&__MBAR[0x009120+((x)*0x800)])) -#define MCF_FEC_GALR(x) (*(vuint32_t*)(&__MBAR[0x009124+((x)*0x800)])) -#define MCF_FEC_FECTFWR(x) (*(vuint32_t*)(&__MBAR[0x009144+((x)*0x800)])) -#define MCF_FEC_FECRFDR(x) (*(vuint32_t*)(&__MBAR[0x009184+((x)*0x800)])) -#define MCF_FEC_FECRFSR(x) (*(vuint32_t*)(&__MBAR[0x009188+((x)*0x800)])) -#define MCF_FEC_FECRFCR(x) (*(vuint32_t*)(&__MBAR[0x00918C+((x)*0x800)])) -#define MCF_FEC_FECRLRFP(x) (*(vuint32_t*)(&__MBAR[0x009190+((x)*0x800)])) -#define MCF_FEC_FECRLWFP(x) (*(vuint32_t*)(&__MBAR[0x009194+((x)*0x800)])) -#define MCF_FEC_FECRFAR(x) (*(vuint32_t*)(&__MBAR[0x009198+((x)*0x800)])) -#define MCF_FEC_FECRFRP(x) (*(vuint32_t*)(&__MBAR[0x00919C+((x)*0x800)])) -#define MCF_FEC_FECRFWP(x) (*(vuint32_t*)(&__MBAR[0x0091A0+((x)*0x800)])) -#define MCF_FEC_FECTFDR(x) (*(vuint32_t*)(&__MBAR[0x0091A4+((x)*0x800)])) -#define MCF_FEC_FECTFSR(x) (*(vuint32_t*)(&__MBAR[0x0091A8+((x)*0x800)])) -#define MCF_FEC_FECTFCR(x) (*(vuint32_t*)(&__MBAR[0x0091AC+((x)*0x800)])) -#define MCF_FEC_FECTLRFP(x) (*(vuint32_t*)(&__MBAR[0x0091B0+((x)*0x800)])) -#define MCF_FEC_FECTLWFP(x) (*(vuint32_t*)(&__MBAR[0x0091B4+((x)*0x800)])) -#define MCF_FEC_FECTFAR(x) (*(vuint32_t*)(&__MBAR[0x0091B8+((x)*0x800)])) -#define MCF_FEC_FECTFRP(x) (*(vuint32_t*)(&__MBAR[0x0091BC+((x)*0x800)])) -#define MCF_FEC_FECTFWP(x) (*(vuint32_t*)(&__MBAR[0x0091C0+((x)*0x800)])) -#define MCF_FEC_FRST(x) (*(vuint32_t*)(&__MBAR[0x0091C4+((x)*0x800)])) -#define MCF_FEC_CTCWR(x) (*(vuint32_t*)(&__MBAR[0x0091C8+((x)*0x800)])) -#define MCF_FEC_RMON_T_DROP(x) (*(vuint32_t*)(&__MBAR[0x009200+((x)*0x800)])) -#define MCF_FEC_RMON_T_PACKETS(x) (*(vuint32_t*)(&__MBAR[0x009204+((x)*0x800)])) -#define MCF_FEC_RMON_T_BC_PKT(x) (*(vuint32_t*)(&__MBAR[0x009208+((x)*0x800)])) -#define MCF_FEC_RMON_T_MC_PKT(x) (*(vuint32_t*)(&__MBAR[0x00920C+((x)*0x800)])) -#define MCF_FEC_RMON_T_CRC_ALIGN(x) (*(vuint32_t*)(&__MBAR[0x009210+((x)*0x800)])) -#define MCF_FEC_RMON_T_UNDERSIZE(x) (*(vuint32_t*)(&__MBAR[0x009214+((x)*0x800)])) -#define MCF_FEC_RMON_T_OVERSIZE(x) (*(vuint32_t*)(&__MBAR[0x009218+((x)*0x800)])) -#define MCF_FEC_RMON_T_FRAG(x) (*(vuint32_t*)(&__MBAR[0x00921C+((x)*0x800)])) -#define MCF_FEC_RMON_T_JAB(x) (*(vuint32_t*)(&__MBAR[0x009220+((x)*0x800)])) -#define MCF_FEC_RMON_T_COL(x) (*(vuint32_t*)(&__MBAR[0x009224+((x)*0x800)])) -#define MCF_FEC_RMON_T_P64(x) (*(vuint32_t*)(&__MBAR[0x009228+((x)*0x800)])) -#define MCF_FEC_RMON_T_P65TO127(x) (*(vuint32_t*)(&__MBAR[0x00922C+((x)*0x800)])) -#define MCF_FEC_RMON_T_P128TO255(x) (*(vuint32_t*)(&__MBAR[0x009230+((x)*0x800)])) -#define MCF_FEC_RMON_T_P256TO511(x) (*(vuint32_t*)(&__MBAR[0x009234+((x)*0x800)])) -#define MCF_FEC_RMON_T_P512TO1023(x) (*(vuint32_t*)(&__MBAR[0x009238+((x)*0x800)])) -#define MCF_FEC_RMON_T_P1024TO2047(x) (*(vuint32_t*)(&__MBAR[0x00923C+((x)*0x800)])) -#define MCF_FEC_RMON_T_P_GTE2048(x) (*(vuint32_t*)(&__MBAR[0x009240+((x)*0x800)])) -#define MCF_FEC_RMON_T_OCTETS(x) (*(vuint32_t*)(&__MBAR[0x009244+((x)*0x800)])) -#define MCF_FEC_IEEE_T_DROP(x) (*(vuint32_t*)(&__MBAR[0x009248+((x)*0x800)])) -#define MCF_FEC_IEEE_T_FRAME_OK(x) (*(vuint32_t*)(&__MBAR[0x00924C+((x)*0x800)])) -#define MCF_FEC_IEEE_T_1COL(x) (*(vuint32_t*)(&__MBAR[0x009250+((x)*0x800)])) -#define MCF_FEC_IEEE_T_MCOL(x) (*(vuint32_t*)(&__MBAR[0x009254+((x)*0x800)])) -#define MCF_FEC_IEEE_T_DEF(x) (*(vuint32_t*)(&__MBAR[0x009258+((x)*0x800)])) -#define MCF_FEC_IEEE_T_LCOL(x) (*(vuint32_t*)(&__MBAR[0x00925C+((x)*0x800)])) -#define MCF_FEC_IEEE_T_EXCOL(x) (*(vuint32_t*)(&__MBAR[0x009260+((x)*0x800)])) -#define MCF_FEC_IEEE_T_MACERR(x) (*(vuint32_t*)(&__MBAR[0x009264+((x)*0x800)])) -#define MCF_FEC_IEEE_T_CSERR(x) (*(vuint32_t*)(&__MBAR[0x009268+((x)*0x800)])) -#define MCF_FEC_IEEE_T_SQE(x) (*(vuint32_t*)(&__MBAR[0x00926C+((x)*0x800)])) -#define MCF_FEC_IEEE_T_FDXFC(x) (*(vuint32_t*)(&__MBAR[0x009270+((x)*0x800)])) -#define MCF_FEC_IEEE_T_OCTETS_OK(x) (*(vuint32_t*)(&__MBAR[0x009274+((x)*0x800)])) -#define MCF_FEC_RMON_R_DROP(x) (*(vuint32_t*)(&__MBAR[0x009280+((x)*0x800)])) -#define MCF_FEC_RMON_R_PACKETS(x) (*(vuint32_t*)(&__MBAR[0x009284+((x)*0x800)])) -#define MCF_FEC_RMON_R_BC_PKT(x) (*(vuint32_t*)(&__MBAR[0x009288+((x)*0x800)])) -#define MCF_FEC_RMON_R_MC_PKT(x) (*(vuint32_t*)(&__MBAR[0x00928C+((x)*0x800)])) -#define MCF_FEC_RMON_R_CRC_ALIGN(x) (*(vuint32_t*)(&__MBAR[0x009290+((x)*0x800)])) -#define MCF_FEC_RMON_R_UNDERSIZE(x) (*(vuint32_t*)(&__MBAR[0x009294+((x)*0x800)])) -#define MCF_FEC_RMON_R_OVERSIZE(x) (*(vuint32_t*)(&__MBAR[0x009298+((x)*0x800)])) -#define MCF_FEC_RMON_R_FRAG(x) (*(vuint32_t*)(&__MBAR[0x00929C+((x)*0x800)])) -#define MCF_FEC_RMON_R_JAB(x) (*(vuint32_t*)(&__MBAR[0x0092A0+((x)*0x800)])) -#define MCF_FEC_RMON_R_RESVD_0(x) (*(vuint32_t*)(&__MBAR[0x0092A4+((x)*0x800)])) -#define MCF_FEC_RMON_R_P64(x) (*(vuint32_t*)(&__MBAR[0x0092A8+((x)*0x800)])) -#define MCF_FEC_RMON_R_P65TO127(x) (*(vuint32_t*)(&__MBAR[0x0092AC+((x)*0x800)])) -#define MCF_FEC_RMON_R_P128TO255(x) (*(vuint32_t*)(&__MBAR[0x0092B0+((x)*0x800)])) -#define MCF_FEC_RMON_R_P256TO511(x) (*(vuint32_t*)(&__MBAR[0x0092B4+((x)*0x800)])) -#define MCF_FEC_RMON_R_512TO1023(x) (*(vuint32_t*)(&__MBAR[0x0092B8+((x)*0x800)])) -#define MCF_FEC_RMON_R_1024TO2047(x) (*(vuint32_t*)(&__MBAR[0x0092BC+((x)*0x800)])) -#define MCF_FEC_RMON_R_P_GTE2048(x) (*(vuint32_t*)(&__MBAR[0x0092C0+((x)*0x800)])) -#define MCF_FEC_RMON_R_OCTETS(x) (*(vuint32_t*)(&__MBAR[0x0092C4+((x)*0x800)])) -#define MCF_FEC_IEEE_R_DROP(x) (*(vuint32_t*)(&__MBAR[0x0092C8+((x)*0x800)])) -#define MCF_FEC_IEEE_R_FRAME_OK(x) (*(vuint32_t*)(&__MBAR[0x0092CC+((x)*0x800)])) -#define MCF_FEC_IEEE_R_CRC(x) (*(vuint32_t*)(&__MBAR[0x0092D0+((x)*0x800)])) -#define MCF_FEC_IEEE_R_ALIGN(x) (*(vuint32_t*)(&__MBAR[0x0092D4+((x)*0x800)])) -#define MCF_FEC_IEEE_R_MACERR(x) (*(vuint32_t*)(&__MBAR[0x0092D8+((x)*0x800)])) -#define MCF_FEC_IEEE_R_FDXFC(x) (*(vuint32_t*)(&__MBAR[0x0092DC+((x)*0x800)])) -#define MCF_FEC_IEEE_R_OCTETS_OK(x) (*(vuint32_t*)(&__MBAR[0x0092E0+((x)*0x800)])) - -/* Bit definitions and macros for MCF_FEC_EIR */ -#define MCF_FEC_EIR_RFERR (0x00020000) -#define MCF_FEC_EIR_XFERR (0x00040000) -#define MCF_FEC_EIR_XFUN (0x00080000) -#define MCF_FEC_EIR_RL (0x00100000) -#define MCF_FEC_EIR_LC (0x00200000) -#define MCF_FEC_EIR_MII (0x00800000) -#define MCF_FEC_EIR_TXF (0x08000000) -#define MCF_FEC_EIR_GRA (0x10000000) -#define MCF_FEC_EIR_BABT (0x20000000) -#define MCF_FEC_EIR_BABR (0x40000000) -#define MCF_FEC_EIR_HBERR (0x80000000) -#define MCF_FEC_EIR_CLEAR_ALL (0xFFFFFFFF) - -/* Bit definitions and macros for MCF_FEC_EIMR */ -#define MCF_FEC_EIMR_RFERR (0x00020000) -#define MCF_FEC_EIMR_XFERR (0x00040000) -#define MCF_FEC_EIMR_XFUN (0x00080000) -#define MCF_FEC_EIMR_RL (0x00100000) -#define MCF_FEC_EIMR_LC (0x00200000) -#define MCF_FEC_EIMR_MII (0x00800000) -#define MCF_FEC_EIMR_TXF (0x08000000) -#define MCF_FEC_EIMR_GRA (0x10000000) -#define MCF_FEC_EIMR_BABT (0x20000000) -#define MCF_FEC_EIMR_BABR (0x40000000) -#define MCF_FEC_EIMR_HBERR (0x80000000) -#define MCF_FEC_EIMR_MASK_ALL (0x00000000) -#define MCF_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF) - -/* Bit definitions and macros for MCF_FEC_ECR */ -#define MCF_FEC_ECR_RESET (0x00000001) -#define MCF_FEC_ECR_ETHER_EN (0x00000002) - -/* Bit definitions and macros for MCF_FEC_MMFR */ -#define MCF_FEC_MMFR_DATA(x) (((x)&0x0000FFFF)<<0) -#define MCF_FEC_MMFR_TA(x) (((x)&0x00000003)<<16) -#define MCF_FEC_MMFR_RA(x) (((x)&0x0000001F)<<18) -#define MCF_FEC_MMFR_PA(x) (((x)&0x0000001F)<<23) -#define MCF_FEC_MMFR_OP(x) (((x)&0x00000003)<<28) -#define MCF_FEC_MMFR_ST(x) (((x)&0x00000003)<<30) -#define MCF_FEC_MMFR_ST_01 (0x40000000) -#define MCF_FEC_MMFR_OP_READ (0x20000000) -#define MCF_FEC_MMFR_OP_WRITE (0x10000000) -#define MCF_FEC_MMFR_TA_10 (0x00020000) - -/* Bit definitions and macros for MCF_FEC_MSCR */ -#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x0000003F)<<1) -#define MCF_FEC_MSCR_DIS_PREAMBLE (0x00000080) -#define MCF_FEC_MSCR_MII_SPEED_133 (0x1B<<1) -#define MCF_FEC_MSCR_MII_SPEED_120 (0x18<<1) -#define MCF_FEC_MSCR_MII_SPEED_66 (0xE<<1) -#define MCF_FEC_MSCR_MII_SPEED_60 (0xC<<1) - -/* Bit definitions and macros for MCF_FEC_MIBC */ -#define MCF_FEC_MIBC_MIB_IDLE (0x40000000) -#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000) - -/* Bit definitions and macros for MCF_FEC_RCR */ -#define MCF_FEC_RCR_LOOP (0x00000001) -#define MCF_FEC_RCR_DRT (0x00000002) -#define MCF_FEC_RCR_MII_MODE (0x00000004) -#define MCF_FEC_RCR_PROM (0x00000008) -#define MCF_FEC_RCR_BC_REJ (0x00000010) -#define MCF_FEC_RCR_FCE (0x00000020) -#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x000007FF)<<16) - -/* Bit definitions and macros for MCF_FEC_R_HASH */ -#define MCF_FEC_R_HASH_HASH(x) (((x)&0x0000003F)<<24) -#define MCF_FEC_R_HASH_MULTCAST (0x40000000) -#define MCF_FEC_R_HASH_FCE_DC (0x80000000) - -/* Bit definitions and macros for MCF_FEC_TCR */ -#define MCF_FEC_TCR_GTS (0x00000001) -#define MCF_FEC_TCR_HBC (0x00000002) -#define MCF_FEC_TCR_FDEN (0x00000004) -#define MCF_FEC_TCR_TFC_PAUSE (0x00000008) -#define MCF_FEC_TCR_RFC_PAUSE (0x00000010) - -/* Bit definitions and macros for MCF_FEC_PAUR */ -#define MCF_FEC_PAUR_TYPE(x) (((x)&0x0000FFFF)<<0) -#define MCF_FEC_PAUR_PADDR2(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_FEC_OPD */ -#define MCF_FEC_OPD_OP_PAUSE(x) (((x)&0x0000FFFF)<<0) -#define MCF_FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_FEC_FECTFWR */ -#define MCF_FEC_FECTFWR_X_WMRK(x) (((x)&0x0000000F)<<0) -#define MCF_FEC_FECTFWR_X_WMRK_64 (0x00000000) -#define MCF_FEC_FECTFWR_X_WMRK_128 (0x00000001) -#define MCF_FEC_FECTFWR_X_WMRK_192 (0x00000002) -#define MCF_FEC_FECTFWR_X_WMRK_256 (0x00000003) -#define MCF_FEC_FECTFWR_X_WMRK_320 (0x00000004) -#define MCF_FEC_FECTFWR_X_WMRK_384 (0x00000005) -#define MCF_FEC_FECTFWR_X_WMRK_448 (0x00000006) -#define MCF_FEC_FECTFWR_X_WMRK_512 (0x00000007) -#define MCF_FEC_FECTFWR_X_WMRK_576 (0x00000008) -#define MCF_FEC_FECTFWR_X_WMRK_640 (0x00000009) -#define MCF_FEC_FECTFWR_X_WMRK_704 (0x0000000A) -#define MCF_FEC_FECTFWR_X_WMRK_768 (0x0000000B) -#define MCF_FEC_FECTFWR_X_WMRK_832 (0x0000000C) -#define MCF_FEC_FECTFWR_X_WMRK_896 (0x0000000D) -#define MCF_FEC_FECTFWR_X_WMRK_960 (0x0000000E) -#define MCF_FEC_FECTFWR_X_WMRK_1024 (0x0000000F) - -/* Bit definitions and macros for MCF_FEC_FECRFDR */ -#define MCF_FEC_FECRFDR_ADDR0 ((void*)(&__MBAR[0x009184])) -#define MCF_FEC_FECRFDR_ADDR1 ((void*)(&__MBAR[0x009984])) -#define MCF_FEC_FECRFDR_ADDR(x) ((void*)(&__MBAR[0x009184+(0x800*ch)])) - -/* Bit definitions and macros for MCF_FEC_FECRFSR */ -#define MCF_FEC_FECRFSR_EMT (0x00010000) -#define MCF_FEC_FECRFSR_ALARM (0x00020000) -#define MCF_FEC_FECRFSR_FU (0x00040000) -#define MCF_FEC_FECRFSR_FR (0x00080000) -#define MCF_FEC_FECRFSR_OF (0x00100000) -#define MCF_FEC_FECRFSR_UF (0x00200000) -#define MCF_FEC_FECRFSR_RXW (0x00400000) -#define MCF_FEC_FECRFSR_FAE (0x00800000) -#define MCF_FEC_FECRFSR_FRM(x) (((x)&0x0000000F)<<24) -#define MCF_FEC_FECRFSR_IP (0x80000000) - -/* Bit definitions and macros for MCF_FEC_FECRFCR */ -#define MCF_FEC_FECRFCR_COUNTER(x) (((x)&0x0000FFFF)<<0) -#define MCF_FEC_FECRFCR_OF_MSK (0x00080000) -#define MCF_FEC_FECRFCR_UF_MSK (0x00100000) -#define MCF_FEC_FECRFCR_RXW_MSK (0x00200000) -#define MCF_FEC_FECRFCR_FAE_MSK (0x00400000) -#define MCF_FEC_FECRFCR_IP_MSK (0x00800000) -#define MCF_FEC_FECRFCR_GR(x) (((x)&0x00000007)<<24) -#define MCF_FEC_FECRFCR_FRM (0x08000000) -#define MCF_FEC_FECRFCR_TIMER (0x10000000) -#define MCF_FEC_FECRFCR_WFR (0x20000000) -#define MCF_FEC_FECRFCR_WCTL (0x40000000) - -/* Bit definitions and macros for MCF_FEC_FECRLRFP */ -#define MCF_FEC_FECRLRFP_LRFP(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_FEC_FECRLWFP */ -#define MCF_FEC_FECRLWFP_LWFP(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_FEC_FECRFAR */ -#define MCF_FEC_FECRFAR_ALARM(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_FEC_FECRFRP */ -#define MCF_FEC_FECRFRP_READ(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_FEC_FECRFWP */ -#define MCF_FEC_FECRFWP_WRITE(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_FEC_FECTFDR */ -#define MCF_FEC_FECTFDR_TFCW_TC (0x04000000) -#define MCF_FEC_FECTFDR_TFCW_ABC (0x02000000) -#define MCF_FEC_FECTFDR_ADDR0 ((void*)(&__MBAR[0x0091A4])) -#define MCF_FEC_FECTFDR_ADDR1 ((void*)(&__MBAR[0x0099A4])) -#define MCF_FEC_FECTFDR_ADDR(x) ((void*)(&__MBAR[0x0091A4+(0x800*ch)])) - -/* Bit definitions and macros for MCF_FEC_FECTFSR */ -#define MCF_FEC_FECTFSR_EMT (0x00010000) -#define MCF_FEC_FECTFSR_ALARM (0x00020000) -#define MCF_FEC_FECTFSR_FU (0x00040000) -#define MCF_FEC_FECTFSR_FR (0x00080000) -#define MCF_FEC_FECTFSR_OF (0x00100000) -#define MCF_FEC_FECTFSR_UP (0x00200000) -#define MCF_FEC_FECTFSR_FAE (0x00800000) -#define MCF_FEC_FECTFSR_FRM(x) (((x)&0x0000000F)<<24) -#define MCF_FEC_FECTFSR_TXW (0x40000000) -#define MCF_FEC_FECTFSR_IP (0x80000000) - -/* Bit definitions and macros for MCF_FEC_FECTFCR */ -#define MCF_FEC_FECTFCR_RESERVED (0x00200000) -#define MCF_FEC_FECTFCR_COUNTER(x) (((x)&0x0000FFFF)<<0|0x00200000) -#define MCF_FEC_FECTFCR_TXW_MSK (0x00240000) -#define MCF_FEC_FECTFCR_OF_MSK (0x00280000) -#define MCF_FEC_FECTFCR_UF_MSK (0x00300000) -#define MCF_FEC_FECTFCR_FAE_MSK (0x00600000) -#define MCF_FEC_FECTFCR_IP_MSK (0x00A00000) -#define MCF_FEC_FECTFCR_GR(x) (((x)&0x00000007)<<24|0x00200000) -#define MCF_FEC_FECTFCR_FRM (0x08200000) -#define MCF_FEC_FECTFCR_TIMER (0x10200000) -#define MCF_FEC_FECTFCR_WFR (0x20200000) -#define MCF_FEC_FECTFCR_WCTL (0x40200000) - -/* Bit definitions and macros for MCF_FEC_FECTLRFP */ -#define MCF_FEC_FECTLRFP_LRFP(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_FEC_FECTLWFP */ -#define MCF_FEC_FECTLWFP_LWFP(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_FEC_FECTFAR */ -#define MCF_FEC_FECTFAR_ALARM(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_FEC_FECTFRP */ -#define MCF_FEC_FECTFRP_READ(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_FEC_FECTFWP */ -#define MCF_FEC_FECTFWP_WRITE(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_FEC_FRST */ -#define MCF_FEC_FRST_RST_CTL (0x01000000) -#define MCF_FEC_FRST_SW_RST (0x02000000) - -/* Bit definitions and macros for MCF_FEC_CTCWR */ -#define MCF_FEC_CTCWR_TFCW (0x01000000) -#define MCF_FEC_CTCWR_CRC (0x02000000) - - -struct mcf54xx_fec -{ - vuint32_t RES0; - vuint32_t eir; // 004 - vuint32_t eimr; // 008 - vuint32_t RES1[6]; - vuint32_t ecr; // 024 - vuint32_t RES2[6]; - vuint32_t mmfr; // 040 - vuint32_t mscr; // 044 - vuint32_t RES3[7]; - vuint32_t mibc; // 064 - vuint32_t RES4[7]; - vuint32_t rcr; // 084 - vuint32_t r_hash; // 088 - vuint32_t RES5[14]; - vuint32_t tcr; // 0c4 - vuint32_t RES6[7]; - vuint32_t palr; // 0e4 - vuint32_t paur; // 0e8 - vuint32_t opd; // 0ec - vuint32_t RES7[10]; - vuint32_t iaur; // 118 - vuint32_t ialr; // 11c - vuint32_t gaur; // 120 - vuint32_t galr; // 124 - vuint32_t RES8[7]; - vuint32_t fectfwr; // 144 - vuint32_t RES8a[15]; - vuint32_t fecrfdr; // 184 - vuint32_t fecrfsr; // 188 - vuint32_t fecrfcr; // 18c - vuint32_t fecrlrfp; // 190 - vuint32_t fecrlwfp; // 194 - vuint32_t fecrfar; // 198 - vuint32_t fecrfrp; // 19c - vuint32_t fecrfwp; // 1a0 - vuint32_t fectfdr; // 1a4 - vuint32_t fectfsr; // 1a8 - vuint32_t fectfcr; // 1ac - vuint32_t fectlrfp; // 1b0 - vuint32_t fectlwfp; // 1b4 - vuint32_t fectfar; // 1b8 - vuint32_t fectfrp; // 1bc - vuint32_t fectfwp; // 1c0 - vuint32_t frst; // 1c4 - vuint32_t ctcwr; // 1c8 - vuint32_t RES9[13]; - - /* MIB Counters Memory Map */ - vuint32_t rmon_t_drop; // 200 - vuint32_t rmon_t_packets; // 204 - vuint32_t rmon_t_bc_pkt; // 208 - vuint32_t rmon_t_mc_pkt; // 20C - vuint32_t rmon_t_crc_align; // 210 - vuint32_t rmon_t_undersize; // 214 - vuint32_t rmon_t_oversize; // 218 - vuint32_t rmon_t_frag; // 21C - vuint32_t rmon_t_jab; // 220 - vuint32_t rmon_t_col; // 224 - vuint32_t rmon_t_p64; // 228 - vuint32_t rmon_t_p65to127; // 22C - vuint32_t rmon_t_p128to255; // 230 - vuint32_t rmon_t_p256to511; // 234 - vuint32_t rmon_t_p512to1023; // 238 - vuint32_t rmon_t_p1024to2047; // 23C - vuint32_t rmon_t_p_gte2048; // 240 - vuint32_t rmon_t_octets; // 244 - vuint32_t ieee_t_drop; // 248 - vuint32_t ieee_t_frame_ok; // 24C - vuint32_t ieee_t_1col; // 250 - vuint32_t ieee_t_mcol; // 254 - vuint32_t ieee_t_def; // 258 - vuint32_t ieee_t_lcol; // 25C - vuint32_t ieee_t_excol; // 260 - vuint32_t ieee_t_macerr; // 264 - vuint32_t ieee_t_cserr; // 268 - vuint32_t ieee_t_sqe; // 26C - vuint32_t ieee_t_fdxfc; // 270 - vuint32_t ieee_t_octets_ok; // 274 - vuint32_t RES10[2]; - - vuint32_t rmon_r_drop; // 280 - vuint32_t rmon_r_packets; // 284 - vuint32_t rmon_r_bc_pkt; // 288 - vuint32_t rmon_r_mc_pkt; // 28C - vuint32_t rmon_r_crc_align; // 290 - vuint32_t rmon_r_undersize; // 294 - vuint32_t rmon_r_oversize; // 298 - vuint32_t rmon_r_frag; // 29C - vuint32_t rmon_r_jab; // 2A0 - vuint32_t rmon_r_resvd_0; // 2A4 - vuint32_t rmon_r_p64; // 2A8 - vuint32_t rmon_r_p65to127; // 2AC - vuint32_t rmon_r_p128to255; // 2B0 - vuint32_t rmon_r_p256to511; // 2B4 - vuint32_t rmon_r_512to1023; // 2B8 - vuint32_t rmon_r_1024to2047; // 2BC - vuint32_t rmon_r_p_gte2048; // 2C0 - vuint32_t rmon_r_octets; // 2C4 - vuint32_t ieee_r_drop; // 2C8 - vuint32_t ieee_r_frame_ok; // 2CC - vuint32_t ieee_r_crc; // 2D0 - vuint32_t ieee_r_align; // 2D4 - vuint32_t ieee_r_macerr; // 2D8 - vuint32_t ieee_r_fdxfc; // 2DC - vuint32_t ieee_r_octets_ok; // 2e0 -}; - -#define MCF_FEC_ADDR(ch) ((void*)(&__MBAR[0x009000+(0x800*ch)])) -#define MCF_FEC_SIZE(ch) ((uint32_t)(0x800)) - -#endif /* __MCF548X_FEC_H__ */ diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_gpio.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_gpio.h deleted file mode 100644 index d2200714f1..0000000000 --- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_gpio.h +++ /dev/null @@ -1,708 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * General Purpose I/O (GPIO) - */ -#ifndef __MCF548X_GPIO_H__ -#define __MCF548X_GPIO_H__ - -/* - * General Purpose I/O (GPIO) - */ - -/* Register read/write macros */ -#define MCF_GPIO_PODR_FBCTL (*(vuint8_t *)(&__MBAR[0x000A00])) -#define MCF_GPIO_PODR_FBCS (*(vuint8_t *)(&__MBAR[0x000A01])) -#define MCF_GPIO_PODR_DMA (*(vuint8_t *)(&__MBAR[0x000A02])) -#define MCF_GPIO_PODR_FEC0H (*(vuint8_t *)(&__MBAR[0x000A04])) -#define MCF_GPIO_PODR_FEC0L (*(vuint8_t *)(&__MBAR[0x000A05])) -#define MCF_GPIO_PODR_FEC1H (*(vuint8_t *)(&__MBAR[0x000A06])) -#define MCF_GPIO_PODR_FEC1L (*(vuint8_t *)(&__MBAR[0x000A07])) -#define MCF_GPIO_PODR_FECI2C (*(vuint8_t *)(&__MBAR[0x000A08])) -#define MCF_GPIO_PODR_PCIBG (*(vuint8_t *)(&__MBAR[0x000A09])) -#define MCF_GPIO_PODR_PCIBR (*(vuint8_t *)(&__MBAR[0x000A0A])) -#define MCF_GPIO_PODR_PSC3PSC2 (*(vuint8_t *)(&__MBAR[0x000A0C])) -#define MCF_GPIO_PODR_PSC1PSC0 (*(vuint8_t *)(&__MBAR[0x000A0D])) -#define MCF_GPIO_PODR_DSPI (*(vuint8_t *)(&__MBAR[0x000A0E])) -#define MCF_GPIO_PDDR_FBCTL (*(vuint8_t *)(&__MBAR[0x000A10])) -#define MCF_GPIO_PDDR_FBCS (*(vuint8_t *)(&__MBAR[0x000A11])) -#define MCF_GPIO_PDDR_DMA (*(vuint8_t *)(&__MBAR[0x000A12])) -#define MCF_GPIO_PDDR_FEC0H (*(vuint8_t *)(&__MBAR[0x000A14])) -#define MCF_GPIO_PDDR_FEC0L (*(vuint8_t *)(&__MBAR[0x000A15])) -#define MCF_GPIO_PDDR_FEC1H (*(vuint8_t *)(&__MBAR[0x000A16])) -#define MCF_GPIO_PDDR_FEC1L (*(vuint8_t *)(&__MBAR[0x000A17])) -#define MCF_GPIO_PDDR_FECI2C (*(vuint8_t *)(&__MBAR[0x000A18])) -#define MCF_GPIO_PDDR_PCIBG (*(vuint8_t *)(&__MBAR[0x000A19])) -#define MCF_GPIO_PDDR_PCIBR (*(vuint8_t *)(&__MBAR[0x000A1A])) -#define MCF_GPIO_PDDR_PSC3PSC2 (*(vuint8_t *)(&__MBAR[0x000A1C])) -#define MCF_GPIO_PDDR_PSC1PSC0 (*(vuint8_t *)(&__MBAR[0x000A1D])) -#define MCF_GPIO_PDDR_DSPI (*(vuint8_t *)(&__MBAR[0x000A1E])) -#define MCF_GPIO_PPDSDR_FBCTL (*(vuint8_t *)(&__MBAR[0x000A20])) -#define MCF_GPIO_PPDSDR_FBCS (*(vuint8_t *)(&__MBAR[0x000A21])) -#define MCF_GPIO_PPDSDR_DMA (*(vuint8_t *)(&__MBAR[0x000A22])) -#define MCF_GPIO_PPDSDR_FEC0H (*(vuint8_t *)(&__MBAR[0x000A24])) -#define MCF_GPIO_PPDSDR_FEC0L (*(vuint8_t *)(&__MBAR[0x000A25])) -#define MCF_GPIO_PPDSDR_FEC1H (*(vuint8_t *)(&__MBAR[0x000A26])) -#define MCF_GPIO_PPDSDR_FEC1L (*(vuint8_t *)(&__MBAR[0x000A27])) -#define MCF_GPIO_PPDSDR_FECI2C (*(vuint8_t *)(&__MBAR[0x000A28])) -#define MCF_GPIO_PPDSDR_PCIBG (*(vuint8_t *)(&__MBAR[0x000A29])) -#define MCF_GPIO_PPDSDR_PCIBR (*(vuint8_t *)(&__MBAR[0x000A2A])) -#define MCF_GPIO_PPDSDR_PSC3PSC2 (*(vuint8_t *)(&__MBAR[0x000A2C])) -#define MCF_GPIO_PPDSDR_PSC1PSC0 (*(vuint8_t *)(&__MBAR[0x000A2D])) -#define MCF_GPIO_PPDSDR_DSPI (*(vuint8_t *)(&__MBAR[0x000A2E])) -#define MCF_GPIO_PCLRR_FBCTL (*(vuint8_t *)(&__MBAR[0x000A30])) -#define MCF_GPIO_PCLRR_FBCS (*(vuint8_t *)(&__MBAR[0x000A31])) -#define MCF_GPIO_PCLRR_DMA (*(vuint8_t *)(&__MBAR[0x000A32])) -#define MCF_GPIO_PCLRR_FEC0H (*(vuint8_t *)(&__MBAR[0x000A34])) -#define MCF_GPIO_PCLRR_FEC0L (*(vuint8_t *)(&__MBAR[0x000A35])) -#define MCF_GPIO_PCLRR_FEC1H (*(vuint8_t *)(&__MBAR[0x000A36])) -#define MCF_GPIO_PCLRR_FEC1L (*(vuint8_t *)(&__MBAR[0x000A37])) -#define MCF_GPIO_PCLRR_FECI2C (*(vuint8_t *)(&__MBAR[0x000A38])) -#define MCF_GPIO_PCLRR_PCIBG (*(vuint8_t *)(&__MBAR[0x000A39])) -#define MCF_GPIO_PCLRR_PCIBR (*(vuint8_t *)(&__MBAR[0x000A3A])) -#define MCF_GPIO_PCLRR_PSC3PSC2 (*(vuint8_t *)(&__MBAR[0x000A3C])) -#define MCF_GPIO_PCLRR_PSC1PSC0 (*(vuint8_t *)(&__MBAR[0x000A3D])) -#define MCF_GPIO_PCLRR_DSPI (*(vuint8_t *)(&__MBAR[0x000A3E])) -#define MCF_GPIO_PAR_FBCTL (*(vuint16_t*)(&__MBAR[0x000A40])) -#define MCF_GPIO_PAR_FBCS (*(vuint8_t *)(&__MBAR[0x000A42])) -#define MCF_GPIO_PAR_DMA (*(vuint8_t *)(&__MBAR[0x000A43])) -#define MCF_GPIO_PAR_FECI2CIRQ (*(vuint16_t*)(&__MBAR[0x000A44])) -#define MCF_GPIO_PAR_PCIBG (*(vuint16_t*)(&__MBAR[0x000A48])) -#define MCF_GPIO_PAR_PCIBR (*(vuint16_t*)(&__MBAR[0x000A4A])) -#define MCF_GPIO_PAR_PSC3 (*(vuint8_t *)(&__MBAR[0x000A4C])) -#define MCF_GPIO_PAR_PSC2 (*(vuint8_t *)(&__MBAR[0x000A4D])) -#define MCF_GPIO_PAR_PSC1 (*(vuint8_t *)(&__MBAR[0x000A4E])) -#define MCF_GPIO_PAR_PSC0 (*(vuint8_t *)(&__MBAR[0x000A4F])) -#define MCF_GPIO_PAR_DSPI (*(vuint16_t*)(&__MBAR[0x000A50])) -#define MCF_GPIO_PAR_TIMER (*(vuint8_t *)(&__MBAR[0x000A52])) - -/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */ -#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL0 (0x01) -#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL1 (0x02) -#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL2 (0x04) -#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL3 (0x08) -#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL4 (0x10) -#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL5 (0x20) -#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL6 (0x40) -#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */ -#define MCF_GPIO_PODR_FBCS_PODR_FBCS1 (0x02) -#define MCF_GPIO_PODR_FBCS_PODR_FBCS2 (0x04) -#define MCF_GPIO_PODR_FBCS_PODR_FBCS3 (0x08) -#define MCF_GPIO_PODR_FBCS_PODR_FBCS4 (0x10) -#define MCF_GPIO_PODR_FBCS_PODR_FBCS5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PODR_DMA */ -#define MCF_GPIO_PODR_DMA_PODR_DMA0 (0x01) -#define MCF_GPIO_PODR_DMA_PODR_DMA1 (0x02) -#define MCF_GPIO_PODR_DMA_PODR_DMA2 (0x04) -#define MCF_GPIO_PODR_DMA_PODR_DMA3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */ -#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H0 (0x01) -#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H1 (0x02) -#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H2 (0x04) -#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H3 (0x08) -#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H4 (0x10) -#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H5 (0x20) -#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H6 (0x40) -#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */ -#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L0 (0x01) -#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L1 (0x02) -#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L2 (0x04) -#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L3 (0x08) -#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L4 (0x10) -#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L5 (0x20) -#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L6 (0x40) -#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */ -#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H0 (0x01) -#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H1 (0x02) -#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H2 (0x04) -#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H3 (0x08) -#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H4 (0x10) -#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H5 (0x20) -#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H6 (0x40) -#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */ -#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L0 (0x01) -#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L1 (0x02) -#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L2 (0x04) -#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L3 (0x08) -#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L4 (0x10) -#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L5 (0x20) -#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L6 (0x40) -#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */ -#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01) -#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02) -#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04) -#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */ -#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG0 (0x01) -#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG1 (0x02) -#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG2 (0x04) -#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG3 (0x08) -#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */ -#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR0 (0x01) -#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR1 (0x02) -#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR2 (0x04) -#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR3 (0x08) -#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC2 */ -#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC20 (0x01) -#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC21 (0x02) -#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC22 (0x04) -#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC23 (0x08) -#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC24 (0x10) -#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC25 (0x20) -#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC26 (0x40) -#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC27 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC0 */ -#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC00 (0x01) -#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC01 (0x02) -#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC02 (0x04) -#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC03 (0x08) -#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC04 (0x10) -#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC05 (0x20) -#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC06 (0x40) -#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC07 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */ -#define MCF_GPIO_PODR_DSPI_PODR_DSPI0 (0x01) -#define MCF_GPIO_PODR_DSPI_PODR_DSPI1 (0x02) -#define MCF_GPIO_PODR_DSPI_PODR_DSPI2 (0x04) -#define MCF_GPIO_PODR_DSPI_PODR_DSPI3 (0x08) -#define MCF_GPIO_PODR_DSPI_PODR_DSPI4 (0x10) -#define MCF_GPIO_PODR_DSPI_PODR_DSPI5 (0x20) -#define MCF_GPIO_PODR_DSPI_PODR_DSPI6 (0x40) - -/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */ -#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL0 (0x01) -#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL1 (0x02) -#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL2 (0x04) -#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL3 (0x08) -#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL4 (0x10) -#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL5 (0x20) -#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL6 (0x40) -#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */ -#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS1 (0x02) -#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS2 (0x04) -#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS3 (0x08) -#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS4 (0x10) -#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */ -#define MCF_GPIO_PDDR_DMA_PDDR_DMA0 (0x01) -#define MCF_GPIO_PDDR_DMA_PDDR_DMA1 (0x02) -#define MCF_GPIO_PDDR_DMA_PDDR_DMA2 (0x04) -#define MCF_GPIO_PDDR_DMA_PDDR_DMA3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */ -#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H0 (0x01) -#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H1 (0x02) -#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H2 (0x04) -#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H3 (0x08) -#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H4 (0x10) -#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H5 (0x20) -#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H6 (0x40) -#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */ -#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L0 (0x01) -#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L1 (0x02) -#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L2 (0x04) -#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L3 (0x08) -#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L4 (0x10) -#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L5 (0x20) -#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L6 (0x40) -#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */ -#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H0 (0x01) -#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H1 (0x02) -#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H2 (0x04) -#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H3 (0x08) -#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H4 (0x10) -#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H5 (0x20) -#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H6 (0x40) -#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */ -#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L0 (0x01) -#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1 (0x02) -#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2 (0x04) -#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3 (0x08) -#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 (0x10) -#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L5 (0x20) -#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L6 (0x40) -#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */ -#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01) -#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02) -#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04) -#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */ -#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG0 (0x01) -#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG1 (0x02) -#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG2 (0x04) -#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG3 (0x08) -#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */ -#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR0 (0x01) -#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR1 (0x02) -#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR2 (0x04) -#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR3 (0x08) -#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC2 */ -#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC20 (0x01) -#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC21 (0x02) -#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC22 (0x04) -#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC23 (0x08) -#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC24 (0x10) -#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC25 (0x20) -#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC26 (0x40) -#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC27 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC0 */ -#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC00 (0x01) -#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC01 (0x02) -#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC02 (0x04) -#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC03 (0x08) -#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC04 (0x10) -#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC05 (0x20) -#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC06 (0x40) -#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC07 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */ -#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI0 (0x01) -#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI1 (0x02) -#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI2 (0x04) -#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI3 (0x08) -#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI4 (0x10) -#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI5 (0x20) -#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI6 (0x40) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */ -#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL0 (0x01) -#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL1 (0x02) -#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL2 (0x04) -#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL3 (0x08) -#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL4 (0x10) -#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL5 (0x20) -#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL6 (0x40) -#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */ -#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS1 (0x02) -#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS2 (0x04) -#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS3 (0x08) -#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS4 (0x10) -#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */ -#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA0 (0x01) -#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA1 (0x02) -#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA2 (0x04) -#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */ -#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H0 (0x01) -#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H1 (0x02) -#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H2 (0x04) -#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H3 (0x08) -#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H4 (0x10) -#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H5 (0x20) -#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H6 (0x40) -#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */ -#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L0 (0x01) -#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L1 (0x02) -#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L2 (0x04) -#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L3 (0x08) -#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L4 (0x10) -#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L5 (0x20) -#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L6 (0x40) -#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */ -#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H0 (0x01) -#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H1 (0x02) -#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H2 (0x04) -#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H3 (0x08) -#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H4 (0x10) -#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H5 (0x20) -#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H6 (0x40) -#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */ -#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L0 (0x01) -#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L1 (0x02) -#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L2 (0x04) -#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L3 (0x08) -#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L4 (0x10) -#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L5 (0x20) -#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L6 (0x40) -#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */ -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01) -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02) -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04) -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */ -#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG0 (0x01) -#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG1 (0x02) -#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG2 (0x04) -#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG3 (0x08) -#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */ -#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR0 (0x01) -#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR1 (0x02) -#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR2 (0x04) -#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR3 (0x08) -#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC2 */ -#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC20 (0x01) -#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC21 (0x02) -#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC22 (0x04) -#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC23 (0x08) -#define MCF_GPIO_PPDSDR_PSC3PSC2_PDDR_PSC3PSC24 (0x10) -#define MCF_GPIO_PPDSDR_PSC3PSC2_PDDR_PSC3PSC25 (0x20) -#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC26 (0x40) -#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC27 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC0 */ -#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC00 (0x01) -#define MCF_GPIO_PPDSDR_PSC1PSC0_PDDR_PSC1PSC01 (0x02) -#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC02 (0x04) -#define MCF_GPIO_PPDSDR_PSC1PSC0_PDDR_PSC1PSC03 (0x08) -#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC04 (0x10) -#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC05 (0x20) -#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC06 (0x40) -#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC07 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */ -#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI0 (0x01) -#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI1 (0x02) -#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI2 (0x04) -#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI3 (0x08) -#define MCF_GPIO_PPDSDR_DSPI_PDDR_DSPI4 (0x10) -#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI5 (0x20) -#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI6 (0x40) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */ -#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL0 (0x01) -#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL1 (0x02) -#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL2 (0x04) -#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL3 (0x08) -#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL4 (0x10) -#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL5 (0x20) -#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL6 (0x40) -#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */ -#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS1 (0x02) -#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS2 (0x04) -#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS3 (0x08) -#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS4 (0x10) -#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */ -#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA0 (0x01) -#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA1 (0x02) -#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA2 (0x04) -#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */ -#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H0 (0x01) -#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H1 (0x02) -#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H2 (0x04) -#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H3 (0x08) -#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H4 (0x10) -#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H5 (0x20) -#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H6 (0x40) -#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */ -#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L0 (0x01) -#define MCF_GPIO_PCLRR_FEC0L_PODR_FEC0L1 (0x02) -#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L2 (0x04) -#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L3 (0x08) -#define MCF_GPIO_PCLRR_FEC0L_PODR_FEC0L4 (0x10) -#define MCF_GPIO_PCLRR_FEC0L_PODR_FEC0L5 (0x20) -#define MCF_GPIO_PCLRR_FEC0L_PODR_FEC0L6 (0x40) -#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */ -#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H0 (0x01) -#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H1 (0x02) -#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H2 (0x04) -#define MCF_GPIO_PCLRR_FEC1H_PODR_FEC1H3 (0x08) -#define MCF_GPIO_PCLRR_FEC1H_PODR_FEC1H4 (0x10) -#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H5 (0x20) -#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H6 (0x40) -#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */ -#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L0 (0x01) -#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L1 (0x02) -#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L2 (0x04) -#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L3 (0x08) -#define MCF_GPIO_PCLRR_FEC1L_PODR_FEC1L4 (0x10) -#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L5 (0x20) -#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L6 (0x40) -#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */ -#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01) -#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02) -#define MCF_GPIO_PCLRR_FECI2C_PODR_FECI2C2 (0x04) -#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */ -#define MCF_GPIO_PCLRR_PCIBG_PODR_PCIBG0 (0x01) -#define MCF_GPIO_PCLRR_PCIBG_PODR_PCIBG1 (0x02) -#define MCF_GPIO_PCLRR_PCIBG_PODR_PCIBG2 (0x04) -#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG3 (0x08) -#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */ -#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR0 (0x01) -#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR1 (0x02) -#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR2 (0x04) -#define MCF_GPIO_PCLRR_PCIBR_PODR_PCIBR3 (0x08) -#define MCF_GPIO_PCLRR_PCIBR_PODR_PCIBR4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC2 */ -#define MCF_GPIO_PCLRR_PSC3PSC2_PODR_PSC3PSC20 (0x01) -#define MCF_GPIO_PCLRR_PSC3PSC2_PODR_PSC3PSC21 (0x02) -#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRR_PSC3PSC22 (0x04) -#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRR_PSC3PSC23 (0x08) -#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRR_PSC3PSC24 (0x10) -#define MCF_GPIO_PCLRR_PSC3PSC2_PODR_PSC3PSC25 (0x20) -#define MCF_GPIO_PCLRR_PSC3PSC2_PODR_PSC3PSC26 (0x40) -#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRR_PSC3PSC27 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC0 */ -#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC00 (0x01) -#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC01 (0x02) -#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC02 (0x04) -#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC03 (0x08) -#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC04 (0x10) -#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC05 (0x20) -#define MCF_GPIO_PCLRR_PSC1PSC0_PODR_PSC1PSC06 (0x40) -#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC07 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */ -#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI0 (0x01) -#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI1 (0x02) -#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI2 (0x04) -#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI3 (0x08) -#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI4 (0x10) -#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI5 (0x20) -#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI6 (0x40) - -/* Bit definitions and macros for MCF_GPIO_PAR_FBCTL */ -#define MCF_GPIO_PAR_FBCTL_PAR_TS(x) (((x)&0x0003)<<0) -#define MCF_GPIO_PAR_FBCTL_PAR_TA (0x0004) -#define MCF_GPIO_PAR_FBCTL_PAR_RWB(x) (((x)&0x0003)<<4) -#define MCF_GPIO_PAR_FBCTL_PAR_OE (0x0040) -#define MCF_GPIO_PAR_FBCTL_PAR_BWE0 (0x0100) -#define MCF_GPIO_PAR_FBCTL_PAR_BWE1 (0x0400) -#define MCF_GPIO_PAR_FBCTL_PAR_BWE2 (0x1000) -#define MCF_GPIO_PAR_FBCTL_PAR_BWE3 (0x4000) -#define MCF_GPIO_PAR_FBCTL_PAR_TS_GPIO (0) -#define MCF_GPIO_PAR_FBCTL_PAR_TS_TBST (2) -#define MCF_GPIO_PAR_FBCTL_PAR_TS_TS (3) -#define MCF_GPIO_PAR_FBCTL_PAR_RWB_GPIO (0x0000) -#define MCF_GPIO_PAR_FBCTL_PAR_RWB_TBST (0x0020) -#define MCF_GPIO_PAR_FBCTL_PAR_RWB_RWB (0x0030) - -/* Bit definitions and macros for MCF_GPIO_PAR_FBCS */ -#define MCF_GPIO_PAR_FBCS_PAR_CS1 (0x02) -#define MCF_GPIO_PAR_FBCS_PAR_CS2 (0x04) -#define MCF_GPIO_PAR_FBCS_PAR_CS3 (0x08) -#define MCF_GPIO_PAR_FBCS_PAR_CS4 (0x10) -#define MCF_GPIO_PAR_FBCS_PAR_CS5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PAR_DMA */ -#define MCF_GPIO_PAR_DMA_PAR_DREQ0(x) (((x)&0x03)<<0) -#define MCF_GPIO_PAR_DMA_PAR_DREQ1(x) (((x)&0x03)<<2) -#define MCF_GPIO_PAR_DMA_PAR_DACK0(x) (((x)&0x03)<<4) -#define MCF_GPIO_PAR_DMA_PAR_DACK1(x) (((x)&0x03)<<6) -#define MCF_GPIO_PAR_DMA_PAR_DACKx_GPIO (0) -#define MCF_GPIO_PAR_DMA_PAR_DACKx_TOUT (2) -#define MCF_GPIO_PAR_DMA_PAR_DACKx_DACK (3) -#define MCF_GPIO_PAR_DMA_PAR_DREQx_GPIO (0) -#define MCF_GPIO_PAR_DMA_PAR_DREQx_TIN (2) -#define MCF_GPIO_PAR_DMA_PAR_DREQx_DREQ (3) - -/* Bit definitions and macros for MCF_GPIO_PAR_FECI2CIRQ */ -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_IRQ5 (0x0001) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_IRQ6 (0x0002) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_SCL (0x0004) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_SDA (0x0008) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC(x) (((x)&0x0003)<<6) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO(x) (((x)&0x0003)<<8) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MII (0x0400) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E17 (0x0800) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDC (0x1000) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO (0x2000) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MII (0x4000) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E07 (0x8000) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_CANRX (0x0000) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_SDA (0x0200) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO (0x0300) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_CANTX (0x0000) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_SCL (0x0080) -#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC (0x00C0) - -/* Bit definitions and macros for MCF_GPIO_PAR_PCIBG */ -#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG0(x) (((x)&0x0003)<<0) -#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG1(x) (((x)&0x0003)<<2) -#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG2(x) (((x)&0x0003)<<4) -#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG3(x) (((x)&0x0003)<<6) -#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG4(x) (((x)&0x0003)<<8) - -/* Bit definitions and macros for MCF_GPIO_PAR_PCIBR */ -#define MCF_GPIO_PAR_PCIBR_PAR_PCIBR0(x) (((x)&0x0003)<<0) -#define MCF_GPIO_PAR_PCIBR_PAR_PCIBR1(x) (((x)&0x0003)<<2) -#define MCF_GPIO_PAR_PCIBR_PAR_PCIBR2(x) (((x)&0x0003)<<4) -#define MCF_GPIO_PAR_PCIBR_PAR_PCIBR3(x) (((x)&0x0003)<<6) -#define MCF_GPIO_PAR_PCIBR_PAR_PCIBR4(x) (((x)&0x0003)<<8) - -/* Bit definitions and macros for MCF_GPIO_PAR_PSC3 */ -#define MCF_GPIO_PAR_PSC3_PAR_TXD3 (0x04) -#define MCF_GPIO_PAR_PSC3_PAR_RXD3 (0x08) -#define MCF_GPIO_PAR_PSC3_PAR_RTS3(x) (((x)&0x03)<<4) -#define MCF_GPIO_PAR_PSC3_PAR_CTS3(x) (((x)&0x03)<<6) -#define MCF_GPIO_PAR_PSC3_PAR_CTS3_GPIO (0x00) -#define MCF_GPIO_PAR_PSC3_PAR_CTS3_BCLK (0x80) -#define MCF_GPIO_PAR_PSC3_PAR_CTS3_CTS (0xC0) -#define MCF_GPIO_PAR_PSC3_PAR_RTS3_GPIO (0x00) -#define MCF_GPIO_PAR_PSC3_PAR_RTS3_FSYNC (0x20) -#define MCF_GPIO_PAR_PSC3_PAR_RTS3_RTS (0x30) -#define MCF_GPIO_PAR_PSC3_PAR_CTS2_CANRX (0x40) - -/* Bit definitions and macros for MCF_GPIO_PAR_PSC2 */ -#define MCF_GPIO_PAR_PSC2_PAR_TXD2 (0x04) -#define MCF_GPIO_PAR_PSC2_PAR_RXD2 (0x08) -#define MCF_GPIO_PAR_PSC2_PAR_RTS2(x) (((x)&0x03)<<4) -#define MCF_GPIO_PAR_PSC2_PAR_CTS2(x) (((x)&0x03)<<6) -#define MCF_GPIO_PAR_PSC2_PAR_CTS2_GPIO (0x00) -#define MCF_GPIO_PAR_PSC2_PAR_CTS2_BCLK (0x80) -#define MCF_GPIO_PAR_PSC2_PAR_CTS2_CTS (0xC0) -#define MCF_GPIO_PAR_PSC2_PAR_RTS2_GPIO (0x00) -#define MCF_GPIO_PAR_PSC2_PAR_RTS2_CANTX (0x10) -#define MCF_GPIO_PAR_PSC2_PAR_RTS2_FSYNC (0x20) -#define MCF_GPIO_PAR_PSC2_PAR_RTS2_RTS (0x30) - -/* Bit definitions and macros for MCF_GPIO_PAR_PSC1 */ -#define MCF_GPIO_PAR_PSC1_PAR_TXD1 (0x04) -#define MCF_GPIO_PAR_PSC1_PAR_RXD1 (0x08) -#define MCF_GPIO_PAR_PSC1_PAR_RTS1(x) (((x)&0x03)<<4) -#define MCF_GPIO_PAR_PSC1_PAR_CTS1(x) (((x)&0x03)<<6) -#define MCF_GPIO_PAR_PSC1_PAR_CTS1_GPIO (0x00) -#define MCF_GPIO_PAR_PSC1_PAR_CTS1_BCLK (0x80) -#define MCF_GPIO_PAR_PSC1_PAR_CTS1_CTS (0xC0) -#define MCF_GPIO_PAR_PSC1_PAR_RTS1_GPIO (0x00) -#define MCF_GPIO_PAR_PSC1_PAR_RTS1_FSYNC (0x20) -#define MCF_GPIO_PAR_PSC1_PAR_RTS1_RTS (0x30) - -/* Bit definitions and macros for MCF_GPIO_PAR_PSC0 */ -#define MCF_GPIO_PAR_PSC0_PAR_TXD0 (0x04) -#define MCF_GPIO_PAR_PSC0_PAR_RXD0 (0x08) -#define MCF_GPIO_PAR_PSC0_PAR_RTS0(x) (((x)&0x03)<<4) -#define MCF_GPIO_PAR_PSC0_PAR_CTS0(x) (((x)&0x03)<<6) -#define MCF_GPIO_PAR_PSC0_PAR_CTS0_GPIO (0x00) -#define MCF_GPIO_PAR_PSC0_PAR_CTS0_BCLK (0x80) -#define MCF_GPIO_PAR_PSC0_PAR_CTS0_CTS (0xC0) -#define MCF_GPIO_PAR_PSC0_PAR_RTS0_GPIO (0x00) -#define MCF_GPIO_PAR_PSC0_PAR_RTS0_FSYNC (0x20) -#define MCF_GPIO_PAR_PSC0_PAR_RTS0_RTS (0x30) - -/* Bit definitions and macros for MCF_GPIO_PAR_DSPI */ -#define MCF_GPIO_PAR_DSPI_PAR_SOUT(x) (((x)&0x0003)<<0) -#define MCF_GPIO_PAR_DSPI_PAR_SIN(x) (((x)&0x0003)<<2) -#define MCF_GPIO_PAR_DSPI_PAR_SCK(x) (((x)&0x0003)<<4) -#define MCF_GPIO_PAR_DSPI_PAR_CS0(x) (((x)&0x0003)<<6) -#define MCF_GPIO_PAR_DSPI_PAR_CS2(x) (((x)&0x0003)<<8) -#define MCF_GPIO_PAR_DSPI_PAR_CS3(x) (((x)&0x0003)<<10) -#define MCF_GPIO_PAR_DSPI_PAR_CS5 (0x1000) -#define MCF_GPIO_PAR_DSPI_PAR_CS3_GPIO (0x0000) -#define MCF_GPIO_PAR_DSPI_PAR_CS3_CANTX (0x0400) -#define MCF_GPIO_PAR_DSPI_PAR_CS3_TOUT (0x0800) -#define MCF_GPIO_PAR_DSPI_PAR_CS3_DSPICS (0x0C00) -#define MCF_GPIO_PAR_DSPI_PAR_CS2_GPIO (0x0000) -#define MCF_GPIO_PAR_DSPI_PAR_CS2_CANTX (0x0100) -#define MCF_GPIO_PAR_DSPI_PAR_CS2_TOUT (0x0200) -#define MCF_GPIO_PAR_DSPI_PAR_CS2_DSPICS (0x0300) -#define MCF_GPIO_PAR_DSPI_PAR_CS0_GPIO (0x0000) -#define MCF_GPIO_PAR_DSPI_PAR_CS0_FSYNC (0x0040) -#define MCF_GPIO_PAR_DSPI_PAR_CS0_RTS (0x0080) -#define MCF_GPIO_PAR_DSPI_PAR_CS0_DSPICS (0x00C0) -#define MCF_GPIO_PAR_DSPI_PAR_SCK_GPIO (0x0000) -#define MCF_GPIO_PAR_DSPI_PAR_SCK_BCLK (0x0010) -#define MCF_GPIO_PAR_DSPI_PAR_SCK_CTS (0x0020) -#define MCF_GPIO_PAR_DSPI_PAR_SCK_SCK (0x0030) -#define MCF_GPIO_PAR_DSPI_PAR_SIN_GPIO (0x0000) -#define MCF_GPIO_PAR_DSPI_PAR_SIN_RXD (0x0008) -#define MCF_GPIO_PAR_DSPI_PAR_SIN_SIN (0x000C) -#define MCF_GPIO_PAR_DSPI_PAR_SOUT_GPIO (0x0000) -#define MCF_GPIO_PAR_DSPI_PAR_SOUT_TXD (0x0002) -#define MCF_GPIO_PAR_DSPI_PAR_SOUT_SOUT (0x0003) - -/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */ -#define MCF_GPIO_PAR_TIMER_PAR_TOUT2 (0x01) -#define MCF_GPIO_PAR_TIMER_PAR_TIN2(x) (((x)&0x03)<<1) -#define MCF_GPIO_PAR_TIMER_PAR_TOUT3 (0x08) -#define MCF_GPIO_PAR_TIMER_PAR_TIN3(x) (((x)&0x03)<<4) -#define MCF_GPIO_PAR_TIMER_PAR_TIN3_CANRX (0x00) -#define MCF_GPIO_PAR_TIMER_PAR_TIN3_IRQ (0x20) -#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TIN (0x30) -#define MCF_GPIO_PAR_TIMER_PAR_TIN2_CANRX (0x00) -#define MCF_GPIO_PAR_TIMER_PAR_TIN2_IRQ (0x04) -#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TIN (0x06) - -#endif /* __MCF548X_GPIO_H__ */ diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_gpt.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_gpt.h deleted file mode 100644 index 4ec8fdffca..0000000000 --- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_gpt.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * General Purpose Timers (GPT) - */ -#ifndef __MCF548X_GPT_H__ -#define __MCF548X_GPT_H__ - -/* - * General Purpose Timers (GPT) - */ - -/* Register read/write macros */ -#define MCF_GPT_GMS0 (*(vuint32_t*)(&__MBAR[0x000800])) -#define MCF_GPT_GCIR0 (*(vuint32_t*)(&__MBAR[0x000804])) -#define MCF_GPT_GPWM0 (*(vuint32_t*)(&__MBAR[0x000808])) -#define MCF_GPT_GSR0 (*(vuint32_t*)(&__MBAR[0x00080C])) -#define MCF_GPT_GMS1 (*(vuint32_t*)(&__MBAR[0x000810])) -#define MCF_GPT_GCIR1 (*(vuint32_t*)(&__MBAR[0x000814])) -#define MCF_GPT_GPWM1 (*(vuint32_t*)(&__MBAR[0x000818])) -#define MCF_GPT_GSR1 (*(vuint32_t*)(&__MBAR[0x00081C])) -#define MCF_GPT_GMS2 (*(vuint32_t*)(&__MBAR[0x000820])) -#define MCF_GPT_GCIR2 (*(vuint32_t*)(&__MBAR[0x000824])) -#define MCF_GPT_GPWM2 (*(vuint32_t*)(&__MBAR[0x000828])) -#define MCF_GPT_GSR2 (*(vuint32_t*)(&__MBAR[0x00082C])) -#define MCF_GPT_GMS3 (*(vuint32_t*)(&__MBAR[0x000830])) -#define MCF_GPT_GCIR3 (*(vuint32_t*)(&__MBAR[0x000834])) -#define MCF_GPT_GPWM3 (*(vuint32_t*)(&__MBAR[0x000838])) -#define MCF_GPT_GSR3 (*(vuint32_t*)(&__MBAR[0x00083C])) -#define MCF_GPT_GMS(x) (*(vuint32_t*)(&__MBAR[0x000800+((x)*0x010)])) -#define MCF_GPT_GCIR(x) (*(vuint32_t*)(&__MBAR[0x000804+((x)*0x010)])) -#define MCF_GPT_GPWM(x) (*(vuint32_t*)(&__MBAR[0x000808+((x)*0x010)])) -#define MCF_GPT_GSR(x) (*(vuint32_t*)(&__MBAR[0x00080C+((x)*0x010)])) - -/* Bit definitions and macros for MCF_GPT_GMS */ -#define MCF_GPT_GMS_TMS(x) (((x)&0x00000007)<<0) -#define MCF_GPT_GMS_GPIO(x) (((x)&0x00000003)<<4) -#define MCF_GPT_GMS_IEN (0x00000100) -#define MCF_GPT_GMS_OD (0x00000200) -#define MCF_GPT_GMS_SC (0x00000400) -#define MCF_GPT_GMS_CE (0x00001000) -#define MCF_GPT_GMS_WDEN (0x00008000) -#define MCF_GPT_GMS_ICT(x) (((x)&0x00000003)<<16) -#define MCF_GPT_GMS_OCT(x) (((x)&0x00000003)<<20) -#define MCF_GPT_GMS_OCPW(x) (((x)&0x000000FF)<<24) -#define MCF_GPT_GMS_OCT_FRCLOW (0x00000000) -#define MCF_GPT_GMS_OCT_PULSEHI (0x00100000) -#define MCF_GPT_GMS_OCT_PULSELO (0x00200000) -#define MCF_GPT_GMS_OCT_TOGGLE (0x00300000) -#define MCF_GPT_GMS_ICT_ANY (0x00000000) -#define MCF_GPT_GMS_ICT_RISE (0x00010000) -#define MCF_GPT_GMS_ICT_FALL (0x00020000) -#define MCF_GPT_GMS_ICT_PULSE (0x00030000) -#define MCF_GPT_GMS_GPIO_INPUT (0x00000000) -#define MCF_GPT_GMS_GPIO_OUTLO (0x00000020) -#define MCF_GPT_GMS_GPIO_OUTHI (0x00000030) -#define MCF_GPT_GMS_TMS_DISABLE (0x00000000) -#define MCF_GPT_GMS_TMS_INCAPT (0x00000001) -#define MCF_GPT_GMS_TMS_OUTCAPT (0x00000002) -#define MCF_GPT_GMS_TMS_PWM (0x00000003) -#define MCF_GPT_GMS_TMS_GPIO (0x00000004) - -/* Bit definitions and macros for MCF_GPT_GCIR */ -#define MCF_GPT_GCIR_CNT(x) (((x)&0x0000FFFF)<<0) -#define MCF_GPT_GCIR_PRE(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_GPT_GPWM */ -#define MCF_GPT_GPWM_LOAD (0x00000001) -#define MCF_GPT_GPWM_PWMOP (0x00000100) -#define MCF_GPT_GPWM_WIDTH(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_GPT_GSR */ -#define MCF_GPT_GSR_CAPT (0x00000001) -#define MCF_GPT_GSR_COMP (0x00000002) -#define MCF_GPT_GSR_PWMP (0x00000004) -#define MCF_GPT_GSR_TEXP (0x00000008) -#define MCF_GPT_GSR_PIN (0x00000100) -#define MCF_GPT_GSR_OVF(x) (((x)&0x00000007)<<12) -#define MCF_GPT_GSR_CAPTURE(x) (((x)&0x0000FFFF)<<16) - -#endif /* __MCF548X_GPT_H__ */ diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_i2c.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_i2c.h deleted file mode 100644 index 9f54aaeadb..0000000000 --- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_i2c.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * I2C Module (I2C) - */ -#ifndef __MCF548X_I2C_H__ -#define __MCF548X_I2C_H__ - -/* - * I2C Module (I2C) - */ - -/* Register read/write macros */ -#define MCF_I2C_I2AR (*(vuint8_t *)(&__MBAR[0x008F00])) -#define MCF_I2C_I2FDR (*(vuint8_t *)(&__MBAR[0x008F04])) -#define MCF_I2C_I2CR (*(vuint8_t *)(&__MBAR[0x008F08])) -#define MCF_I2C_I2SR (*(vuint8_t *)(&__MBAR[0x008F0C])) -#define MCF_I2C_I2DR (*(vuint8_t *)(&__MBAR[0x008F10])) -#define MCF_I2C_I2ICR (*(vuint8_t *)(&__MBAR[0x008F20])) - -/* Bit definitions and macros for MCF_I2C_I2AR */ -#define MCF_I2C_I2AR_ADR(x) (((x)&0x7F)<<1) - -/* Bit definitions and macros for MCF_I2C_I2FDR */ -#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0) - -/* Bit definitions and macros for MCF_I2C_I2CR */ -#define MCF_I2C_I2CR_RSTA (0x04) -#define MCF_I2C_I2CR_TXAK (0x08) -#define MCF_I2C_I2CR_MTX (0x10) -#define MCF_I2C_I2CR_MSTA (0x20) -#define MCF_I2C_I2CR_IIEN (0x40) -#define MCF_I2C_I2CR_IEN (0x80) - -/* Bit definitions and macros for MCF_I2C_I2SR */ -#define MCF_I2C_I2SR_RXAK (0x01) -#define MCF_I2C_I2SR_IIF (0x02) -#define MCF_I2C_I2SR_SRW (0x04) -#define MCF_I2C_I2SR_IAL (0x10) -#define MCF_I2C_I2SR_IBB (0x20) -#define MCF_I2C_I2SR_IAAS (0x40) -#define MCF_I2C_I2SR_ICF (0x80) - -/* Bit definitions and macros for MCF_I2C_I2ICR */ -#define MCF_I2C_I2ICR_IE (0x01) -#define MCF_I2C_I2ICR_RE (0x02) -#define MCF_I2C_I2ICR_TE (0x04) -#define MCF_I2C_I2ICR_BNBE (0x08) - -#endif /* __MCF548X_I2C_H__ */ diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_intc.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_intc.h deleted file mode 100644 index fa3a2c9dbe..0000000000 --- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_intc.h +++ /dev/null @@ -1,329 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * Interrupt Controller (INTC) - */ -#ifndef __MCF548X_INTC_H__ -#define __MCF548X_INTC_H__ - -/* - * Interrupt Controller (INTC) - */ - -/* Register read/write macros */ -#define MCF_INTC_IPRH (*(vuint32_t*)(&__MBAR[0x000700])) -#define MCF_INTC_IPRL (*(vuint32_t*)(&__MBAR[0x000704])) -#define MCF_INTC_IMRH (*(vuint32_t*)(&__MBAR[0x000708])) -#define MCF_INTC_IMRL (*(vuint32_t*)(&__MBAR[0x00070C])) -#define MCF_INTC_INTFRCH (*(vuint32_t*)(&__MBAR[0x000710])) -#define MCF_INTC_INTFRCL (*(vuint32_t*)(&__MBAR[0x000714])) -#define MCF_INTC_IRLR (*(vuint8_t *)(&__MBAR[0x000718])) -#define MCF_INTC_IACKLPR (*(vuint8_t *)(&__MBAR[0x000719])) -#define MCF_INTC_ICR0 (*(vuint8_t *)(&__MBAR[0x000740])) -#define MCF_INTC_ICR1 (*(vuint8_t *)(&__MBAR[0x000741])) -#define MCF_INTC_ICR2 (*(vuint8_t *)(&__MBAR[0x000742])) -#define MCF_INTC_ICR3 (*(vuint8_t *)(&__MBAR[0x000743])) -#define MCF_INTC_ICR4 (*(vuint8_t *)(&__MBAR[0x000744])) -#define MCF_INTC_ICR5 (*(vuint8_t *)(&__MBAR[0x000745])) -#define MCF_INTC_ICR6 (*(vuint8_t *)(&__MBAR[0x000746])) -#define MCF_INTC_ICR7 (*(vuint8_t *)(&__MBAR[0x000747])) -#define MCF_INTC_ICR8 (*(vuint8_t *)(&__MBAR[0x000748])) -#define MCF_INTC_ICR9 (*(vuint8_t *)(&__MBAR[0x000749])) -#define MCF_INTC_ICR10 (*(vuint8_t *)(&__MBAR[0x00074A])) -#define MCF_INTC_ICR11 (*(vuint8_t *)(&__MBAR[0x00074B])) -#define MCF_INTC_ICR12 (*(vuint8_t *)(&__MBAR[0x00074C])) -#define MCF_INTC_ICR13 (*(vuint8_t *)(&__MBAR[0x00074D])) -#define MCF_INTC_ICR14 (*(vuint8_t *)(&__MBAR[0x00074E])) -#define MCF_INTC_ICR15 (*(vuint8_t *)(&__MBAR[0x00074F])) -#define MCF_INTC_ICR16 (*(vuint8_t *)(&__MBAR[0x000750])) -#define MCF_INTC_ICR17 (*(vuint8_t *)(&__MBAR[0x000751])) -#define MCF_INTC_ICR18 (*(vuint8_t *)(&__MBAR[0x000752])) -#define MCF_INTC_ICR19 (*(vuint8_t *)(&__MBAR[0x000753])) -#define MCF_INTC_ICR20 (*(vuint8_t *)(&__MBAR[0x000754])) -#define MCF_INTC_ICR21 (*(vuint8_t *)(&__MBAR[0x000755])) -#define MCF_INTC_ICR22 (*(vuint8_t *)(&__MBAR[0x000756])) -#define MCF_INTC_ICR23 (*(vuint8_t *)(&__MBAR[0x000757])) -#define MCF_INTC_ICR24 (*(vuint8_t *)(&__MBAR[0x000758])) -#define MCF_INTC_ICR25 (*(vuint8_t *)(&__MBAR[0x000759])) -#define MCF_INTC_ICR26 (*(vuint8_t *)(&__MBAR[0x00075A])) -#define MCF_INTC_ICR27 (*(vuint8_t *)(&__MBAR[0x00075B])) -#define MCF_INTC_ICR28 (*(vuint8_t *)(&__MBAR[0x00075C])) -#define MCF_INTC_ICR29 (*(vuint8_t *)(&__MBAR[0x00075D])) -#define MCF_INTC_ICR30 (*(vuint8_t *)(&__MBAR[0x00075E])) -#define MCF_INTC_ICR31 (*(vuint8_t *)(&__MBAR[0x00075F])) -#define MCF_INTC_ICR32 (*(vuint8_t *)(&__MBAR[0x000760])) -#define MCF_INTC_ICR33 (*(vuint8_t *)(&__MBAR[0x000761])) -#define MCF_INTC_ICR34 (*(vuint8_t *)(&__MBAR[0x000762])) -#define MCF_INTC_ICR35 (*(vuint8_t *)(&__MBAR[0x000763])) -#define MCF_INTC_ICR36 (*(vuint8_t *)(&__MBAR[0x000764])) -#define MCF_INTC_ICR37 (*(vuint8_t *)(&__MBAR[0x000765])) -#define MCF_INTC_ICR38 (*(vuint8_t *)(&__MBAR[0x000766])) -#define MCF_INTC_ICR39 (*(vuint8_t *)(&__MBAR[0x000767])) -#define MCF_INTC_ICR40 (*(vuint8_t *)(&__MBAR[0x000768])) -#define MCF_INTC_ICR41 (*(vuint8_t *)(&__MBAR[0x000769])) -#define MCF_INTC_ICR42 (*(vuint8_t *)(&__MBAR[0x00076A])) -#define MCF_INTC_ICR43 (*(vuint8_t *)(&__MBAR[0x00076B])) -#define MCF_INTC_ICR44 (*(vuint8_t *)(&__MBAR[0x00076C])) -#define MCF_INTC_ICR45 (*(vuint8_t *)(&__MBAR[0x00076D])) -#define MCF_INTC_ICR46 (*(vuint8_t *)(&__MBAR[0x00076E])) -#define MCF_INTC_ICR47 (*(vuint8_t *)(&__MBAR[0x00076F])) -#define MCF_INTC_ICR48 (*(vuint8_t *)(&__MBAR[0x000770])) -#define MCF_INTC_ICR49 (*(vuint8_t *)(&__MBAR[0x000771])) -#define MCF_INTC_ICR50 (*(vuint8_t *)(&__MBAR[0x000772])) -#define MCF_INTC_ICR51 (*(vuint8_t *)(&__MBAR[0x000773])) -#define MCF_INTC_ICR52 (*(vuint8_t *)(&__MBAR[0x000774])) -#define MCF_INTC_ICR53 (*(vuint8_t *)(&__MBAR[0x000775])) -#define MCF_INTC_ICR54 (*(vuint8_t *)(&__MBAR[0x000776])) -#define MCF_INTC_ICR55 (*(vuint8_t *)(&__MBAR[0x000777])) -#define MCF_INTC_ICR56 (*(vuint8_t *)(&__MBAR[0x000778])) -#define MCF_INTC_ICR57 (*(vuint8_t *)(&__MBAR[0x000779])) -#define MCF_INTC_ICR58 (*(vuint8_t *)(&__MBAR[0x00077A])) -#define MCF_INTC_ICR59 (*(vuint8_t *)(&__MBAR[0x00077B])) -#define MCF_INTC_ICR60 (*(vuint8_t *)(&__MBAR[0x00077C])) -#define MCF_INTC_ICR61 (*(vuint8_t *)(&__MBAR[0x00077D])) -#define MCF_INTC_ICR62 (*(vuint8_t *)(&__MBAR[0x00077E])) -#define MCF_INTC_ICR63 (*(vuint8_t *)(&__MBAR[0x00077F])) -#define MCF_INTC_ICRn(x) (*(vuint8_t *)(&__MBAR[0x000740+((x)*0x001)])) -#define MCF_INTC_SWIACK (*(vuint8_t *)(&__MBAR[0x0007E0])) -#define MCF_INTC_L1IACK (*(vuint8_t *)(&__MBAR[0x0007E4])) -#define MCF_INTC_L2IACK (*(vuint8_t *)(&__MBAR[0x0007E8])) -#define MCF_INTC_L3IACK (*(vuint8_t *)(&__MBAR[0x0007EC])) -#define MCF_INTC_L4IACK (*(vuint8_t *)(&__MBAR[0x0007F0])) -#define MCF_INTC_L5IACK (*(vuint8_t *)(&__MBAR[0x0007F4])) -#define MCF_INTC_L6IACK (*(vuint8_t *)(&__MBAR[0x0007F8])) -#define MCF_INTC_L7IACK (*(vuint8_t *)(&__MBAR[0x0007FC])) -#define MCF_INTC_LnIACK(x) (*(vuint8_t *)(&__MBAR[0x0007E4+((x)*0x004)])) - -/* Bit definitions and macros for MCF_INTC_IPRH */ -#define MCF_INTC_IPRH_INT32 (0x00000001) -#define MCF_INTC_IPRH_INT33 (0x00000002) -#define MCF_INTC_IPRH_INT34 (0x00000004) -#define MCF_INTC_IPRH_INT35 (0x00000008) -#define MCF_INTC_IPRH_INT36 (0x00000010) -#define MCF_INTC_IPRH_INT37 (0x00000020) -#define MCF_INTC_IPRH_INT38 (0x00000040) -#define MCF_INTC_IPRH_INT39 (0x00000080) -#define MCF_INTC_IPRH_INT40 (0x00000100) -#define MCF_INTC_IPRH_INT41 (0x00000200) -#define MCF_INTC_IPRH_INT42 (0x00000400) -#define MCF_INTC_IPRH_INT43 (0x00000800) -#define MCF_INTC_IPRH_INT44 (0x00001000) -#define MCF_INTC_IPRH_INT45 (0x00002000) -#define MCF_INTC_IPRH_INT46 (0x00004000) -#define MCF_INTC_IPRH_INT47 (0x00008000) -#define MCF_INTC_IPRH_INT48 (0x00010000) -#define MCF_INTC_IPRH_INT49 (0x00020000) -#define MCF_INTC_IPRH_INT50 (0x00040000) -#define MCF_INTC_IPRH_INT51 (0x00080000) -#define MCF_INTC_IPRH_INT52 (0x00100000) -#define MCF_INTC_IPRH_INT53 (0x00200000) -#define MCF_INTC_IPRH_INT54 (0x00400000) -#define MCF_INTC_IPRH_INT55 (0x00800000) -#define MCF_INTC_IPRH_INT56 (0x01000000) -#define MCF_INTC_IPRH_INT57 (0x02000000) -#define MCF_INTC_IPRH_INT58 (0x04000000) -#define MCF_INTC_IPRH_INT59 (0x08000000) -#define MCF_INTC_IPRH_INT60 (0x10000000) -#define MCF_INTC_IPRH_INT61 (0x20000000) -#define MCF_INTC_IPRH_INT62 (0x40000000) -#define MCF_INTC_IPRH_INT63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_IPRL */ -#define MCF_INTC_IPRL_INT1 (0x00000002) -#define MCF_INTC_IPRL_INT2 (0x00000004) -#define MCF_INTC_IPRL_INT3 (0x00000008) -#define MCF_INTC_IPRL_INT4 (0x00000010) -#define MCF_INTC_IPRL_INT5 (0x00000020) -#define MCF_INTC_IPRL_INT6 (0x00000040) -#define MCF_INTC_IPRL_INT7 (0x00000080) -#define MCF_INTC_IPRL_INT8 (0x00000100) -#define MCF_INTC_IPRL_INT9 (0x00000200) -#define MCF_INTC_IPRL_INT10 (0x00000400) -#define MCF_INTC_IPRL_INT11 (0x00000800) -#define MCF_INTC_IPRL_INT12 (0x00001000) -#define MCF_INTC_IPRL_INT13 (0x00002000) -#define MCF_INTC_IPRL_INT14 (0x00004000) -#define MCF_INTC_IPRL_INT15 (0x00008000) -#define MCF_INTC_IPRL_INT16 (0x00010000) -#define MCF_INTC_IPRL_INT17 (0x00020000) -#define MCF_INTC_IPRL_INT18 (0x00040000) -#define MCF_INTC_IPRL_INT19 (0x00080000) -#define MCF_INTC_IPRL_INT20 (0x00100000) -#define MCF_INTC_IPRL_INT21 (0x00200000) -#define MCF_INTC_IPRL_INT22 (0x00400000) -#define MCF_INTC_IPRL_INT23 (0x00800000) -#define MCF_INTC_IPRL_INT24 (0x01000000) -#define MCF_INTC_IPRL_INT25 (0x02000000) -#define MCF_INTC_IPRL_INT26 (0x04000000) -#define MCF_INTC_IPRL_INT27 (0x08000000) -#define MCF_INTC_IPRL_INT28 (0x10000000) -#define MCF_INTC_IPRL_INT29 (0x20000000) -#define MCF_INTC_IPRL_INT30 (0x40000000) -#define MCF_INTC_IPRL_INT31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_IMRH */ -#define MCF_INTC_IMRH_INT_MASK32 (0x00000001) -#define MCF_INTC_IMRH_INT_MASK33 (0x00000002) -#define MCF_INTC_IMRH_INT_MASK34 (0x00000004) -#define MCF_INTC_IMRH_INT_MASK35 (0x00000008) -#define MCF_INTC_IMRH_INT_MASK36 (0x00000010) -#define MCF_INTC_IMRH_INT_MASK37 (0x00000020) -#define MCF_INTC_IMRH_INT_MASK38 (0x00000040) -#define MCF_INTC_IMRH_INT_MASK39 (0x00000080) -#define MCF_INTC_IMRH_INT_MASK40 (0x00000100) -#define MCF_INTC_IMRH_INT_MASK41 (0x00000200) -#define MCF_INTC_IMRH_INT_MASK42 (0x00000400) -#define MCF_INTC_IMRH_INT_MASK43 (0x00000800) -#define MCF_INTC_IMRH_INT_MASK44 (0x00001000) -#define MCF_INTC_IMRH_INT_MASK45 (0x00002000) -#define MCF_INTC_IMRH_INT_MASK46 (0x00004000) -#define MCF_INTC_IMRH_INT_MASK47 (0x00008000) -#define MCF_INTC_IMRH_INT_MASK48 (0x00010000) -#define MCF_INTC_IMRH_INT_MASK49 (0x00020000) -#define MCF_INTC_IMRH_INT_MASK50 (0x00040000) -#define MCF_INTC_IMRH_INT_MASK51 (0x00080000) -#define MCF_INTC_IMRH_INT_MASK52 (0x00100000) -#define MCF_INTC_IMRH_INT_MASK53 (0x00200000) -#define MCF_INTC_IMRH_INT_MASK54 (0x00400000) -#define MCF_INTC_IMRH_INT_MASK55 (0x00800000) -#define MCF_INTC_IMRH_INT_MASK56 (0x01000000) -#define MCF_INTC_IMRH_INT_MASK57 (0x02000000) -#define MCF_INTC_IMRH_INT_MASK58 (0x04000000) -#define MCF_INTC_IMRH_INT_MASK59 (0x08000000) -#define MCF_INTC_IMRH_INT_MASK60 (0x10000000) -#define MCF_INTC_IMRH_INT_MASK61 (0x20000000) -#define MCF_INTC_IMRH_INT_MASK62 (0x40000000) -#define MCF_INTC_IMRH_INT_MASK63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_IMRL */ -#define MCF_INTC_IMRL_MASKALL (0x00000001) -#define MCF_INTC_IMRL_INT_MASK1 (0x00000002) -#define MCF_INTC_IMRL_INT_MASK2 (0x00000004) -#define MCF_INTC_IMRL_INT_MASK3 (0x00000008) -#define MCF_INTC_IMRL_INT_MASK4 (0x00000010) -#define MCF_INTC_IMRL_INT_MASK5 (0x00000020) -#define MCF_INTC_IMRL_INT_MASK6 (0x00000040) -#define MCF_INTC_IMRL_INT_MASK7 (0x00000080) -#define MCF_INTC_IMRL_INT_MASK8 (0x00000100) -#define MCF_INTC_IMRL_INT_MASK9 (0x00000200) -#define MCF_INTC_IMRL_INT_MASK10 (0x00000400) -#define MCF_INTC_IMRL_INT_MASK11 (0x00000800) -#define MCF_INTC_IMRL_INT_MASK12 (0x00001000) -#define MCF_INTC_IMRL_INT_MASK13 (0x00002000) -#define MCF_INTC_IMRL_INT_MASK14 (0x00004000) -#define MCF_INTC_IMRL_INT_MASK15 (0x00008000) -#define MCF_INTC_IMRL_INT_MASK16 (0x00010000) -#define MCF_INTC_IMRL_INT_MASK17 (0x00020000) -#define MCF_INTC_IMRL_INT_MASK18 (0x00040000) -#define MCF_INTC_IMRL_INT_MASK19 (0x00080000) -#define MCF_INTC_IMRL_INT_MASK20 (0x00100000) -#define MCF_INTC_IMRL_INT_MASK21 (0x00200000) -#define MCF_INTC_IMRL_INT_MASK22 (0x00400000) -#define MCF_INTC_IMRL_INT_MASK23 (0x00800000) -#define MCF_INTC_IMRL_INT_MASK24 (0x01000000) -#define MCF_INTC_IMRL_INT_MASK25 (0x02000000) -#define MCF_INTC_IMRL_INT_MASK26 (0x04000000) -#define MCF_INTC_IMRL_INT_MASK27 (0x08000000) -#define MCF_INTC_IMRL_INT_MASK28 (0x10000000) -#define MCF_INTC_IMRL_INT_MASK29 (0x20000000) -#define MCF_INTC_IMRL_INT_MASK30 (0x40000000) -#define MCF_INTC_IMRL_INT_MASK31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_INTFRCH */ -#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001) -#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002) -#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004) -#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008) -#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010) -#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020) -#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040) -#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080) -#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100) -#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200) -#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400) -#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800) -#define MCF_INTC_INTFRCH_INTFRC44 (0x00001000) -#define MCF_INTC_INTFRCH_INTFRC45 (0x00002000) -#define MCF_INTC_INTFRCH_INTFRC46 (0x00004000) -#define MCF_INTC_INTFRCH_INTFRC47 (0x00008000) -#define MCF_INTC_INTFRCH_INTFRC48 (0x00010000) -#define MCF_INTC_INTFRCH_INTFRC49 (0x00020000) -#define MCF_INTC_INTFRCH_INTFRC50 (0x00040000) -#define MCF_INTC_INTFRCH_INTFRC51 (0x00080000) -#define MCF_INTC_INTFRCH_INTFRC52 (0x00100000) -#define MCF_INTC_INTFRCH_INTFRC53 (0x00200000) -#define MCF_INTC_INTFRCH_INTFRC54 (0x00400000) -#define MCF_INTC_INTFRCH_INTFRC55 (0x00800000) -#define MCF_INTC_INTFRCH_INTFRC56 (0x01000000) -#define MCF_INTC_INTFRCH_INTFRC57 (0x02000000) -#define MCF_INTC_INTFRCH_INTFRC58 (0x04000000) -#define MCF_INTC_INTFRCH_INTFRC59 (0x08000000) -#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000) -#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000) -#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000) -#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_INTFRCL */ -#define MCF_INTC_INTFRCL_INTFRC1 (0x00000002) -#define MCF_INTC_INTFRCL_INTFRC2 (0x00000004) -#define MCF_INTC_INTFRCL_INTFRC3 (0x00000008) -#define MCF_INTC_INTFRCL_INTFRC4 (0x00000010) -#define MCF_INTC_INTFRCL_INTFRC5 (0x00000020) -#define MCF_INTC_INTFRCL_INT6 (0x00000040) -#define MCF_INTC_INTFRCL_INT7 (0x00000080) -#define MCF_INTC_INTFRCL_INT8 (0x00000100) -#define MCF_INTC_INTFRCL_INT9 (0x00000200) -#define MCF_INTC_INTFRCL_INT10 (0x00000400) -#define MCF_INTC_INTFRCL_INTFRC11 (0x00000800) -#define MCF_INTC_INTFRCL_INTFRC12 (0x00001000) -#define MCF_INTC_INTFRCL_INTFRC13 (0x00002000) -#define MCF_INTC_INTFRCL_INTFRC14 (0x00004000) -#define MCF_INTC_INTFRCL_INT15 (0x00008000) -#define MCF_INTC_INTFRCL_INTFRC16 (0x00010000) -#define MCF_INTC_INTFRCL_INTFRC17 (0x00020000) -#define MCF_INTC_INTFRCL_INTFRC18 (0x00040000) -#define MCF_INTC_INTFRCL_INTFRC19 (0x00080000) -#define MCF_INTC_INTFRCL_INTFRC20 (0x00100000) -#define MCF_INTC_INTFRCL_INTFRC21 (0x00200000) -#define MCF_INTC_INTFRCL_INTFRC22 (0x00400000) -#define MCF_INTC_INTFRCL_INTFRC23 (0x00800000) -#define MCF_INTC_INTFRCL_INTFRC24 (0x01000000) -#define MCF_INTC_INTFRCL_INTFRC25 (0x02000000) -#define MCF_INTC_INTFRCL_INTFRC26 (0x04000000) -#define MCF_INTC_INTFRCL_INTFRC27 (0x08000000) -#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000) -#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000) -#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000) -#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_IRLR */ -#define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<1) - -/* Bit definitions and macros for MCF_INTC_IACKLPR */ -#define MCF_INTC_IACKLPR_PRI(x) (((x)&0x0F)<<0) -#define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x07)<<4) - -/* Bit definitions and macros for MCF_INTC_ICRn */ -#define MCF_INTC_ICRn_IP(x) (((x)&0x07)<<0) -#define MCF_INTC_ICRn_IL(x) (((x)&0x07)<<3) - -#endif /* __MCF548X_INTC_H__ */ diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_pci.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_pci.h deleted file mode 100644 index 23c6743133..0000000000 --- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_pci.h +++ /dev/null @@ -1,349 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * PCI Bus Controller (PCI) - */ -#ifndef __MCF548X_PCI_H__ -#define __MCF548X_PCI_H__ - -/* - * PCI Bus Controller (PCI) - */ -#define MCF_PCI_HDR_BASE (&__MBAR[0x000B00]) - -/* Register read/write macros */ - -/* type 0 header */ -#define MCF_PCI_PCIIDR (*(vuint32_t*)(&__MBAR[0x000B00])) -#define MCF_PCI_PCISCR (*(vuint32_t*)(&__MBAR[0x000B04])) -#define MCF_PCI_PCICCRIR (*(vuint32_t*)(&__MBAR[0x000B08])) -#define MCF_PCI_PCICR1 (*(vuint32_t*)(&__MBAR[0x000B0C])) -#define MCF_PCI_PCIBAR0 (*(vuint32_t*)(&__MBAR[0x000B10])) -#define MCF_PCI_PCIBAR1 (*(vuint32_t*)(&__MBAR[0x000B14])) -#define MCF_PCI_PCISID (*(vuint32_t*)(&__MBAR[0x000B2c])) -#define MCF_PCI_PCICR2 (*(vuint32_t*)(&__MBAR[0x000B3C])) - -/* Target Controls */ -#define MCF_PCI_PCIGSCR (*(vuint32_t*)(&__MBAR[0x000B60])) -#define MCF_PCI_PCITBATR0 (*(vuint32_t*)(&__MBAR[0x000B64])) -#define MCF_PCI_PCITBATR1 (*(vuint32_t*)(&__MBAR[0x000B68])) -#define MCF_PCI_PCITCR (*(vuint32_t*)(&__MBAR[0x000B6C])) -#define MCF_PCI_PCIIW0BTAR (*(vuint32_t*)(&__MBAR[0x000B70])) -#define MCF_PCI_PCIIW1BTAR (*(vuint32_t*)(&__MBAR[0x000B74])) -#define MCF_PCI_PCIIW2BTAR (*(vuint32_t*)(&__MBAR[0x000B78])) -#define MCF_PCI_PCIIWCR (*(vuint32_t*)(&__MBAR[0x000B80])) -#define MCF_PCI_PCIICR (*(vuint32_t*)(&__MBAR[0x000B84])) -#define MCF_PCI_PCIISR (*(vuint32_t*)(&__MBAR[0x000B88])) -#define MCF_PCI_PCICAR (*(vuint32_t*)(&__MBAR[0x000BF8])) -#define MCF_PCI_PCITPSR (*(vuint32_t*)(&__MBAR[0x008400])) -#define MCF_PCI_PCITSAR (*(vuint32_t*)(&__MBAR[0x008404])) -#define MCF_PCI_PCITTCR (*(vuint32_t*)(&__MBAR[0x008408])) -#define MCF_PCI_PCITER (*(vuint32_t*)(&__MBAR[0x00840C])) -#define MCF_PCI_PCITNAR (*(vuint32_t*)(&__MBAR[0x008410])) -#define MCF_PCI_PCITLWR (*(vuint32_t*)(&__MBAR[0x008414])) -#define MCF_PCI_PCITDCR (*(vuint32_t*)(&__MBAR[0x008418])) -#define MCF_PCI_PCITSR (*(vuint32_t*)(&__MBAR[0x00841C])) -#define MCF_PCI_PCITFDR (*(vuint32_t*)(&__MBAR[0x008440])) -#define MCF_PCI_PCITFSR (*(vuint32_t*)(&__MBAR[0x008444])) -#define MCF_PCI_PCITFCR (*(vuint32_t*)(&__MBAR[0x008448])) -#define MCF_PCI_PCITFAR (*(vuint32_t*)(&__MBAR[0x00844C])) -#define MCF_PCI_PCITFRPR (*(vuint32_t*)(&__MBAR[0x008450])) -#define MCF_PCI_PCITFWPR (*(vuint32_t*)(&__MBAR[0x008454])) -#define MCF_PCI_PCIRPSR (*(vuint32_t*)(&__MBAR[0x008480])) -#define MCF_PCI_PCIRSAR (*(vuint32_t*)(&__MBAR[0x008484])) -#define MCF_PCI_PCIRTCR (*(vuint32_t*)(&__MBAR[0x008488])) -#define MCF_PCI_PCIRER (*(vuint32_t*)(&__MBAR[0x00848C])) -#define MCF_PCI_PCIRNAR (*(vuint32_t*)(&__MBAR[0x008490])) -#define MCF_PCI_PCIRDCR (*(vuint32_t*)(&__MBAR[0x008498])) -#define MCF_PCI_PCIRSR (*(vuint32_t*)(&__MBAR[0x00849C])) -#define MCF_PCI_PCIRFDR (*(vuint32_t*)(&__MBAR[0x0084C0])) -#define MCF_PCI_PCIRFSR (*(vuint32_t*)(&__MBAR[0x0084C4])) -#define MCF_PCI_PCIRFCR (*(vuint32_t*)(&__MBAR[0x0084C8])) -#define MCF_PCI_PCIRFAR (*(vuint32_t*)(&__MBAR[0x0084CC])) -#define MCF_PCI_PCIRFRPR (*(vuint32_t*)(&__MBAR[0x0084D0])) -#define MCF_PCI_PCIRFWPR (*(vuint32_t*)(&__MBAR[0x0084D4])) - - -/* - * Type 0 Config Header Regs - */ - -/* Bit definitions and macros for MCF_PCI_PCIIDR */ -#define MCF_PCI_PCIIDR_VENDORID(x) (((x)&0x0000FFFF)<<0) -#define MCF_PCI_PCIIDR_DEVICEID(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_PCI_PCISCR */ -#define MCF_PCI_PCISCR_M (0x00000002) -#define MCF_PCI_PCISCR_B (0x00000004) -#define MCF_PCI_PCISCR_SP (0x00000008) -#define MCF_PCI_PCISCR_MW (0x00000010) -#define MCF_PCI_PCISCR_PER (0x00000040) -#define MCF_PCI_PCISCR_S (0x00000100) -#define MCF_PCI_PCISCR_F (0x00000200) -#define MCF_PCI_PCISCR_C (0x00100000) -#define MCF_PCI_PCISCR_66M (0x00200000) -#define MCF_PCI_PCISCR_R (0x00400000) -#define MCF_PCI_PCISCR_FC (0x00800000) -#define MCF_PCI_PCISCR_DP (0x01000000) -#define MCF_PCI_PCISCR_DT(x) (((x)&0x00000003)<<25) -#define MCF_PCI_PCISCR_TS (0x08000000) -#define MCF_PCI_PCISCR_TR (0x10000000) -#define MCF_PCI_PCISCR_MA (0x20000000) -#define MCF_PCI_PCISCR_SE (0x40000000) -#define MCF_PCI_PCISCR_PE (0x80000000) - -/* Bit definitions and macros for MCF_PCI_PCICCRIR */ -#define MCF_PCI_PCICCRIR_REVID(x) (((x)&0x000000FF)<<0) -#define MCF_PCI_PCICCRIR_CLASSCODE(x) (((x)&0x00FFFFFF)<<8) - -/* Bit definitions and macros for MCF_PCI_PCICR1 */ -#define MCF_PCI_PCICR1_CACHELINESIZE(x) (((x)&0x0000000F)<<0) -#define MCF_PCI_PCICR1_LATTIMER(x) (((x)&0x000000FF)<<8) -#define MCF_PCI_PCICR1_HEADERTYPE(x) (((x)&0x000000FF)<<16) -#define MCF_PCI_PCICR1_BIST(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_PCI_PCIBAR0 */ -#define MCF_PCI_PCIBAR0_IO (0x00000001) -#define MCF_PCI_PCIBAR0_RANGE(x) (((x)&0x00000003)<<1) -#define MCF_PCI_PCIBAR0_PREF (0x00000008) -#define MCF_PCI_PCIBAR0_BAR0(x) (((x)&0x00003FFF)<<18) - -/* Bit definitions and macros for MCF_PCI_PCIBAR1 */ -#define MCF_PCI_PCIBAR1_IO (0x00000001) -#define MCF_PCI_PCIBAR1_PREF (0x00000008) -#define MCF_PCI_PCIBAR1_BAR1(x) (((x)&0x00000003)<<30) - -/* Bit definitions and macros for MCF_PCI_PCICR2 */ -#define MCF_PCI_PCICR2_INTLINE(x) (((x)&0x000000FF)<<0) -#define MCF_PCI_PCICR2_INTPIN(x) (((x)&0x000000FF)<<8) -#define MCF_PCI_PCICR2_MINGNT(x) (((x)&0x000000FF)<<16) -#define MCF_PCI_PCICR2_MAXLAT(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_PCI_PCIGSCR */ -#define MCF_PCI_PCIGSCR_PR (0x00000001) -#define MCF_PCI_PCIGSCR_SEE (0x00001000) -#define MCF_PCI_PCIGSCR_PEE (0x00002000) -#define MCF_PCI_PCIGSCR_SE (0x10000000) -#define MCF_PCI_PCIGSCR_PE (0x20000000) - -/* - * Target device controls - */ - -/* Bit definitions and macros for MCF_PCI_PCITBATR0 */ -#define MCF_PCI_PCITBATR0_EN (0x00000001) -#define MCF_PCI_PCITBATR0_BAT0(x) (((x)&0x00003FFF)<<18) - -/* Bit definitions and macros for MCF_PCI_PCITBATR1 */ -#define MCF_PCI_PCITBATR1_EN (0x00000001) -#define MCF_PCI_PCITBATR1_BAT1(x) (((x)&0x00000003)<<30) - -/* Bit definitions and macros for MCF_PCI_PCITCR */ -#define MCF_PCI_PCITCR_P (0x00010000) -#define MCF_PCI_PCITCR_LD (0x01000000) - -/* Bit definitions and macros for MCF_PCI_PCIIW0BTAR */ -#define MCF_PCI_PCIIW0BTAR_WTA0(x) (((x)&0x000000FF)<<8) -#define MCF_PCI_PCIIW0BTAR_WAM0(x) (((x)&0x000000FF)<<16) -#define MCF_PCI_PCIIW0BTAR_WBA0(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_PCI_PCIIW1BTAR */ -#define MCF_PCI_PCIIW1BTAR_WTA1(x) (((x)&0x000000FF)<<8) -#define MCF_PCI_PCIIW1BTAR_WAM1(x) (((x)&0x000000FF)<<16) -#define MCF_PCI_PCIIW1BTAR_WBA1(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_PCI_PCIIW2BTAR */ -#define MCF_PCI_PCIIW2BTAR_WTA2(x) (((x)&0x000000FF)<<8) -#define MCF_PCI_PCIIW2BTAR_WAM2(x) (((x)&0x000000FF)<<16) -#define MCF_PCI_PCIIW2BTAR_WBA2(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_PCI_PCIIWCR */ -#define MCF_PCI_PCIIWCR_WINCTRL2(x) (((x)&0x0000000F)<<8) -#define MCF_PCI_PCIIWCR_WINCTRL1(x) (((x)&0x0000000F)<<16) -#define MCF_PCI_PCIIWCR_WINCTRL0(x) (((x)&0x0000000F)<<24) -#define MCF_PCI_PCIIWCR_WINCTRL0_MEMREAD (0x01000000) -#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE (0x03000000) -#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDMUL (0x05000000) -#define MCF_PCI_PCIIWCR_WINCTRL0_IO (0x09000000) -#define MCF_PCI_PCIIWCR_WINCTRL1_MEMREAD (0x00010000) -#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDLINE (0x00030000) -#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDMUL (0x00050000) -#define MCF_PCI_PCIIWCR_WINCTRL1_IO (0x00090000) -#define MCF_PCI_PCIIWCR_WINCTRL2_MEMREAD (0x00000100) -#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDLINE (0x00000300) -#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDMUL (0x00000500) -#define MCF_PCI_PCIIWCR_WINCTRL2_IO (0x00000900) - -/* Bit definitions and macros for MCF_PCI_PCIICR */ -#define MCF_PCI_PCIICR_MAXRETRY(x) (((x)&0x000000FF)<<0) -#define MCF_PCI_PCIICR_TAE (0x01000000) -#define MCF_PCI_PCIICR_IAE (0x02000000) -#define MCF_PCI_PCIICR_REE (0x04000000) - -/* Bit definitions and macros for MCF_PCI_PCIISR */ -#define MCF_PCI_PCIISR_TA (0x01000000) -#define MCF_PCI_PCIISR_IA (0x02000000) -#define MCF_PCI_PCIISR_RE (0x04000000) - -/* Bit definitions and macros for MCF_PCI_PCICAR */ -#define MCF_PCI_PCICAR_DWORD(x) (((x)&0x0000003F)<<2) -#define MCF_PCI_PCICAR_FUNCNUM(x) (((x)&0x00000007)<<8) -#define MCF_PCI_PCICAR_DEVNUM(x) (((x)&0x0000001F)<<11) -#define MCF_PCI_PCICAR_BUSNUM(x) (((x)&0x000000FF)<<16) -#define MCF_PCI_PCICAR_E (0x80000000) - - -/* - * PCI Fifos - */ - -/* Bit definitions and macros for MCF_PCI_PCITPSR */ -#define MCF_PCI_PCITPSR_PKTSIZE(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_PCI_PCITTCR */ -#define MCF_PCI_PCITTCR_DI (0x00000001) -#define MCF_PCI_PCITTCR_W (0x00000010) -#define MCF_PCI_PCITTCR_MAXBEATS(x) (((x)&0x00000007)<<8) -#define MCF_PCI_PCITTCR_MAXRETRY(x) (((x)&0x000000FF)<<16) -#define MCF_PCI_PCITTCR_PCICMD(x) (((x)&0x0000000F)<<24) - -/* Bit definitions and macros for MCF_PCI_PCITER */ -#define MCF_PCI_PCITER_NE (0x00010000) -#define MCF_PCI_PCITER_IAE (0x00020000) -#define MCF_PCI_PCITER_TAE (0x00040000) -#define MCF_PCI_PCITER_RE (0x00080000) -#define MCF_PCI_PCITER_SE (0x00100000) -#define MCF_PCI_PCITER_FEE (0x00200000) -#define MCF_PCI_PCITER_ME (0x01000000) -#define MCF_PCI_PCITER_BE (0x08000000) -#define MCF_PCI_PCITER_CM (0x10000000) -#define MCF_PCI_PCITER_RF (0x40000000) -#define MCF_PCI_PCITER_RC (0x80000000) - -/* Bit definitions and macros for MCF_PCI_PCITDCR */ -#define MCF_PCI_PCITDCR_PKTSDONE(x) (((x)&0x0000FFFF)<<0) -#define MCF_PCI_PCITDCR_BYTESDONE(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_PCI_PCITSR */ -#define MCF_PCI_PCITSR_IA (0x00010000) -#define MCF_PCI_PCITSR_TA (0x00020000) -#define MCF_PCI_PCITSR_RE (0x00040000) -#define MCF_PCI_PCITSR_SE (0x00080000) -#define MCF_PCI_PCITSR_FE (0x00100000) -#define MCF_PCI_PCITSR_BE1 (0x00200000) -#define MCF_PCI_PCITSR_BE2 (0x00400000) -#define MCF_PCI_PCITSR_BE3 (0x00800000) -#define MCF_PCI_PCITSR_NT (0x01000000) - -/* Bit definitions and macros for MCF_PCI_PCITFSR */ -#define MCF_PCI_PCITFSR_EMT (0x00010000) -#define MCF_PCI_PCITFSR_ALARM (0x00020000) -#define MCF_PCI_PCITFSR_FU (0x00040000) -#define MCF_PCI_PCITFSR_FR (0x00080000) -#define MCF_PCI_PCITFSR_OF (0x00100000) -#define MCF_PCI_PCITFSR_UF (0x00200000) -#define MCF_PCI_PCITFSR_RXW (0x00400000) - -/* Bit definitions and macros for MCF_PCI_PCITFCR */ -#define MCF_PCI_PCITFCR_OF_MSK (0x00080000) -#define MCF_PCI_PCITFCR_UF_MSK (0x00100000) -#define MCF_PCI_PCITFCR_RXW_MSK (0x00200000) -#define MCF_PCI_PCITFCR_FAE_MSK (0x00400000) -#define MCF_PCI_PCITFCR_IP_MSK (0x00800000) -#define MCF_PCI_PCITFCR_GR(x) (((x)&0x00000007)<<24) - -/* Bit definitions and macros for MCF_PCI_PCITFAR */ -#define MCF_PCI_PCITFAR_ALARM(x) (((x)&0x0000007F)<<0) - -/* Bit definitions and macros for MCF_PCI_PCITFRPR */ -#define MCF_PCI_PCITFRPR_READ(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_PCI_PCITFWPR */ -#define MCF_PCI_PCITFWPR_WRITE(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_PCI_PCIRPSR */ -#define MCF_PCI_PCIRPSR_PKTSIZE(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_PCI_PCIRTCR */ -#define MCF_PCI_PCIRTCR_DI (0x00000001) -#define MCF_PCI_PCIRTCR_W (0x00000010) -#define MCF_PCI_PCIRTCR_MAXBEATS(x) (((x)&0x00000007)<<8) -#define MCF_PCI_PCIRTCR_FB (0x00001000) -#define MCF_PCI_PCIRTCR_MAXRETRY(x) (((x)&0x000000FF)<<16) -#define MCF_PCI_PCIRTCR_PCICMD(x) (((x)&0x0000000F)<<24) - -/* Bit definitions and macros for MCF_PCI_PCIRER */ -#define MCF_PCI_PCIRER_NE (0x00010000) -#define MCF_PCI_PCIRER_IAE (0x00020000) -#define MCF_PCI_PCIRER_TAE (0x00040000) -#define MCF_PCI_PCIRER_RE (0x00080000) -#define MCF_PCI_PCIRER_SE (0x00100000) -#define MCF_PCI_PCIRER_FEE (0x00200000) -#define MCF_PCI_PCIRER_ME (0x01000000) -#define MCF_PCI_PCIRER_BE (0x08000000) -#define MCF_PCI_PCIRER_CM (0x10000000) -#define MCF_PCI_PCIRER_FE (0x20000000) -#define MCF_PCI_PCIRER_RF (0x40000000) -#define MCF_PCI_PCIRER_RC (0x80000000) - -/* Bit definitions and macros for MCF_PCI_PCIRDCR */ -#define MCF_PCI_PCIRDCR_PKTSDONE(x) (((x)&0x0000FFFF)<<0) -#define MCF_PCI_PCIRDCR_BYTESDONE(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_PCI_PCIRSR */ -#define MCF_PCI_PCIRSR_IA (0x00010000) -#define MCF_PCI_PCIRSR_TA (0x00020000) -#define MCF_PCI_PCIRSR_RE (0x00040000) -#define MCF_PCI_PCIRSR_SE (0x00080000) -#define MCF_PCI_PCIRSR_FE (0x00100000) -#define MCF_PCI_PCIRSR_BE1 (0x00200000) -#define MCF_PCI_PCIRSR_BE2 (0x00400000) -#define MCF_PCI_PCIRSR_BE3 (0x00800000) -#define MCF_PCI_PCIRSR_NT (0x01000000) - -/* Bit definitions and macros for MCF_PCI_PCIRFSR */ -#define MCF_PCI_PCIRFSR_EMT (0x00010000) -#define MCF_PCI_PCIRFSR_ALARM (0x00020000) -#define MCF_PCI_PCIRFSR_FU (0x00040000) -#define MCF_PCI_PCIRFSR_FR (0x00080000) -#define MCF_PCI_PCIRFSR_OF (0x00100000) -#define MCF_PCI_PCIRFSR_UF (0x00200000) -#define MCF_PCI_PCIRFSR_RXW (0x00400000) - -/* Bit definitions and macros for MCF_PCI_PCIRFCR */ -#define MCF_PCI_PCIRFCR_OF_MSK (0x00080000) -#define MCF_PCI_PCIRFCR_UF_MSK (0x00100000) -#define MCF_PCI_PCIRFCR_RXW_MSK (0x00200000) -#define MCF_PCI_PCIRFCR_FAE_MSK (0x00400000) -#define MCF_PCI_PCIRFCR_IP_MSK (0x00800000) -#define MCF_PCI_PCIRFCR_GR(x) (((x)&0x00000007)<<24) - -/* Bit definitions and macros for MCF_PCI_PCIRFAR */ -#define MCF_PCI_PCIRFAR_ALARM(x) (((x)&0x0000007F)<<0) - -/* Bit definitions and macros for MCF_PCI_PCIRFRPR */ -#define MCF_PCI_PCIRFRPR_READ(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_PCI_PCIRFWPR */ -#define MCF_PCI_PCIRFWPR_WRITE(x) (((x)&0x00000FFF)<<0) - -#endif /* __MCF548X_PCI_H__ */ diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_pciarb.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_pciarb.h deleted file mode 100644 index 8c11647300..0000000000 --- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_pciarb.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * PCI Arbiter Module (PCIARB) - */ -#ifndef __MCF548X_PCIARB_H__ -#define __MCF548X_PCIARB_H__ - -/* - * PCI Arbiter Module (PCIARB) - */ - -/* Register read/write macros */ -#define MCF_PCIARB_PACR (*(vuint32_t*)(&__MBAR[0x000C00])) -#define MCF_PCIARB_PASR (*(vuint32_t*)(&__MBAR[0x000C04])) - -/* Bit definitions and macros for MCF_PCIARB_PACR */ -#define MCF_PCIARB_PACR_INTMPRI (0x00000001) -#define MCF_PCIARB_PACR_EXTMPRI(x) (((x)&0x0000001F)<<1) -#define MCF_PCIARB_PACR_INTMINTEN (0x00010000) -#define MCF_PCIARB_PACR_EXTMINTEN(x) (((x)&0x0000001F)<<17) -/* Not documented! - * #define MCF_PCIARB_PACR_PKMD (0x40000000) - */ -#define MCF_PCIARB_PACR_DS (0x80000000) - -/* Bit definitions and macros for MCF_PCIARB_PASR */ -#define MCF_PCIARB_PASR_ITLMBK (0x00010000) -#define MCF_PCIARB_PASR_EXTMBK(x) (((x)&0x0000001F)<<17) - -#endif /* __MCF548X_PCIARB_H__ */ diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_psc.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_psc.h deleted file mode 100644 index c685af8240..0000000000 --- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_psc.h +++ /dev/null @@ -1,486 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * Programmable Serial Controller (PSC) - */ -#ifndef __MCF548X_PSC_H__ -#define __MCF548X_PSC_H__ - -/* - * Programmable Serial Controller (PSC) - */ - -/* Register read/write macros */ -#define MCF_PSC_MR0 (*(vuint8_t *)(&__MBAR[0x008600])) -#define MCF_PSC_SR0 (*(vuint16_t*)(&__MBAR[0x008604])) -#define MCF_PSC_CSR0 (*(vuint8_t *)(&__MBAR[0x008604])) -#define MCF_PSC_CR0 (*(vuint8_t *)(&__MBAR[0x008608])) -#define MCF_PSC_RB0 (*(vuint32_t*)(&__MBAR[0x00860C])) -#define MCF_PSC_TB0 (*(vuint32_t*)(&__MBAR[0x00860C])) -#define MCF_PSC_TB_8BIT0 (*(vuint32_t*)(&__MBAR[0x00860C])) -#define MCF_PSC_TB_16BIT0 (*(vuint32_t*)(&__MBAR[0x00860C])) -#define MCF_PSC_TB_AC970 (*(vuint32_t*)(&__MBAR[0x00860C])) -#define MCF_PSC_IPCR0 (*(vuint8_t *)(&__MBAR[0x008610])) -#define MCF_PSC_ACR0 (*(vuint8_t *)(&__MBAR[0x008610])) -#define MCF_PSC_ISR0 (*(vuint16_t*)(&__MBAR[0x008614])) -#define MCF_PSC_IMR0 (*(vuint16_t*)(&__MBAR[0x008614])) -#define MCF_PSC_CTUR0 (*(vuint8_t *)(&__MBAR[0x008618])) -#define MCF_PSC_CTLR0 (*(vuint8_t *)(&__MBAR[0x00861C])) -#define MCF_PSC_IP0 (*(vuint8_t *)(&__MBAR[0x008634])) -#define MCF_PSC_OPSET0 (*(vuint8_t *)(&__MBAR[0x008638])) -#define MCF_PSC_OPRESET0 (*(vuint8_t *)(&__MBAR[0x00863C])) -#define MCF_PSC_SICR0 (*(vuint8_t *)(&__MBAR[0x008640])) -#define MCF_PSC_IRCR10 (*(vuint8_t *)(&__MBAR[0x008644])) -#define MCF_PSC_IRCR20 (*(vuint8_t *)(&__MBAR[0x008648])) -#define MCF_PSC_IRSDR0 (*(vuint8_t *)(&__MBAR[0x00864C])) -#define MCF_PSC_IRMDR0 (*(vuint8_t *)(&__MBAR[0x008650])) -#define MCF_PSC_IRFDR0 (*(vuint8_t *)(&__MBAR[0x008654])) -#define MCF_PSC_RFCNT0 (*(vuint16_t*)(&__MBAR[0x008658])) -#define MCF_PSC_TFCNT0 (*(vuint16_t*)(&__MBAR[0x00865C])) -#define MCF_PSC_RFSR0 (*(vuint16_t*)(&__MBAR[0x008664])) -#define MCF_PSC_TFSR0 (*(vuint16_t*)(&__MBAR[0x008684])) -#define MCF_PSC_RFCR0 (*(vuint32_t*)(&__MBAR[0x008668])) -#define MCF_PSC_TFCR0 (*(vuint32_t*)(&__MBAR[0x008688])) -#define MCF_PSC_RFAR0 (*(vuint16_t*)(&__MBAR[0x00866E])) -#define MCF_PSC_TFAR0 (*(vuint16_t*)(&__MBAR[0x00868E])) -#define MCF_PSC_RFRP0 (*(vuint16_t*)(&__MBAR[0x008672])) -#define MCF_PSC_TFRP0 (*(vuint16_t*)(&__MBAR[0x008692])) -#define MCF_PSC_RFWP0 (*(vuint16_t*)(&__MBAR[0x008676])) -#define MCF_PSC_TFWP0 (*(vuint16_t*)(&__MBAR[0x008696])) -#define MCF_PSC_RLRFP0 (*(vuint16_t*)(&__MBAR[0x00867A])) -#define MCF_PSC_TLRFP0 (*(vuint16_t*)(&__MBAR[0x00869A])) -#define MCF_PSC_RLWFP0 (*(vuint16_t*)(&__MBAR[0x00867E])) -#define MCF_PSC_TLWFP0 (*(vuint16_t*)(&__MBAR[0x00869E])) -#define MCF_PSC_MR1 (*(vuint8_t *)(&__MBAR[0x008700])) -#define MCF_PSC_SR1 (*(vuint16_t*)(&__MBAR[0x008704])) -#define MCF_PSC_CSR1 (*(vuint8_t *)(&__MBAR[0x008704])) -#define MCF_PSC_CR1 (*(vuint8_t *)(&__MBAR[0x008708])) -#define MCF_PSC_RB1 (*(vuint32_t*)(&__MBAR[0x00870C])) -#define MCF_PSC_TB1 (*(vuint32_t*)(&__MBAR[0x00870C])) -#define MCF_PSC_TB_8BIT1 (*(vuint32_t*)(&__MBAR[0x00870C])) -#define MCF_PSC_TB_16BIT1 (*(vuint32_t*)(&__MBAR[0x00870C])) -#define MCF_PSC_TB_AC971 (*(vuint32_t*)(&__MBAR[0x00870C])) -#define MCF_PSC_IPCR1 (*(vuint8_t *)(&__MBAR[0x008710])) -#define MCF_PSC_ACR1 (*(vuint8_t *)(&__MBAR[0x008710])) -#define MCF_PSC_ISR1 (*(vuint16_t*)(&__MBAR[0x008714])) -#define MCF_PSC_IMR1 (*(vuint16_t*)(&__MBAR[0x008714])) -#define MCF_PSC_CTUR1 (*(vuint8_t *)(&__MBAR[0x008718])) -#define MCF_PSC_CTLR1 (*(vuint8_t *)(&__MBAR[0x00871C])) -#define MCF_PSC_IP1 (*(vuint8_t *)(&__MBAR[0x008734])) -#define MCF_PSC_OPSET1 (*(vuint8_t *)(&__MBAR[0x008738])) -#define MCF_PSC_OPRESET1 (*(vuint8_t *)(&__MBAR[0x00873C])) -#define MCF_PSC_SICR1 (*(vuint8_t *)(&__MBAR[0x008740])) -#define MCF_PSC_IRCR11 (*(vuint8_t *)(&__MBAR[0x008744])) -#define MCF_PSC_IRCR21 (*(vuint8_t *)(&__MBAR[0x008748])) -#define MCF_PSC_IRSDR1 (*(vuint8_t *)(&__MBAR[0x00874C])) -#define MCF_PSC_IRMDR1 (*(vuint8_t *)(&__MBAR[0x008750])) -#define MCF_PSC_IRFDR1 (*(vuint8_t *)(&__MBAR[0x008754])) -#define MCF_PSC_RFCNT1 (*(vuint16_t*)(&__MBAR[0x008758])) -#define MCF_PSC_TFCNT1 (*(vuint16_t*)(&__MBAR[0x00875C])) -#define MCF_PSC_RFSR1 (*(vuint16_t*)(&__MBAR[0x008764])) -#define MCF_PSC_TFSR1 (*(vuint16_t*)(&__MBAR[0x008784])) -#define MCF_PSC_RFCR1 (*(vuint32_t*)(&__MBAR[0x008768])) -#define MCF_PSC_TFCR1 (*(vuint32_t*)(&__MBAR[0x008788])) -#define MCF_PSC_RFAR1 (*(vuint16_t*)(&__MBAR[0x00876E])) -#define MCF_PSC_TFAR1 (*(vuint16_t*)(&__MBAR[0x00878E])) -#define MCF_PSC_RFRP1 (*(vuint16_t*)(&__MBAR[0x008772])) -#define MCF_PSC_TFRP1 (*(vuint16_t*)(&__MBAR[0x008792])) -#define MCF_PSC_RFWP1 (*(vuint16_t*)(&__MBAR[0x008776])) -#define MCF_PSC_TFWP1 (*(vuint16_t*)(&__MBAR[0x008796])) -#define MCF_PSC_RLRFP1 (*(vuint16_t*)(&__MBAR[0x00877A])) -#define MCF_PSC_TLRFP1 (*(vuint16_t*)(&__MBAR[0x00879A])) -#define MCF_PSC_RLWFP1 (*(vuint16_t*)(&__MBAR[0x00877E])) -#define MCF_PSC_TLWFP1 (*(vuint16_t*)(&__MBAR[0x00879E])) -#define MCF_PSC_MR2 (*(vuint8_t *)(&__MBAR[0x008800])) -#define MCF_PSC_SR2 (*(vuint16_t*)(&__MBAR[0x008804])) -#define MCF_PSC_CSR2 (*(vuint8_t *)(&__MBAR[0x008804])) -#define MCF_PSC_CR2 (*(vuint8_t *)(&__MBAR[0x008808])) -#define MCF_PSC_RB2 (*(vuint32_t*)(&__MBAR[0x00880C])) -#define MCF_PSC_TB2 (*(vuint32_t*)(&__MBAR[0x00880C])) -#define MCF_PSC_TB_8BIT2 (*(vuint32_t*)(&__MBAR[0x00880C])) -#define MCF_PSC_TB_16BIT2 (*(vuint32_t*)(&__MBAR[0x00880C])) -#define MCF_PSC_TB_AC972 (*(vuint32_t*)(&__MBAR[0x00880C])) -#define MCF_PSC_IPCR2 (*(vuint8_t *)(&__MBAR[0x008810])) -#define MCF_PSC_ACR2 (*(vuint8_t *)(&__MBAR[0x008810])) -#define MCF_PSC_ISR2 (*(vuint16_t*)(&__MBAR[0x008814])) -#define MCF_PSC_IMR2 (*(vuint16_t*)(&__MBAR[0x008814])) -#define MCF_PSC_CTUR2 (*(vuint8_t *)(&__MBAR[0x008818])) -#define MCF_PSC_CTLR2 (*(vuint8_t *)(&__MBAR[0x00881C])) -#define MCF_PSC_IP2 (*(vuint8_t *)(&__MBAR[0x008834])) -#define MCF_PSC_OPSET2 (*(vuint8_t *)(&__MBAR[0x008838])) -#define MCF_PSC_OPRESET2 (*(vuint8_t *)(&__MBAR[0x00883C])) -#define MCF_PSC_SICR2 (*(vuint8_t *)(&__MBAR[0x008840])) -#define MCF_PSC_IRCR12 (*(vuint8_t *)(&__MBAR[0x008844])) -#define MCF_PSC_IRCR22 (*(vuint8_t *)(&__MBAR[0x008848])) -#define MCF_PSC_IRSDR2 (*(vuint8_t *)(&__MBAR[0x00884C])) -#define MCF_PSC_IRMDR2 (*(vuint8_t *)(&__MBAR[0x008850])) -#define MCF_PSC_IRFDR2 (*(vuint8_t *)(&__MBAR[0x008854])) -#define MCF_PSC_RFCNT2 (*(vuint16_t*)(&__MBAR[0x008858])) -#define MCF_PSC_TFCNT2 (*(vuint16_t*)(&__MBAR[0x00885C])) -#define MCF_PSC_RFSR2 (*(vuint16_t*)(&__MBAR[0x008864])) -#define MCF_PSC_TFSR2 (*(vuint16_t*)(&__MBAR[0x008884])) -#define MCF_PSC_RFCR2 (*(vuint32_t*)(&__MBAR[0x008868])) -#define MCF_PSC_TFCR2 (*(vuint32_t*)(&__MBAR[0x008888])) -#define MCF_PSC_RFAR2 (*(vuint16_t*)(&__MBAR[0x00886E])) -#define MCF_PSC_TFAR2 (*(vuint16_t*)(&__MBAR[0x00888E])) -#define MCF_PSC_RFRP2 (*(vuint16_t*)(&__MBAR[0x008872])) -#define MCF_PSC_TFRP2 (*(vuint16_t*)(&__MBAR[0x008892])) -#define MCF_PSC_RFWP2 (*(vuint16_t*)(&__MBAR[0x008876])) -#define MCF_PSC_TFWP2 (*(vuint16_t*)(&__MBAR[0x008896])) -#define MCF_PSC_RLRFP2 (*(vuint16_t*)(&__MBAR[0x00887A])) -#define MCF_PSC_TLRFP2 (*(vuint16_t*)(&__MBAR[0x00889A])) -#define MCF_PSC_RLWFP2 (*(vuint16_t*)(&__MBAR[0x00887E])) -#define MCF_PSC_TLWFP2 (*(vuint16_t*)(&__MBAR[0x00889E])) -#define MCF_PSC_MR3 (*(vuint8_t *)(&__MBAR[0x008900])) -#define MCF_PSC_SR3 (*(vuint16_t*)(&__MBAR[0x008904])) -#define MCF_PSC_CSR3 (*(vuint8_t *)(&__MBAR[0x008904])) -#define MCF_PSC_CR3 (*(vuint8_t *)(&__MBAR[0x008908])) -#define MCF_PSC_RB3 (*(vuint32_t*)(&__MBAR[0x00890C])) -#define MCF_PSC_TB3 (*(vuint32_t*)(&__MBAR[0x00890C])) -#define MCF_PSC_TB_8BIT3 (*(vuint32_t*)(&__MBAR[0x00890C])) -#define MCF_PSC_TB_16BIT3 (*(vuint32_t*)(&__MBAR[0x00890C])) -#define MCF_PSC_TB_AC973 (*(vuint32_t*)(&__MBAR[0x00890C])) -#define MCF_PSC_IPCR3 (*(vuint8_t *)(&__MBAR[0x008910])) -#define MCF_PSC_ACR3 (*(vuint8_t *)(&__MBAR[0x008910])) -#define MCF_PSC_ISR3 (*(vuint16_t*)(&__MBAR[0x008914])) -#define MCF_PSC_IMR3 (*(vuint16_t*)(&__MBAR[0x008914])) -#define MCF_PSC_CTUR3 (*(vuint8_t *)(&__MBAR[0x008918])) -#define MCF_PSC_CTLR3 (*(vuint8_t *)(&__MBAR[0x00891C])) -#define MCF_PSC_IP3 (*(vuint8_t *)(&__MBAR[0x008934])) -#define MCF_PSC_OPSET3 (*(vuint8_t *)(&__MBAR[0x008938])) -#define MCF_PSC_OPRESET3 (*(vuint8_t *)(&__MBAR[0x00893C])) -#define MCF_PSC_SICR3 (*(vuint8_t *)(&__MBAR[0x008940])) -#define MCF_PSC_IRCR13 (*(vuint8_t *)(&__MBAR[0x008944])) -#define MCF_PSC_IRCR23 (*(vuint8_t *)(&__MBAR[0x008948])) -#define MCF_PSC_IRSDR3 (*(vuint8_t *)(&__MBAR[0x00894C])) -#define MCF_PSC_IRMDR3 (*(vuint8_t *)(&__MBAR[0x008950])) -#define MCF_PSC_IRFDR3 (*(vuint8_t *)(&__MBAR[0x008954])) -#define MCF_PSC_RFCNT3 (*(vuint16_t*)(&__MBAR[0x008958])) -#define MCF_PSC_TFCNT3 (*(vuint16_t*)(&__MBAR[0x00895C])) -#define MCF_PSC_RFSR3 (*(vuint16_t*)(&__MBAR[0x008964])) -#define MCF_PSC_TFSR3 (*(vuint16_t*)(&__MBAR[0x008984])) -#define MCF_PSC_RFCR3 (*(vuint32_t*)(&__MBAR[0x008968])) -#define MCF_PSC_TFCR3 (*(vuint32_t*)(&__MBAR[0x008988])) -#define MCF_PSC_RFAR3 (*(vuint16_t*)(&__MBAR[0x00896E])) -#define MCF_PSC_TFAR3 (*(vuint16_t*)(&__MBAR[0x00898E])) -#define MCF_PSC_RFRP3 (*(vuint16_t*)(&__MBAR[0x008972])) -#define MCF_PSC_TFRP3 (*(vuint16_t*)(&__MBAR[0x008992])) -#define MCF_PSC_RFWP3 (*(vuint16_t*)(&__MBAR[0x008976])) -#define MCF_PSC_TFWP3 (*(vuint16_t*)(&__MBAR[0x008996])) -#define MCF_PSC_RLRFP3 (*(vuint16_t*)(&__MBAR[0x00897A])) -#define MCF_PSC_TLRFP3 (*(vuint16_t*)(&__MBAR[0x00899A])) -#define MCF_PSC_RLWFP3 (*(vuint16_t*)(&__MBAR[0x00897E])) -#define MCF_PSC_TLWFP3 (*(vuint16_t*)(&__MBAR[0x00899E])) -#define MCF_PSC_MR(x) (*(vuint8_t *)(&__MBAR[0x008600+((x)*0x100)])) -#define MCF_PSC_SR(x) (*(vuint16_t*)(&__MBAR[0x008604+((x)*0x100)])) -#define MCF_PSC_CSR(x) (*(vuint8_t *)(&__MBAR[0x008604+((x)*0x100)])) -#define MCF_PSC_CR(x) (*(vuint8_t *)(&__MBAR[0x008608+((x)*0x100)])) -#define MCF_PSC_RB(x) (*(vuint32_t*)(&__MBAR[0x00860C+((x)*0x100)])) -#define MCF_PSC_TB(x) (*(vuint32_t*)(&__MBAR[0x00860C+((x)*0x100)])) -#define MCF_PSC_TB_8BIT(x) (*(vuint32_t*)(&__MBAR[0x00860C+((x)*0x100)])) -#define MCF_PSC_TB_16BIT(x) (*(vuint32_t*)(&__MBAR[0x00860C+((x)*0x100)])) -#define MCF_PSC_TB_AC97(x) (*(vuint32_t*)(&__MBAR[0x00860C+((x)*0x100)])) -#define MCF_PSC_IPCR(x) (*(vuint8_t *)(&__MBAR[0x008610+((x)*0x100)])) -#define MCF_PSC_ACR(x) (*(vuint8_t *)(&__MBAR[0x008610+((x)*0x100)])) -#define MCF_PSC_ISR(x) (*(vuint16_t*)(&__MBAR[0x008614+((x)*0x100)])) -#define MCF_PSC_IMR(x) (*(vuint16_t*)(&__MBAR[0x008614+((x)*0x100)])) -#define MCF_PSC_CTUR(x) (*(vuint8_t *)(&__MBAR[0x008618+((x)*0x100)])) -#define MCF_PSC_CTLR(x) (*(vuint8_t *)(&__MBAR[0x00861C+((x)*0x100)])) -#define MCF_PSC_IP(x) (*(vuint8_t *)(&__MBAR[0x008634+((x)*0x100)])) -#define MCF_PSC_OPSET(x) (*(vuint8_t *)(&__MBAR[0x008638+((x)*0x100)])) -#define MCF_PSC_OPRESET(x) (*(vuint8_t *)(&__MBAR[0x00863C+((x)*0x100)])) -#define MCF_PSC_SICR(x) (*(vuint8_t *)(&__MBAR[0x008640+((x)*0x100)])) -#define MCF_PSC_IRCR1(x) (*(vuint8_t *)(&__MBAR[0x008644+((x)*0x100)])) -#define MCF_PSC_IRCR2(x) (*(vuint8_t *)(&__MBAR[0x008648+((x)*0x100)])) -#define MCF_PSC_IRSDR(x) (*(vuint8_t *)(&__MBAR[0x00864C+((x)*0x100)])) -#define MCF_PSC_IRMDR(x) (*(vuint8_t *)(&__MBAR[0x008650+((x)*0x100)])) -#define MCF_PSC_IRFDR(x) (*(vuint8_t *)(&__MBAR[0x008654+((x)*0x100)])) -#define MCF_PSC_RFCNT(x) (*(vuint16_t*)(&__MBAR[0x008658+((x)*0x100)])) -#define MCF_PSC_TFCNT(x) (*(vuint16_t*)(&__MBAR[0x00865C+((x)*0x100)])) -#define MCF_PSC_RFSR(x) (*(vuint16_t*)(&__MBAR[0x008664+((x)*0x100)])) -#define MCF_PSC_TFSR(x) (*(vuint16_t*)(&__MBAR[0x008684+((x)*0x100)])) -#define MCF_PSC_RFCR(x) (*(vuint32_t*)(&__MBAR[0x008668+((x)*0x100)])) -#define MCF_PSC_TFCR(x) (*(vuint32_t*)(&__MBAR[0x008688+((x)*0x100)])) -#define MCF_PSC_RFAR(x) (*(vuint16_t*)(&__MBAR[0x00866E+((x)*0x100)])) -#define MCF_PSC_TFAR(x) (*(vuint16_t*)(&__MBAR[0x00868E+((x)*0x100)])) -#define MCF_PSC_RFRP(x) (*(vuint16_t*)(&__MBAR[0x008672+((x)*0x100)])) -#define MCF_PSC_TFRP(x) (*(vuint16_t*)(&__MBAR[0x008692+((x)*0x100)])) -#define MCF_PSC_RFWP(x) (*(vuint16_t*)(&__MBAR[0x008676+((x)*0x100)])) -#define MCF_PSC_TFWP(x) (*(vuint16_t*)(&__MBAR[0x008696+((x)*0x100)])) -#define MCF_PSC_RLRFP(x) (*(vuint16_t*)(&__MBAR[0x00867A+((x)*0x100)])) -#define MCF_PSC_TLRFP(x) (*(vuint16_t*)(&__MBAR[0x00869A+((x)*0x100)])) -#define MCF_PSC_RLWFP(x) (*(vuint16_t*)(&__MBAR[0x00867E+((x)*0x100)])) -#define MCF_PSC_TLWFP(x) (*(vuint16_t*)(&__MBAR[0x00869E+((x)*0x100)])) - -/* Bit definitions and macros for MCF_PSC_MR */ -#define MCF_PSC_MR_BC(x) (((x)&0x03)<<0) -#define MCF_PSC_MR_PT (0x04) -#define MCF_PSC_MR_PM(x) (((x)&0x03)<<3) -#define MCF_PSC_MR_ERR (0x20) -#define MCF_PSC_MR_RXIRQ (0x40) -#define MCF_PSC_MR_RXRTS (0x80) -#define MCF_PSC_MR_SB(x) (((x)&0x0F)<<0) -#define MCF_PSC_MR_TXCTS (0x10) -#define MCF_PSC_MR_TXRTS (0x20) -#define MCF_PSC_MR_CM(x) (((x)&0x03)<<6) -#define MCF_PSC_MR_PM_MULTI_ADDR (0x1C) -#define MCF_PSC_MR_PM_MULTI_DATA (0x18) -#define MCF_PSC_MR_PM_NONE (0x10) -#define MCF_PSC_MR_PM_FORCE_HI (0x0C) -#define MCF_PSC_MR_PM_FORCE_LO (0x08) -#define MCF_PSC_MR_PM_ODD (0x04) -#define MCF_PSC_MR_PM_EVEN (0x00) -#define MCF_PSC_MR_BC_5 (0x00) -#define MCF_PSC_MR_BC_6 (0x01) -#define MCF_PSC_MR_BC_7 (0x02) -#define MCF_PSC_MR_BC_8 (0x03) -#define MCF_PSC_MR_CM_NORMAL (0x00) -#define MCF_PSC_MR_CM_ECHO (0x40) -#define MCF_PSC_MR_CM_LOCAL_LOOP (0x80) -#define MCF_PSC_MR_CM_REMOTE_LOOP (0xC0) -#define MCF_PSC_MR_SB_STOP_BITS_1 (0x07) -#define MCF_PSC_MR_SB_STOP_BITS_15 (0x08) -#define MCF_PSC_MR_SB_STOP_BITS_2 (0x0F) - -/* Bit definitions and macros for MCF_PSC_SR */ -#define MCF_PSC_SR_ERR (0x0040) -#define MCF_PSC_SR_CDE_DEOF (0x0080) -#define MCF_PSC_SR_RXRDY (0x0100) -#define MCF_PSC_SR_FU (0x0200) -#define MCF_PSC_SR_TXRDY (0x0400) -#define MCF_PSC_SR_TXEMP_URERR (0x0800) -#define MCF_PSC_SR_OE (0x1000) -#define MCF_PSC_SR_PE_CRCERR (0x2000) -#define MCF_PSC_SR_FE_PHYERR (0x4000) -#define MCF_PSC_SR_RB_NEOF (0x8000) - -/* Bit definitions and macros for MCF_PSC_CSR */ -#define MCF_PSC_CSR_TCSEL(x) (((x)&0x0F)<<0) -#define MCF_PSC_CSR_RCSEL(x) (((x)&0x0F)<<4) -#define MCF_PSC_CSR_RCSEL_SYS_CLK (0xD0) -#define MCF_PSC_CSR_RCSEL_CTM16 (0xE0) -#define MCF_PSC_CSR_RCSEL_CTM (0xF0) -#define MCF_PSC_CSR_TCSEL_SYS_CLK (0x0D) -#define MCF_PSC_CSR_TCSEL_CTM16 (0x0E) -#define MCF_PSC_CSR_TCSEL_CTM (0x0F) - -/* Bit definitions and macros for MCF_PSC_CR */ -#define MCF_PSC_CR_RXC(x) (((x)&0x03)<<0) -#define MCF_PSC_CR_TXC(x) (((x)&0x03)<<2) -#define MCF_PSC_CR_MISC(x) (((x)&0x07)<<4) -#define MCF_PSC_CR_NONE (0x00) -#define MCF_PSC_CR_STOP_BREAK (0x70) -#define MCF_PSC_CR_START_BREAK (0x60) -#define MCF_PSC_CR_BKCHGINT (0x50) -#define MCF_PSC_CR_RESET_ERROR (0x40) -#define MCF_PSC_CR_RESET_TX (0x30) -#define MCF_PSC_CR_RESET_RX (0x20) -#define MCF_PSC_CR_RESET_MR (0x10) -#define MCF_PSC_CR_TX_DISABLED (0x08) -#define MCF_PSC_CR_TX_ENABLED (0x04) -#define MCF_PSC_CR_RX_DISABLED (0x02) -#define MCF_PSC_CR_RX_ENABLED (0x01) - -/* Bit definitions and macros for MCF_PSC_TB_8BIT */ -#define MCF_PSC_TB_8BIT_TB3(x) (((x)&0x000000FF)<<0) -#define MCF_PSC_TB_8BIT_TB2(x) (((x)&0x000000FF)<<8) -#define MCF_PSC_TB_8BIT_TB1(x) (((x)&0x000000FF)<<16) -#define MCF_PSC_TB_8BIT_TB0(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_PSC_TB_16BIT */ -#define MCF_PSC_TB_16BIT_TB1(x) (((x)&0x0000FFFF)<<0) -#define MCF_PSC_TB_16BIT_TB0(x) (((x)&0x0000FFFF)<<16) - -/* Bit definitions and macros for MCF_PSC_TB_AC97 */ -#define MCF_PSC_TB_AC97_SOF (0x00000800) -#define MCF_PSC_TB_AC97_TB(x) (((x)&0x000FFFFF)<<12) - -/* Bit definitions and macros for MCF_PSC_IPCR */ -#define MCF_PSC_IPCR_RESERVED (0x0C) -#define MCF_PSC_IPCR_CTS (0x0D) -#define MCF_PSC_IPCR_D_CTS (0x1C) -#define MCF_PSC_IPCR_SYNC (0x8C) - -/* Bit definitions and macros for MCF_PSC_ACR */ -#define MCF_PSC_ACR_IEC0 (0x01) -#define MCF_PSC_ACR_CTMS(x) (((x)&0x07)<<4) -#define MCF_PSC_ACR_BRG (0x80) - -/* Bit definitions and macros for MCF_PSC_ISR */ -#define MCF_PSC_ISR_ERR (0x0040) -#define MCF_PSC_ISR_DEOF (0x0080) -#define MCF_PSC_ISR_TXRDY (0x0100) -#define MCF_PSC_ISR_RXRDY_FU (0x0200) -#define MCF_PSC_ISR_DB (0x0400) -#define MCF_PSC_ISR_IPC (0x8000) - -/* Bit definitions and macros for MCF_PSC_IMR */ -#define MCF_PSC_IMR_ERR (0x0040) -#define MCF_PSC_IMR_DEOF (0x0080) -#define MCF_PSC_IMR_TXRDY (0x0100) -#define MCF_PSC_IMR_RXRDY_FU (0x0200) -#define MCF_PSC_IMR_DB (0x0400) -#define MCF_PSC_IMR_IPC (0x8000) - -/* Bit definitions and macros for MCF_PSC_IP */ -#define MCF_PSC_IP_CTS (0x01) -#define MCF_PSC_IP_TGL (0x40) -#define MCF_PSC_IP_LWPR_B (0x80) - -/* Bit definitions and macros for MCF_PSC_OPSET */ -#define MCF_PSC_OPSET_RTS (0x01) - -/* Bit definitions and macros for MCF_PSC_OPRESET */ -#define MCF_PSC_OPRESET_RTS (0x01) - -/* Bit definitions and macros for MCF_PSC_SICR */ -#define MCF_PSC_SICR_SIM(x) (((x)&0x07)<<0) -#define MCF_PSC_SICR_SHDIR (0x10) -#define MCF_PSC_SICR_DTS (0x20) -#define MCF_PSC_SICR_AWR (0x40) -#define MCF_PSC_SICR_ACRB (0x80) -#define MCF_PSC_SICR_SIM_UART (0x00) -#define MCF_PSC_SICR_SIM_MODEM8 (0x01) -#define MCF_PSC_SICR_SIM_MODEM16 (0x02) -#define MCF_PSC_SICR_SIM_AC97 (0x03) -#define MCF_PSC_SICR_SIM_SIR (0x04) -#define MCF_PSC_SICR_SIM_MIR (0x05) -#define MCF_PSC_SICR_SIM_FIR (0x06) - -/* Bit definitions and macros for MCF_PSC_IRCR1 */ -#define MCF_PSC_IRCR1_SPUL (0x01) -#define MCF_PSC_IRCR1_SIPEN (0x02) -#define MCF_PSC_IRCR1_FD (0x04) - -/* Bit definitions and macros for MCF_PSC_IRCR2 */ -#define MCF_PSC_IRCR2_NXTEOF (0x01) -#define MCF_PSC_IRCR2_ABORT (0x02) -#define MCF_PSC_IRCR2_SIPREQ (0x04) - -/* Bit definitions and macros for MCF_PSC_IRMDR */ -#define MCF_PSC_IRMDR_M_FDIV(x) (((x)&0x7F)<<0) -#define MCF_PSC_IRMDR_FREQ (0x80) - -/* Bit definitions and macros for MCF_PSC_IRFDR */ -#define MCF_PSC_IRFDR_F_FDIV(x) (((x)&0x0F)<<0) - -/* Bit definitions and macros for MCF_PSC_RFCNT */ -#define MCF_PSC_RFCNT_CNT(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF_PSC_TFCNT */ -#define MCF_PSC_TFCNT_CNT(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF_PSC_RFSR */ -#define MCF_PSC_RFSR_EMT (0x0001) -#define MCF_PSC_RFSR_ALARM (0x0002) -#define MCF_PSC_RFSR_FU (0x0004) -#define MCF_PSC_RFSR_FRMRY (0x0008) -#define MCF_PSC_RFSR_OF (0x0010) -#define MCF_PSC_RFSR_UF (0x0020) -#define MCF_PSC_RFSR_RXW (0x0040) -#define MCF_PSC_RFSR_FAE (0x0080) -#define MCF_PSC_RFSR_FRM(x) (((x)&0x000F)<<8) -#define MCF_PSC_RFSR_TAG (0x1000) -#define MCF_PSC_RFSR_TXW (0x4000) -#define MCF_PSC_RFSR_IP (0x8000) -#define MCF_PSC_RFSR_FRM_BYTE0 (0x0800) -#define MCF_PSC_RFSR_FRM_BYTE1 (0x0400) -#define MCF_PSC_RFSR_FRM_BYTE2 (0x0200) -#define MCF_PSC_RFSR_FRM_BYTE3 (0x0100) - -/* Bit definitions and macros for MCF_PSC_TFSR */ -#define MCF_PSC_TFSR_EMT (0x0001) -#define MCF_PSC_TFSR_ALARM (0x0002) -#define MCF_PSC_TFSR_FU (0x0004) -#define MCF_PSC_TFSR_FRMRY (0x0008) -#define MCF_PSC_TFSR_OF (0x0010) -#define MCF_PSC_TFSR_UF (0x0020) -#define MCF_PSC_TFSR_RXW (0x0040) -#define MCF_PSC_TFSR_FAE (0x0080) -#define MCF_PSC_TFSR_FRM(x) (((x)&0x000F)<<8) -#define MCF_PSC_TFSR_TAG (0x1000) -#define MCF_PSC_TFSR_TXW (0x4000) -#define MCF_PSC_TFSR_IP (0x8000) -#define MCF_PSC_TFSR_FRM_BYTE0 (0x0800) -#define MCF_PSC_TFSR_FRM_BYTE1 (0x0400) -#define MCF_PSC_TFSR_FRM_BYTE2 (0x0200) -#define MCF_PSC_TFSR_FRM_BYTE3 (0x0100) - -/* Bit definitions and macros for MCF_PSC_RFCR */ -#define MCF_PSC_RFCR_CNTR(x) (((x)&0x0000FFFF)<<0) -#define MCF_PSC_RFCR_TXW_MSK (0x00040000) -#define MCF_PSC_RFCR_OF_MSK (0x00080000) -#define MCF_PSC_RFCR_UF_MSK (0x00100000) -#define MCF_PSC_RFCR_RXW_MSK (0x00200000) -#define MCF_PSC_RFCR_FAE_MSK (0x00400000) -#define MCF_PSC_RFCR_IP_MSK (0x00800000) -#define MCF_PSC_RFCR_GR(x) (((x)&0x00000007)<<24) -#define MCF_PSC_RFCR_FRMEN (0x08000000) -#define MCF_PSC_RFCR_TIMER (0x10000000) -#define MCF_PSC_RFCR_WRITETAG (0x20000000) -#define MCF_PSC_RFCR_SHADOW (0x80000000) - -/* Bit definitions and macros for MCF_PSC_TFCR */ -#define MCF_PSC_TFCR_CNTR(x) (((x)&0x0000FFFF)<<0) -#define MCF_PSC_TFCR_TXW_MSK (0x00040000) -#define MCF_PSC_TFCR_OF_MSK (0x00080000) -#define MCF_PSC_TFCR_UF_MSK (0x00100000) -#define MCF_PSC_TFCR_RXW_MSK (0x00200000) -#define MCF_PSC_TFCR_FAE_MSK (0x00400000) -#define MCF_PSC_TFCR_IP_MSK (0x00800000) -#define MCF_PSC_TFCR_GR(x) (((x)&0x00000007)<<24) -#define MCF_PSC_TFCR_FRMEN (0x08000000) -#define MCF_PSC_TFCR_TIMER (0x10000000) -#define MCF_PSC_TFCR_WRITETAG (0x20000000) -#define MCF_PSC_TFCR_SHADOW (0x80000000) - -/* Bit definitions and macros for MCF_PSC_RFAR */ -#define MCF_PSC_RFAR_ALARM(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF_PSC_TFAR */ -#define MCF_PSC_TFAR_ALARM(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF_PSC_RFRP */ -#define MCF_PSC_RFRP_READ(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF_PSC_TFRP */ -#define MCF_PSC_TFRP_READ(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF_PSC_RFWP */ -#define MCF_PSC_RFWP_WRITE(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF_PSC_TFWP */ -#define MCF_PSC_TFWP_WRITE(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF_PSC_RLRFP */ -#define MCF_PSC_RLRFP_LFP(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF_PSC_TLRFP */ -#define MCF_PSC_TLRFP_LFP(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF_PSC_RLWFP */ -#define MCF_PSC_RLWFP_LFP(x) (((x)&0x01FF)<<0) - -/* Bit definitions and macros for MCF_PSC_TLWFP */ -#define MCF_PSC_TLWFP_LFP(x) (((x)&0x01FF)<<0) - -#endif /* __MCF548X_PSC_H__ */ diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_sdramc.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_sdramc.h deleted file mode 100644 index 452332d1d9..0000000000 --- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_sdramc.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * SDRAM Controller (SDRAMC) - */ -#ifndef __MCF548X_SDRAMC_H__ -#define __MCF548X_SDRAMC_H__ - -/* - * SDRAM Controller (SDRAMC) - */ - -/* Register read/write macros */ -#define MCF_SDRAMC_SDRAMDS (*(vuint32_t*)(&__MBAR[0x000004])) -#define MCF_SDRAMC_CS0CFG (*(vuint32_t*)(&__MBAR[0x000020])) -#define MCF_SDRAMC_CS1CFG (*(vuint32_t*)(&__MBAR[0x000024])) -#define MCF_SDRAMC_CS2CFG (*(vuint32_t*)(&__MBAR[0x000028])) -#define MCF_SDRAMC_CS3CFG (*(vuint32_t*)(&__MBAR[0x00002C])) -#define MCF_SDRAMC_CSnCFG(x) (*(vuint32_t*)(&__MBAR[0x000020+((x)*0x004)])) -#define MCF_SDRAMC_SDMR (*(vuint32_t*)(&__MBAR[0x000100])) -#define MCF_SDRAMC_SDCR (*(vuint32_t*)(&__MBAR[0x000104])) -#define MCF_SDRAMC_SDCFG1 (*(vuint32_t*)(&__MBAR[0x000108])) -#define MCF_SDRAMC_SDCFG2 (*(vuint32_t*)(&__MBAR[0x00010C])) - -/* Bit definitions and macros for MCF_SDRAMC_SDRAMDS */ -#define MCF_SDRAMC_SDRAMDS_SB_D(x) (((x)&0x00000003)<<0) -#define MCF_SDRAMC_SDRAMDS_SB_S(x) (((x)&0x00000003)<<2) -#define MCF_SDRAMC_SDRAMDS_SB_A(x) (((x)&0x00000003)<<4) -#define MCF_SDRAMC_SDRAMDS_SB_C(x) (((x)&0x00000003)<<6) -#define MCF_SDRAMC_SDRAMDS_SB_E(x) (((x)&0x00000003)<<8) -#define MCF_SDRAMC_SDRAMDS_DRIVE_8MA (0x02) -#define MCF_SDRAMC_SDRAMDS_DRIVE_16MA (0x01) -#define MCF_SDRAMC_SDRAMDS_DRIVE_24MA (0x00) -#define MCF_SDRAMC_SDRAMDS_DRIVE_NONE (0x03) - -/* Bit definitions and macros for MCF_SDRAMC_CSnCFG */ -#define MCF_SDRAMC_CSnCFG_CSSZ(x) (((x)&0x0000001F)<<0) -#define MCF_SDRAMC_CSnCFG_CSBA(x) (((x)&0x00000FFF)<<20) -#define MCF_SDRAMC_CSnCFG_CSSZ_DIABLE (0x00000000) -#define MCF_SDRAMC_CSnCFG_CSSZ_1MBYTE (0x00000013) -#define MCF_SDRAMC_CSnCFG_CSSZ_2MBYTE (0x00000014) -#define MCF_SDRAMC_CSnCFG_CSSZ_4MBYTE (0x00000015) -#define MCF_SDRAMC_CSnCFG_CSSZ_8MBYTE (0x00000016) -#define MCF_SDRAMC_CSnCFG_CSSZ_16MBYTE (0x00000017) -#define MCF_SDRAMC_CSnCFG_CSSZ_32MBYTE (0x00000018) -#define MCF_SDRAMC_CSnCFG_CSSZ_64MBYTE (0x00000019) -#define MCF_SDRAMC_CSnCFG_CSSZ_128MBYTE (0x0000001A) -#define MCF_SDRAMC_CSnCFG_CSSZ_256MBYTE (0x0000001B) -#define MCF_SDRAMC_CSnCFG_CSSZ_512MBYTE (0x0000001C) -#define MCF_SDRAMC_CSnCFG_CSSZ_1GBYTE (0x0000001D) -#define MCF_SDRAMC_CSnCFG_CSSZ_2GBYTE (0x0000001E) -#define MCF_SDRAMC_CSnCFG_CSSZ_4GBYTE (0x0000001F) - -/* Bit definitions and macros for MCF_SDRAMC_SDMR */ -#define MCF_SDRAMC_SDMR_CMD (0x00010000) -#define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) -#define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x00000003)<<30) -#define MCF_SDRAMC_SDMR_BNKAD_LMR (0x00000000) -#define MCF_SDRAMC_SDMR_BNKAD_LEMR (0x40000000) - -/* Bit definitions and macros for MCF_SDRAMC_SDCR */ -#define MCF_SDRAMC_SDCR_IPALL (0x00000002) -#define MCF_SDRAMC_SDCR_IREF (0x00000004) -#define MCF_SDRAMC_SDCR_BUFF (0x00000010) -#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8) -#define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16) -#define MCF_SDRAMC_SDCR_DRIVE (0x00400000) -#define MCF_SDRAMC_SDCR_AP (0x00800000) -#define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24) -#define MCF_SDRAMC_SDCR_REF (0x10000000) -#define MCF_SDRAMC_SDCR_DDR (0x20000000) -#define MCF_SDRAMC_SDCR_CKE (0x40000000) -#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000) - -/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */ -#define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4) -#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) -#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) -#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) -#define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20) -#define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24) -#define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28) - -/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */ -#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) -#define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20) -#define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24) -#define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28) - -#endif /* __MCF548X_SDRAMC_H__ */ diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_sec.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_sec.h deleted file mode 100644 index 552527d381..0000000000 --- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_sec.h +++ /dev/null @@ -1,389 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * Integrated Security Engine (SEC) - */ -#ifndef __MCF548X_SEC_H__ -#define __MCF548X_SEC_H__ - -/* - * Integrated Security Engine (SEC) - */ - -/* Register read/write macros */ -#define MCF_SEC_EUACRH (*(vuint32_t*)(&__MBAR[0x021000])) -#define MCF_SEC_EUACRL (*(vuint32_t*)(&__MBAR[0x021004])) -#define MCF_SEC_EUASRH (*(vuint32_t*)(&__MBAR[0x021028])) -#define MCF_SEC_EUASRL (*(vuint32_t*)(&__MBAR[0x02102C])) -#define MCF_SEC_SIMRH (*(vuint32_t*)(&__MBAR[0x021008])) -#define MCF_SEC_SIMRL (*(vuint32_t*)(&__MBAR[0x02100C])) -#define MCF_SEC_SISRH (*(vuint32_t*)(&__MBAR[0x021010])) -#define MCF_SEC_SISRL (*(vuint32_t*)(&__MBAR[0x021014])) -#define MCF_SEC_SICRH (*(vuint32_t*)(&__MBAR[0x021018])) -#define MCF_SEC_SICRL (*(vuint32_t*)(&__MBAR[0x02101C])) -#define MCF_SEC_SIDR (*(vuint32_t*)(&__MBAR[0x021020])) -#define MCF_SEC_SMCR (*(vuint32_t*)(&__MBAR[0x021030])) -#define MCF_SEC_MEAR (*(vuint32_t*)(&__MBAR[0x021038])) -#define MCF_SEC_CCCR0 (*(vuint32_t*)(&__MBAR[0x02200C])) -#define MCF_SEC_CCCR1 (*(vuint32_t*)(&__MBAR[0x02300C])) -#define MCF_SEC_CCPSRH0 (*(vuint32_t*)(&__MBAR[0x022010])) -#define MCF_SEC_CCPSRH1 (*(vuint32_t*)(&__MBAR[0x023010])) -#define MCF_SEC_CCPSRL0 (*(vuint32_t*)(&__MBAR[0x022014])) -#define MCF_SEC_CCPSRL1 (*(vuint32_t*)(&__MBAR[0x023014])) -#define MCF_SEC_CDPR0 (*(vuint32_t*)(&__MBAR[0x022044])) -#define MCF_SEC_CDPR1 (*(vuint32_t*)(&__MBAR[0x023044])) -#define MCF_SEC_FR0 (*(vuint32_t*)(&__MBAR[0x02204C])) -#define MCF_SEC_FR1 (*(vuint32_t*)(&__MBAR[0x02304C])) -#define MCF_SEC_AFRCR (*(vuint32_t*)(&__MBAR[0x028018])) -#define MCF_SEC_AFSR (*(vuint32_t*)(&__MBAR[0x028028])) -#define MCF_SEC_AFISR (*(vuint32_t*)(&__MBAR[0x028030])) -#define MCF_SEC_AFIMR (*(vuint32_t*)(&__MBAR[0x028038])) -#define MCF_SEC_DRCR (*(vuint32_t*)(&__MBAR[0x02A018])) -#define MCF_SEC_DSR (*(vuint32_t*)(&__MBAR[0x02A028])) -#define MCF_SEC_DISR (*(vuint32_t*)(&__MBAR[0x02A030])) -#define MCF_SEC_DIMR (*(vuint32_t*)(&__MBAR[0x02A038])) -#define MCF_SEC_MDRCR (*(vuint32_t*)(&__MBAR[0x02C018])) -#define MCF_SEC_MDSR (*(vuint32_t*)(&__MBAR[0x02C028])) -#define MCF_SEC_MDISR (*(vuint32_t*)(&__MBAR[0x02C030])) -#define MCF_SEC_MDIMR (*(vuint32_t*)(&__MBAR[0x02C038])) -#define MCF_SEC_RNGRCR (*(vuint32_t*)(&__MBAR[0x02E018])) -#define MCF_SEC_RNGSR (*(vuint32_t*)(&__MBAR[0x02E028])) -#define MCF_SEC_RNGISR (*(vuint32_t*)(&__MBAR[0x02E030])) -#define MCF_SEC_RNGIMR (*(vuint32_t*)(&__MBAR[0x02E038])) -#define MCF_SEC_AESRCR (*(vuint32_t*)(&__MBAR[0x032018])) -#define MCF_SEC_AESSR (*(vuint32_t*)(&__MBAR[0x032028])) -#define MCF_SEC_AESISR (*(vuint32_t*)(&__MBAR[0x032030])) -#define MCF_SEC_AESIMR (*(vuint32_t*)(&__MBAR[0x032038])) - -/* Bit definitions and macros for MCF_SEC_EUACRH */ -#define MCF_SEC_EUACRH_AFEU(x) (((x)&0x0000000F)<<0) -#define MCF_SEC_EUACRH_MDEU(x) (((x)&0x0000000F)<<8) -#define MCF_SEC_EUACRH_RNG(x) (((x)&0x0000000F)<<24) -#define MCF_SEC_EUACRH_RNG_NOASSIGN (0x00000000) -#define MCF_SEC_EUACRH_RNG_CHA0 (0x01000000) -#define MCF_SEC_EUACRH_RNG_CHA1 (0x02000000) -#define MCF_SEC_EUACRH_MDEU_NOASSIGN (0x00000000) -#define MCF_SEC_EUACRH_MDEU_CHA0 (0x00000100) -#define MCF_SEC_EUACRH_MDEU_CHA1 (0x00000200) -#define MCF_SEC_EUACRH_AFEU_NOASSIGN (0x00000000) -#define MCF_SEC_EUACRH_AFEU_CHA0 (0x00000001) -#define MCF_SEC_EUACRH_AFEU_CHA1 (0x00000002) - -/* Bit definitions and macros for MCF_SEC_EUACRL */ -#define MCF_SEC_EUACRL_AESU(x) (((x)&0x0000000F)<<16) -#define MCF_SEC_EUACRL_DEU(x) (((x)&0x0000000F)<<24) -#define MCF_SEC_EUACRL_DEU_NOASSIGN (0x00000000) -#define MCF_SEC_EUACRL_DEU_CHA0 (0x01000000) -#define MCF_SEC_EUACRL_DEU_CHA1 (0x02000000) -#define MCF_SEC_EUACRL_AESU_NOASSIGN (0x00000000) -#define MCF_SEC_EUACRL_AESU_CHA0 (0x00010000) -#define MCF_SEC_EUACRL_AESU_CHA1 (0x00020000) - -/* Bit definitions and macros for MCF_SEC_EUASRH */ -#define MCF_SEC_EUASRH_AFEU(x) (((x)&0x0000000F)<<0) -#define MCF_SEC_EUASRH_MDEU(x) (((x)&0x0000000F)<<8) -#define MCF_SEC_EUASRH_RNG(x) (((x)&0x0000000F)<<24) - -/* Bit definitions and macros for MCF_SEC_EUASRL */ -#define MCF_SEC_EUASRL_AESU(x) (((x)&0x0000000F)<<16) -#define MCF_SEC_EUASRL_DEU(x) (((x)&0x0000000F)<<24) - -/* Bit definitions and macros for MCF_SEC_SIMRH */ -#define MCF_SEC_SIMRH_AERR (0x08000000) -#define MCF_SEC_SIMRH_CHA0DN (0x10000000) -#define MCF_SEC_SIMRH_CHA0ERR (0x20000000) -#define MCF_SEC_SIMRH_CHA1DN (0x40000000) -#define MCF_SEC_SIMRH_CHA1ERR (0x80000000) - -/* Bit definitions and macros for MCF_SEC_SIMRL */ -#define MCF_SEC_SIMRL_TEA (0x00000040) -#define MCF_SEC_SIMRL_DEUDN (0x00000100) -#define MCF_SEC_SIMRL_DEUERR (0x00000200) -#define MCF_SEC_SIMRL_AESUDN (0x00001000) -#define MCF_SEC_SIMRL_AESUERR (0x00002000) -#define MCF_SEC_SIMRL_MDEUDN (0x00010000) -#define MCF_SEC_SIMRL_MDEUERR (0x00020000) -#define MCF_SEC_SIMRL_AFEUDN (0x00100000) -#define MCF_SEC_SIMRL_AFEUERR (0x00200000) -#define MCF_SEC_SIMRL_RNGDN (0x01000000) -#define MCF_SEC_SIMRL_RNGERR (0x02000000) - -/* Bit definitions and macros for MCF_SEC_SISRH */ -#define MCF_SEC_SISRH_AERR (0x08000000) -#define MCF_SEC_SISRH_CHA0DN (0x10000000) -#define MCF_SEC_SISRH_CHA0ERR (0x20000000) -#define MCF_SEC_SISRH_CHA1DN (0x40000000) -#define MCF_SEC_SISRH_CHA1ERR (0x80000000) - -/* Bit definitions and macros for MCF_SEC_SISRL */ -#define MCF_SEC_SISRL_TEA (0x00000040) -#define MCF_SEC_SISRL_DEUDN (0x00000100) -#define MCF_SEC_SISRL_DEUERR (0x00000200) -#define MCF_SEC_SISRL_AESUDN (0x00001000) -#define MCF_SEC_SISRL_AESUERR (0x00002000) -#define MCF_SEC_SISRL_MDEUDN (0x00010000) -#define MCF_SEC_SISRL_MDEUERR (0x00020000) -#define MCF_SEC_SISRL_AFEUDN (0x00100000) -#define MCF_SEC_SISRL_AFEUERR (0x00200000) -#define MCF_SEC_SISRL_RNGDN (0x01000000) -#define MCF_SEC_SISRL_RNGERR (0x02000000) - -/* Bit definitions and macros for MCF_SEC_SICRH */ -#define MCF_SEC_SICRH_AERR (0x08000000) -#define MCF_SEC_SICRH_CHA0DN (0x10000000) -#define MCF_SEC_SICRH_CHA0ERR (0x20000000) -#define MCF_SEC_SICRH_CHA1DN (0x40000000) -#define MCF_SEC_SICRH_CHA1ERR (0x80000000) - -/* Bit definitions and macros for MCF_SEC_SICRL */ -#define MCF_SEC_SICRL_TEA (0x00000040) -#define MCF_SEC_SICRL_DEUDN (0x00000100) -#define MCF_SEC_SICRL_DEUERR (0x00000200) -#define MCF_SEC_SICRL_AESUDN (0x00001000) -#define MCF_SEC_SICRL_AESUERR (0x00002000) -#define MCF_SEC_SICRL_MDEUDN (0x00010000) -#define MCF_SEC_SICRL_MDEUERR (0x00020000) -#define MCF_SEC_SICRL_AFEUDN (0x00100000) -#define MCF_SEC_SICRL_AFEUERR (0x00200000) -#define MCF_SEC_SICRL_RNGDN (0x01000000) -#define MCF_SEC_SICRL_RNGERR (0x02000000) - -/* Bit definitions and macros for MCF_SEC_SMCR */ -#define MCF_SEC_SMCR_CURR_CHAN(x) (((x)&0x0000000F)<<4) -#define MCF_SEC_SMCR_SWR (0x01000000) -#define MCF_SEC_SMCR_CURR_CHAN_1 (0x00000010) -#define MCF_SEC_SMCR_CURR_CHAN_2 (0x00000020) - -/* Bit definitions and macros for MCF_SEC_CCCRn */ -#define MCF_SEC_CCCRn_RST (0x00000001) -#define MCF_SEC_CCCRn_CDIE (0x00000002) -#define MCF_SEC_CCCRn_NT (0x00000004) -#define MCF_SEC_CCCRn_NE (0x00000008) -#define MCF_SEC_CCCRn_WE (0x00000010) -#define MCF_SEC_CCCRn_BURST_SIZE(x) (((x)&0x00000007)<<8) -#define MCF_SEC_CCCRn_BURST_SIZE_2 (0x00000000) -#define MCF_SEC_CCCRn_BURST_SIZE_8 (0x00000100) -#define MCF_SEC_CCCRn_BURST_SIZE_16 (0x00000200) -#define MCF_SEC_CCCRn_BURST_SIZE_24 (0x00000300) -#define MCF_SEC_CCCRn_BURST_SIZE_32 (0x00000400) -#define MCF_SEC_CCCRn_BURST_SIZE_40 (0x00000500) -#define MCF_SEC_CCCRn_BURST_SIZE_48 (0x00000600) -#define MCF_SEC_CCCRn_BURST_SIZE_56 (0x00000700) - -/* Bit definitions and macros for MCF_SEC_CCPSRHn */ -#define MCF_SEC_CCPSRHn_STATE(x) (((x)&0x000000FF)<<0) - -/* Bit definitions and macros for MCF_SEC_CCPSRLn */ -#define MCF_SEC_CCPSRLn_PAIR_PTR(x) (((x)&0x000000FF)<<0) -#define MCF_SEC_CCPSRLn_EUERR (0x00000100) -#define MCF_SEC_CCPSRLn_SERR (0x00000200) -#define MCF_SEC_CCPSRLn_DERR (0x00000400) -#define MCF_SEC_CCPSRLn_PERR (0x00001000) -#define MCF_SEC_CCPSRLn_TEA (0x00002000) -#define MCF_SEC_CCPSRLn_SD (0x00010000) -#define MCF_SEC_CCPSRLn_PD (0x00020000) -#define MCF_SEC_CCPSRLn_SRD (0x00040000) -#define MCF_SEC_CCPSRLn_PRD (0x00080000) -#define MCF_SEC_CCPSRLn_SG (0x00100000) -#define MCF_SEC_CCPSRLn_PG (0x00200000) -#define MCF_SEC_CCPSRLn_SR (0x00400000) -#define MCF_SEC_CCPSRLn_PR (0x00800000) -#define MCF_SEC_CCPSRLn_MO (0x01000000) -#define MCF_SEC_CCPSRLn_MI (0x02000000) -#define MCF_SEC_CCPSRLn_STAT (0x04000000) - -/* Bit definitions and macros for MCF_SEC_AFRCR */ -#define MCF_SEC_AFRCR_SR (0x01000000) -#define MCF_SEC_AFRCR_MI (0x02000000) -#define MCF_SEC_AFRCR_RI (0x04000000) - -/* Bit definitions and macros for MCF_SEC_AFSR */ -#define MCF_SEC_AFSR_RD (0x01000000) -#define MCF_SEC_AFSR_ID (0x02000000) -#define MCF_SEC_AFSR_IE (0x04000000) -#define MCF_SEC_AFSR_OFE (0x08000000) -#define MCF_SEC_AFSR_IFW (0x10000000) -#define MCF_SEC_AFSR_HALT (0x20000000) - -/* Bit definitions and macros for MCF_SEC_AFISR */ -#define MCF_SEC_AFISR_DSE (0x00010000) -#define MCF_SEC_AFISR_KSE (0x00020000) -#define MCF_SEC_AFISR_CE (0x00040000) -#define MCF_SEC_AFISR_ERE (0x00080000) -#define MCF_SEC_AFISR_IE (0x00100000) -#define MCF_SEC_AFISR_OFU (0x02000000) -#define MCF_SEC_AFISR_IFO (0x04000000) -#define MCF_SEC_AFISR_IFE (0x10000000) -#define MCF_SEC_AFISR_OFE (0x20000000) -#define MCF_SEC_AFISR_AE (0x40000000) -#define MCF_SEC_AFISR_ME (0x80000000) - -/* Bit definitions and macros for MCF_SEC_AFIMR */ -#define MCF_SEC_AFIMR_DSE (0x00010000) -#define MCF_SEC_AFIMR_KSE (0x00020000) -#define MCF_SEC_AFIMR_CE (0x00040000) -#define MCF_SEC_AFIMR_ERE (0x00080000) -#define MCF_SEC_AFIMR_IE (0x00100000) -#define MCF_SEC_AFIMR_OFU (0x02000000) -#define MCF_SEC_AFIMR_IFO (0x04000000) -#define MCF_SEC_AFIMR_IFE (0x10000000) -#define MCF_SEC_AFIMR_OFE (0x20000000) -#define MCF_SEC_AFIMR_AE (0x40000000) -#define MCF_SEC_AFIMR_ME (0x80000000) - -/* Bit definitions and macros for MCF_SEC_DRCR */ -#define MCF_SEC_DRCR_SR (0x01000000) -#define MCF_SEC_DRCR_MI (0x02000000) -#define MCF_SEC_DRCR_RI (0x04000000) - -/* Bit definitions and macros for MCF_SEC_DSR */ -#define MCF_SEC_DSR_RD (0x01000000) -#define MCF_SEC_DSR_ID (0x02000000) -#define MCF_SEC_DSR_IE (0x04000000) -#define MCF_SEC_DSR_OFR (0x08000000) -#define MCF_SEC_DSR_IFW (0x10000000) -#define MCF_SEC_DSR_HALT (0x20000000) - -/* Bit definitions and macros for MCF_SEC_DISR */ -#define MCF_SEC_DISR_DSE (0x00010000) -#define MCF_SEC_DISR_KSE (0x00020000) -#define MCF_SEC_DISR_CE (0x00040000) -#define MCF_SEC_DISR_ERE (0x00080000) -#define MCF_SEC_DISR_IE (0x00100000) -#define MCF_SEC_DISR_KPE (0x00200000) -#define MCF_SEC_DISR_OFU (0x02000000) -#define MCF_SEC_DISR_IFO (0x04000000) -#define MCF_SEC_DISR_IFE (0x10000000) -#define MCF_SEC_DISR_OFE (0x20000000) -#define MCF_SEC_DISR_AE (0x40000000) -#define MCF_SEC_DISR_ME (0x80000000) - -/* Bit definitions and macros for MCF_SEC_DIMR */ -#define MCF_SEC_DIMR_DSE (0x00010000) -#define MCF_SEC_DIMR_KSE (0x00020000) -#define MCF_SEC_DIMR_CE (0x00040000) -#define MCF_SEC_DIMR_ERE (0x00080000) -#define MCF_SEC_DIMR_IE (0x00100000) -#define MCF_SEC_DIMR_KPE (0x00200000) -#define MCF_SEC_DIMR_OFU (0x02000000) -#define MCF_SEC_DIMR_IFO (0x04000000) -#define MCF_SEC_DIMR_IFE (0x10000000) -#define MCF_SEC_DIMR_OFE (0x20000000) -#define MCF_SEC_DIMR_AE (0x40000000) -#define MCF_SEC_DIMR_ME (0x80000000) - -/* Bit definitions and macros for MCF_SEC_MDRCR */ -#define MCF_SEC_MDRCR_SR (0x01000000) -#define MCF_SEC_MDRCR_MI (0x02000000) -#define MCF_SEC_MDRCR_RI (0x04000000) - -/* Bit definitions and macros for MCF_SEC_MDSR */ -#define MCF_SEC_MDSR_RD (0x01000000) -#define MCF_SEC_MDSR_ID (0x02000000) -#define MCF_SEC_MDSR_IE (0x04000000) -#define MCF_SEC_MDSR_IFW (0x10000000) -#define MCF_SEC_MDSR_HALT (0x20000000) - -/* Bit definitions and macros for MCF_SEC_MDISR */ -#define MCF_SEC_MDISR_DSE (0x00010000) -#define MCF_SEC_MDISR_KSE (0x00020000) -#define MCF_SEC_MDISR_CE (0x00040000) -#define MCF_SEC_MDISR_ERE (0x00080000) -#define MCF_SEC_MDISR_IE (0x00100000) -#define MCF_SEC_MDISR_IFO (0x04000000) -#define MCF_SEC_MDISR_AE (0x40000000) -#define MCF_SEC_MDISR_ME (0x80000000) - -/* Bit definitions and macros for MCF_SEC_MDIMR */ -#define MCF_SEC_MDIMR_DSE (0x00010000) -#define MCF_SEC_MDIMR_KSE (0x00020000) -#define MCF_SEC_MDIMR_CE (0x00040000) -#define MCF_SEC_MDIMR_ERE (0x00080000) -#define MCF_SEC_MDIMR_IE (0x00100000) -#define MCF_SEC_MDIMR_IFO (0x04000000) -#define MCF_SEC_MDIMR_AE (0x40000000) -#define MCF_SEC_MDIMR_ME (0x80000000) - -/* Bit definitions and macros for MCF_SEC_RNGRCR */ -#define MCF_SEC_RNGRCR_SR (0x01000000) -#define MCF_SEC_RNGRCR_MI (0x02000000) -#define MCF_SEC_RNGRCR_RI (0x04000000) - -/* Bit definitions and macros for MCF_SEC_RNGSR */ -#define MCF_SEC_RNGSR_RD (0x01000000) -#define MCF_SEC_RNGSR_O (0x02000000) -#define MCF_SEC_RNGSR_IE (0x04000000) -#define MCF_SEC_RNGSR_OFR (0x08000000) -#define MCF_SEC_RNGSR_HALT (0x20000000) - -/* Bit definitions and macros for MCF_SEC_RNGISR */ -#define MCF_SEC_RNGISR_IE (0x00100000) -#define MCF_SEC_RNGISR_OFU (0x02000000) -#define MCF_SEC_RNGISR_AE (0x40000000) -#define MCF_SEC_RNGISR_ME (0x80000000) - -/* Bit definitions and macros for MCF_SEC_RNGIMR */ -#define MCF_SEC_RNGIMR_IE (0x00100000) -#define MCF_SEC_RNGIMR_OFU (0x02000000) -#define MCF_SEC_RNGIMR_AE (0x40000000) -#define MCF_SEC_RNGIMR_ME (0x80000000) - -/* Bit definitions and macros for MCF_SEC_AESRCR */ -#define MCF_SEC_AESRCR_SR (0x01000000) -#define MCF_SEC_AESRCR_MI (0x02000000) -#define MCF_SEC_AESRCR_RI (0x04000000) - -/* Bit definitions and macros for MCF_SEC_AESSR */ -#define MCF_SEC_AESSR_RD (0x01000000) -#define MCF_SEC_AESSR_ID (0x02000000) -#define MCF_SEC_AESSR_IE (0x04000000) -#define MCF_SEC_AESSR_OFR (0x08000000) -#define MCF_SEC_AESSR_IFW (0x10000000) -#define MCF_SEC_AESSR_HALT (0x20000000) - -/* Bit definitions and macros for MCF_SEC_AESISR */ -#define MCF_SEC_AESISR_DSE (0x00010000) -#define MCF_SEC_AESISR_KSE (0x00020000) -#define MCF_SEC_AESISR_CE (0x00040000) -#define MCF_SEC_AESISR_ERE (0x00080000) -#define MCF_SEC_AESISR_IE (0x00100000) -#define MCF_SEC_AESISR_OFU (0x02000000) -#define MCF_SEC_AESISR_IFO (0x04000000) -#define MCF_SEC_AESISR_IFE (0x10000000) -#define MCF_SEC_AESISR_OFE (0x20000000) -#define MCF_SEC_AESISR_AE (0x40000000) -#define MCF_SEC_AESISR_ME (0x80000000) - -/* Bit definitions and macros for MCF_SEC_AESIMR */ -#define MCF_SEC_AESIMR_DSE (0x00010000) -#define MCF_SEC_AESIMR_KSE (0x00020000) -#define MCF_SEC_AESIMR_CE (0x00040000) -#define MCF_SEC_AESIMR_ERE (0x00080000) -#define MCF_SEC_AESIMR_IE (0x00100000) -#define MCF_SEC_AESIMR_OFU (0x02000000) -#define MCF_SEC_AESIMR_IFO (0x04000000) -#define MCF_SEC_AESIMR_IFE (0x10000000) -#define MCF_SEC_AESIMR_OFE (0x20000000) -#define MCF_SEC_AESIMR_AE (0x40000000) -#define MCF_SEC_AESIMR_ME (0x80000000) - -#endif /* __MCF548X_SEC_H__ */ diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_siu.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_siu.h deleted file mode 100644 index 558530d34f..0000000000 --- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_siu.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * DMA Serial Peripheral Interface (DSPI) - */ -#ifndef __MCF548X_SIU_H__ -#define __MCF548X_SIU_H__ - -/* - * System Integration Unit (SIU) - */ - -/* Register read/write macros */ -#define MCF_SIU_SBCR (*(vuint32_t*)(&__MBAR[0x000010])) -#define MCF_SIU_SECSACR (*(vuint32_t*)(&__MBAR[0x000038])) -#define MCF_SIU_RSR (*(vuint32_t*)(&__MBAR[0x000044])) -#define MCF_SIU_JTAGID (*(vuint32_t*)(&__MBAR[0x000050])) - -/* Bit definitions and macros for MCF_SIU_SBCR */ -#define MCF_SIU_SBCR_PIN2DSPI (0x08000000) -#define MCF_SIU_SBCR_DMA2CPU (0x10000000) -#define MCF_SIU_SBCR_CPU2DMA (0x20000000) -#define MCF_SIU_SBCR_PIN2DMA (0x40000000) -#define MCF_SIU_SBCR_PIN2CPU (0x80000000) - -/* Bit definitions and macros for MCF_SIU_SECSACR */ -#define MCF_SIU_SECSACR_SEQEN (0x00000001) - -/* Bit definitions and macros for MCF_SIU_RSR */ -#define MCF_SIU_RSR_RST (0x00000001) -#define MCF_SIU_RSR_RSTWD (0x00000002) -#define MCF_SIU_RSR_RSTJTG (0x00000008) - -/* Bit definitions and macros for MCF_SIU_JTAGID */ -#define MCF_SIU_JTAGID_REV (0xF0000000) -#define MCF_SIU_JTAGID_PROCESSOR (0x0FFFFFFF) -#define MCF_SIU_JTAGID_MCF5485 (0x0800C01D) -#define MCF_SIU_JTAGID_MCF5484 (0x0800D01D) -#define MCF_SIU_JTAGID_MCF5483 (0x0800E01D) -#define MCF_SIU_JTAGID_MCF5482 (0x0800F01D) -#define MCF_SIU_JTAGID_MCF5481 (0x0801001D) -#define MCF_SIU_JTAGID_MCF5480 (0x0801101D) -#define MCF_SIU_JTAGID_MCF5475 (0x0801201D) -#define MCF_SIU_JTAGID_MCF5474 (0x0801301D) -#define MCF_SIU_JTAGID_MCF5473 (0x0801401D) -#define MCF_SIU_JTAGID_MCF5472 (0x0801501D) -#define MCF_SIU_JTAGID_MCF5471 (0x0801601D) -#define MCF_SIU_JTAGID_MCF5470 (0x0801701D) - -#endif /* __MCF548X_SIU_H__ */ diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_slt.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_slt.h deleted file mode 100644 index 10d94a4117..0000000000 --- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_slt.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * Slice Timers (SLT) - */ -#ifndef __MCF548X_SLT_H__ -#define __MCF548X_SLT_H__ - -/* - * Slice Timers (SLT) - */ - -/* Register read/write macros */ -#define MCF_SLT_SLTCNT0 (*(vuint32_t*)(&__MBAR[0x000900])) -#define MCF_SLT_SCR0 (*(vuint32_t*)(&__MBAR[0x000904])) -#define MCF_SLT_SCNT0 (*(vuint32_t*)(&__MBAR[0x000908])) -#define MCF_SLT_SSR0 (*(vuint32_t*)(&__MBAR[0x00090C])) - -#define MCF_SLT_SLTCNT1 (*(vuint32_t*)(&__MBAR[0x000910])) -#define MCF_SLT_SCR1 (*(vuint32_t*)(&__MBAR[0x000914])) -#define MCF_SLT_SCNT1 (*(vuint32_t*)(&__MBAR[0x000918])) -#define MCF_SLT_SSR1 (*(vuint32_t*)(&__MBAR[0x00091C])) - -#define MCF_SLT_SLTCNT(x) (*(vuint32_t*)(&__MBAR[0x000900+((x)*0x010)])) -#define MCF_SLT_SCR(x) (*(vuint32_t*)(&__MBAR[0x000904+((x)*0x010)])) -#define MCF_SLT_SCNT(x) (*(vuint32_t*)(&__MBAR[0x000908+((x)*0x010)])) -#define MCF_SLT_SSR(x) (*(vuint32_t*)(&__MBAR[0x00090C+((x)*0x010)])) - -/* Bit definitions and macros for MCF_SLT_SCR */ -#define MCF_SLT_SCR_TEN (0x01000000) -#define MCF_SLT_SCR_IEN (0x02000000) -#define MCF_SLT_SCR_RUN (0x04000000) - -/* Bit definitions and macros for MCF_SLT_SSR */ -#define MCF_SLT_SSR_ST (0x01000000) -#define MCF_SLT_SSR_BE (0x02000000) - - -#ifndef __ASSEMBLY__ - -#define MCF_SLT_Address(x) ((struct mcf5xxx_slt*)(void*)(&__MBAR[0x000900+((x)*0x010)])) - -struct mcf5xxx_slt { - vuint32_t STCNT; /* Slice Terminal Count */ - vuint32_t SCR; /* Slice Timer Control Register */ - vuint32_t SCNT; /* Slice Count Value */ - vuint32_t SSR; /* Slice Timer Status Register */ -}; - -#endif - -#endif /* __MCF548X_SLT_H__ */ diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_sram.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_sram.h deleted file mode 100644 index a706306f2b..0000000000 --- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_sram.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * 32KByte System SRAM (SRAM) - */ -#ifndef __MCF548X_SRAM_H__ -#define __MCF548X_SRAM_H__ - -/* - * 32KByte System SRAM (SRAM) - */ - -/* Register read/write macros */ -#define MCF_SRAM_SSCR (*(vuint32_t*)(&__MBAR[0x01FFC0])) -#define MCF_SRAM_TCCR (*(vuint32_t*)(&__MBAR[0x01FFC4])) -#define MCF_SRAM_TCCRDR (*(vuint32_t*)(&__MBAR[0x01FFC8])) -#define MCF_SRAM_TCCRDW (*(vuint32_t*)(&__MBAR[0x01FFCC])) -#define MCF_SRAM_TCCRSEC (*(vuint32_t*)(&__MBAR[0x01FFD0])) - -/* Bit definitions and macros for MCF_SRAM_SSCR */ -#define MCF_SRAM_SSCR_INLV (0x00010000) - -/* Bit definitions and macros for MCF_SRAM_TCCR */ -#define MCF_SRAM_TCCR_BANK0_TC(x) (((x)&0x0000000F)<<0) -#define MCF_SRAM_TCCR_BANK1_TC(x) (((x)&0x0000000F)<<8) -#define MCF_SRAM_TCCR_BANK2_TC(x) (((x)&0x0000000F)<<16) -#define MCF_SRAM_TCCR_BANK3_TC(x) (((x)&0x0000000F)<<24) - -/* Bit definitions and macros for MCF_SRAM_TCCRDR */ -#define MCF_SRAM_TCCRDR_BANK0_TC(x) (((x)&0x0000000F)<<0) -#define MCF_SRAM_TCCRDR_BANK1_TC(x) (((x)&0x0000000F)<<8) -#define MCF_SRAM_TCCRDR_BANK2_TC(x) (((x)&0x0000000F)<<16) -#define MCF_SRAM_TCCRDR_BANK3_TC(x) (((x)&0x0000000F)<<24) - -/* Bit definitions and macros for MCF_SRAM_TCCRDW */ -#define MCF_SRAM_TCCRDW_BANK0_TC(x) (((x)&0x0000000F)<<0) -#define MCF_SRAM_TCCRDW_BANK1_TC(x) (((x)&0x0000000F)<<8) -#define MCF_SRAM_TCCRDW_BANK2_TC(x) (((x)&0x0000000F)<<16) -#define MCF_SRAM_TCCRDW_BANK3_TC(x) (((x)&0x0000000F)<<24) - -/* Bit definitions and macros for MCF_SRAM_TCCRSEC */ -#define MCF_SRAM_TCCRSEC_BANK0_TC(x) (((x)&0x0000000F)<<0) -#define MCF_SRAM_TCCRSEC_BANK1_TC(x) (((x)&0x0000000F)<<8) -#define MCF_SRAM_TCCRSEC_BANK2_TC(x) (((x)&0x0000000F)<<16) -#define MCF_SRAM_TCCRSEC_BANK3_TC(x) (((x)&0x0000000F)<<24) - -#endif /* __MCF548X_SRAM_H__ */ diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_uart.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_uart.h deleted file mode 100644 index 2fa25ce3b4..0000000000 --- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_uart.h +++ /dev/null @@ -1,233 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * Programmable Serial Controller (UART Compatible Definitions) (UART) - */ -#ifndef __MCF548X_UART_H__ -#define __MCF548X_UART_H__ - -/* - * Programmable Serial Controller (UART Compatible Definitions) (UART) - */ - -/* Register read/write macros */ -#define MCF_UART_UMR0 (*(vuint8_t *)(&__MBAR[0x008600])) -#define MCF_UART_USR0 (*(vuint8_t *)(&__MBAR[0x008604])) -#define MCF_UART_UCSR0 (*(vuint8_t *)(&__MBAR[0x008604])) -#define MCF_UART_UCR0 (*(vuint8_t *)(&__MBAR[0x008608])) -#define MCF_UART_URB0 (*(vuint8_t *)(&__MBAR[0x00860C])) -#define MCF_UART_UTB0 (*(vuint8_t *)(&__MBAR[0x00860C])) -#define MCF_UART_UIPCR0 (*(vuint8_t *)(&__MBAR[0x008610])) -#define MCF_UART_UACR0 (*(vuint8_t *)(&__MBAR[0x008610])) -#define MCF_UART_UISR0 (*(vuint8_t *)(&__MBAR[0x008614])) -#define MCF_UART_UIMR0 (*(vuint8_t *)(&__MBAR[0x008614])) -#define MCF_UART_UBG10 (*(vuint8_t *)(&__MBAR[0x008618])) -#define MCF_UART_UBG20 (*(vuint8_t *)(&__MBAR[0x00861C])) -#define MCF_UART_UIP0 (*(vuint8_t *)(&__MBAR[0x008634])) -#define MCF_UART_UOP10 (*(vuint8_t *)(&__MBAR[0x008638])) -#define MCF_UART_UOP00 (*(vuint8_t *)(&__MBAR[0x00863C])) - -#define MCF_UART_UMR1 (*(vuint8_t *)(&__MBAR[0x008700])) -#define MCF_UART_USR1 (*(vuint8_t *)(&__MBAR[0x008704])) -#define MCF_UART_UCSR1 (*(vuint8_t *)(&__MBAR[0x008704])) -#define MCF_UART_UCR1 (*(vuint8_t *)(&__MBAR[0x008708])) -#define MCF_UART_URB1 (*(vuint8_t *)(&__MBAR[0x00870C])) -#define MCF_UART_UTB1 (*(vuint8_t *)(&__MBAR[0x00870C])) -#define MCF_UART_UIPCR1 (*(vuint8_t *)(&__MBAR[0x008710])) -#define MCF_UART_UACR1 (*(vuint8_t *)(&__MBAR[0x008710])) -#define MCF_UART_UISR1 (*(vuint8_t *)(&__MBAR[0x008714])) -#define MCF_UART_UIMR1 (*(vuint8_t *)(&__MBAR[0x008714])) -#define MCF_UART_UBG11 (*(vuint8_t *)(&__MBAR[0x008718])) -#define MCF_UART_UBG21 (*(vuint8_t *)(&__MBAR[0x00871C])) -#define MCF_UART_UIP1 (*(vuint8_t *)(&__MBAR[0x008734])) -#define MCF_UART_UOP11 (*(vuint8_t *)(&__MBAR[0x008738])) -#define MCF_UART_UOP01 (*(vuint8_t *)(&__MBAR[0x00873C])) - -#define MCF_UART_UMR2 (*(vuint8_t *)(&__MBAR[0x008800])) -#define MCF_UART_USR2 (*(vuint8_t *)(&__MBAR[0x008804])) -#define MCF_UART_UCSR2 (*(vuint8_t *)(&__MBAR[0x008804])) -#define MCF_UART_UCR2 (*(vuint8_t *)(&__MBAR[0x008808])) -#define MCF_UART_URB2 (*(vuint8_t *)(&__MBAR[0x00880C])) -#define MCF_UART_UTB2 (*(vuint8_t *)(&__MBAR[0x00880C])) -#define MCF_UART_UIPCR2 (*(vuint8_t *)(&__MBAR[0x008810])) -#define MCF_UART_UACR2 (*(vuint8_t *)(&__MBAR[0x008810])) -#define MCF_UART_UISR2 (*(vuint8_t *)(&__MBAR[0x008814])) -#define MCF_UART_UIMR2 (*(vuint8_t *)(&__MBAR[0x008814])) -#define MCF_UART_UBG12 (*(vuint8_t *)(&__MBAR[0x008818])) -#define MCF_UART_UBG22 (*(vuint8_t *)(&__MBAR[0x00881C])) -#define MCF_UART_UIP2 (*(vuint8_t *)(&__MBAR[0x008834])) -#define MCF_UART_UOP12 (*(vuint8_t *)(&__MBAR[0x008838])) -#define MCF_UART_UOP02 (*(vuint8_t *)(&__MBAR[0x00883C])) - -#define MCF_UART_UMR3 (*(vuint8_t *)(&__MBAR[0x008900])) -#define MCF_UART_USR3 (*(vuint8_t *)(&__MBAR[0x008904])) -#define MCF_UART_UCSR3 (*(vuint8_t *)(&__MBAR[0x008904])) -#define MCF_UART_UCR3 (*(vuint8_t *)(&__MBAR[0x008908])) -#define MCF_UART_URB3 (*(vuint8_t *)(&__MBAR[0x00890C])) -#define MCF_UART_UTB3 (*(vuint8_t *)(&__MBAR[0x00890C])) -#define MCF_UART_UIPCR3 (*(vuint8_t *)(&__MBAR[0x008910])) -#define MCF_UART_UACR3 (*(vuint8_t *)(&__MBAR[0x008910])) -#define MCF_UART_UISR3 (*(vuint8_t *)(&__MBAR[0x008914])) -#define MCF_UART_UIMR3 (*(vuint8_t *)(&__MBAR[0x008914])) -#define MCF_UART_UBG13 (*(vuint8_t *)(&__MBAR[0x008918])) -#define MCF_UART_UBG23 (*(vuint8_t *)(&__MBAR[0x00891C])) -#define MCF_UART_UIP3 (*(vuint8_t *)(&__MBAR[0x008934])) -#define MCF_UART_UOP13 (*(vuint8_t *)(&__MBAR[0x008938])) -#define MCF_UART_UOP03 (*(vuint8_t *)(&__MBAR[0x00893C])) - - -#define MCF_UART_UMR(x) (*(vuint8_t *)(&__MBAR[0x008600+((x)*0x100)])) -#define MCF_UART_USR(x) (*(vuint8_t *)(&__MBAR[0x008604+((x)*0x100)])) -#define MCF_UART_UCSR(x) (*(vuint8_t *)(&__MBAR[0x008604+((x)*0x100)])) -#define MCF_UART_UCR(x) (*(vuint8_t *)(&__MBAR[0x008608+((x)*0x100)])) -#define MCF_UART_URB(x) (*(vuint8_t *)(&__MBAR[0x00860C+((x)*0x100)])) -#define MCF_UART_UTB(x) (*(vuint8_t *)(&__MBAR[0x00860C+((x)*0x100)])) -#define MCF_UART_UIPCR(x) (*(vuint8_t *)(&__MBAR[0x008610+((x)*0x100)])) -#define MCF_UART_UACR(x) (*(vuint8_t *)(&__MBAR[0x008610+((x)*0x100)])) -#define MCF_UART_UISR(x) (*(vuint8_t *)(&__MBAR[0x008614+((x)*0x100)])) -#define MCF_UART_UIMR(x) (*(vuint8_t *)(&__MBAR[0x008614+((x)*0x100)])) -#define MCF_UART_UBG1(x) (*(vuint8_t *)(&__MBAR[0x008618+((x)*0x100)])) -#define MCF_UART_UBG2(x) (*(vuint8_t *)(&__MBAR[0x00861C+((x)*0x100)])) -#define MCF_UART_UIP(x) (*(vuint8_t *)(&__MBAR[0x008634+((x)*0x100)])) -#define MCF_UART_UOP1(x) (*(vuint8_t *)(&__MBAR[0x008638+((x)*0x100)])) -#define MCF_UART_UOP0(x) (*(vuint8_t *)(&__MBAR[0x00863C+((x)*0x100)])) - -/* Bit definitions and macros for MCF_UART_UMR */ -#define MCF_UART_UMR_BC(x) (((x)&0x03)<<0) -#define MCF_UART_UMR_PT (0x04) -#define MCF_UART_UMR_PM(x) (((x)&0x03)<<3) -#define MCF_UART_UMR_ERR (0x20) -#define MCF_UART_UMR_RXIRQ (0x40) -#define MCF_UART_UMR_RXRTS (0x80) -#define MCF_UART_UMR_SB(x) (((x)&0x0F)<<0) -#define MCF_UART_UMR_TXCTS (0x10) -#define MCF_UART_UMR_TXRTS (0x20) -#define MCF_UART_UMR_CM(x) (((x)&0x03)<<6) -#define MCF_UART_UMR_PM_MULTI_ADDR (0x1C) -#define MCF_UART_UMR_PM_MULTI_DATA (0x18) -#define MCF_UART_UMR_PM_NONE (0x10) -#define MCF_UART_UMR_PM_FORCE_HI (0x0C) -#define MCF_UART_UMR_PM_FORCE_LO (0x08) -#define MCF_UART_UMR_PM_ODD (0x04) -#define MCF_UART_UMR_PM_EVEN (0x00) -#define MCF_UART_UMR_BC_5 (0x00) -#define MCF_UART_UMR_BC_6 (0x01) -#define MCF_UART_UMR_BC_7 (0x02) -#define MCF_UART_UMR_BC_8 (0x03) -#define MCF_UART_UMR_CM_NORMAL (0x00) -#define MCF_UART_UMR_CM_ECHO (0x40) -#define MCF_UART_UMR_CM_LOCAL_LOOP (0x80) -#define MCF_UART_UMR_CM_REMOTE_LOOP (0xC0) -#define MCF_UART_UMR_SB_STOP_BITS_1 (0x07) -#define MCF_UART_UMR_SB_STOP_BITS_15 (0x08) -#define MCF_UART_UMR_SB_STOP_BITS_2 (0x0F) - -/* Bit definitions and macros for MCF_UART_USR */ -#define MCF_UART_USR_RXRDY (0x01) -#define MCF_UART_USR_FFULL (0x02) -#define MCF_UART_USR_TXRDY (0x04) -#define MCF_UART_USR_TXEMP (0x08) -#define MCF_UART_USR_OE (0x10) -#define MCF_UART_USR_PE (0x20) -#define MCF_UART_USR_FE (0x40) -#define MCF_UART_USR_RB (0x80) - -/* Bit definitions and macros for MCF_UART_UCSR */ -#define MCF_UART_UCSR_TCS(x) (((x)&0x0F)<<0) -#define MCF_UART_UCSR_RCS(x) (((x)&0x0F)<<4) -#define MCF_UART_UCSR_RCS_SYS_CLK (0xD0) -#define MCF_UART_UCSR_RCS_CTM16 (0xE0) -#define MCF_UART_UCSR_RCS_CTM (0xF0) -#define MCF_UART_UCSR_TCS_SYS_CLK (0x0D) -#define MCF_UART_UCSR_TCS_CTM16 (0x0E) -#define MCF_UART_UCSR_TCS_CTM (0x0F) - -/* Bit definitions and macros for MCF_UART_UCR */ -#define MCF_UART_UCR_RXC(x) (((x)&0x03)<<0) -#define MCF_UART_UCR_TXC(x) (((x)&0x03)<<2) -#define MCF_UART_UCR_MISC(x) (((x)&0x07)<<4) -#define MCF_UART_UCR_NONE (0x00) -#define MCF_UART_UCR_STOP_BREAK (0x70) -#define MCF_UART_UCR_START_BREAK (0x60) -#define MCF_UART_UCR_BKCHGINT (0x50) -#define MCF_UART_UCR_RESET_ERROR (0x40) -#define MCF_UART_UCR_RESET_TX (0x30) -#define MCF_UART_UCR_RESET_RX (0x20) -#define MCF_UART_UCR_RESET_MR (0x10) -#define MCF_UART_UCR_TX_DISABLED (0x08) -#define MCF_UART_UCR_TX_ENABLED (0x04) -#define MCF_UART_UCR_RX_DISABLED (0x02) -#define MCF_UART_UCR_RX_ENABLED (0x01) - -/* Bit definitions and macros for MCF_UART_UIPCR */ -#define MCF_UART_UIPCR_CTS (0x01) -#define MCF_UART_UIPCR_COS (0x10) - -/* Bit definitions and macros for MCF_UART_UACR */ -#define MCF_UART_UACR_IEC (0x01) - -/* Bit definitions and macros for MCF_UART_UISR */ -#define MCF_UART_UISR_TXRDY (0x01) -#define MCF_UART_UISR_RXRDY_FU (0x02) -#define MCF_UART_UISR_DB (0x04) -#define MCF_UART_UISR_RXFTO (0x08) -#define MCF_UART_UISR_TXFIFO (0x10) -#define MCF_UART_UISR_RXFIFO (0x20) -#define MCF_UART_UISR_COS (0x80) - -/* Bit definitions and macros for MCF_UART_UIMR */ -#define MCF_UART_UIMR_TXRDY (0x01) -#define MCF_UART_UIMR_RXRDY_FU (0x02) -#define MCF_UART_UIMR_DB (0x04) -#define MCF_UART_UIMR_COS (0x80) - -/* Bit definitions and macros for MCF_UART_UIP */ -#define MCF_UART_UIP_CTS (0x01) - -/* Bit definitions and macros for MCF_UART_UOP1 */ -#define MCF_UART_UOP1_RTS (0x01) - -/* Bit definitions and macros for MCF_UART_UOP0 */ -#define MCF_UART_UOP0_RTS (0x01) - -/* The UART registers for mem mapped access */ -struct m5407uart -{ - vuint8_t umr; vuint24_t reserved0; - vuint8_t usr; vuint24_t reserved1; /* ucsr */ - vuint8_t ucr; vuint24_t reserved2; - vuint8_t urb; vuint24_t reserved3; /* utb */ - vuint8_t uipcr; vuint24_t reserved4; /* uacr */ - vuint8_t uisr; vuint24_t reserved5; /* uimr */ - vuint8_t udu; vuint24_t reserved6; - vuint8_t ubg1; vuint24_t reserved7; - vuint8_t ubg2; vuint24_t reserved8; - const uint8_t uip; vuint24_t reserved9; - vuint8_t uop1; vuint24_t reserved10; - vuint8_t uop0; vuint24_t reserved11; -} __attribute((packed)); - -#define MCF_UART(x) (*(struct m5407uart *)(&__MBAR[0x008600+((x)*0x100)])) - - -#endif /* __MCF548X_UART_H__ */ - diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_usb.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_usb.h deleted file mode 100644 index 0c256ef528..0000000000 --- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_usb.h +++ /dev/null @@ -1,509 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * Universal Serial Bus (USB) - * - * @note According to FreeScale errata sheet, the USB controller - * isn't really usable on MCF54xx V4E CPUs. - * Check V4M cores or wait for errata fixed - * Last update: 25.02.2008 10:55:00 - */ -#ifndef __MCF548X_USB_H__ -#define __MCF548X_USB_H__ - -/* - * Universal Serial Bus (USB) - */ - -/* Register read/write macros */ -#define MCF_USB_USBAISR (*(vuint8_t *)(&__MBAR[0x00B000])) -#define MCF_USB_USBAIMR (*(vuint8_t *)(&__MBAR[0x00B001])) -#define MCF_USB_EPINFO (*(vuint8_t *)(&__MBAR[0x00B003])) -#define MCF_USB_CFGR (*(vuint8_t *)(&__MBAR[0x00B004])) -#define MCF_USB_CFGAR (*(vuint8_t *)(&__MBAR[0x00B005])) -#define MCF_USB_SPEEDR (*(vuint8_t *)(&__MBAR[0x00B006])) -#define MCF_USB_FRMNUMR (*(vuint16_t*)(&__MBAR[0x00B00E])) -#define MCF_USB_EPTNR (*(vuint16_t*)(&__MBAR[0x00B010])) -#define MCF_USB_IFUR (*(vuint16_t*)(&__MBAR[0x00B014])) -#define MCF_USB_IFR0 (*(vuint16_t*)(&__MBAR[0x00B040])) -#define MCF_USB_IFR1 (*(vuint16_t*)(&__MBAR[0x00B042])) -#define MCF_USB_IFR2 (*(vuint16_t*)(&__MBAR[0x00B044])) -#define MCF_USB_IFR3 (*(vuint16_t*)(&__MBAR[0x00B046])) -#define MCF_USB_IFR4 (*(vuint16_t*)(&__MBAR[0x00B048])) -#define MCF_USB_IFR5 (*(vuint16_t*)(&__MBAR[0x00B04A])) -#define MCF_USB_IFR6 (*(vuint16_t*)(&__MBAR[0x00B04C])) -#define MCF_USB_IFR7 (*(vuint16_t*)(&__MBAR[0x00B04E])) -#define MCF_USB_IFR8 (*(vuint16_t*)(&__MBAR[0x00B050])) -#define MCF_USB_IFR9 (*(vuint16_t*)(&__MBAR[0x00B052])) -#define MCF_USB_IFR10 (*(vuint16_t*)(&__MBAR[0x00B054])) -#define MCF_USB_IFR11 (*(vuint16_t*)(&__MBAR[0x00B056])) -#define MCF_USB_IFR12 (*(vuint16_t*)(&__MBAR[0x00B058])) -#define MCF_USB_IFR13 (*(vuint16_t*)(&__MBAR[0x00B05A])) -#define MCF_USB_IFR14 (*(vuint16_t*)(&__MBAR[0x00B05C])) -#define MCF_USB_IFR15 (*(vuint16_t*)(&__MBAR[0x00B05E])) -#define MCF_USB_IFR16 (*(vuint16_t*)(&__MBAR[0x00B060])) -#define MCF_USB_IFR17 (*(vuint16_t*)(&__MBAR[0x00B062])) -#define MCF_USB_IFR18 (*(vuint16_t*)(&__MBAR[0x00B064])) -#define MCF_USB_IFR19 (*(vuint16_t*)(&__MBAR[0x00B066])) -#define MCF_USB_IFR20 (*(vuint16_t*)(&__MBAR[0x00B068])) -#define MCF_USB_IFR21 (*(vuint16_t*)(&__MBAR[0x00B06A])) -#define MCF_USB_IFR22 (*(vuint16_t*)(&__MBAR[0x00B06C])) -#define MCF_USB_IFR23 (*(vuint16_t*)(&__MBAR[0x00B06E])) -#define MCF_USB_IFR24 (*(vuint16_t*)(&__MBAR[0x00B070])) -#define MCF_USB_IFR25 (*(vuint16_t*)(&__MBAR[0x00B072])) -#define MCF_USB_IFR26 (*(vuint16_t*)(&__MBAR[0x00B074])) -#define MCF_USB_IFR27 (*(vuint16_t*)(&__MBAR[0x00B076])) -#define MCF_USB_IFR28 (*(vuint16_t*)(&__MBAR[0x00B078])) -#define MCF_USB_IFR29 (*(vuint16_t*)(&__MBAR[0x00B07A])) -#define MCF_USB_IFR30 (*(vuint16_t*)(&__MBAR[0x00B07C])) -#define MCF_USB_IFR31 (*(vuint16_t*)(&__MBAR[0x00B07E])) -#define MCF_USB_IFRn(x) (*(vuint16_t*)(&__MBAR[0x00B040+((x)*0x002)])) -#define MCF_USB_PPCNT (*(vuint16_t*)(&__MBAR[0x00B080])) -#define MCF_USB_DPCNT (*(vuint16_t*)(&__MBAR[0x00B082])) -#define MCF_USB_CRCECNT (*(vuint16_t*)(&__MBAR[0x00B084])) -#define MCF_USB_BSECNT (*(vuint16_t*)(&__MBAR[0x00B086])) -#define MCF_USB_PIDECNT (*(vuint16_t*)(&__MBAR[0x00B088])) -#define MCF_USB_FRMECNT (*(vuint16_t*)(&__MBAR[0x00B08A])) -#define MCF_USB_TXPCNT (*(vuint16_t*)(&__MBAR[0x00B08C])) -#define MCF_USB_CNTOVR (*(vuint8_t *)(&__MBAR[0x00B08E])) -#define MCF_USB_EP0ACR (*(vuint8_t *)(&__MBAR[0x00B101])) -#define MCF_USB_EP0MPSR (*(vuint16_t*)(&__MBAR[0x00B102])) -#define MCF_USB_EP0IFR (*(vuint8_t *)(&__MBAR[0x00B104])) -#define MCF_USB_EP0SR (*(vuint8_t *)(&__MBAR[0x00B105])) -#define MCF_USB_BMRTR (*(vuint8_t *)(&__MBAR[0x00B106])) -#define MCF_USB_BRTR (*(vuint8_t *)(&__MBAR[0x00B107])) -#define MCF_USB_WVALUER (*(vuint16_t*)(&__MBAR[0x00B108])) -#define MCF_USB_WINDEXR (*(vuint16_t*)(&__MBAR[0x00B10A])) -#define MCF_USB_WLENGTH (*(vuint16_t*)(&__MBAR[0x00B10C])) -#define MCF_USB_EP1OUTACR (*(vuint8_t *)(&__MBAR[0x00B131])) -#define MCF_USB_EP2OUTACR (*(vuint8_t *)(&__MBAR[0x00B161])) -#define MCF_USB_EP3OUTACR (*(vuint8_t *)(&__MBAR[0x00B191])) -#define MCF_USB_EP4OUTACR (*(vuint8_t *)(&__MBAR[0x00B1C1])) -#define MCF_USB_EP5OUTACR (*(vuint8_t *)(&__MBAR[0x00B1F1])) -#define MCF_USB_EP6OUTACR (*(vuint8_t *)(&__MBAR[0x00B221])) -#define MCF_USB_EPnOUTACR(x) (*(vuint8_t *)(&__MBAR[0x00B131+((x)*0x030)])) -#define MCF_USB_EP1OUTMPSR (*(vuint16_t*)(&__MBAR[0x00B132])) -#define MCF_USB_EP2OUTMPSR (*(vuint16_t*)(&__MBAR[0x00B162])) -#define MCF_USB_EP3OUTMPSR (*(vuint16_t*)(&__MBAR[0x00B192])) -#define MCF_USB_EP4OUTMPSR (*(vuint16_t*)(&__MBAR[0x00B1C2])) -#define MCF_USB_EP5OUTMPSR (*(vuint16_t*)(&__MBAR[0x00B1F2])) -#define MCF_USB_EP6OUTMPSR (*(vuint16_t*)(&__MBAR[0x00B222])) -#define MCF_USB_EPnOUTMPSR(x) (*(vuint16_t*)(&__MBAR[0x00B132+((x)*0x030)])) -#define MCF_USB_EP1OUTIFR (*(vuint8_t *)(&__MBAR[0x00B134])) -#define MCF_USB_EP2OUTIFR (*(vuint8_t *)(&__MBAR[0x00B164])) -#define MCF_USB_EP3OUTIFR (*(vuint8_t *)(&__MBAR[0x00B194])) -#define MCF_USB_EP4OUTIFR (*(vuint8_t *)(&__MBAR[0x00B1C4])) -#define MCF_USB_EP5OUTIFR (*(vuint8_t *)(&__MBAR[0x00B1F4])) -#define MCF_USB_EP6OUTIFR (*(vuint8_t *)(&__MBAR[0x00B224])) -#define MCF_USB_EPnOUTIFR(x) (*(vuint8_t *)(&__MBAR[0x00B134+((x)*0x030)])) -#define MCF_USB_EP1OUTSR (*(vuint8_t *)(&__MBAR[0x00B135])) -#define MCF_USB_EP2OUTSR (*(vuint8_t *)(&__MBAR[0x00B165])) -#define MCF_USB_EP3OUTSR (*(vuint8_t *)(&__MBAR[0x00B195])) -#define MCF_USB_EP4OUTSR (*(vuint8_t *)(&__MBAR[0x00B1C5])) -#define MCF_USB_EP5OUTSR (*(vuint8_t *)(&__MBAR[0x00B1F5])) -#define MCF_USB_EP6OUTSR (*(vuint8_t *)(&__MBAR[0x00B225])) -#define MCF_USB_EPnOUTSR(x) (*(vuint8_t *)(&__MBAR[0x00B135+((x)*0x030)])) -#define MCF_USB_EP1OUTSFR (*(vuint16_t*)(&__MBAR[0x00B13E])) -#define MCF_USB_EP2OUTSFR (*(vuint16_t*)(&__MBAR[0x00B16E])) -#define MCF_USB_EP3OUTSFR (*(vuint16_t*)(&__MBAR[0x00B19E])) -#define MCF_USB_EP4OUTSFR (*(vuint16_t*)(&__MBAR[0x00B1CE])) -#define MCF_USB_EP5OUTSFR (*(vuint16_t*)(&__MBAR[0x00B1FE])) -#define MCF_USB_EP6OUTSFR (*(vuint16_t*)(&__MBAR[0x00B22E])) -#define MCF_USB_EPnOUTSFR(x) (*(vuint16_t*)(&__MBAR[0x00B13E+((x)*0x030)])) -#define MCF_USB_EP1INACR (*(vuint8_t *)(&__MBAR[0x00B149])) -#define MCF_USB_EP2INACR (*(vuint8_t *)(&__MBAR[0x00B179])) -#define MCF_USB_EP3INACR (*(vuint8_t *)(&__MBAR[0x00B1A9])) -#define MCF_USB_EP4INACR (*(vuint8_t *)(&__MBAR[0x00B1D9])) -#define MCF_USB_EP5INACR (*(vuint8_t *)(&__MBAR[0x00B209])) -#define MCF_USB_EP6INACR (*(vuint8_t *)(&__MBAR[0x00B239])) -#define MCF_USB_EPnINACR(x) (*(vuint8_t *)(&__MBAR[0x00B149+((x)*0x030)])) -#define MCF_USB_EP1INMPSR (*(vuint16_t*)(&__MBAR[0x00B14A])) -#define MCF_USB_EP2INMPSR (*(vuint16_t*)(&__MBAR[0x00B17A])) -#define MCF_USB_EP3INMPSR (*(vuint16_t*)(&__MBAR[0x00B1AA])) -#define MCF_USB_EP4INMPSR (*(vuint16_t*)(&__MBAR[0x00B1DA])) -#define MCF_USB_EP5INMPSR (*(vuint16_t*)(&__MBAR[0x00B20A])) -#define MCF_USB_EP6INMPSR (*(vuint16_t*)(&__MBAR[0x00B23A])) -#define MCF_USB_EPnINMPSR(x) (*(vuint16_t*)(&__MBAR[0x00B14A+((x)*0x030)])) -#define MCF_USB_EP1INIFR (*(vuint8_t *)(&__MBAR[0x00B14C])) -#define MCF_USB_EP2INIFR (*(vuint8_t *)(&__MBAR[0x00B17C])) -#define MCF_USB_EP3INIFR (*(vuint8_t *)(&__MBAR[0x00B1AC])) -#define MCF_USB_EP4INIFR (*(vuint8_t *)(&__MBAR[0x00B1DC])) -#define MCF_USB_EP5INIFR (*(vuint8_t *)(&__MBAR[0x00B20C])) -#define MCF_USB_EP6INIFR (*(vuint8_t *)(&__MBAR[0x00B23C])) -#define MCF_USB_EPnINIFR(x) (*(vuint8_t *)(&__MBAR[0x00B14C+((x)*0x030)])) -#define MCF_USB_EP1INSR (*(vuint8_t *)(&__MBAR[0x00B14D])) -#define MCF_USB_EP2INSR (*(vuint8_t *)(&__MBAR[0x00B17D])) -#define MCF_USB_EP3INSR (*(vuint8_t *)(&__MBAR[0x00B1AD])) -#define MCF_USB_EP4INSR (*(vuint8_t *)(&__MBAR[0x00B1DD])) -#define MCF_USB_EP5INSR (*(vuint8_t *)(&__MBAR[0x00B20D])) -#define MCF_USB_EP6INSR (*(vuint8_t *)(&__MBAR[0x00B23D])) -#define MCF_USB_EPnINSR(x) (*(vuint8_t *)(&__MBAR[0x00B14D+((x)*0x030)])) -#define MCF_USB_EP1INSFR (*(vuint16_t*)(&__MBAR[0x00B15A])) -#define MCF_USB_EP2INSFR (*(vuint16_t*)(&__MBAR[0x00B18A])) -#define MCF_USB_EP3INSFR (*(vuint16_t*)(&__MBAR[0x00B1BA])) -#define MCF_USB_EP4INSFR (*(vuint16_t*)(&__MBAR[0x00B1EA])) -#define MCF_USB_EP5INSFR (*(vuint16_t*)(&__MBAR[0x00B21A])) -#define MCF_USB_EP6INSFR (*(vuint16_t*)(&__MBAR[0x00B24A])) -#define MCF_USB_EPnINSFR(x) (*(vuint16_t*)(&__MBAR[0x00B15A+((x)*0x030)])) -#define MCF_USB_USBSR (*(vuint32_t*)(&__MBAR[0x00B400])) -#define MCF_USB_USBCR (*(vuint32_t*)(&__MBAR[0x00B404])) -#define MCF_USB_DRAMCR (*(vuint32_t*)(&__MBAR[0x00B408])) -#define MCF_USB_DRAMDR (*(vuint32_t*)(&__MBAR[0x00B40C])) -#define MCF_USB_USBISR (*(vuint32_t*)(&__MBAR[0x00B410])) -#define MCF_USB_USBIMR (*(vuint32_t*)(&__MBAR[0x00B414])) -#define MCF_USB_EP0STAT (*(vuint32_t*)(&__MBAR[0x00B440])) -#define MCF_USB_EP1STAT (*(vuint32_t*)(&__MBAR[0x00B470])) -#define MCF_USB_EP2STAT (*(vuint32_t*)(&__MBAR[0x00B4A0])) -#define MCF_USB_EP3STAT (*(vuint32_t*)(&__MBAR[0x00B4D0])) -#define MCF_USB_EP4STAT (*(vuint32_t*)(&__MBAR[0x00B500])) -#define MCF_USB_EP5STAT (*(vuint32_t*)(&__MBAR[0x00B530])) -#define MCF_USB_EP6STAT (*(vuint32_t*)(&__MBAR[0x00B560])) -#define MCF_USB_EPnSTAT(x) (*(vuint32_t*)(&__MBAR[0x00B440+((x)*0x030)])) -#define MCF_USB_EP0ISR (*(vuint32_t*)(&__MBAR[0x00B444])) -#define MCF_USB_EP1ISR (*(vuint32_t*)(&__MBAR[0x00B474])) -#define MCF_USB_EP2ISR (*(vuint32_t*)(&__MBAR[0x00B4A4])) -#define MCF_USB_EP3ISR (*(vuint32_t*)(&__MBAR[0x00B4D4])) -#define MCF_USB_EP4ISR (*(vuint32_t*)(&__MBAR[0x00B504])) -#define MCF_USB_EP5ISR (*(vuint32_t*)(&__MBAR[0x00B534])) -#define MCF_USB_EP6ISR (*(vuint32_t*)(&__MBAR[0x00B564])) -#define MCF_USB_EPnISR(x) (*(vuint32_t*)(&__MBAR[0x00B444+((x)*0x030)])) -#define MCF_USB_EP0IMR (*(vuint32_t*)(&__MBAR[0x00B448])) -#define MCF_USB_EP1IMR (*(vuint32_t*)(&__MBAR[0x00B478])) -#define MCF_USB_EP2IMR (*(vuint32_t*)(&__MBAR[0x00B4A8])) -#define MCF_USB_EP3IMR (*(vuint32_t*)(&__MBAR[0x00B4D8])) -#define MCF_USB_EP4IMR (*(vuint32_t*)(&__MBAR[0x00B508])) -#define MCF_USB_EP5IMR (*(vuint32_t*)(&__MBAR[0x00B538])) -#define MCF_USB_EP6IMR (*(vuint32_t*)(&__MBAR[0x00B568])) -#define MCF_USB_EPnIMR(x) (*(vuint32_t*)(&__MBAR[0x00B448+((x)*0x030)])) -#define MCF_USB_EP0FRCFGR (*(vuint32_t*)(&__MBAR[0x00B44C])) -#define MCF_USB_EP1FRCFGR (*(vuint32_t*)(&__MBAR[0x00B47C])) -#define MCF_USB_EP2FRCFGR (*(vuint32_t*)(&__MBAR[0x00B4AC])) -#define MCF_USB_EP3FRCFGR (*(vuint32_t*)(&__MBAR[0x00B4DC])) -#define MCF_USB_EP4FRCFGR (*(vuint32_t*)(&__MBAR[0x00B50C])) -#define MCF_USB_EP5FRCFGR (*(vuint32_t*)(&__MBAR[0x00B53C])) -#define MCF_USB_EP6FRCFGR (*(vuint32_t*)(&__MBAR[0x00B56C])) -#define MCF_USB_EPnFRCFGR(x) (*(vuint32_t*)(&__MBAR[0x00B44C+((x)*0x030)])) -#define MCF_USB_EP0FDR (*(vuint32_t*)(&__MBAR[0x00B450])) -#define MCF_USB_EP1FDR (*(vuint32_t*)(&__MBAR[0x00B480])) -#define MCF_USB_EP2FDR (*(vuint32_t*)(&__MBAR[0x00B4B0])) -#define MCF_USB_EP3FDR (*(vuint32_t*)(&__MBAR[0x00B4E0])) -#define MCF_USB_EP4FDR (*(vuint32_t*)(&__MBAR[0x00B510])) -#define MCF_USB_EP5FDR (*(vuint32_t*)(&__MBAR[0x00B540])) -#define MCF_USB_EP6FDR (*(vuint32_t*)(&__MBAR[0x00B570])) -#define MCF_USB_EPnFDR(x) (*(vuint32_t*)(&__MBAR[0x00B450+((x)*0x030)])) -#define MCF_USB_EP0FSR (*(vuint32_t*)(&__MBAR[0x00B454])) -#define MCF_USB_EP1FSR (*(vuint32_t*)(&__MBAR[0x00B484])) -#define MCF_USB_EP2FSR (*(vuint32_t*)(&__MBAR[0x00B4B4])) -#define MCF_USB_EP3FSR (*(vuint32_t*)(&__MBAR[0x00B4E4])) -#define MCF_USB_EP4FSR (*(vuint32_t*)(&__MBAR[0x00B514])) -#define MCF_USB_EP5FSR (*(vuint32_t*)(&__MBAR[0x00B544])) -#define MCF_USB_EP6FSR (*(vuint32_t*)(&__MBAR[0x00B574])) -#define MCF_USB_EPnFSR(x) (*(vuint32_t*)(&__MBAR[0x00B454+((x)*0x030)])) -#define MCF_USB_EP0FCR (*(vuint32_t*)(&__MBAR[0x00B458])) -#define MCF_USB_EP1FCR (*(vuint32_t*)(&__MBAR[0x00B488])) -#define MCF_USB_EP2FCR (*(vuint32_t*)(&__MBAR[0x00B4B8])) -#define MCF_USB_EP3FCR (*(vuint32_t*)(&__MBAR[0x00B4E8])) -#define MCF_USB_EP4FCR (*(vuint32_t*)(&__MBAR[0x00B518])) -#define MCF_USB_EP5FCR (*(vuint32_t*)(&__MBAR[0x00B548])) -#define MCF_USB_EP6FCR (*(vuint32_t*)(&__MBAR[0x00B578])) -#define MCF_USB_EPnFCR(x) (*(vuint32_t*)(&__MBAR[0x00B458+((x)*0x030)])) -#define MCF_USB_EP0FAR (*(vuint32_t*)(&__MBAR[0x00B45C])) -#define MCF_USB_EP1FAR (*(vuint32_t*)(&__MBAR[0x00B48C])) -#define MCF_USB_EP2FAR (*(vuint32_t*)(&__MBAR[0x00B4BC])) -#define MCF_USB_EP3FAR (*(vuint32_t*)(&__MBAR[0x00B4EC])) -#define MCF_USB_EP4FAR (*(vuint32_t*)(&__MBAR[0x00B51C])) -#define MCF_USB_EP5FAR (*(vuint32_t*)(&__MBAR[0x00B54C])) -#define MCF_USB_EP6FAR (*(vuint32_t*)(&__MBAR[0x00B57C])) -#define MCF_USB_EPnFAR(x) (*(vuint32_t*)(&__MBAR[0x00B45C+((x)*0x030)])) -#define MCF_USB_EP0FRP (*(vuint32_t*)(&__MBAR[0x00B460])) -#define MCF_USB_EP1FRP (*(vuint32_t*)(&__MBAR[0x00B490])) -#define MCF_USB_EP2FRP (*(vuint32_t*)(&__MBAR[0x00B4C0])) -#define MCF_USB_EP3FRP (*(vuint32_t*)(&__MBAR[0x00B4F0])) -#define MCF_USB_EP4FRP (*(vuint32_t*)(&__MBAR[0x00B520])) -#define MCF_USB_EP5FRP (*(vuint32_t*)(&__MBAR[0x00B550])) -#define MCF_USB_EP6FRP (*(vuint32_t*)(&__MBAR[0x00B580])) -#define MCF_USB_EPnFRP(x) (*(vuint32_t*)(&__MBAR[0x00B460+((x)*0x030)])) -#define MCF_USB_EP0FWP (*(vuint32_t*)(&__MBAR[0x00B464])) -#define MCF_USB_EP1FWP (*(vuint32_t*)(&__MBAR[0x00B494])) -#define MCF_USB_EP2FWP (*(vuint32_t*)(&__MBAR[0x00B4C4])) -#define MCF_USB_EP3FWP (*(vuint32_t*)(&__MBAR[0x00B4F4])) -#define MCF_USB_EP4FWP (*(vuint32_t*)(&__MBAR[0x00B524])) -#define MCF_USB_EP5FWP (*(vuint32_t*)(&__MBAR[0x00B554])) -#define MCF_USB_EP6FWP (*(vuint32_t*)(&__MBAR[0x00B584])) -#define MCF_USB_EPnFWP(x) (*(vuint32_t*)(&__MBAR[0x00B464+((x)*0x030)])) -#define MCF_USB_EP0LRFP (*(vuint32_t*)(&__MBAR[0x00B468])) -#define MCF_USB_EP1LRFP (*(vuint32_t*)(&__MBAR[0x00B498])) -#define MCF_USB_EP2LRFP (*(vuint32_t*)(&__MBAR[0x00B4C8])) -#define MCF_USB_EP3LRFP (*(vuint32_t*)(&__MBAR[0x00B4F8])) -#define MCF_USB_EP4LRFP (*(vuint32_t*)(&__MBAR[0x00B528])) -#define MCF_USB_EP5LRFP (*(vuint32_t*)(&__MBAR[0x00B558])) -#define MCF_USB_EP6LRFP (*(vuint32_t*)(&__MBAR[0x00B588])) -#define MCF_USB_EPnLRFP(x) (*(vuint32_t*)(&__MBAR[0x00B468+((x)*0x030)])) -#define MCF_USB_EP0LWFP (*(vuint32_t*)(&__MBAR[0x00B46C])) -#define MCF_USB_EP1LWFP (*(vuint32_t*)(&__MBAR[0x00B49C])) -#define MCF_USB_EP2LWFP (*(vuint32_t*)(&__MBAR[0x00B4CC])) -#define MCF_USB_EP3LWFP (*(vuint32_t*)(&__MBAR[0x00B4FC])) -#define MCF_USB_EP4LWFP (*(vuint32_t*)(&__MBAR[0x00B52C])) -#define MCF_USB_EP5LWFP (*(vuint32_t*)(&__MBAR[0x00B55C])) -#define MCF_USB_EP6LWFP (*(vuint32_t*)(&__MBAR[0x00B58C])) -#define MCF_USB_EPnLWFP(x) (*(vuint32_t*)(&__MBAR[0x00B46C+((x)*0x030)])) - -/* Bit definitions and macros for MCF_USB_USBAISR */ -#define MCF_USB_USBAISR_SETUP (0x01) -#define MCF_USB_USBAISR_IN (0x02) -#define MCF_USB_USBAISR_OUT (0x04) -#define MCF_USB_USBAISR_EPHALT (0x08) -#define MCF_USB_USBAISR_TRANSERR (0x10) -#define MCF_USB_USBAISR_ACK (0x20) -#define MCF_USB_USBAISR_CTROVFL (0x40) -#define MCF_USB_USBAISR_EPSTALL (0x80) - -/* Bit definitions and macros for MCF_USB_USBAIMR */ -#define MCF_USB_USBAIMR_SETUPEN (0x01) -#define MCF_USB_USBAIMR_INEN (0x02) -#define MCF_USB_USBAIMR_OUTEN (0x04) -#define MCF_USB_USBAIMR_EPHALTEN (0x08) -#define MCF_USB_USBAIMR_TRANSERREN (0x10) -#define MCF_USB_USBAIMR_ACKEN (0x20) -#define MCF_USB_USBAIMR_CTROVFLEN (0x40) -#define MCF_USB_USBAIMR_EPSTALLEN (0x80) - -/* Bit definitions and macros for MCF_USB_EPINFO */ -#define MCF_USB_EPINFO_EPDIR (0x01) -#define MCF_USB_EPINFO_EPNUM(x) (((x)&0x07)<<1) - -/* Bit definitions and macros for MCF_USB_CFGAR */ -#define MCF_USB_CFGAR_RESERVED (0xA0) -#define MCF_USB_CFGAR_RMTWKEUP (0xE0) - -/* Bit definitions and macros for MCF_USB_SPEEDR */ -#define MCF_USB_SPEEDR_HS (0x01) -#define MCF_USB_SPEEDR_FS (0x02) - -/* Bit definitions and macros for MCF_USB_FRMNUMR */ -#define MCF_USB_FRMNUMR_FRMNUM(x) (((x)&0x0FFF)<<0) - -/* Bit definitions and macros for MCF_USB_EPTNR */ -#define MCF_USB_EPTNR_EP1T(x) (((x)&0x0003)<<0) -#define MCF_USB_EPTNR_EP2T(x) (((x)&0x0003)<<2) -#define MCF_USB_EPTNR_EP3T(x) (((x)&0x0003)<<4) -#define MCF_USB_EPTNR_EP4T(x) (((x)&0x0003)<<6) -#define MCF_USB_EPTNR_EP5T(x) (((x)&0x0003)<<8) -#define MCF_USB_EPTNR_EP6T(x) (((x)&0x0003)<<10) -#define MCF_USB_EPTNR_EPnT1 (0) -#define MCF_USB_EPTNR_EPnT2 (1) -#define MCF_USB_EPTNR_EPnT3 (2) - -/* Bit definitions and macros for MCF_USB_IFUR */ -#define MCF_USB_IFUR_ALTSET(x) (((x)&0x00FF)<<0) -#define MCF_USB_IFUR_IFNUM(x) (((x)&0x00FF)<<8) - -/* Bit definitions and macros for MCF_USB_IFRn */ -#define MCF_USB_IFRn_ALTSET(x) (((x)&0x00FF)<<0) -#define MCF_USB_IFRn_IFNUM(x) (((x)&0x00FF)<<8) - -/* Bit definitions and macros for MCF_USB_CNTOVR */ -#define MCF_USB_CNTOVR_PPCNT (0x01) -#define MCF_USB_CNTOVR_DPCNT (0x02) -#define MCF_USB_CNTOVR_CRCECNT (0x04) -#define MCF_USB_CNTOVR_BSECNT (0x08) -#define MCF_USB_CNTOVR_PIDECNT (0x10) -#define MCF_USB_CNTOVR_FRMECNT (0x20) -#define MCF_USB_CNTOVR_TXPCNT (0x40) - -/* Bit definitions and macros for MCF_USB_EP0ACR */ -#define MCF_USB_EP0ACR_TTYPE(x) (((x)&0x03)<<0) -#define MCF_USB_EP0ACR_TTYPE_CTRL (0) -#define MCF_USB_EP0ACR_TTYPE_ISOC (1) -#define MCF_USB_EP0ACR_TTYPE_BULK (2) -#define MCF_USB_EP0ACR_TTYPE_INT (3) - -/* Bit definitions and macros for MCF_USB_EP0MPSR */ -#define MCF_USB_EP0MPSR_MAXPKTSZ(x) (((x)&0x07FF)<<0) -#define MCF_USB_EP0MPSR_ADDTRANS(x) (((x)&0x0003)<<11) - -/* Bit definitions and macros for MCF_USB_EP0SR */ -#define MCF_USB_EP0SR_HALT (0x01) -#define MCF_USB_EP0SR_ACTIVE (0x02) -#define MCF_USB_EP0SR_PSTALL (0x04) -#define MCF_USB_EP0SR_CCOMP (0x08) -#define MCF_USB_EP0SR_TXZERO (0x20) -#define MCF_USB_EP0SR_INT (0x80) - -/* Bit definitions and macros for MCF_USB_BMRTR */ -#define MCF_USB_BMRTR_DIR (0x80) -#define MCF_USB_BMRTR_TYPE_STANDARD (0x00) -#define MCF_USB_BMRTR_TYPE_CLASS (0x20) -#define MCF_USB_BMRTR_TYPE_VENDOR (0x40) -#define MCF_USB_BMRTR_REC_DEVICE (0x00) -#define MCF_USB_BMRTR_REC_INTERFACE (0x01) -#define MCF_USB_BMRTR_REC_ENDPOINT (0x02) -#define MCF_USB_BMRTR_REC_OTHER (0x03) - -/* Bit definitions and macros for MCF_USB_EPnOUTACR */ -#define MCF_USB_EPnOUTACR_TTYPE(x) (((x)&0x03)<<0) - -/* Bit definitions and macros for MCF_USB_EPnOUTMPSR */ -#define MCF_USB_EPnOUTMPSR_MAXPKTSZ(x) (((x)&0x07FF)<<0) -#define MCF_USB_EPnOUTMPSR_ADDTRANS(x) (((x)&0x0003)<<11) - -/* Bit definitions and macros for MCF_USB_EPnOUTSR */ -#define MCF_USB_EPnOUTSR_HALT (0x01) -#define MCF_USB_EPnOUTSR_ACTIVE (0x02) -#define MCF_USB_EPnOUTSR_PSTALL (0x04) -#define MCF_USB_EPnOUTSR_CCOMP (0x08) -#define MCF_USB_EPnOUTSR_TXZERO (0x20) -#define MCF_USB_EPnOUTSR_INT (0x80) - -/* Bit definitions and macros for MCF_USB_EPnOUTSFR */ -#define MCF_USB_EPnOUTSFR_FRMNUM(x) (((x)&0x07FF)<<0) - -/* Bit definitions and macros for MCF_USB_EPnINACR */ -#define MCF_USB_EPnINACR_TTYPE(x) (((x)&0x03)<<0) - -/* Bit definitions and macros for MCF_USB_EPnINMPSR */ -#define MCF_USB_EPnINMPSR_MAXPKTSZ(x) (((x)&0x07FF)<<0) -#define MCF_USB_EPnINMPSR_ADDTRANS(x) (((x)&0x0003)<<11) - -/* Bit definitions and macros for MCF_USB_EPnINSR */ -#define MCF_USB_EPnINSR_HALT (0x01) -#define MCF_USB_EPnINSR_ACTIVE (0x02) -#define MCF_USB_EPnINSR_PSTALL (0x04) -#define MCF_USB_EPnINSR_CCOMP (0x08) -#define MCF_USB_EPnINSR_TXZERO (0x20) -#define MCF_USB_EPnINSR_INT (0x80) - -/* Bit definitions and macros for MCF_USB_EPnINSFR */ -#define MCF_USB_EPnINSFR_FRMNUM(x) (((x)&0x07FF)<<0) - -/* Bit definitions and macros for MCF_USB_USBSR */ -#define MCF_USB_USBSR_SUSP (0x00000080) -#define MCF_USB_USBSR_ISOERREP (0x0000000F) - -/* Bit definitions and macros for MCF_USB_USBCR */ -#define MCF_USB_USBCR_RESUME (0x00000001) -#define MCF_USB_USBCR_APPLOCK (0x00000002) -#define MCF_USB_USBCR_RST (0x00000004) -#define MCF_USB_USBCR_RAMEN (0x00000008) -#define MCF_USB_USBCR_RAMSPLIT (0x00000020) - -/* Bit definitions and macros for MCF_USB_DRAMCR */ -#define MCF_USB_DRAMCR_DADR(x) (((x)&0x000003FF)<<0) -#define MCF_USB_DRAMCR_DSIZE(x) (((x)&0x000007FF)<<16) -#define MCF_USB_DRAMCR_BSY (0x40000000) -#define MCF_USB_DRAMCR_START (0x80000000) - -/* Bit definitions and macros for MCF_USB_DRAMDR */ -#define MCF_USB_DRAMDR_DDAT(x) (((x)&0x000000FF)<<0) - -/* Bit definitions and macros for MCF_USB_USBISR */ -#define MCF_USB_USBISR_ISOERR (0x00000001) -#define MCF_USB_USBISR_FTUNLCK (0x00000002) -#define MCF_USB_USBISR_SUSP (0x00000004) -#define MCF_USB_USBISR_RES (0x00000008) -#define MCF_USB_USBISR_UPDSOF (0x00000010) -#define MCF_USB_USBISR_RSTSTOP (0x00000020) -#define MCF_USB_USBISR_SOF (0x00000040) -#define MCF_USB_USBISR_MSOF (0x00000080) - -/* Bit definitions and macros for MCF_USB_USBIMR */ -#define MCF_USB_USBIMR_ISOERR (0x00000001) -#define MCF_USB_USBIMR_FTUNLCK (0x00000002) -#define MCF_USB_USBIMR_SUSP (0x00000004) -#define MCF_USB_USBIMR_RES (0x00000008) -#define MCF_USB_USBIMR_UPDSOF (0x00000010) -#define MCF_USB_USBIMR_RSTSTOP (0x00000020) -#define MCF_USB_USBIMR_SOF (0x00000040) -#define MCF_USB_USBIMR_MSOF (0x00000080) - -/* Bit definitions and macros for MCF_USB_EPnSTAT */ -#define MCF_USB_EPnSTAT_RST (0x00000001) -#define MCF_USB_EPnSTAT_FLUSH (0x00000002) -#define MCF_USB_EPnSTAT_DIR (0x00000080) -#define MCF_USB_EPnSTAT_BYTECNT(x) (((x)&0x00000FFF)<<16) - -/* Bit definitions and macros for MCF_USB_EPnISR */ -#define MCF_USB_EPnISR_EOF (0x00000001) -#define MCF_USB_EPnISR_EOT (0x00000004) -#define MCF_USB_EPnISR_FIFOLO (0x00000010) -#define MCF_USB_EPnISR_FIFOHI (0x00000020) -#define MCF_USB_EPnISR_ERR (0x00000040) -#define MCF_USB_EPnISR_EMT (0x00000080) -#define MCF_USB_EPnISR_FU (0x00000100) - -/* Bit definitions and macros for MCF_USB_EPnIMR */ -#define MCF_USB_EPnIMR_EOF (0x00000001) -#define MCF_USB_EPnIMR_EOT (0x00000004) -#define MCF_USB_EPnIMR_FIFOLO (0x00000010) -#define MCF_USB_EPnIMR_FIFOHI (0x00000020) -#define MCF_USB_EPnIMR_ERR (0x00000040) -#define MCF_USB_EPnIMR_EMT (0x00000080) -#define MCF_USB_EPnIMR_FU (0x00000100) - -/* Bit definitions and macros for MCF_USB_EPnFRCFGR */ -#define MCF_USB_EPnFRCFGR_DEPTH(x) (((x)&0x00001FFF)<<0) -#define MCF_USB_EPnFRCFGR_BASE(x) (((x)&0x00000FFF)<<16) - -/* Bit definitions and macros for MCF_USB_EPnFSR */ -#define MCF_USB_EPnFSR_EMT (0x00010000) -#define MCF_USB_EPnFSR_ALRM (0x00020000) -#define MCF_USB_EPnFSR_FR (0x00040000) -#define MCF_USB_EPnFSR_FU (0x00080000) -#define MCF_USB_EPnFSR_OF (0x00100000) -#define MCF_USB_EPnFSR_UF (0x00200000) -#define MCF_USB_EPnFSR_RXW (0x00400000) -#define MCF_USB_EPnFSR_FAE (0x00800000) -#define MCF_USB_EPnFSR_FRM(x) (((x)&0x0000000F)<<24) -#define MCF_USB_EPnFSR_TXW (0x40000000) -#define MCF_USB_EPnFSR_IP (0x80000000) - -/* Bit definitions and macros for MCF_USB_EPnFCR */ -#define MCF_USB_EPnFCR_COUNTER(x) (((x)&0x0000FFFF)<<0) -#define MCF_USB_EPnFCR_TXWMSK (0x00040000) -#define MCF_USB_EPnFCR_OFMSK (0x00080000) -#define MCF_USB_EPnFCR_UFMSK (0x00100000) -#define MCF_USB_EPnFCR_RXWMSK (0x00200000) -#define MCF_USB_EPnFCR_FAEMSK (0x00400000) -#define MCF_USB_EPnFCR_IPMSK (0x00800000) -#define MCF_USB_EPnFCR_GR(x) (((x)&0x00000007)<<24) -#define MCF_USB_EPnFCR_FRM (0x08000000) -#define MCF_USB_EPnFCR_TMR (0x10000000) -#define MCF_USB_EPnFCR_WFR (0x20000000) -#define MCF_USB_EPnFCR_SHAD (0x80000000) - -/* Bit definitions and macros for MCF_USB_EPnFAR */ -#define MCF_USB_EPnFAR_ALRMP(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_USB_EPnFRP */ -#define MCF_USB_EPnFRP_RP(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_USB_EPnFWP */ -#define MCF_USB_EPnFWP_WP(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_USB_EPnLRFP */ -#define MCF_USB_EPnLRFP_LRFP(x) (((x)&0x00000FFF)<<0) - -/* Bit definitions and macros for MCF_USB_EPnLWFP */ -#define MCF_USB_EPnLWFP_LWFP(x) (((x)&0x00000FFF)<<0) - - -#endif /* __MCF548X_USB_H__ */ diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_xlbarb.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_xlbarb.h deleted file mode 100644 index f4df976b37..0000000000 --- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_xlbarb.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Register and bit definitions for the MCF548X and MCF547x - * XLB bus arbiter - */ -#ifndef __MCF548X_XLBARB_H__ -#define __MCF548X_XLBARB_H__ - -/* - * XLB arbiter register - */ -#define MCF_XLBARB_ACFG (*(vuint32*)(&__MBAR[0x000240])) -#define MCF_XLBARB_VER (*(vuint32*)(&__MBAR[0x000244])) -#define MCF_XLBARB_STA (*(vuint32*)(&__MBAR[0x000248])) -#define MCF_XLBARB_INTEN (*(vuint32*)(&__MBAR[0x00024C])) -#define MCF_XLBARB_ADRCAP (*(vuint32*)(&__MBAR[0x000250])) -#define MCF_XLBARB_SIGCAP (*(vuint32*)(&__MBAR[0x000254])) -#define MCF_XLBARB_ADRTO (*(vuint32*)(&__MBAR[0x000258])) -#define MCF_XLBARB_DATTO (*(vuint32*)(&__MBAR[0x00025C])) -#define MCF_XLBARB_BUSTO (*(vuint32*)(&__MBAR[0x000260])) -#define MCF_XLBARB_PRIEN (*(vuint32*)(&__MBAR[0x000264])) -#define MCF_XLBARB_PRI (*(vuint32*)(&__MBAR[0x000268])) -#define MCF_XLBARB_BAR (*(vuint32*)(&__MBAR[0x00026C])) - - -#endif /* __MCF548X_XLBARB_H__ */ diff --git a/arch/m68k/include/asm/coldfire/mcf5xxx.h b/arch/m68k/include/asm/coldfire/mcf5xxx.h deleted file mode 100644 index 5edde1e8b3..0000000000 --- a/arch/m68k/include/asm/coldfire/mcf5xxx.h +++ /dev/null @@ -1,258 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Definitions common across all ColdFire processors - */ -#ifndef __MCF5XXX__H -#define __MCF5XXX__H - -/* - * Common M68K & ColdFire definitions - */ -#define ADDRESS uint32_t -#define INSTRUCTION uint16_t -#define ILLEGAL 0x4AFC -#define CPU_WORD_SIZE 16 - -/* - * Definitions for CPU status register (SR) - */ -#define MCF5XXX_SR_T (0x8000) -#define MCF5XXX_SR_S (0x2000) -#define MCF5XXX_SR_M (0x1000) -#define MCF5XXX_SR_IPL (0x0700) -#define MCF5XXX_SR_IPL_0 (0x0000) -#define MCF5XXX_SR_IPL_1 (0x0100) -#define MCF5XXX_SR_IPL_2 (0x0200) -#define MCF5XXX_SR_IPL_3 (0x0300) -#define MCF5XXX_SR_IPL_4 (0x0400) -#define MCF5XXX_SR_IPL_5 (0x0500) -#define MCF5XXX_SR_IPL_6 (0x0600) -#define MCF5XXX_SR_IPL_7 (0x0700) -#define MCF5XXX_SR_X (0x0010) -#define MCF5XXX_SR_N (0x0008) -#define MCF5XXX_SR_Z (0x0004) -#define MCF5XXX_SR_V (0x0002) -#define MCF5XXX_SR_C (0x0001) - -/* - * Definitions for CPU cache control register - */ -#define MCF5XXX_CACR_CENB (0x80000000) -#define MCF5XXX_CACR_DEC (0x80000000) -#define MCF5XXX_CACR_DW (0x40000000) -#define MCF5XXX_CACR_DESB (0x20000000) -#define MCF5XXX_CACR_CPDI (0x10000000) -#define MCF5XXX_CACR_DDPI (0x10000000) -#define MCF5XXX_CACR_CPD (0x10000000) -#define MCF5XXX_CACR_CFRZ (0x08000000) -#define MCF5XXX_CACR_DHLCK (0x08000000) -#define MCF5XXX_CACR_DDCM_WT (0x00000000) -#define MCF5XXX_CACR_DDCM_CB (0x02000000) -#define MCF5XXX_CACR_DDCM_IP (0x04000000) -#define MCF5XXX_CACR_DDCM_II (0x06000000) -#define MCF5XXX_CACR_CINV (0x01000000) -#define MCF5XXX_CACR_DCINVA (0x01000000) -#define MCF5XXX_CACR_DIDI (0x00800000) -#define MCF5XXX_CACR_DDSP (0x00800000) -#define MCF5XXX_CACR_DISD (0x00400000) -#define MCF5XXX_CACR_INVI (0x00200000) -#define MCF5XXX_CACR_INVD (0x00100000) -#define MCF5XXX_CACR_BEC (0x00080000) -#define MCF5XXX_CACR_BCINVA (0x00040000) -#define MCF5XXX_CACR_IEC (0x00008000) -#define MCF5XXX_CACR_DNFB (0x00002000) -#define MCF5XXX_CACR_IDPI (0x00001000) -#define MCF5XXX_CACR_IHLCK (0x00000800) -#define MCF5XXX_CACR_CEIB (0x00000400) -#define MCF5XXX_CACR_IDCM (0x00000400) -#define MCF5XXX_CACR_DCM_WR (0x00000000) -#define MCF5XXX_CACR_DCM_CB (0x00000100) -#define MCF5XXX_CACR_DCM_IP (0x00000200) -#define MCF5XXX_CACR_DCM (0x00000200) -#define MCF5XXX_CACR_DCM_II (0x00000300) -#define MCF5XXX_CACR_DBWE (0x00000100) -#define MCF5XXX_CACR_ICINVA (0x00000100) -#define MCF5XXX_CACR_IDSP (0x00000080) -#define MCF5XXX_CACR_DWP (0x00000020) -#define MCF5XXX_CACR_EUSP (0x00000020) -#define MCF5XXX_CACR_EUST (0x00000020) -#define MCF5XXX_CACR_DF (0x00000010) -#define MCF5XXX_CACR_CLNF_00 (0x00000000) -#define MCF5XXX_CACR_CLNF_01 (0x00000002) -#define MCF5XXX_CACR_CLNF_10 (0x00000004) -#define MCF5XXX_CACR_CLNF_11 (0x00000006) - -/* - * Definition for CPU access control register - */ -#define MCF5XXX_ACR_AB(a) ((a)&0xFF000000) -#define MCF5XXX_ACR_AM(a) (((a)&0xFF000000) >> 8) -#define MCF5XXX_ACR_EN (0x00008000) -#define MCF5XXX_ACR_SM_USER (0x00000000) -#define MCF5XXX_ACR_SM_SUPER (0x00002000) -#define MCF5XXX_ACR_SM_IGNORE (0x00006000) -#define MCF5XXX_ACR_ENIB (0x00000080) -#define MCF5XXX_ACR_CM (0x00000040) -#define MCF5XXX_ACR_DCM_WR (0x00000000) -#define MCF5XXX_ACR_DCM_CB (0x00000020) -#define MCF5XXX_ACR_DCM_IP (0x00000040) -#define MCF5XXX_ACR_DCM_II (0x00000060) -#define MCF5XXX_ACR_CM (0x00000040) -#define MCF5XXX_ACR_BWE (0x00000020) -#define MCF5XXX_ACR_WP (0x00000004) - -/* - * Definitions for CPU core sram control registers - */ -#define MCF5XXX_RAMBAR_BA(a) ((a)&0xFFFFC000) -#define MCF5XXX_RAMBAR_PRI_00 (0x00000000) -#define MCF5XXX_RAMBAR_PRI_01 (0x00004000) -#define MCF5XXX_RAMBAR_PRI_10 (0x00008000) -#define MCF5XXX_RAMBAR_PRI_11 (0x0000C000) -#define MCF5XXX_RAMBAR_WP (0x00000100) -#define MCF5XXX_RAMBAR_CI (0x00000020) -#define MCF5XXX_RAMBAR_SC (0x00000010) -#define MCF5XXX_RAMBAR_SD (0x00000008) -#define MCF5XXX_RAMBAR_UC (0x00000004) -#define MCF5XXX_RAMBAR_UD (0x00000002) -#define MCF5XXX_RAMBAR_V (0x00000001) - - -#ifndef __ASSEMBLY__ - -extern char __MBAR[]; - - -/* - * Extention to thhe basic POSIX data types - */ -typedef volatile uint8_t vuint8_t; /* 8 bits */ -typedef volatile uint16_t vuint16_t; /* 16 bits */ -typedef volatile uint32_t vuint32_t; /* 32 bits */ - -/* - * Routines and macros for accessing Input/Output devices - */ - -#define mcf_iord_8(ADDR) *((vuint8_t *)(ADDR)) -#define mcf_iord_16(ADDR) *((vuint16_t *)(ADDR)) -#define mcf_iord_32(ADDR) *((vuint32_t *)(ADDR)) - -#define mcf_iowr_8(ADDR,DATA) *((vuint8_t *)(ADDR)) = (DATA) -#define mcf_iowr_16(ADDR,DATA) *((vuint16_t *)(ADDR)) = (DATA) -#define mcf_iowr_32(ADDR,DATA) *((vuint32_t *)(ADDR)) = (DATA) - -/* - * The ColdFire family of processors has a simplified exception stack - * frame that looks like the following: - * - * 3322222222221111 111111 - * 1098765432109876 5432109876543210 - * 8 +----------------+----------------+ - * | Program Counter | - * 4 +----------------+----------------+ - * |FS/Fmt/Vector/FS| SR | - * SP --> 0 +----------------+----------------+ - * - * The stack self-aligns to a 4-byte boundary at an exception, with - * the FS/Fmt/Vector/FS field indicating the size of the adjustment - * (SP += 0,1,2,3 bytes). - */ -#define MCF5XXX_RD_SF_FORMAT(PTR) \ - ((*((uint16_t *)(PTR)) >> 12) & 0x00FF) - -#define MCF5XXX_RD_SF_VECTOR(PTR) \ - ((*((uint16_t *)(PTR)) >> 2) & 0x00FF) - -#define MCF5XXX_RD_SF_FS(PTR) \ - ( ((*((uint16_t *)(PTR)) & 0x0C00) >> 8) | (*((uint16_t *)(PTR)) & 0x0003) ) - -#define MCF5XXX_SF_SR(PTR) *((uint16_t *)(PTR)+1) -#define MCF5XXX_SF_PC(PTR) *((uint32_t *)(PTR)+1) - -/* - * Functions provided as inline code to access supervisor mode - * registers from C. - * - * Note: Most registers are write-only. So you must use shadow registers in - * RAM to track the state of each register! - */ -static __inline__ uint16_t mcf5xxx_rd_sr(void) { uint16_t rc; __asm__ __volatile__( "move.w %%sr,%0\n" : "=r" (rc) ); return rc; } -static __inline__ void mcf5xxx_wr_sr(uint16_t value) { __asm__ __volatile__( "move.w %0,%%sr\n" : : "r" (value) ); } - -static __inline__ int asm_set_ipl(uint32_t value) -{ - uint32_t oldipl,newipl; - value = (value & 0x7) << 8U; - oldipl = mcf5xxx_rd_sr(); - newipl = oldipl & ~0x0700U; - newipl |= value; - mcf5xxx_wr_sr(newipl); - oldipl = (oldipl & 0x0700U) >> 8U; - return oldipl; -} - -static __inline__ void mcf5xxx_cpushl_bc(uint32_t* value) { __asm__ __volatile__( " move.l %0,%%a0 \n .word 0xF4E8\n nop\n" : : "a" (value) : "a0"); } - // cpushl bc,%%a0@ ??? - -static __inline__ void mcf5xxx_wr_cacr(uint32_t value) { __asm__ __volatile__( "movec %0,%%cacr\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_asid(uint32_t value) { __asm__ __volatile__( "movec %0,%%asid\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_acr0(uint32_t value) { __asm__ __volatile__( "movec %0,#4\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_acr1(uint32_t value) { __asm__ __volatile__( "movec %0,#5\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_acr2(uint32_t value) { __asm__ __volatile__( "movec %0,#6\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_acr3(uint32_t value) { __asm__ __volatile__( "movec %0,#7\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_mmubar(uint32_t value) { __asm__ __volatile__( "movec %0,%%mmubar\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_other_a7(uint32_t value) { __asm__ __volatile__( "movec %0,%%other_sp\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_vbr(uint32_t value) { __asm__ __volatile__( "movec %0,%%vbr\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_macsr(uint32_t value) { __asm__ __volatile__( "movec %0,%%macsr\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_mask(uint32_t value) { __asm__ __volatile__( "movec %0,%%mask\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_acc0(uint32_t value) { __asm__ __volatile__( "movec %0,%%acc0\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_accext01(uint32_t value) { __asm__ __volatile__( "movec %0,%%accext01\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_accext23(uint32_t value) { __asm__ __volatile__( "movec %0,%%accext23\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_acc1(uint32_t value) { __asm__ __volatile__( "movec %0,%%acc1\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_acc2(uint32_t value) { __asm__ __volatile__( "movec %0,%%acc2\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_acc3(uint32_t value) { __asm__ __volatile__( "movec %0,%%acc3\n nop\n" : : "r" (value) ); } -//static __inline__ void mcf5xxx_wr_sr(uint32_t value) { __asm__ __volatile__( "movec %0,%%sr\n nop\n" : : "r" (value) ); } -//static __inline__ void mcf5xxx_wr_pc(uint32_t value) { __asm__ __volatile__( "movec %0,#0x080F\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_rombar0(uint32_t value) { __asm__ __volatile__( "movec %0,%%rombar0\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_rombar1(uint32_t value) { __asm__ __volatile__( "movec %0,%%rombar1\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_rambar0(uint32_t value) { __asm__ __volatile__( "movec %0,%%rambar0\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_rambar1(uint32_t value) { __asm__ __volatile__( "movec %0,%%rambar1\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_mpcr(uint32_t value) { __asm__ __volatile__( "movec %0,%%mpcr\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_secmbar(uint32_t value) { __asm__ __volatile__( "movec %0,%%mbar1\n nop\n" : : "r" (value) ); } -static __inline__ void mcf5xxx_wr_mbar(uint32_t value) { __asm__ __volatile__( "movec %0,%%mbar0\n nop\n" : : "r" (value) ); } - -#endif - -/* - * Now do specific ColdFire processor - */ - -#if (defined(CONFIG_ARCH_MCF54xx)) -#include "asm/coldfire/mcf548x.h" - -#else -#error "Error: Yet unsupported ColdFire processor." -#endif - - -#endif /* __MCF5XXX__H */ diff --git a/arch/m68k/include/asm/common.h b/arch/m68k/include/asm/common.h deleted file mode 100644 index 202ccad0b3..0000000000 --- a/arch/m68k/include/asm/common.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Common include file wrapper for m68k architecture - */ - -/* nothing */ diff --git a/arch/m68k/include/asm/elf.h b/arch/m68k/include/asm/elf.h deleted file mode 100644 index 57fdcb2633..0000000000 --- a/arch/m68k/include/asm/elf.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Defines for M68k ELF Files - */ -#ifndef __ASMm68k_ELF_H -#define __ASMm68k_ELF_H - -/* - * ELF register definitions.. - */ - -//#include <linux/config.h> -#include <asm/ptrace.h> -//#include <asm/user.h> - -/* - * 68k ELF relocation types - */ -#define R_68K_NONE 0 -#define R_68K_32 1 -#define R_68K_16 2 -#define R_68K_8 3 -#define R_68K_PC32 4 -#define R_68K_PC16 5 -#define R_68K_PC8 6 -#define R_68K_GOT32 7 -#define R_68K_GOT16 8 -#define R_68K_GOT8 9 -#define R_68K_GOT32O 10 -#define R_68K_GOT16O 11 -#define R_68K_GOT8O 12 -#define R_68K_PLT32 13 -#define R_68K_PLT16 14 -#define R_68K_PLT8 15 -#define R_68K_PLT32O 16 -#define R_68K_PLT16O 17 -#define R_68K_PLT8O 18 -#define R_68K_COPY 19 -#define R_68K_GLOB_DAT 20 -#define R_68K_JMP_SLOT 21 -#define R_68K_RELATIVE 22 - -typedef unsigned long elf_greg_t; - -//#define ELF_NGREG (sizeof(struct user_regs_struct) / sizeof(elf_greg_t)) -#define ELF_NGREG 20 -typedef elf_greg_t elf_gregset_t[ELF_NGREG]; - -typedef struct user_m68kfp_struct elf_fpregset_t; - -/* - * This is used to ensure we don't load something for the wrong architecture. - */ -#define elf_check_arch(x) ((x)->e_machine == EM_68K) - -/* - * These are used to set parameters in the core dumps. - */ -#define ELF_CLASS ELFCLASS32 -#define ELF_DATA ELFDATA2MSB -#define ELF_ARCH EM_68K - -/* For SVR4/m68k the function pointer to be registered with `atexit' is - passed in %a1. Although my copy of the ABI has no such statement, it - is actually used on ASV. */ -#define ELF_PLAT_INIT(_r, load_addr) _r->a1 = 0 - -#define USE_ELF_CORE_DUMP -#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE) -#define ELF_EXEC_PAGESIZE 4096 -#else -#define ELF_EXEC_PAGESIZE 8192 -#endif - -/* This is the location that an ET_DYN program is loaded if exec'ed. Typical - use of this is to invoke "./ld.so someprog" to test out a new version of - the loader. We need to make sure that it is out of the way of the program - that it will "exec", and that there is sufficient room for the brk. */ - -#ifndef CONFIG_SUN3 -#define ELF_ET_DYN_BASE 0xD0000000UL -#else -#define ELF_ET_DYN_BASE 0x0D800000UL -#endif - -#define ELF_CORE_COPY_REGS(pr_reg, regs) \ - /* Bleech. */ \ - pr_reg[0] = regs->d1; \ - pr_reg[1] = regs->d2; \ - pr_reg[2] = regs->d3; \ - pr_reg[3] = regs->d4; \ - pr_reg[4] = regs->d5; \ - pr_reg[7] = regs->a0; \ - pr_reg[8] = regs->a1; \ - pr_reg[9] = regs->a2; \ - pr_reg[14] = regs->d0; \ - pr_reg[15] = rdusp(); \ - pr_reg[16] = regs->orig_d0; \ - pr_reg[17] = regs->sr; \ - pr_reg[18] = regs->pc; \ - pr_reg[19] = (regs->format << 12) | regs->vector; \ - { \ - struct switch_stack *sw = ((struct switch_stack *)regs) - 1; \ - pr_reg[5] = sw->d6; \ - pr_reg[6] = sw->d7; \ - pr_reg[10] = sw->a3; \ - pr_reg[11] = sw->a4; \ - pr_reg[12] = sw->a5; \ - pr_reg[13] = sw->a6; \ - } - -/* This yields a mask that user programs can use to figure out what - instruction set this cpu supports. */ - -#define ELF_HWCAP (0) - -/* This yields a string that ld.so will use to load implementation - specific libraries for optimization. This is more specific in - intent than poking at uname or /proc/cpuinfo. */ - -#define ELF_PLATFORM (NULL) - -#ifdef __KERNEL__ -#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX) -#endif - -#endif diff --git a/arch/m68k/include/asm/hardware.h b/arch/m68k/include/asm/hardware.h deleted file mode 100644 index eeca64eb95..0000000000 --- a/arch/m68k/include/asm/hardware.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Common hardware definitions - */ - -#ifndef __M68K_HARDWARE_H -#define __M68K_HARDWARE_H - -#include <mach/hardware.h> - -#endif diff --git a/arch/m68k/include/asm/io.h b/arch/m68k/include/asm/io.h deleted file mode 100644 index b6b01cb184..0000000000 --- a/arch/m68k/include/asm/io.h +++ /dev/null @@ -1,304 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Generic virtual read/write. Note that we don't support half-word - * read/writes. We define __arch_*[bl] here, and leave __arch_*w - * to the architecture specific code. - */ -#ifndef __ASM_M68K_IO_H -#define __ASM_M68K_IO_H - -#ifdef __KERNEL__ - -#include <linux/types.h> -#include <asm/byteorder.h> -#include <asm/memory.h> - -/* - */ -#define __arch_getb(a) (*(volatile unsigned char *)(a)) -#define __arch_getw(a) (*(volatile unsigned short *)(a)) -#define __arch_getl(a) (*(volatile unsigned int *)(a)) - -#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) -#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) - -extern void __raw_writesb(unsigned int addr, const void *data, int bytelen); -extern void __raw_writesw(unsigned int addr, const void *data, int wordlen); -extern void __raw_writesl(unsigned int addr, const void *data, int longlen); - -extern void __raw_readsb(unsigned int addr, void *data, int bytelen); -extern void __raw_readsw(unsigned int addr, void *data, int wordlen); -extern void __raw_readsl(unsigned int addr, void *data, int longlen); - -#define __raw_writeb(v,a) __arch_putb(v,a) -#define __raw_writew(v,a) __arch_putw(v,a) -#define __raw_writel(v,a) __arch_putl(v,a) - -#define __raw_readb(a) __arch_getb(a) -#define __raw_readw(a) __arch_getw(a) -#define __raw_readl(a) __arch_getl(a) - -#define writeb(v,a) __arch_putb(v,a) -#define writew(v,a) __arch_putw(v,a) -#define writel(v,a) __arch_putl(v,a) - -#define readb(a) __arch_getb(a) -#define readw(a) __arch_getw(a) -#define readl(a) __arch_getl(a) - -/* - * The compiler seems to be incapable of optimising constants - * properly. Spell it out to the compiler in some cases. - * These are only valid for small values of "off" (< 1<<12) - */ -#define __raw_base_writeb(val,base,off) __arch_base_putb(val,base,off) -#define __raw_base_writew(val,base,off) __arch_base_putw(val,base,off) -#define __raw_base_writel(val,base,off) __arch_base_putl(val,base,off) - -#define __raw_base_readb(base,off) __arch_base_getb(base,off) -#define __raw_base_readw(base,off) __arch_base_getw(base,off) -#define __raw_base_readl(base,off) __arch_base_getl(base,off) - -/* - * Now, pick up the machine-defined IO definitions - */ - -/* - * IO port access primitives - * ------------------------- - * - * The M68k doesn't have special IO access instructions; all IO is memory - * mapped. Note that these are defined to perform little endian accesses - * only. Their primary purpose is to access PCI and ISA peripherals. - * - * Note that for a big endian machine, this implies that the following - * big endian mode connectivity is in place, as described by numerious - * ARM documents: - * - * PCI: D0-D7 D8-D15 D16-D23 D24-D31 - * ARM: D24-D31 D16-D23 D8-D15 D0-D7 - * - * The machine specific io.h include defines __io to translate an "IO" - * address to a memory address. - * - * Note that we prevent GCC re-ordering or caching values in expressions - * by introducing sequence points into the in*() definitions. Note that - * __raw_* do not guarantee this behaviour. - * - * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. - */ -#ifdef __io -#define outb(v,p) __raw_writeb(v,__io(p)) -#define outw(v,p) __raw_writew(cpu_to_le16(v),__io(p)) -#define outl(v,p) __raw_writel(cpu_to_le32(v),__io(p)) - -#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; }) -#define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; }) -#define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; }) - -#define outsb(p,d,l) __raw_writesb(__io(p),d,l) -#define outsw(p,d,l) __raw_writesw(__io(p),d,l) -#define outsl(p,d,l) __raw_writesl(__io(p),d,l) - -#define insb(p,d,l) __raw_readsb(__io(p),d,l) -#define insw(p,d,l) __raw_readsw(__io(p),d,l) -#define insl(p,d,l) __raw_readsl(__io(p),d,l) -#endif - -#define outb_p(val,port) outb((val),(port)) -#define outw_p(val,port) outw((val),(port)) -#define outl_p(val,port) outl((val),(port)) -#define inb_p(port) inb((port)) -#define inw_p(port) inw((port)) -#define inl_p(port) inl((port)) - -#define outsb_p(port,from,len) outsb(port,from,len) -#define outsw_p(port,from,len) outsw(port,from,len) -#define outsl_p(port,from,len) outsl(port,from,len) -#define insb_p(port,to,len) insb(port,to,len) -#define insw_p(port,to,len) insw(port,to,len) -#define insl_p(port,to,len) insl(port,to,len) - -/* - * ioremap and friends. - * - * ioremap takes a PCI memory address, as specified in - * linux/Documentation/IO-mapping.txt. If you want a - * physical address, use __ioremap instead. - */ -extern void * __ioremap(unsigned long offset, size_t size, unsigned long flags); -extern void __iounmap(void *addr); - -/* - * Generic ioremap support. - * - * Define: - * iomem_valid_addr(off,size) - * iomem_to_phys(off) - */ -#ifdef iomem_valid_addr -#define __arch_ioremap(off,sz,nocache) \ - ({ \ - unsigned long _off = (off), _size = (sz); \ - void *_ret = (void *)0; \ - if (iomem_valid_addr(_off, _size)) \ - _ret = __ioremap(iomem_to_phys(_off),_size,0); \ - _ret; \ - }) - -#define __arch_iounmap __iounmap -#endif - -#define ioremap(off,sz) __arch_ioremap((off),(sz),0) -#define ioremap_nocache(off,sz) __arch_ioremap((off),(sz),1) -#define iounmap(_addr) __arch_iounmap(_addr) - -/* - * DMA-consistent mapping functions. These allocate/free a region of - * uncached, unwrite-buffered mapped memory space for use with DMA - * devices. This is the "generic" version. The PCI specific version - * is in pci.h - */ -extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle); -extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle); -extern void consistent_sync(void *vaddr, size_t size, int rw); - -/* - * String version of IO memory access ops: - */ -extern void _memcpy_fromio(void *, unsigned long, size_t); -extern void _memcpy_toio(unsigned long, const void *, size_t); -extern void _memset_io(unsigned long, int, size_t); - -extern void __readwrite_bug(const char *fn); - -/* - * If this architecture has PCI memory IO, then define the read/write - * macros. These should only be used with the cookie passed from - * ioremap. - */ -#ifdef __mem_pci - -#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; }) -#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; }) -#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; }) - -#define writeb(v,c) __raw_writeb(v,__mem_pci(c)) -#define writew(v,c) __raw_writew(cpu_to_le16(v),__mem_pci(c)) -#define writel(v,c) __raw_writel(cpu_to_le32(v),__mem_pci(c)) - -#define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l)) -#define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l)) -#define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l)) - -#define eth_io_copy_and_sum(s,c,l,b) \ - eth_copy_and_sum((s),__mem_pci(c),(l),(b)) - -static inline int -check_signature(unsigned long io_addr, const unsigned char *signature, - int length) -{ - int retval = 0; - do { - if (readb(io_addr) != *signature) - goto out; - io_addr++; - signature++; - length--; - } while (length); - retval = 1; -out: - return retval; -} - -#elif !defined(readb) - -#define readb(addr) (__readwrite_bug("readb"),0) -#define readw(addr) (__readwrite_bug("readw"),0) -#define readl(addr) (__readwrite_bug("readl"),0) -#define writeb(v,addr) __readwrite_bug("writeb") -#define writew(v,addr) __readwrite_bug("writew") -#define writel(v,addr) __readwrite_bug("writel") - -#define eth_io_copy_and_sum(a,b,c,d) __readwrite_bug("eth_io_copy_and_sum") - -#define check_signature(io,sig,len) (0) - -#endif /* __mem_pci */ - -/* - * If this architecture has ISA IO, then define the isa_read/isa_write - * macros. - */ -#ifdef __mem_isa - -#define isa_readb(addr) __raw_readb(__mem_isa(addr)) -#define isa_readw(addr) __raw_readw(__mem_isa(addr)) -#define isa_readl(addr) __raw_readl(__mem_isa(addr)) -#define isa_writeb(val,addr) __raw_writeb(val,__mem_isa(addr)) -#define isa_writew(val,addr) __raw_writew(val,__mem_isa(addr)) -#define isa_writel(val,addr) __raw_writel(val,__mem_isa(addr)) -#define isa_memset_io(a,b,c) _memset_io(__mem_isa(a),(b),(c)) -#define isa_memcpy_fromio(a,b,c) _memcpy_fromio((a),__mem_isa(b),(c)) -#define isa_memcpy_toio(a,b,c) _memcpy_toio(__mem_isa((a)),(b),(c)) - -#define isa_eth_io_copy_and_sum(a,b,c,d) \ - eth_copy_and_sum((a),__mem_isa(b),(c),(d)) - -static inline int -isa_check_signature(unsigned long io_addr, const unsigned char *signature, - int length) -{ - int retval = 0; - do { - if (isa_readb(io_addr) != *signature) - goto out; - io_addr++; - signature++; - length--; - } while (length); - retval = 1; -out: - return retval; -} - -#else /* __mem_isa */ - -#define isa_readb(addr) (__readwrite_bug("isa_readb"),0) -#define isa_readw(addr) (__readwrite_bug("isa_readw"),0) -#define isa_readl(addr) (__readwrite_bug("isa_readl"),0) -#define isa_writeb(val,addr) __readwrite_bug("isa_writeb") -#define isa_writew(val,addr) __readwrite_bug("isa_writew") -#define isa_writel(val,addr) __readwrite_bug("isa_writel") -#define isa_memset_io(a,b,c) __readwrite_bug("isa_memset_io") -#define isa_memcpy_fromio(a,b,c) __readwrite_bug("isa_memcpy_fromio") -#define isa_memcpy_toio(a,b,c) __readwrite_bug("isa_memcpy_toio") - -#define isa_eth_io_copy_and_sum(a,b,c,d) \ - __readwrite_bug("isa_eth_io_copy_and_sum") - -#define isa_check_signature(io,sig,len) (0) - -#endif /* __mem_isa */ -#endif /* __KERNEL__ */ -#endif /* __ASM_M68K_IO_H */ diff --git a/arch/m68k/include/asm/mach-types.h b/arch/m68k/include/asm/mach-types.h deleted file mode 100644 index d221fcc892..0000000000 --- a/arch/m68k/include/asm/mach-types.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This was automagically generated from arch/m68k/tools/mach-types! - * Do NOT edit - */ - -#ifndef __ASM_M68K_MACH_TYPE_H -#define __ASM_M68K_MACH_TYPE_H - -#ifndef __ASSEMBLY__ -/* The type of machine we're running on */ -extern unsigned int __machine_arch_type; -#endif - -/* see arch/m68k/kernel/arch.c for a description of these */ -#define MACH_TYPE_GENERIC 0 -#define MACH_TYPE_MCF54xx 1 -#define MACH_TYPE_MCF5445x 2 - -#ifdef CONFIG_ARCH_MCF54xx -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MCF54xx -# endif -# define machine_is_mcf54xx() (machine_arch_type == MACH_TYPE_MCF54xx) -#else -# define machine_is_mcf54xx() (0) -#endif - -#ifdef CONFIG_ARCH_MCF5445x -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_MCF5445x -# endif -# define machine_is_mcf5445x() (machine_arch_type == MACH_TYPE_MCF5445x) -#else -# define machine_is_mcf5445x() (0) -#endif - - -#ifndef machine_arch_type -#define machine_arch_type __machine_arch_type -#endif - -#endif diff --git a/arch/m68k/include/asm/memory.h b/arch/m68k/include/asm/memory.h deleted file mode 100644 index 006ea3c68e..0000000000 --- a/arch/m68k/include/asm/memory.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Note: this file should not be included by non-asm/.h files - */ -#ifndef __ASM_M68K_MEMORY_H -#define __ASM_M68K_MEMORY_H - - -#endif /* __ASM_M68K_MEMORY_H */ diff --git a/arch/m68k/include/asm/module.h b/arch/m68k/include/asm/module.h deleted file mode 100644 index f04d794572..0000000000 --- a/arch/m68k/include/asm/module.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Defines for the ELF module loader - */ -#ifndef _ASM_M68K_MODULE_H -#define _ASM_M68K_MODULE_H - -struct mod_arch_specific -{ - int foo; -}; - -#define Elf_Shdr Elf32_Shdr -#define Elf_Sym Elf32_Sym -#define Elf_Ehdr Elf32_Ehdr - -#endif /* _ASM_M68K_MODULE_H */ diff --git a/arch/m68k/include/asm/posix_types.h b/arch/m68k/include/asm/posix_types.h deleted file mode 100644 index d83afe94a2..0000000000 --- a/arch/m68k/include/asm/posix_types.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * This file is generally used by user-level software, so you need to - * be a little careful about namespace pollution etc. Also, we cannot - * assume GCC is being used. - */ -#ifndef __ARCH_M68K_POSIX_TYPES_H -#define __ARCH_M68K_POSIX_TYPES_H - - -typedef unsigned long __kernel_ino_t; -typedef unsigned short __kernel_mode_t; -typedef unsigned short __kernel_nlink_t; -typedef long __kernel_off_t; -typedef int __kernel_pid_t; -typedef unsigned short __kernel_ipc_pid_t; -typedef unsigned short __kernel_uid_t; -typedef unsigned short __kernel_gid_t; -typedef unsigned int __kernel_size_t; -typedef int __kernel_ssize_t; -typedef int __kernel_ptrdiff_t; -typedef long __kernel_time_t; -typedef long __kernel_suseconds_t; -typedef long __kernel_clock_t; -typedef int __kernel_daddr_t; -typedef char * __kernel_caddr_t; -typedef unsigned short __kernel_uid16_t; -typedef unsigned short __kernel_gid16_t; -typedef unsigned int __kernel_uid32_t; -typedef unsigned int __kernel_gid32_t; - -typedef unsigned short __kernel_old_uid_t; -typedef unsigned short __kernel_old_gid_t; - -#ifdef __GNUC__ -typedef long long __kernel_loff_t; -#endif - -typedef struct { -#if defined(__KERNEL__) || defined(__USE_ALL) - int val[2]; -#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ - int __val[2]; -#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ -} __kernel_fsid_t; - -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) - -#undef __FD_SET -#define __FD_SET(fd, fdsetp) \ - (((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31))) - -#undef __FD_CLR -#define __FD_CLR(fd, fdsetp) \ - (((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31))) - -#undef __FD_ISSET -#define __FD_ISSET(fd, fdsetp) \ - ((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0) - -#undef __FD_ZERO -#define __FD_ZERO(fdsetp) \ - (memset (fdsetp, 0, sizeof (*(fd_set *)fdsetp))) - -#endif - -#endif diff --git a/arch/m68k/include/asm/processor.h b/arch/m68k/include/asm/processor.h deleted file mode 100644 index b0f82d084a..0000000000 --- a/arch/m68k/include/asm/processor.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * General processor specific definitions - */ -#ifndef __ASM_M68K_PROCESSOR_H -#define __ASM_M68K_PROCESSOR_H - -/* - * Default implementation of macro that returns current - * instruction pointer ("program counter"). - */ -#define current_text_addr() ({ __label__ _l; _l: &&_l;}) - -static inline unsigned long rdusp(void) -{ - unsigned long usp; - - __asm__ __volatile__("movel %/usp,%0" : "=a" (usp)); - return usp; -} - -static inline void wrusp(unsigned long usp) -{ - __asm__ __volatile__("movel %0,%/usp" : : "a" (usp)); -} - -#endif /* __ASM_M68K_PROCESSOR_H */ diff --git a/arch/m68k/include/asm/ptrace.h b/arch/m68k/include/asm/ptrace.h deleted file mode 100644 index 8f3d39aea1..0000000000 --- a/arch/m68k/include/asm/ptrace.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Remains of the pthread stuff... - * @todo Rework these headers.... - */ -#ifndef __ASM_M68K_PTRACE_H -#define __ASM_M68K_PTRACE_H - -#define PTRACE_GETREGS 12 -#define PTRACE_SETREGS 13 -#define PTRACE_GETFPREGS 14 -#define PTRACE_SETFPREGS 15 - -#define PTRACE_SETOPTIONS 21 - - -#include <proc/ptrace.h> - -#ifndef __ASSEMBLY__ - -#ifndef PS_S -#define PS_S (0x2000) -#define PS_M (0x1000) -#endif - -//#define user_mode(regs) (!((regs)->sr & PS_S)) -#define instruction_pointer(regs) ((regs)->M68K_pc) -#define profile_pc(regs) instruction_pointer(regs) - -#ifdef __KERNEL__ -extern void show_regs(struct pt_regs *); -#endif - -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/arch/m68k/include/asm/setup.h b/arch/m68k/include/asm/setup.h deleted file mode 100644 index ee0bde8b79..0000000000 --- a/arch/m68k/include/asm/setup.h +++ /dev/null @@ -1,412 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Arch dependant barebox defines about linux mach types - */ -#ifndef _M68K_SETUP_H -#define _M68K_SETUP_H - -#include <config.h> - - -/* - * Linux/m68k Architectures - */ - -#define MACH_AMIGA 1 -#define MACH_ATARI 2 -#define MACH_MAC 3 -#define MACH_APOLLO 4 -#define MACH_SUN3 5 -#define MACH_MVME147 6 -#define MACH_MVME16x 7 -#define MACH_BVME6000 8 -#define MACH_HP300 9 -#define MACH_Q40 10 -#define MACH_SUN3X 11 - /* ColdFire boards */ -#define MACH_FIRE_ENGINE 12 - -#ifdef __KERNEL__ - -#ifndef __ASSEMBLY__ -extern unsigned long m68k_machtype; -#endif /* !__ASSEMBLY__ */ - -#if !defined(CONFIG_AMIGA) -# define MACH_IS_AMIGA (0) -#elif defined(CONFIG_ATARI) || defined(CONFIG_MAC) || defined(CONFIG_APOLLO) \ - || defined(CONFIG_MVME16x) || defined(CONFIG_BVME6000) \ - || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ - || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) -# define MACH_IS_AMIGA (m68k_machtype == MACH_AMIGA) -#else -# define MACH_AMIGA_ONLY -# define MACH_IS_AMIGA (1) -# define MACH_TYPE (MACH_AMIGA) -#endif - -#if !defined(CONFIG_ATARI) -# define MACH_IS_ATARI (0) -#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_APOLLO) \ - || defined(CONFIG_MVME16x) || defined(CONFIG_BVME6000) \ - || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ - || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) -# define MACH_IS_ATARI (m68k_machtype == MACH_ATARI) -#else -# define MACH_ATARI_ONLY -# define MACH_IS_ATARI (1) -# define MACH_TYPE (MACH_ATARI) -#endif - -#if !defined(CONFIG_MAC) -# define MACH_IS_MAC (0) -#elif defined(CONFIG_AMIGA) || defined(CONFIG_ATARI) || defined(CONFIG_APOLLO) \ - || defined(CONFIG_MVME16x) || defined(CONFIG_BVME6000) \ - || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ - || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) -# define MACH_IS_MAC (m68k_machtype == MACH_MAC) -#else -# define MACH_MAC_ONLY -# define MACH_IS_MAC (1) -# define MACH_TYPE (MACH_MAC) -#endif - -#if defined(CONFIG_SUN3) -#define MACH_IS_SUN3 (1) -#define MACH_SUN3_ONLY (1) -#define MACH_TYPE (MACH_SUN3) -#else -#define MACH_IS_SUN3 (0) -#endif - -#if !defined (CONFIG_APOLLO) -# define MACH_IS_APOLLO (0) -#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ - || defined(CONFIG_MVME16x) || defined(CONFIG_BVME6000) \ - || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ - || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) -# define MACH_IS_APOLLO (m68k_machtype == MACH_APOLLO) -#else -# define MACH_APOLLO_ONLY -# define MACH_IS_APOLLO (1) -# define MACH_TYPE (MACH_APOLLO) -#endif - -#if !defined (CONFIG_MVME147) -# define MACH_IS_MVME147 (0) -#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ - || defined(CONFIG_APOLLO) || defined(CONFIG_BVME6000) \ - || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ - || defined(CONFIG_SUN3X) || defined(CONFIG_MVME16x) -# define MACH_IS_MVME147 (m68k_machtype == MACH_MVME147) -#else -# define MACH_MVME147_ONLY -# define MACH_IS_MVME147 (1) -# define MACH_TYPE (MACH_MVME147) -#endif - -#if !defined (CONFIG_MVME16x) -# define MACH_IS_MVME16x (0) -#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ - || defined(CONFIG_APOLLO) || defined(CONFIG_BVME6000) \ - || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ - || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) -# define MACH_IS_MVME16x (m68k_machtype == MACH_MVME16x) -#else -# define MACH_MVME16x_ONLY -# define MACH_IS_MVME16x (1) -# define MACH_TYPE (MACH_MVME16x) -#endif - -#if !defined (CONFIG_BVME6000) -# define MACH_IS_BVME6000 (0) -#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ - || defined(CONFIG_APOLLO) || defined(CONFIG_MVME16x) \ - || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ - || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) -# define MACH_IS_BVME6000 (m68k_machtype == MACH_BVME6000) -#else -# define MACH_BVME6000_ONLY -# define MACH_IS_BVME6000 (1) -# define MACH_TYPE (MACH_BVME6000) -#endif - -#if !defined (CONFIG_HP300) -# define MACH_IS_HP300 (0) -#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ - || defined(CONFIG_APOLLO) || defined(CONFIG_MVME16x) \ - || defined(CONFIG_BVME6000) || defined(CONFIG_Q40) \ - || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) -# define MACH_IS_HP300 (m68k_machtype == MACH_HP300) -#else -# define MACH_HP300_ONLY -# define MACH_IS_HP300 (1) -# define MACH_TYPE (MACH_HP300) -#endif - -#if !defined (CONFIG_Q40) -# define MACH_IS_Q40 (0) -#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ - || defined(CONFIG_APOLLO) || defined(CONFIG_MVME16x) \ - || defined(CONFIG_BVME6000) || defined(CONFIG_HP300) \ - || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) -# define MACH_IS_Q40 (m68k_machtype == MACH_Q40) -#else -# define MACH_Q40_ONLY -# define MACH_IS_Q40 (1) -# define MACH_TYPE (MACH_Q40) -#endif - -#if !defined (CONFIG_SUN3X) -# define MACH_IS_SUN3X (0) -#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ - || defined(CONFIG_APOLLO) || defined(CONFIG_MVME16x) \ - || defined(CONFIG_BVME6000) || defined(CONFIG_HP300) \ - || defined(CONFIG_Q40) || defined(CONFIG_MVME147) -# define MACH_IS_SUN3X (m68k_machtype == MACH_SUN3X) -#else -# define CONFIG_SUN3X_ONLY -# define MACH_IS_SUN3X (1) -# define MACH_TYPE (MACH_SUN3X) -#endif - -/* - * We only support one ColdFire board for the moment, so we don't do the - * kind of complicated configuration this file does for the other 68k CPUs. --NL - */ -#if !defined (CONFIG_COLDFIRE) -# define MACH_IS_COLDFIRE (0) -#else -# define CONFIG_COLDFIRE_ONLY -# define MACH_IS_COLDFIRE (1) -# define MACH_TYPE (MACH_COLDFIRE) -#endif - -#ifndef MACH_TYPE -# define MACH_TYPE (m68k_machtype) -#endif - -#endif /* __KERNEL__ */ - - - /* - * CPU, FPU and MMU types - * - * Note: we may rely on the following equalities: - * - * CPU_68020 == MMU_68851 - * CPU_68030 == MMU_68030 - * CPU_68040 == FPU_68040 == MMU_68040 - * CPU_68060 == FPU_68060 == MMU_68060 - */ - -#define CPUB_68020 0 -#define CPUB_68030 1 -#define CPUB_68040 2 -#define CPUB_68060 3 -#define CPUB_CFV4E 4 - -#define CPU_68020 (1<<CPUB_68020) -#define CPU_68030 (1<<CPUB_68030) -#define CPU_68040 (1<<CPUB_68040) -#define CPU_68060 (1<<CPUB_68060) -#define CPU_CFV4E (1<<CPUB_CFV4E) - -#define FPUB_68881 0 -#define FPUB_68882 1 -#define FPUB_68040 2 /* Internal FPU */ -#define FPUB_68060 3 /* Internal FPU */ -#define FPUB_SUNFPA 4 /* Sun-3 FPA */ -#define FPUB_CFV4E 5 - -#define FPU_68881 (1<<FPUB_68881) -#define FPU_68882 (1<<FPUB_68882) -#define FPU_68040 (1<<FPUB_68040) -#define FPU_68060 (1<<FPUB_68060) -#define FPU_SUNFPA (1<<FPUB_SUNFPA) -#define FPU_CFV4E (1<<FPUB_CFV4E) - -#define MMUB_68851 0 -#define MMUB_68030 1 /* Internal MMU */ -#define MMUB_68040 2 /* Internal MMU */ -#define MMUB_68060 3 /* Internal MMU */ -#define MMUB_APOLLO 4 /* Custom Apollo */ -#define MMUB_SUN3 5 /* Custom Sun-3 */ -#define MMUB_CFV4E 6 - -#define MMU_68851 (1<<MMUB_68851) -#define MMU_68030 (1<<MMUB_68030) -#define MMU_68040 (1<<MMUB_68040) -#define MMU_68060 (1<<MMUB_68060) -#define MMU_SUN3 (1<<MMUB_SUN3) -#define MMU_APOLLO (1<<MMUB_APOLLO) -#define MMU_CFV4E (1<<MMUB_CFV4E) - -#ifdef __KERNEL__ - -#ifndef __ASSEMBLY__ -extern unsigned long m68k_cputype; -extern unsigned long m68k_fputype; -extern unsigned long m68k_mmutype; /* Not really used yet */ -#ifdef CONFIG_VME -extern unsigned long vme_brdtype; -#endif - - /* - * m68k_is040or060 is != 0 for a '040 or higher; - * used numbers are 4 for 68040 and 6 for 68060. - */ - -extern int m68k_is040or060; -#endif /* !__ASSEMBLY__ */ - -#if !defined(CONFIG_M68020) -# define CPU_IS_020 (0) -# define MMU_IS_851 (0) -# define MMU_IS_SUN3 (0) -#elif defined(CONFIG_M68030) || defined(CONFIG_M68040) || defined(CONFIG_M68060) -# define CPU_IS_020 (m68k_cputype & CPU_68020) -# define MMU_IS_851 (m68k_mmutype & MMU_68851) -# define MMU_IS_SUN3 (0) /* Sun3 not supported with other CPU enabled */ -#else -# define CPU_M68020_ONLY -# define CPU_IS_020 (1) -#ifdef MACH_SUN3_ONLY -# define MMU_IS_SUN3 (1) -# define MMU_IS_851 (0) -#else -# define MMU_IS_SUN3 (0) -# define MMU_IS_851 (1) -#endif -#endif - -#if !defined(CONFIG_M68030) -# define CPU_IS_030 (0) -# define MMU_IS_030 (0) -#elif defined(CONFIG_M68020) || defined(CONFIG_M68040) || defined(CONFIG_M68060) -# define CPU_IS_030 (m68k_cputype & CPU_68030) -# define MMU_IS_030 (m68k_mmutype & MMU_68030) -#else -# define CPU_M68030_ONLY -# define CPU_IS_030 (1) -# define MMU_IS_030 (1) -#endif - -#if !defined(CONFIG_M68040) -# define CPU_IS_040 (0) -# define MMU_IS_040 (0) -#elif defined(CONFIG_M68020) || defined(CONFIG_M68030) || defined(CONFIG_M68060) -# define CPU_IS_040 (m68k_cputype & CPU_68040) -# define MMU_IS_040 (m68k_mmutype & MMU_68040) -#else -# define CPU_M68040_ONLY -# define CPU_IS_040 (1) -# define MMU_IS_040 (1) -#endif - -#if !defined(CONFIG_M68060) -# define CPU_IS_060 (0) -# define MMU_IS_060 (0) -#elif defined(CONFIG_M68020) || defined(CONFIG_M68030) || defined(CONFIG_M68040) -# define CPU_IS_060 (m68k_cputype & CPU_68060) -# define MMU_IS_060 (m68k_mmutype & MMU_68060) -#else -# define CPU_M68060_ONLY -# define CPU_IS_060 (1) -# define MMU_IS_060 (1) -#endif - -#if !defined(CONFIG_M68020) && !defined(CONFIG_M68030) -# define CPU_IS_020_OR_030 (0) -#else -# define CPU_M68020_OR_M68030 -# if defined(CONFIG_M68040) || defined(CONFIG_M68060) -# define CPU_IS_020_OR_030 (!m68k_is040or060) -# else -# define CPU_M68020_OR_M68030_ONLY -# define CPU_IS_020_OR_030 (1) -# endif -#endif - -#if !defined(CONFIG_M68040) && !defined(CONFIG_M68060) -# define CPU_IS_040_OR_060 (0) -#else -# define CPU_M68040_OR_M68060 -# if defined(CONFIG_M68020) || defined(CONFIG_M68030) -# define CPU_IS_040_OR_060 (m68k_is040or060) -# else -# define CPU_M68040_OR_M68060_ONLY -# define CPU_IS_040_OR_060 (1) -# endif -#endif - -#if !defined(CONFIG_CFV4E) -# define CPU_IS_COLDFIRE (0) -#else -# define CPU_IS_COLDFIRE (1) -# define CPU_IS_CFV4E (1) -# define MMU_IS_CFV4E (1) -#endif - -#define CPU_TYPE (m68k_cputype) - -#ifdef CONFIG_M68KFPU_EMU -# ifdef CONFIG_M68KFPU_EMU_ONLY -# define FPU_IS_EMU (1) -# else -# define FPU_IS_EMU (!m68k_fputype) -# endif -#else -# define FPU_IS_EMU (0) -#endif - - -/* - * Miscellaneous - */ - -#define NUM_MEMINFO 4 -#define CL_SIZE 256 -#define COMMAND_LINE_SIZE CL_SIZE - -#ifndef __ASSEMBLY__ -struct mem_info { - unsigned long addr; /* physical address of memory chunk */ - unsigned long size; /* length of memory chunk (in bytes) */ -}; -extern int m68k_num_memory; /* # of memory blocks found (and used) */ -extern int m68k_realnum_memory; /* real # of memory blocks found */ -extern struct mem_info m68k_memory[NUM_MEMINFO];/* memory description */ - -#endif - -#ifdef CONFIG_COLDFIRE -#define QCHIP_RESTORE_DIRECTIVE ".chip 547x" -#define CHIP_RESTORE_DIRECTIVE .chip 547x -#else -#define QCHIP_RESTORE_DIRECTIVE ".chip 68k" -#define CHIP_RESTORE_DIRECTIVE .chip 68k -#endif - -#endif /* __KERNEL__ */ - -#endif /* _M68K_SETUP_H */ diff --git a/arch/m68k/include/asm/string.h b/arch/m68k/include/asm/string.h deleted file mode 100644 index 19e3de45b6..0000000000 --- a/arch/m68k/include/asm/string.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Arch dependant configuration of std libc string and memory functions. - */ -#ifndef __ASM_M68K_STRING_H -#define __ASM_M68K_STRING_H - -/* - * We don't do inline string functions, since the - * optimised inline asm versions are not small. - */ - -#endif diff --git a/arch/m68k/include/asm/types.h b/arch/m68k/include/asm/types.h deleted file mode 100644 index 90e8bd7f75..0000000000 --- a/arch/m68k/include/asm/types.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Arch dependant types definitions - */ -#ifndef __ASM_M68K_TYPES_H -#define __ASM_M68K_TYPES_H - -#ifndef __ASSEMBLY__ - -typedef unsigned short umode_t; - -/* - * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the - * header files exported to user space - */ - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) -typedef __signed__ long long __s64; -typedef unsigned long long __u64; -#endif - -#endif /* __ASSEMBLY__ */ - -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -#ifdef __KERNEL__ - -#define BITS_PER_LONG 32 - -#ifndef __ASSEMBLY__ - -typedef signed char s8; -typedef unsigned char u8; - -typedef signed short s16; -typedef unsigned short u16; - -typedef signed int s32; -typedef unsigned int u32; - -typedef signed long long s64; -typedef unsigned long long u64; - -/* Dma addresses are 32-bits wide. */ - -typedef u32 dma_addr_t; -typedef u32 dma64_addr_t; - -#endif /* __ASSEMBLY__ */ - -#endif /* __KERNEL__ */ - -#endif diff --git a/arch/m68k/lib/Makefile b/arch/m68k/lib/Makefile deleted file mode 100644 index 09cfb29848..0000000000 --- a/arch/m68k/lib/Makefile +++ /dev/null @@ -1,31 +0,0 @@ -# -# (C) Copyright 2007 Carsten Schlote <schlote@vahanus.net> -# See file CREDITS for list of people who contributed to this project. -# -# This file is part of barebox. -# -# barebox is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# barebox is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with barebox. If not, see <http://www.gnu.org/licenses/>. -# - -# -# Architecture dependant stubs and callbacks -# - -obj-y += m68k-meminit.o - -obj-$(CONFIG_CMD_BOOTM) += m68k-linuxboot.o - -obj-$(CONFIG_MODULES) += m68k-module.o - -extra-$(CONFIG_GENERIC_LINKER_SCRIPT) += barebox.lds diff --git a/arch/m68k/lib/barebox.lds.S b/arch/m68k/lib/barebox.lds.S deleted file mode 100644 index fb6673deec..0000000000 --- a/arch/m68k/lib/barebox.lds.S +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Generic Linker file for M68k targets - */ -#include <asm-generic/barebox.lds.h> - -OUTPUT_FORMAT("elf32-m68k", "elf32-m68k", - "elf32-m68k") -OUTPUT_ARCH(m68k) -ENTRY(_start) -SECTIONS -{ - . = TEXT_BASE; - . = ALIGN(4); - - /* Start of vector, text and rodata section */ - _stext = .; - _text = .; - - /* M68k/CF style vector table */ - .vectors : - { - *(.vectors) - } - - .text : - { - *(.text .stub .text.*) - } =0x4e754e75 - - . = ALIGN(4); - .rodata : - { - *(.rodata .rodata.*) - } =0xdeadbeef - - . = ALIGN(4); - __barebox_cmd_start = .; - .barebox_cmd : { BAREBOX_CMDS } - __barebox_cmd_end = .; - - __barebox_initcalls_start = .; - .barebox_initcalls : { INITCALLS } - __barebox_initcalls_end = .; - - __usymtab_start = .; - __usymtab : { BAREBOX_SYMS } - __usymtab_end = .; - - /* End of text and rodata section */ - . = ALIGN(4); - _etext = .; - - . = ALIGN(4); - .got : { *(.got) } - . = ALIGN(4); - - . = ALIGN(4); - __early_init_data_begin = .; - .early_init_data : { *(.early_init_data) } - __early_init_data_end = .; - - .data : { *(.data .data.*) } - - . = ALIGN(4); - __bss_start = .; - .bss (NOLOAD) : { *(.bss .bass.*) } - __bss_end =.; - _end = .; - - . = ALIGN(4); - _barebox_heap_start = .; -} diff --git a/arch/m68k/lib/m68k-linuxboot.c b/arch/m68k/lib/m68k-linuxboot.c deleted file mode 100644 index 144d5a30b1..0000000000 --- a/arch/m68k/lib/m68k-linuxboot.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * @brief Linux boot preparation code. - * - * This file is responsible to start a linux kernel on - * Coldfire targets. - * - * @note Only Colilo mode supported yet. - */ -#include <common.h> -#include <command.h> -#include <driver.h> -#include <image.h> -#include <zlib.h> -#include <init.h> - -#include <asm/byteorder.h> -#include <asm/setup.h> -#include <environment.h> -#include <boot.h> -#include <asm/barebox-m68k.h> -#include <asm/bootinfo.h> - - -static int m68k_architecture = MACH_TYPE_GENERIC; - - -/* - * Setup M68k/Coldfire bootrecord info - */ -#if defined (CONFIG_SETUP_MEMORY_TAGS) || \ - defined (CONFIG_CMDLINE_TAG) || \ - defined (CONFIG_INITRD_TAG) - - -static void setup_boot_record(char* start_boot_rec, const char* command_line) -{ - struct bi_record* record; - - *start_boot_rec++ = 'C'; - *start_boot_rec++ = 'o'; - *start_boot_rec++ = 'L'; - *start_boot_rec++ = 'i'; - *start_boot_rec++ = 'L'; - *start_boot_rec++ = 'o'; - - record = (struct bi_record*) start_boot_rec; - - /* specify memory layout */ -#ifdef CONFIG_SETUP_MEMORY_TAGS - record->tag = BI_MEMCHUNK; - record->data[0] = 0; - record->data[1] = 64 * 1024 * 1024; // TODO: to be changed for different boards - record->size = sizeof (record->tag) + sizeof (record->size) - + sizeof (record->data[0]) + sizeof (record->data[0]); - record = (struct bi_record *) ((void *) record + record->size); -#endif - - /* add a kernel command line */ -#ifdef CONFIG_CMDLINE_TAG - record->tag = BI_COMMAND_LINE; - strcpy ((char *) &record->data, command_line); - record->size = sizeof (record->tag) + sizeof (record->size) - + max (sizeof (record->data[0]), strlen (command_line)+1); - record = (struct bi_record *) ((void *) record + record->size); -#endif - - /* Add reference to initrd */ -#ifdef CONFIG_INITRD_TAG -#endif - - /* Mark end of tags */ - record->tag = 0; - record->data[0] = 0; - record->data[1] = 0; - record->size = sizeof(record->tag) + sizeof (record->size) - + sizeof (record->data[0]) + sizeof (record->data[0]); -} - -#else -#define setup_boot_record(start_boot_rec,command_line) while (0) { } - -#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */ - - -static int do_bootm_linux(struct image_data *data) -{ - image_header_t *os_header = &data->os->header; - void (*theKernel)(int zero, int arch, uint params); - const char *commandline = getenv ("bootargs"); - uint32_t loadaddr,loadsize; - - if (image_get_type(os_header) == IH_TYPE_MULTI) { - printf("Multifile images not handled at the moment\n"); - return -1; - } - - printf("commandline: %s\n", commandline); - - theKernel = (void (*)(int,int,uint))image_get_ep(os_header); - - debug ("## Transferring control to Linux (at address %08lx) ...\n", - (ulong) theKernel); - - loadaddr = (uint32_t)image_get_load(os_header); - loadsize = (uint32_t)image_get_size(os_header); - setup_boot_record( (char*)(loadaddr+loadsize),(char*)commandline); - - if (relocate_image(data->os, (void *)loadaddr)) - return -1; - - /* we assume that the kernel is in place */ - printf ("\nStarting kernel image at 0x%08x size 0x%08x eentry 0x%08x\n\n", - loadaddr, loadsize, (ulong) theKernel); - - /* Bring board into inactive post-reset state again */ - cleanup_before_linux (); - - /* Jump to kernel entry point */ - theKernel (0, m68k_architecture, 0xdeadbeaf); - - enable_interrupts(); - printf("Error: Loaded kernel returned. Probably it couldn't\n" - "find it's bootrecord.\n"); - return -1; -} - -/* - * Register handler for m68k Kernel Images - */ -static int image_handle_cmdline_parse(struct image_data *data, int opt, char *optarg) -{ - switch (opt) - { - case 'a': - m68k_architecture = simple_strtoul(optarg, NULL, 0); - return 0; - default: - return 1; - } -} - -static struct image_handler handler = -{ - .cmdline_options = "a:", - .cmdline_parse = image_handle_cmdline_parse, - .help_string = " -a <arch> use architecture number <arch>", - - .bootm = do_bootm_linux, - .image_type = IH_OS_LINUX, -}; - -static int m68klinux_register_image_handler(void) -{ - return register_image_handler(&handler); -} - -late_initcall(m68klinux_register_image_handler); diff --git a/arch/m68k/lib/m68k-meminit.c b/arch/m68k/lib/m68k-meminit.c deleted file mode 100644 index 664ef509c5..0000000000 --- a/arch/m68k/lib/m68k-meminit.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Init for memory allocator on m68k/Coldfire - */ -#include <common.h> -#include <init.h> -#include <mem_malloc.h> -#include <asm/barebox-m68k.h> -#include <reloc.h> -#include <asm-generic/memory_layout.h> - -/** Initialize mem allocator on M68k/Coldfire - */ -int m68k_mem_malloc_init(void) -{ - /* Pass start and end address of managed memory */ - - mem_malloc_init((void *)MALLOC_BASE, - (void *)(MALLOC_BASE + MALLOC_SIZE)); - - return 0; -} - -core_initcall(m68k_mem_malloc_init); diff --git a/arch/m68k/lib/m68k-module.c b/arch/m68k/lib/m68k-module.c deleted file mode 100644 index 6a4a2bc1c2..0000000000 --- a/arch/m68k/lib/m68k-module.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Moduleloader Subsystem - * - * These relocation stubs are taken from Linux 2.6.10 They are used by the - * higher level ELF loader code to place ELF files to arbitrary addresses. - */ -#include <common.h> -#include <elf.h> -#include <module.h> -#include <errno.h> - -int apply_relocate(Elf32_Shdr *sechdrs, - const char *strtab, - unsigned int symindex, - unsigned int relsec, - struct module *me) -{ - unsigned int i; - Elf32_Rel *rel = (void *)sechdrs[relsec].sh_addr; - Elf32_Sym *sym; - uint32_t *location; - - DEBUGP("Applying relocate section %u to %u\n", relsec, - sechdrs[relsec].sh_info); - for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { - /* This is where to make the change */ - location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr - + rel[i].r_offset; - /* This is the symbol it is referring to. Note that all - undefined symbols have been resolved. */ - sym = (Elf32_Sym *)sechdrs[symindex].sh_addr - + ELF32_R_SYM(rel[i].r_info); - - switch (ELF32_R_TYPE(rel[i].r_info)) { - case R_68K_32: - /* We add the value into the location given */ - *location += sym->st_value; - break; - case R_68K_PC32: - /* Add the value, subtract its postition */ - *location += sym->st_value - (uint32_t)location; - break; - default: - printk(KERN_ERR "module %s: Unknown relocation: %u\n", - me->name, ELF32_R_TYPE(rel[i].r_info)); - return -ENOEXEC; - } - } - return 0; -} - -int apply_relocate_add(Elf32_Shdr *sechdrs, - const char *strtab, - unsigned int symindex, - unsigned int relsec, - struct module *me) -{ - unsigned int i; - Elf32_Rela *rel = (void *)sechdrs[relsec].sh_addr; - Elf32_Sym *sym; - uint32_t *location; - - DEBUGP("Applying relocate_add section %u to %u\n", relsec, - sechdrs[relsec].sh_info); - for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { - /* This is where to make the change */ - location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr - + rel[i].r_offset; - /* This is the symbol it is referring to. Note that all - undefined symbols have been resolved. */ - sym = (Elf32_Sym *)sechdrs[symindex].sh_addr - + ELF32_R_SYM(rel[i].r_info); - - switch (ELF32_R_TYPE(rel[i].r_info)) { - case R_68K_32: - /* We add the value into the location given */ - *location = rel[i].r_addend + sym->st_value; - break; - case R_68K_PC32: - /* Add the value, subtract its postition */ - *location = rel[i].r_addend + sym->st_value - (uint32_t)location; - break; - default: - printk(KERN_ERR "module %s: Unknown relocation: %u\n", - me->name, ELF32_R_TYPE(rel[i].r_info)); - return -ENOEXEC; - } - } - return 0; -} diff --git a/arch/m68k/mach-mcfv4e.dox b/arch/m68k/mach-mcfv4e.dox deleted file mode 100644 index c6dc8f6929..0000000000 --- a/arch/m68k/mach-mcfv4e.dox +++ /dev/null @@ -1,39 +0,0 @@ -/* This document is intended to provide the developer with information - * how to integrate a new CPU (MACH) into this part of the barebox tree - */ - -/** @page dev_m68k_mach M68k/Coldfire based CPU (MACH) into the tree - -FIXME - fill in further info about Coldfire and so on. Check code - for compliance with the specs given below - move code otherwise. - -@par What's happens when the reset signal is gone - -@note Code running immediately after reset runs at an address it is not linked - to: "runtime address != link address". You should only use branches and - do not refer to fixed data. This implies the use of assembler code only. - -The M68k CPU starts at lable \<reset\> in one of the corresponding start-*.S -files. After some basic hardware setup it can call a function -\<arch_init_lowlevel\> if not disabled. This call is intended to give all -developers a chance to use a standard reset vector file, but also do some -special things required only on their specific CPU. - -After handling some MMU, Stack or similiar issues, \<board_init_lowlevel\> can -be called (if not disabled). This is a board specific function for SDRAM setup -for example. As its board specific, your can do whatever you need to bring -your board up. As stack is already set to internal core RAM, this routine can -be C. - -@note: You are not allowed to call other code here, because we are not running - at link address. - -When \<board_init_lowlevel\> returns it will be assumed that there is now -working RAM that can be used for all further steps. - -Next step is relocation of barebox itself. It gets copied to the end of -available RAM and the last assembly instruction is a jump to \<start_barebox\>. - -At this point of time: "runtime address == link address". - -*/ diff --git a/arch/m68k/mach-mcfv4e/Kconfig b/arch/m68k/mach-mcfv4e/Kconfig deleted file mode 100644 index aaba27e5e8..0000000000 --- a/arch/m68k/mach-mcfv4e/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ - -menu "M68k/Coldfire V4E specific settings" - -config COPY_LOWMEM_VECTORS - bool "Copy vectors to SDRAM address 0" - default y - help - This copies the vector table to SDRAM address 0 (default address) - -config USE_LOWMEM_VECTORS - bool "Use vectors at SDRAM address 0" - default n - depends on COPY_LOWMEM_VECTORS - help - This copies the vector table to SDRAM address 0 (default address) and - also uses this vector location - -endmenu diff --git a/arch/m68k/mach-mcfv4e/Makefile b/arch/m68k/mach-mcfv4e/Makefile deleted file mode 100644 index f75834be54..0000000000 --- a/arch/m68k/mach-mcfv4e/Makefile +++ /dev/null @@ -1,19 +0,0 @@ -# -# Generic code for Coldfire V4E targets (MCF547x/MCF548x) -# -obj-y += mcf_clocksource.o -obj-y += mcf_reset_cpu.o - -# -# FEC support -# -obj-y += multichannel_dma.o -obj-y += dma_utils.o -obj-y += fec.o -obj-y += fecbd.o - -# -# FreeScale MultiDMA Library -# -obj-y += mcdapi/ -obj-y += net/ diff --git a/arch/m68k/mach-mcfv4e/dma_utils.c b/arch/m68k/mach-mcfv4e/dma_utils.c deleted file mode 100644 index adeefea3b1..0000000000 --- a/arch/m68k/mach-mcfv4e/dma_utils.c +++ /dev/null @@ -1,502 +0,0 @@ -/* - * File: dma_utils.c - * Purpose: General purpose utilities for the multi-channel DMA - * - * Notes: The methodology used in these utilities assumes that - * no single initiator will be tied to more than one - * task/channel - */ - -#include <common.h> -#include <init.h> -#include <linux/types.h> -#include <mach/mcf54xx-regs.h> -#include <proc/mcdapi/MCD_dma.h> - -#include <proc/dma_utils.h> - -/* - * This global keeps track of which initiators have been - * used of the available assignments. Initiators 0-15 are - * hardwired. Initiators 16-31 are multiplexed and controlled - * via the Initiatior Mux Control Registe (IMCR). The - * assigned requestor is stored with the associated initiator - * number. - */ -static int8_t used_reqs[32] = -{ - DMA_ALWAYS, DMA_DSPI_RX, DMA_DSPI_TX, DMA_DREQ0, - DMA_PSC0_RX, DMA_PSC0_TX, DMA_USBEP0, DMA_USBEP1, - DMA_USBEP2, DMA_USBEP3, DMA_PCI_TX, DMA_PCI_RX, - DMA_PSC1_RX, DMA_PSC1_TX, DMA_I2C_RX, DMA_I2C_TX, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0 -}; - -/* - * This global keeps track of which channels have been assigned - * to tasks. This methology assumes that no single initiator - * will be tied to more than one task/channel - */ -typedef struct -{ - int req; - void (*handler)(void); -} DMA_CHANNEL_STRUCT; - -static DMA_CHANNEL_STRUCT dma_channel[NCHANNELS] = -{ - {-1,NULL}, {-1,NULL}, {-1,NULL}, {-1,NULL}, - {-1,NULL}, {-1,NULL}, {-1,NULL}, {-1,NULL}, - {-1,NULL}, {-1,NULL}, {-1,NULL}, {-1,NULL}, - {-1,NULL}, {-1,NULL}, {-1,NULL}, {-1,NULL} -}; - -/* - * Enable all DMA interrupts - * - * Parameters: - * pri Interrupt Priority - * lvl Interrupt Level - */ -void -dma_irq_enable(uint8_t lvl, uint8_t pri) -{ -//FIXME ASSERT(lvl > 0 && lvl < 8); -//FIXME ASSERT(pri < 8); - - /* Setup the DMA ICR (#48) */ - MCF_INTC_ICR48 = 0 - | MCF_INTC_ICRn_IP(pri) - | MCF_INTC_ICRn_IL(lvl); - - /* Unmask all task interrupts */ - MCF_DMA_DIMR = 0; - - /* Clear the interrupt pending register */ - MCF_DMA_DIPR = 0; - - /* Unmask the DMA interrupt in the interrupt controller */ - MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK48; -} - -/* - * Disable all DMA interrupts - */ -void -dma_irq_disable(void) -{ - /* Mask all task interrupts */ - MCF_DMA_DIMR = (uint32_t)~0; - - /* Clear any pending task interrupts */ - MCF_DMA_DIPR = (uint32_t)~0; - - /* Mask the DMA interrupt in the interrupt controller */ - MCF_INTC_IMRH |= MCF_INTC_IMRH_INT_MASK48; -} - -/* - * Attempt to enable the provided Initiator in the Initiator - * Mux Control Register - * - * Parameters: - * initiator Initiator identifier - * - * Return Value: - * 1 if unable to make the assignment - * 0 successful - */ -int -dma_set_initiator(int initiator) -{ - switch (initiator) - { - /* These initiators are always active */ - case DMA_ALWAYS: - case DMA_DSPI_RX: - case DMA_DSPI_TX: - case DMA_DREQ0: - case DMA_PSC0_RX: - case DMA_PSC0_TX: - case DMA_USBEP0: - case DMA_USBEP1: - case DMA_USBEP2: - case DMA_USBEP3: - case DMA_PCI_TX: - case DMA_PCI_RX: - case DMA_PSC1_RX: - case DMA_PSC1_TX: - case DMA_I2C_RX: - case DMA_I2C_TX: - break; - case DMA_FEC0_RX: - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC16(3)) - | MCF_DMA_IMCR_SRC16_FEC0RX; - used_reqs[16] = DMA_FEC0_RX; - break; - case DMA_FEC0_TX: - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC17(3)) - | MCF_DMA_IMCR_SRC17_FEC0TX; - used_reqs[17] = DMA_FEC0_TX; - break; - case DMA_FEC1_RX: - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC20(3)) - | MCF_DMA_IMCR_SRC20_FEC1RX; - used_reqs[20] = DMA_FEC1_RX; - break; - case DMA_FEC1_TX: - if (used_reqs[21] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC21(3)) - | MCF_DMA_IMCR_SRC21_FEC1TX; - used_reqs[21] = DMA_FEC1_TX; - } - else if (used_reqs[25] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC25(3)) - | MCF_DMA_IMCR_SRC25_FEC1TX; - used_reqs[25] = DMA_FEC1_TX; - } - else if (used_reqs[31] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC31(3)) - | MCF_DMA_IMCR_SRC31_FEC1TX; - used_reqs[31] = DMA_FEC1_TX; - } - else /* No empty slots */ - return 1; - break; - case DMA_DREQ1: - if (used_reqs[29] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC29(3)) - | MCF_DMA_IMCR_SRC29_DREQ1; - used_reqs[29] = DMA_DREQ1; - } - else if (used_reqs[21] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC21(3)) - | MCF_DMA_IMCR_SRC21_DREQ1; - used_reqs[21] = DMA_DREQ1; - } - else /* No empty slots */ - return 1; - break; - case DMA_CTM0: - if (used_reqs[24] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC24(3)) - | MCF_DMA_IMCR_SRC24_CTM0; - used_reqs[24] = DMA_CTM0; - } - else /* No empty slots */ - return 1; - break; - case DMA_CTM1: - if (used_reqs[25] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC25(3)) - | MCF_DMA_IMCR_SRC25_CTM1; - used_reqs[25] = DMA_CTM1; - } - else /* No empty slots */ - return 1; - break; - case DMA_CTM2: - if (used_reqs[26] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC26(3)) - | MCF_DMA_IMCR_SRC26_CTM2; - used_reqs[26] = DMA_CTM2; - } - else /* No empty slots */ - return 1; - break; - case DMA_CTM3: - if (used_reqs[27] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC27(3)) - | MCF_DMA_IMCR_SRC27_CTM3; - used_reqs[27] = DMA_CTM3; - } - else /* No empty slots */ - return 1; - break; - case DMA_CTM4: - if (used_reqs[28] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC28(3)) - | MCF_DMA_IMCR_SRC28_CTM4; - used_reqs[28] = DMA_CTM4; - } - else /* No empty slots */ - return 1; - break; - case DMA_CTM5: - if (used_reqs[29] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC29(3)) - | MCF_DMA_IMCR_SRC29_CTM5; - used_reqs[29] = DMA_CTM5; - } - else /* No empty slots */ - return 1; - break; - case DMA_CTM6: - if (used_reqs[30] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC30(3)) - | MCF_DMA_IMCR_SRC30_CTM6; - used_reqs[30] = DMA_CTM6; - } - else /* No empty slots */ - return 1; - break; - case DMA_CTM7: - if (used_reqs[31] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC31(3)) - | MCF_DMA_IMCR_SRC31_CTM7; - used_reqs[31] = DMA_CTM7; - } - else /* No empty slots */ - return 1; - break; - case DMA_USBEP4: - if (used_reqs[26] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC26(3)) - | MCF_DMA_IMCR_SRC26_USBEP4; - used_reqs[26] = DMA_USBEP4; - } - else /* No empty slots */ - return 1; - break; - case DMA_USBEP5: - if (used_reqs[27] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC27(3)) - | MCF_DMA_IMCR_SRC27_USBEP5; - used_reqs[27] = DMA_USBEP5; - } - else /* No empty slots */ - return 1; - break; - case DMA_USBEP6: - if (used_reqs[28] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC28(3)) - | MCF_DMA_IMCR_SRC28_USBEP6; - used_reqs[28] = DMA_USBEP6; - } - else /* No empty slots */ - return 1; - break; - case DMA_PSC2_RX: - if (used_reqs[28] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC28(3)) - | MCF_DMA_IMCR_SRC28_PSC2RX; - used_reqs[28] = DMA_PSC2_RX; - } - else /* No empty slots */ - return 1; - break; - case DMA_PSC2_TX: - if (used_reqs[29] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC29(3)) - | MCF_DMA_IMCR_SRC29_PSC2TX; - used_reqs[29] = DMA_PSC2_TX; - } - else /* No empty slots */ - return 1; - break; - case DMA_PSC3_RX: - if (used_reqs[30] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC30(3)) - | MCF_DMA_IMCR_SRC30_PSC3RX; - used_reqs[30] = DMA_PSC3_RX; - } - else /* No empty slots */ - return 1; - break; - case DMA_PSC3_TX: - if (used_reqs[31] == 0) - { - MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC31(3)) - | MCF_DMA_IMCR_SRC31_PSC3TX; - used_reqs[31] = DMA_PSC3_TX; - } - else /* No empty slots */ - return 1; - break; - default: - return 1; - } - return 0; -} - -/* - * Return the initiator number for the given requestor - * - * Parameters: - * requestor Initiator/Requestor identifier - * - * Return Value: - * The initiator number (0-31) if initiator has been assigned - * 0 (always initiator) otherwise - */ -uint32_t -dma_get_initiator(int requestor) -{ - uint32_t i; - - for (i=0; i<sizeof(used_reqs); ++i) - { - if (used_reqs[i] == requestor) - return i; - } - return 0; -} - -/* - * Remove the given initiator from the active list - * - * Parameters: - * requestor Initiator/Requestor identifier - */ -void -dma_free_initiator(int requestor) -{ - uint32_t i; - - for (i=16; i<sizeof(used_reqs); ++i) - { - if (used_reqs[i] == requestor) - { - used_reqs[i] = 0; - break; - } - } -} - -/* - * Attempt to find an available channel and mark it as used - * - * Parameters: - * requestor Initiator/Requestor identifier - * - * Return Value: - * First available channel or -1 if they are all occupied - */ -int -dma_set_channel(int requestor, void (*handler)(void)) -{ - int i; - - /* Check to see if this requestor is already assigned to a channel */ - if ((i = dma_get_channel(requestor)) != -1) - return i; - - for (i=0; i<NCHANNELS; ++i) - { - if (dma_channel[i].req == -1) - { - dma_channel[i].req = requestor; - dma_channel[i].handler = handler; - return i; - } - } - - /* All channels taken */ - return -1; -} - -/* - * Return the channel being initiated by the given requestor - * - * Parameters: - * requestor Initiator/Requestor identifier - * - * Return Value: - * Channel that the requestor is controlling or -1 if hasn't been - * activated - */ -int -dma_get_channel(int requestor) -{ - uint32_t i; - - for (i=0; i<NCHANNELS; ++i) - { - if (dma_channel[i].req == requestor) - return i; - } - return -1; -} - -/* - * Remove the channel being initiated by the given requestor from - * the active list - * - * Parameters: - * requestor Initiator/Requestor identifier - */ -void -dma_free_channel(int requestor) -{ - uint32_t i; - - for (i=0; i<NCHANNELS; ++i) - { - if (dma_channel[i].req == requestor) - { - dma_channel[i].req = -1; - dma_channel[i].handler = NULL; - break; - } - } -} - -/* - * This is the catch-all interrupt handler for the mult-channel DMA - */ -int -dma_interrupt_handler (void *arg1, void *arg2) -{ - uint32_t i, interrupts; - (void)arg1; - (void)arg2; - - disable_interrupts(); // was: board_irq_disable(); - - /* - * Determine which interrupt(s) triggered by AND'ing the - * pending interrupts with those that aren't masked. - */ - interrupts = MCF_DMA_DIPR & ~MCF_DMA_DIMR; - - /* Make sure we are here for a reason */ -// ASSERT(interrupts != 0); - - /* Clear the interrupt in the pending register */ - MCF_DMA_DIPR = interrupts; - - for (i=0; i<16; ++i, interrupts>>=1) - { - if (interrupts & 0x1) - { - /* If there is a handler, call it */ - if (dma_channel[i].handler != NULL) - dma_channel[i].handler(); - } - } - - enable_interrupts(); // board_irq_enable(); - return 1; -} diff --git a/arch/m68k/mach-mcfv4e/fec.c b/arch/m68k/mach-mcfv4e/fec.c deleted file mode 100644 index 7619283f86..0000000000 --- a/arch/m68k/mach-mcfv4e/fec.c +++ /dev/null @@ -1,1440 +0,0 @@ -/* - * File: fec.c - * Purpose: Driver for the Fast Ethernet Controller (FEC) - * - * Notes: - */ -#include <common.h> -#include <linux/types.h> - -#include <mach/mcf54xx-regs.h> -#include <proc/mcdapi/MCD_dma.h> -#include <proc/net/net.h> -#include <proc/fecbd.h> -#include <proc/fec.h> -#include <proc/dma_utils.h> - - -#define TRUE 1 -#define FALSE 0 -#define ASSERT(x) if (!(x)) hang(); -#define nop() __asm__ __volatile__("nop\n") - - -FEC_EVENT_LOG fec_log[2]; - -/* - * Write a value to a PHY's MII register. - * - * Parameters: - * ch FEC channel - * phy_addr Address of the PHY. - * reg_addr Address of the register in the PHY. - * data Data to be written to the PHY register. - * - * Return Values: - * 1 on failure - * 0 on success. - * - * Please refer to your PHY manual for registers and their meanings. - * mii_write() polls for the FEC's MII interrupt event (which should - * be masked from the interrupt handler) and clears it. If after a - * suitable amount of time the event isn't triggered, a value of 0 - * is returned. - */ -int -fec_mii_write(uint8_t ch, uint8_t phy_addr, uint8_t reg_addr, uint16_t data) -{ - int timeout; - uint32_t eimr; - - ASSERT(ch == 0 || ch == 1); - - /* - * Clear the MII interrupt bit - */ - MCF_FEC_EIR(ch) = MCF_FEC_EIR_MII; - - /* - * Write to the MII Management Frame Register to kick-off - * the MII write - */ - MCF_FEC_MMFR(ch) = 0 - | MCF_FEC_MMFR_ST_01 - | MCF_FEC_MMFR_OP_WRITE - | MCF_FEC_MMFR_PA(phy_addr) - | MCF_FEC_MMFR_RA(reg_addr) - | MCF_FEC_MMFR_TA_10 - | MCF_FEC_MMFR_DATA(data); - - /* - * Mask the MII interrupt - */ - eimr = MCF_FEC_EIMR(ch); - MCF_FEC_EIMR(ch) &= ~MCF_FEC_EIMR_MII; - - /* - * Poll for the MII interrupt (interrupt should be masked) - */ - for (timeout = 0; timeout < FEC_MII_TIMEOUT; timeout++) - { - if (MCF_FEC_EIR(ch) & MCF_FEC_EIR_MII) - break; - } - if(timeout == FEC_MII_TIMEOUT) - return 1; - - /* - * Clear the MII interrupt bit - */ - MCF_FEC_EIR(ch) = MCF_FEC_EIR_MII; - - /* - * Restore the EIMR - */ - MCF_FEC_EIMR(ch) = eimr; - - return 0; -} - -/* - * Read a value from a PHY's MII register. - * - * Parameters: - * ch FEC channel - * phy_addr Address of the PHY. - * reg_addr Address of the register in the PHY. - * data Pointer to storage for the Data to be read - * from the PHY register (passed by reference) - * - * Return Values: - * 1 on failure - * 0 on success. - * - * Please refer to your PHY manual for registers and their meanings. - * mii_read() polls for the FEC's MII interrupt event (which should - * be masked from the interrupt handler) and clears it. If after a - * suitable amount of time the event isn't triggered, a value of 0 - * is returned. - */ -int -fec_mii_read(uint8_t ch, uint8_t phy_addr, uint8_t reg_addr, uint16_t *data) -{ - int timeout; - - ASSERT(ch == 0 || ch == 1); - - /* - * Clear the MII interrupt bit - */ - MCF_FEC_EIR(ch) = MCF_FEC_EIR_MII; - - /* - * Write to the MII Management Frame Register to kick-off - * the MII read - */ - MCF_FEC_MMFR(ch) = 0 - | MCF_FEC_MMFR_ST_01 - | MCF_FEC_MMFR_OP_READ - | MCF_FEC_MMFR_PA(phy_addr) - | MCF_FEC_MMFR_RA(reg_addr) - | MCF_FEC_MMFR_TA_10; - - /* - * Poll for the MII interrupt (interrupt should be masked) - */ - for (timeout = 0; timeout < FEC_MII_TIMEOUT; timeout++) - { - if (MCF_FEC_EIR(ch) & MCF_FEC_EIR_MII) - break; - } - - if(timeout == FEC_MII_TIMEOUT) - return 1; - - /* - * Clear the MII interrupt bit - */ - MCF_FEC_EIR(ch) = MCF_FEC_EIR_MII; - - *data = (uint16_t)(MCF_FEC_MMFR(ch) & 0x0000FFFF); - - return 0; -} - -/* - * Initialize the MII interface controller - * - * Parameters: - * ch FEC channel - * sys_clk System Clock Frequency (in MHz) - */ -void -fec_mii_init(uint8_t ch, uint32_t sys_clk) -{ - ASSERT(ch == 0 || ch == 1); - - /* - * Initialize the MII clock (EMDC) frequency - * - * Desired MII clock is 2.5MHz - * MII Speed Setting = System_Clock / (2.5MHz * 2) - * (plus 1 to make sure we round up) - */ - MCF_FEC_MSCR(ch) = MCF_FEC_MSCR_MII_SPEED((sys_clk/5)+1); -} - -/* Initialize the MIB counters - * - * Parameters: - * ch FEC channel - */ -void -fec_mib_init(uint8_t ch) -{ - ASSERT(ch == 0 || ch == 1); -//To do -} - -/* Display the MIB counters - * - * Parameters: - * ch FEC channel - */ -void -fec_mib_dump(uint8_t ch) -{ - ASSERT(ch == 0 || ch == 1); -//To do -} - -/* Initialize the FEC log - * - * Parameters: - * ch FEC channel - */ -void -fec_log_init(uint8_t ch) -{ - ASSERT(ch == 0 || ch == 1); - memset(&fec_log[ch],0,sizeof(FEC_EVENT_LOG)); -} - -/* Display the FEC log - * - * Parameters: - * ch FEC channel - */ -void -fec_log_dump(uint8_t ch) -{ - ASSERT(ch == 0 || ch == 1); - printf("\n FEC%d Log\n---------------\n",ch); - printf("Total: %4d\n",fec_log[ch].total); - printf("hberr: %4d\n",fec_log[ch].hberr); - printf("babr: %4d\n",fec_log[ch].babr); - printf("babt: %4d\n",fec_log[ch].babt); - printf("gra: %4d\n",fec_log[ch].gra); - printf("txf: %4d\n",fec_log[ch].txf); - printf("mii: %4d\n",fec_log[ch].mii); - printf("lc: %4d\n",fec_log[ch].lc); - printf("rl: %4d\n",fec_log[ch].rl); - printf("xfun: %4d\n",fec_log[ch].xfun); - printf("xferr: %4d\n",fec_log[ch].xferr); - printf("rferr: %4d\n",fec_log[ch].rferr); - printf("dtxf: %4d\n",fec_log[ch].dtxf); - printf("drxf: %4d\n",fec_log[ch].drxf); - printf("\nRFSW:\n"); - printf("inv: %4d\n",fec_log[ch].rfsw_inv); - printf("m: %4d\n",fec_log[ch].rfsw_m); - printf("bc: %4d\n",fec_log[ch].rfsw_bc); - printf("mc: %4d\n",fec_log[ch].rfsw_mc); - printf("lg: %4d\n",fec_log[ch].rfsw_lg); - printf("no: %4d\n",fec_log[ch].rfsw_no); - printf("cr: %4d\n",fec_log[ch].rfsw_cr); - printf("ov: %4d\n",fec_log[ch].rfsw_ov); - printf("tr: %4d\n",fec_log[ch].rfsw_tr); - printf("---------------\n\n"); -} - -/* - * Display some of the registers for debugging - * - * Parameters: - * ch FEC channel - */ -void -fec_debug_dump(uint8_t ch) -{ - printf("\n------------- FEC%d -------------\n",ch); - printf("EIR %08x \n",MCF_FEC_EIR(ch)); - printf("EIMR %08x \n",MCF_FEC_EIMR(ch)); - printf("ECR %08x \n",MCF_FEC_ECR(ch)); - printf("RCR %08x \n",MCF_FEC_RCR(ch)); - printf("R_HASH %08x \n",MCF_FEC_R_HASH(ch)); - printf("TCR %08x \n",MCF_FEC_TCR(ch)); - printf("FECTFWR %08x \n",MCF_FEC_FECTFWR(ch)); - printf("FECRFSR %08x \n",MCF_FEC_FECRFSR(ch)); - printf("FECRFCR %08x \n",MCF_FEC_FECRFCR(ch)); - printf("FECRLRFP %08x \n",MCF_FEC_FECRLRFP(ch)); - printf("FECRLWFP %08x \n",MCF_FEC_FECRLWFP(ch)); - printf("FECRFAR %08x \n",MCF_FEC_FECRFAR(ch)); - printf("FECRFRP %08x \n",MCF_FEC_FECRFRP(ch)); - printf("FECRFWP %08x \n",MCF_FEC_FECRFWP(ch)); - printf("FECTFSR %08x \n",MCF_FEC_FECTFSR(ch)); - printf("FECTFCR %08x \n",MCF_FEC_FECTFCR(ch)); - printf("FECTLRFP %08x \n",MCF_FEC_FECTLRFP(ch)); - printf("FECTLWFP %08x \n",MCF_FEC_FECTLWFP(ch)); - printf("FECTFAR %08x \n",MCF_FEC_FECTFAR(ch)); - printf("FECTFRP %08x \n",MCF_FEC_FECTFRP(ch)); - printf("FECTFWP %08x \n",MCF_FEC_FECTFWP(ch)); - printf("FRST %08x \n",MCF_FEC_FRST(ch)); - printf("--------------------------------\n\n"); -} - -/* - * Set the duplex on the selected FEC controller - * - * Parameters: - * ch FEC channel - * duplex FEC_MII_FULL_DUPLEX or FEC_MII_HALF_DUPLEX - */ -void -fec_duplex (uint8_t ch, uint8_t duplex) -{ - ASSERT(ch == 0 || ch == 1); - - switch (duplex) - { - case FEC_MII_HALF_DUPLEX: - MCF_FEC_RCR(ch) |= MCF_FEC_RCR_DRT; - MCF_FEC_TCR(ch) &= (uint32_t)~MCF_FEC_TCR_FDEN; - break; - case FEC_MII_FULL_DUPLEX: - default: - MCF_FEC_RCR(ch) &= (uint32_t)~MCF_FEC_RCR_DRT; - MCF_FEC_TCR(ch) |= MCF_FEC_TCR_FDEN; - break; - } -} - -/* - * Generate the hash table settings for the given address - * - * Parameters: - * addr 48-bit (6 byte) Address to generate the hash for - * - * Return Value: - * The 6 most significant bits of the 32-bit CRC result - */ -uint8_t -fec_hash_address(const uint8_t *addr) -{ - uint32_t crc; - uint8_t byte; - int i, j; - - crc = 0xFFFFFFFF; - for(i=0; i<6; ++i) - { - byte = addr[i]; - for(j=0; j<8; ++j) - { - if((byte & 0x01)^(crc & 0x01)) - { - crc >>= 1; - crc = crc ^ 0xEDB88320; - } - else - crc >>= 1; - byte >>= 1; - } - } - return (uint8_t)(crc >> 26); -} - -/* - * Set the Physical (Hardware) Address and the Individual Address - * Hash in the selected FEC - * - * Parameters: - * ch FEC channel - * pa Physical (Hardware) Address for the selected FEC - */ -void -fec_set_address (uint8_t ch, const uint8_t *pa) -{ - uint8_t crc; - - ASSERT(ch == 0 || ch == 1); - - /* - * Set the Physical Address - */ - MCF_FEC_PALR(ch) = (uint32_t)((pa[0]<<24) | (pa[1]<<16) | (pa[2]<<8) | pa[3]); - MCF_FEC_PAUR(ch) = (uint32_t)((pa[4]<<24) | (pa[5]<<16)); - - /* - * Calculate and set the hash for given Physical Address - * in the Individual Address Hash registers - */ - crc = fec_hash_address(pa); - if(crc >= 32) - MCF_FEC_IAUR(ch) |= (uint32_t)(1 << (crc - 32)); - else - MCF_FEC_IALR(ch) |= (uint32_t)(1 << crc); -} - -/* - * Reset the selected FEC controller - * - * Parameters: - * ch FEC channel - */ -void -fec_reset (uint8_t ch) -{ - int i; - - ASSERT(ch == 0 || ch == 1); - - /* Clear any events in the FIFO status registers */ - MCF_FEC_FECRFSR(ch) = (0 - | MCF_FEC_FECRFSR_OF - | MCF_FEC_FECRFSR_UF - | MCF_FEC_FECRFSR_RXW - | MCF_FEC_FECRFSR_FAE - | MCF_FEC_FECRFSR_IP); - MCF_FEC_FECTFSR(ch) = (0 - | MCF_FEC_FECRFSR_OF - | MCF_FEC_FECRFSR_UF - | MCF_FEC_FECRFSR_RXW - | MCF_FEC_FECRFSR_FAE - | MCF_FEC_FECRFSR_IP); - - /* Reset the FIFOs */ - MCF_FEC_FRST(ch) |= MCF_FEC_FRST_SW_RST; - MCF_FEC_FRST(ch) &= ~MCF_FEC_FRST_SW_RST; - - /* Set the Reset bit and clear the Enable bit */ - MCF_FEC_ECR(ch) = MCF_FEC_ECR_RESET; - - /* Wait at least 8 clock cycles */ - for (i=0; i<10; ++i) - nop(); -} - -/* - * Initialize the selected FEC - * - * Parameters: - * ch FEC channel - * mode External interface mode (MII, 7-wire, or internal loopback) - * pa Physical (Hardware) Address for the selected FEC - */ -void -fec_init (uint8_t ch, uint8_t mode, const uint8_t *pa) -{ - ASSERT(ch == 0 || ch == 1); - - /* - * Enable all the external interface signals - */ - if (mode == FEC_MODE_7WIRE) - { - if (ch == 1) - MCF_GPIO_PAR_FECI2CIRQ |= MCF_GPIO_PAR_FECI2CIRQ_PAR_E17; - else - MCF_GPIO_PAR_FECI2CIRQ |= MCF_GPIO_PAR_FECI2CIRQ_PAR_E07; - } - else if (mode == FEC_MODE_MII) - { - if (ch == 1) - MCF_GPIO_PAR_FECI2CIRQ |= 0 - | MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC - | MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO - | MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MII - | MCF_GPIO_PAR_FECI2CIRQ_PAR_E17; - else - MCF_GPIO_PAR_FECI2CIRQ |= 0 - | MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDC - | MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO - | MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MII - | MCF_GPIO_PAR_FECI2CIRQ_PAR_E07; - } - - /* - * Clear the Individual and Group Address Hash registers - */ - MCF_FEC_IALR(ch) = 0; - MCF_FEC_IAUR(ch) = 0; - MCF_FEC_GALR(ch) = 0; - MCF_FEC_GAUR(ch) = 0; - - /* - * Set the Physical Address for the selected FEC - */ - fec_set_address(ch, pa); - - /* - * Mask all FEC interrupts - */ - MCF_FEC_EIMR(ch) = MCF_FEC_EIMR_MASK_ALL; - - /* - * Clear all FEC interrupt events - */ - MCF_FEC_EIR(ch) = MCF_FEC_EIR_CLEAR_ALL; - - /* - * Initialize the Receive Control Register - */ - MCF_FEC_RCR(ch) = 0 - | MCF_FEC_RCR_MAX_FL(ETH_MAX_FRM) - #ifdef FEC_PROMISCUOUS - | MCF_FEC_RCR_PROM - #endif - | MCF_FEC_RCR_FCE; - - if (mode == FEC_MODE_MII) - MCF_FEC_RCR(ch) |= MCF_FEC_RCR_MII_MODE; - - else if (mode == FEC_MODE_LOOPBACK) - MCF_FEC_RCR(ch) |= MCF_FEC_RCR_LOOP; - - /* - * Initialize the Transmit Control Register - */ - MCF_FEC_TCR(ch) = MCF_FEC_TCR_FDEN; - - /* - * Set Rx FIFO alarm and granularity - */ - MCF_FEC_FECRFCR(ch) = 0 - | MCF_FEC_FECRFCR_FRM - | MCF_FEC_FECRFCR_RXW_MSK - | MCF_FEC_FECRFCR_GR(7); - MCF_FEC_FECRFAR(ch) = MCF_FEC_FECRFAR_ALARM(768); - - /* - * Set Tx FIFO watermark, alarm and granularity - */ - MCF_FEC_FECTFCR(ch) = 0 - | MCF_FEC_FECTFCR_FRM - | MCF_FEC_FECTFCR_TXW_MSK - | MCF_FEC_FECTFCR_GR(7); - MCF_FEC_FECTFAR(ch) = MCF_FEC_FECTFAR_ALARM(256); - MCF_FEC_FECTFWR(ch) = MCF_FEC_FECTFWR_X_WMRK_256; - - /* - * Enable the transmitter to append the CRC - */ - MCF_FEC_CTCWR(ch) = 0 - | MCF_FEC_CTCWR_TFCW - | MCF_FEC_CTCWR_CRC; -} - -/* - * Start the FEC Rx DMA task - * - * Parameters: - * ch FEC channel - * rxbd First Rx buffer descriptor in the chain - */ -void -fec_rx_start(uint8_t ch, int8_t *rxbd) -{ - uint32_t initiator; - int channel, result; - - ASSERT(ch == 0 || ch == 1); - - /* - * Make the initiator assignment - */ - result = dma_set_initiator(DMA_FEC_RX(ch)); - ASSERT(result == 0); - - /* - * Grab the initiator number - */ - initiator = dma_get_initiator(DMA_FEC_RX(ch)); - - /* - * Determine the DMA channel running the task for the - * selected FEC - */ - channel = dma_set_channel(DMA_FEC_RX(ch), - (ch == 0) ? fec0_rx_frame : fec1_rx_frame); - ASSERT(channel != -1); - - /* - * Start the Rx DMA task - */ - /* - * Start the Rx DMA task - */ - MCD_startDma(channel, - (s8*)rxbd, - 0, - (s8*)MCF_FEC_FECRFDR_ADDR(ch), - 0, - RX_BUF_SZ, - 0, - initiator, - FECRX_DMA_PRI(ch), - 0 - | MCD_FECRX_DMA - | MCD_INTERRUPT - | MCD_TT_FLAGS_CW - | MCD_TT_FLAGS_RL - | MCD_TT_FLAGS_SP - , - 0 - | MCD_NO_CSUM - | MCD_NO_BYTE_SWAP - ); -} - -/* - * Continue the Rx DMA task - * - * This routine is called after the DMA task has halted after - * encountering an Rx buffer descriptor that wasn't marked as - * ready. There is no harm in calling the DMA continue routine - * if the DMA is not halted. - * - * Parameters: - * ch FEC channel - */ -void -fec_rx_continue(uint8_t ch) -{ - int channel; - - ASSERT(ch == 0 || ch == 1); - - /* - * Determine the DMA channel running the task for the - * selected FEC - */ - channel = dma_get_channel(DMA_FEC_RX(ch)); - ASSERT(channel != -1); - - /* - * Continue/restart the DMA task - */ - MCD_continDma(channel); -} - -/* - * Stop all frame receptions on the selected FEC - * - * Parameters: - * ch FEC channel - */ -void -fec_rx_stop (uint8_t ch) -{ - uint32_t mask; - int channel; - - ASSERT(ch == 0 || ch == 1); - - /* Save off the EIMR value */ - mask = MCF_FEC_EIMR(ch); - - /* Mask all interrupts */ - MCF_FEC_EIMR(ch) = 0; - - /* - * Determine the DMA channel running the task for the - * selected FEC - */ - channel = dma_get_channel(DMA_FEC_RX(ch)); - ASSERT(channel != -1); - - /* Kill the FEC Rx DMA task */ - MCD_killDma(channel); - - /* - * Free up the FEC requestor from the software maintained - * initiator list - */ - dma_free_initiator(DMA_FEC_RX(ch)); - - /* Free up the DMA channel */ - dma_free_channel(DMA_FEC_RX(ch)); - - /* Restore the interrupt mask register value */ - MCF_FEC_EIMR(ch) = mask; -} - -/* - * Receive Frame interrupt handler - this handler is called by the - * DMA interrupt handler indicating that a packet was successfully - * transferred out of the Rx FIFO. - * - * Parameters: - * nif Pointer to Network Interface structure - * ch FEC channel - */ -NBUF * -fec_rx_frame(uint8_t ch, NIF *nif) -{ -// ETH_HDR *eth_hdr; - FECBD *pRxBD; - NBUF *cur_nbuf, *new_nbuf; - int keep; - - while ((pRxBD = fecbd_rx_alloc(ch)) != NULL) - { - fec_log[ch].drxf++; - keep = TRUE; - - /* - * Check the Receive Frame Status Word for errors - * - The L bit should always be set - * - No undefined bits should be set - * - The upper 5 bits of the length should be cleared - */ - if (!(pRxBD->status & RX_BD_L) || (pRxBD->status & 0x0608) - || (pRxBD->length & 0xF800)) - { - keep = FALSE; - fec_log[ch].rfsw_inv++; - } - else if (pRxBD->status & RX_BD_ERROR) - { - keep = FALSE; - if (pRxBD->status & RX_BD_NO) - fec_log[ch].rfsw_no++; - if (pRxBD->status & RX_BD_CR) - fec_log[ch].rfsw_cr++; - if (pRxBD->status & RX_BD_OV) - fec_log[ch].rfsw_ov++; - if (pRxBD->status & RX_BD_TR) - fec_log[ch].rfsw_tr++; - } - else - { - if (pRxBD->status & RX_BD_LG) - fec_log[ch].rfsw_lg++; - if (pRxBD->status & RX_BD_M) - fec_log[ch].rfsw_m++; - if (pRxBD->status & RX_BD_BC) - fec_log[ch].rfsw_bc++; - if (pRxBD->status & RX_BD_MC) - fec_log[ch].rfsw_mc++; - } - - if (keep) - { - /* - * Pull the network buffer off the Rx ring queue - */ - cur_nbuf = nbuf_remove(NBUF_RX_RING); - ASSERT(cur_nbuf); - ASSERT(cur_nbuf->data == pRxBD->data); - - /* - * Copy the buffer descriptor information to the network buffer - */ -// cur_nbuf->length = (pRxBD->length - (ETH_HDR_LEN + ETH_CRC_LEN)); -// cur_nbuf->offset = ETH_HDR_LEN; - cur_nbuf->length = (pRxBD->length - (ETH_CRC_LEN)); - cur_nbuf->offset = 0; - - /* - * Get a new buffer pointer for this buffer descriptor - */ - new_nbuf = nbuf_alloc(); - if (new_nbuf == NULL) - { - #ifdef CONFIG_DRIVER_NET_MCF54XX_DEBUG - printf("nbuf_alloc() failed\n"); - #endif - /* - * Can't allocate a new network buffer, so we - * have to trash the received data and reuse the buffer - * hoping that some buffers will free up in the system - * and this frame will be re-transmitted by the host - */ - pRxBD->length = RX_BUF_SZ; - pRxBD->status &= (RX_BD_W | RX_BD_INTERRUPT); - pRxBD->status |= RX_BD_E; - nbuf_add(NBUF_RX_RING, cur_nbuf); - fec_rx_continue(ch); - continue; - } - - /* - * Add the new network buffer to the Rx ring queue - */ - nbuf_add(NBUF_RX_RING, new_nbuf); - - /* - * Re-initialize the buffer descriptor - pointing it - * to the new data buffer. The previous data buffer - * will be passed up the stack - */ - pRxBD->data = new_nbuf->data; - pRxBD->length = RX_BUF_SZ; - pRxBD->status &= (RX_BD_W | RX_BD_INTERRUPT); - pRxBD->status |= RX_BD_E; - - - /* - * Let the DMA know that there is a new Rx BD (in case the - * ring was full and the DMA was waiting for an empty one) - */ - fec_rx_continue(ch); - - /* - * Get pointer to the frame data inside the network buffer - */ -// eth_hdr = (ETH_HDR *)cur_nbuf->data; - - /* - * Pass the received packet up the network stack if the - * protocol is supported in our network interface (NIF) - */ -//FIXME if (nif_protocol_exist(nif,eth_hdr->type)) -// { -// nif_protocol_handler(nif, eth_hdr->type, cur_nbuf); -// } -// else -// nbuf_free(cur_nbuf); - return(cur_nbuf); - } - else - { - /* - * This frame isn't a keeper - * Reset the status and length, but don't need to get another - * buffer since we are trashing the data in the current one - */ - pRxBD->length = RX_BUF_SZ; - pRxBD->status &= (RX_BD_W | RX_BD_INTERRUPT); - pRxBD->status |= RX_BD_E; - - /* - * Move the current buffer from the beginning to the end of the - * Rx ring queue - */ - cur_nbuf = nbuf_remove(NBUF_RX_RING); - nbuf_add(NBUF_RX_RING, cur_nbuf); - - /* - * Let the DMA know that there are new Rx BDs (in case - * it is waiting for an empty one) - */ - fec_rx_continue(ch); - } - } - return NULL; -} - -void -fec0_rx_frame(void) -{ -// extern NIF nif1; -// fec_rx_frame(0, 0); -} - -void -fec1_rx_frame(void) -{ -// extern NIF nif1; -// fec_rx_frame(1, 0); -} - -/* - * Start the FEC Tx DMA task - * - * Parameters: - * ch FEC channel - * txbd First Tx buffer descriptor in the chain - */ -void -fec_tx_start(uint8_t ch, int8_t *txbd) -{ - uint32_t initiator; - int channel, result; - void fec0_tx_frame(void); - void fec1_tx_frame(void); - - /* - * Make the initiator assignment - */ - result = dma_set_initiator(DMA_FEC_TX(ch)); - ASSERT(result == 0); - - /* - * Grab the initiator number - */ - initiator = dma_get_initiator(DMA_FEC_TX(ch)); - ASSERT(initiator != 0); - - /* - * Determine the DMA channel running the task for the - * selected FEC - */ - channel = dma_set_channel(DMA_FEC_TX(ch), - (ch == 0) ? fec0_tx_frame : fec1_tx_frame); - ASSERT(channel != -1); - - /* - * Start the Tx DMA task - */ - MCD_startDma(channel, - (s8*)txbd, - 0, - (s8*)MCF_FEC_FECTFDR_ADDR(ch), - 0, - ETH_MTU, - 0, - initiator, - FECTX_DMA_PRI(ch), - 0 - | MCD_FECTX_DMA - | MCD_INTERRUPT - | MCD_TT_FLAGS_CW - | MCD_TT_FLAGS_RL - | MCD_TT_FLAGS_SP - , - 0 - | MCD_NO_CSUM - | MCD_NO_BYTE_SWAP - ); -} - -/* - * Continue the Tx DMA task - * - * This routine is called after the DMA task has halted after - * encountering an Tx buffer descriptor that wasn't marked as - * ready. There is no harm in calling the continue DMA routine - * if the DMA was not paused. - * - * Parameters: - * ch FEC channel - */ -void -fec_tx_continue(uint8_t ch) -{ - int channel; - - /* - * Determine the DMA channel running the task for the - * selected FEC - */ - channel = dma_get_channel(DMA_FEC_TX(ch)); - ASSERT(channel > 0); - - /* - * Continue/restart the DMA task - */ - MCD_continDma((int)channel); -} - -/* - * Stop all transmissions on the selected FEC and kill the DMA task - * - * Parameters: - * ch FEC channel - */ -void -fec_tx_stop (uint8_t ch) -{ - uint32_t mask; - int channel; - - ASSERT(ch == 0 || ch == 1); - - /* Save off the EIMR value */ - mask = MCF_FEC_EIMR(ch); - - /* Mask all interrupts */ - MCF_FEC_EIMR(ch) = 0; - - /* If the Ethernet is still enabled... */ - if (MCF_FEC_ECR(ch) & MCF_FEC_ECR_ETHER_EN) - { - /* Issue the Graceful Transmit Stop */ - MCF_FEC_TCR(ch) |= MCF_FEC_TCR_GTS; - - /* Wait for the Graceful Stop Complete interrupt */ - while(!(MCF_FEC_EIR(ch) & MCF_FEC_EIR_GRA)) - { - if (!(MCF_FEC_ECR(ch) & MCF_FEC_ECR_ETHER_EN)) - break; - } - - /* Clear the Graceful Stop Complete interrupt */ - MCF_FEC_EIR(ch) = MCF_FEC_EIR_GRA; - } - - /* - * Determine the DMA channel running the task for the - * selected FEC - */ - channel = dma_get_channel(DMA_FEC_TX(ch)); - ASSERT(channel > 0); - - /* Kill the FEC Tx DMA task */ - MCD_killDma(channel); - - /* - * Free up the FEC requestor from the software maintained - * initiator list - */ - dma_free_initiator(DMA_FEC_TX(ch)); - - /* Free up the DMA channel */ - dma_free_channel(DMA_FEC_TX(ch)); - - /* Restore the interrupt mask register value */ - MCF_FEC_EIMR(ch) = mask; -} - -/* - * Trasmit Frame interrupt handler - this handler is called by the - * DMA interrupt handler indicating that a packet was successfully - * transferred to the Tx FIFO. - * - * Parameters: - * ch FEC channel - */ -void -fec_tx_frame(uint8_t ch) -{ - FECBD *pTxBD; - NBUF *pNbuf; - - while ((pTxBD = fecbd_tx_free(ch)) != NULL) - { - fec_log[ch].dtxf++; - - /* - * Grab the network buffer associated with this buffer descriptor - */ - pNbuf = nbuf_remove(NBUF_TX_RING); - ASSERT(pNbuf); - ASSERT(pNbuf->data == pTxBD->data); - - /* - * Free up the network buffer that was just transmitted - */ - nbuf_free(pNbuf); - - /* - * Re-initialize the Tx BD - */ - pTxBD->data = NULL; - pTxBD->length = 0; - } -} - -void -fec0_tx_frame(void) -{ - fec_tx_frame(0); -} - -void -fec1_tx_frame(void) -{ - fec_tx_frame(1); -} - -/* - * Send a packet out the selected FEC - * - * Parameters: - * ch FEC channel - * nif Pointer to Network Interface (NIF) structure - * dst Destination MAC Address - * src Source MAC Address - * type Ethernet Frame Type - * length Number of bytes to be transmitted (doesn't include type, - * src, or dest byte count) - * pkt Pointer packet network buffer - * - * Return Value: - * 1 success - * 0 otherwise - */ -int -fec_send (uint8_t ch, NIF *nif, uint8_t *dst, uint8_t *src, uint16_t type, NBUF *nbuf) -{ - FECBD *pTxBD; - ASSERT(ch == 0 || ch == 1); - - /* Check the length */ - if ((nbuf->length + ETH_HDR_LEN) > ETH_MTU) - return 0; - - /* - * Copy the destination address, source address, and Ethernet - * type into the packet - */ -// memcpy(&nbuf->data[0], dst, 6); -// memcpy(&nbuf->data[6], src, 6); -// memcpy(&nbuf->data[12], &type, 2); - - /* - * Grab the next available Tx Buffer Descriptor - */ - while ((pTxBD = fecbd_tx_alloc(ch)) == NULL) {}; - - /* - * Put the network buffer into the Tx waiting queue - */ - nbuf_add(NBUF_TX_RING, nbuf); - - /* - * Setup the buffer descriptor for transmission - */ - pTxBD->data = nbuf->data; - pTxBD->length = nbuf->length; // + ETH_HDR_LEN; - pTxBD->status |= (TX_BD_R | TX_BD_L); - - /* - * Continue the Tx DMA task (in case it was waiting for a new - * TxBD to be ready - */ - fec_tx_continue(ch); - - return 1; -} - -int -fec0_send(NIF *nif, uint8_t *dst, uint8_t *src, uint16_t type, NBUF *nbuf) -{ - return fec_send(0, nif, dst, src, type, nbuf); -} - -int -fec1_send(NIF *nif, uint8_t *dst, uint8_t *src, uint16_t type, NBUF *nbuf) -{ - return fec_send(1, nif, dst, src, type, nbuf); -} - -/* - * Enable interrupts on the selected FEC - * - * Parameters: - * ch FEC channel - * pri Interrupt Priority - * lvl Interrupt Level - */ -void -fec_irq_enable(uint8_t ch, uint8_t lvl, uint8_t pri) -{ - ASSERT(ch == 0 || ch == 1); - ASSERT(lvl > 0 && lvl < 8); - ASSERT(pri < 8); - - /* - * Setup the appropriate ICR - */ - MCF_INTC_ICRn((ch == 0) ? 39 : 38) = (uint8_t)(0 - | MCF_INTC_ICRn_IP(pri) - | MCF_INTC_ICRn_IL(lvl)); - - /* - * Clear any pending FEC interrupt events - */ - MCF_FEC_EIR(ch) = MCF_FEC_EIR_CLEAR_ALL; - - /* - * Unmask all FEC interrupts - */ - MCF_FEC_EIMR(ch) = MCF_FEC_EIMR_UNMASK_ALL; - - /* - * Unmask the FEC interrupt in the interrupt controller - */ - if (ch == 0) - MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK39; - else - MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK38; -} - -/* - * Disable interrupts on the selected FEC - * - * Parameters: - * ch FEC channel - */ -void -fec_irq_disable(uint8_t ch) -{ - ASSERT(ch == 0 || ch == 1); - - /* - * Mask all FEC interrupts - */ - MCF_FEC_EIMR(ch) = MCF_FEC_EIMR_MASK_ALL; - - /* - * Mask the FEC interrupt in the interrupt controller - */ - if (ch == 0) - MCF_INTC_IMRH |= MCF_INTC_IMRH_INT_MASK39; - else - MCF_INTC_IMRH |= MCF_INTC_IMRH_INT_MASK38; -} - -/* - * FEC interrupt handler - * All interrupts are multiplexed into a single vector for each - * FEC module. The lower level interrupt handler passes in the - * channel to this handler. Note that the receive interrupt is - * generated by the Multi-channel DMA FEC Rx task. - * - * Parameters: - * ch FEC channel - */ -static void -fec_irq_handler(uint8_t ch) -{ - uint32_t event, eir; - - /* - * Determine which interrupt(s) asserted by AND'ing the - * pending interrupts with those that aren't masked. - */ - eir = MCF_FEC_EIR(ch); - event = eir & MCF_FEC_EIMR(ch); - - #ifdef CONFIG_DRIVER_NET_MCF54XX_DEBUG - if (event != eir) - printf("Pending but not enabled: 0x%08X\n",(event ^ eir)); - #endif - - /* - * Clear the event(s) in the EIR immediately - */ - MCF_FEC_EIR(ch) = event; - - if (event & MCF_FEC_EIR_RFERR) - { - fec_log[ch].total++; - fec_log[ch].rferr++; - #ifdef CONFIG_DRIVER_NET_MCF54XX_DEBUG - printf("RFERR\n"); - printf("FECRFSR%d = 0x%08x\n",ch,MCF_FEC_FECRFSR(ch)); - fec_eth_stop(ch); - #endif - } - if (event & MCF_FEC_EIR_XFERR) - { - fec_log[ch].total++; - fec_log[ch].xferr++; - #ifdef CONFIG_DRIVER_NET_MCF54XX_DEBUG - printf("XFERR\n"); - #endif - } - if (event & MCF_FEC_EIR_XFUN) - { - fec_log[ch].total++; - fec_log[ch].xfun++; - #ifdef CONFIG_DRIVER_NET_MCF54XX_DEBUG - printf("XFUN\n"); - fec_eth_stop(ch); - #endif - } - if (event & MCF_FEC_EIR_RL) - { - fec_log[ch].total++; - fec_log[ch].rl++; - #ifdef CONFIG_DRIVER_NET_MCF54XX_DEBUG - printf("RL\n"); - #endif - } - if (event & MCF_FEC_EIR_LC) - { - fec_log[ch].total++; - fec_log[ch].lc++; - #ifdef CONFIG_DRIVER_NET_MCF54XX_DEBUG - printf("LC\n"); - #endif - } - if (event & MCF_FEC_EIR_MII) - { - fec_log[ch].mii++; - } - if (event & MCF_FEC_EIR_TXF) - { - fec_log[ch].txf++; - } - if (event & MCF_FEC_EIR_GRA) - { - fec_log[ch].gra++; - } - if (event & MCF_FEC_EIR_BABT) - { - fec_log[ch].total++; - fec_log[ch].babt++; - #ifdef CONFIG_DRIVER_NET_MCF54XX_DEBUG - printf("BABT\n"); - #endif - } - if (event & MCF_FEC_EIR_BABR) - { - fec_log[ch].total++; - fec_log[ch].babr++; - #ifdef CONFIG_DRIVER_NET_MCF54XX_DEBUG - printf("BABR\n"); - #endif - } - if (event & MCF_FEC_EIR_HBERR) - { - fec_log[ch].total++; - fec_log[ch].hberr++; - #ifdef CONFIG_DRIVER_NET_MCF54XX_DEBUG - printf("HBERR\n"); - #endif - } -} - -int -fec0_interrupt_handler(void* arg1, void* arg2) -{ - (void) arg1; - (void) arg2; - fec_irq_handler(0); - return 1; -} - -int -fec1_interrupt_handler(void* arg1, void* arg2) -{ - (void) arg1; - (void) arg2; - fec_irq_handler(1); - return 1; -} - -/* - * Configure the selected Ethernet port and enable all operations - * - * Parameters: - * ch FEC channel - * trcvr Transceiver mode (MII, 7-Wire or internal loopback) - * speed Maximum operating speed (MII only) - * duplex Full or Half-duplex (MII only) - * mac Physical (MAC) Address - */ -void -fec_eth_setup(uint8_t ch, uint8_t trcvr, uint8_t speed, uint8_t duplex, const uint8_t *mac) -{ - ASSERT(ch == 0 || ch == 1); - - /* - * Disable FEC interrupts - */ - fec_irq_disable(ch); - - /* - * Initialize the event log - */ - fec_log_init(ch); - - /* - * Initialize the network buffers and fec buffer descriptors - */ - nbuf_init(); - fecbd_init(ch); - - /* - * Initialize the FEC - */ - fec_reset(ch); - fec_init(ch,trcvr,mac); - - if (trcvr == FEC_MODE_MII) - { - /* - * Initialize the MII interface - */ - fec_mii_init(ch, CFG_SYSTEM_CORE_CLOCK); - } - - /* - * Initialize and enable FEC interrupts - */ - fec_irq_enable(ch, FEC_INTC_LVL(ch), FEC_INTC_PRI(ch)); - - /* - * Enable the multi-channel DMA tasks - */ - fec_rx_start(ch, (int8_t*)fecbd_get_start(ch,Rx)); - fec_tx_start(ch, (int8_t*)fecbd_get_start(ch,Tx)); - - /* - * Enable the FEC channel - */ - MCF_FEC_ECR(ch) |= MCF_FEC_ECR_ETHER_EN; -} -/* - * Reset the selected Ethernet port - * - * Parameters: - * ch FEC channel - */ -void -fec_eth_reset(uint8_t ch) -{ -// To do -} - -/* - * Stop the selected Ethernet port - * - * Parameters: - * ch FEC channel - */ -void -fec_eth_stop(uint8_t ch) -{ - int level; - - /* - * Disable interrupts - */ - level = asm_set_ipl(7); - - /* - * Gracefully disable the receiver and transmitter - */ - fec_tx_stop(ch); - fec_rx_stop(ch); - - /* - * Disable FEC interrupts - */ - fec_irq_disable(ch); - - /* - * Disable the FEC channel - */ - MCF_FEC_ECR(ch) &= ~MCF_FEC_ECR_ETHER_EN; - - #ifdef CONFIG_DRIVER_NET_MCF54XX_DEBUG - nbuf_debug_dump(); - fec_log_dump(ch); - #endif - - /* - * Flush the network buffers - */ - nbuf_flush(); - - /* - * Restore interrupt level - */ - asm_set_ipl(level); -} diff --git a/arch/m68k/mach-mcfv4e/fecbd.c b/arch/m68k/mach-mcfv4e/fecbd.c deleted file mode 100644 index a8e732b3ac..0000000000 --- a/arch/m68k/mach-mcfv4e/fecbd.c +++ /dev/null @@ -1,232 +0,0 @@ -/* - * File: fecbd.c - * Purpose: Provide a simple buffer management driver - * - * Notes: - */ -#include <common.h> -#include <linux/types.h> - -#include <mach/mcf54xx-regs.h> -#include <proc/mcdapi/MCD_dma.h> -#include <proc/net/net.h> -#include <proc/fecbd.h> -#include <proc/fec.h> -#include <proc/dma_utils.h> - -#define ASSERT(x) if (!(x)) hang(); - -/* - * This implements a simple static buffer descriptor - * ring for each channel and each direction - * - * FEC Buffer Descriptors need to be aligned to a 4-byte boundary. - * In order to accomplish this, data is over-allocated and manually - * aligned at runtime - * - * Enough space is allocated for each of the two FEC channels to have - * NRXBD Rx BDs and NTXBD Tx BDs - * - */ -FECBD unaligned_bds[(2 * NRXBD) + (2 * NTXBD) + 1]; - -/* - * These pointers are used to reference into the chunck of data set - * aside for buffer descriptors - */ -FECBD *RxBD; -FECBD *TxBD; - -/* - * Macros to easier access to the BD ring - */ -#define RxBD(ch,i) RxBD[(ch * NRXBD) + i] -#define TxBD(ch,i) TxBD[(ch * NTXBD) + i] - -/* - * Buffer descriptor indexes - */ -static int iTxbd_new; -static int iTxbd_old; -static int iRxbd; - -/* - * Initialize the FEC Buffer Descriptor ring - * Buffer Descriptor format is defined by the MCDAPI - * - * Parameters: - * ch FEC channel - */ -void -fecbd_init(uint8_t ch) -{ - NBUF *nbuf; - int i; - - /* - * Align Buffer Descriptors to 4-byte boundary - */ - RxBD = (FECBD *)(((int)unaligned_bds + 3) & 0xFFFFFFFC); - TxBD = (FECBD *)((int)RxBD + (sizeof(FECBD) * 2 * NRXBD)); - - /* - * Initialize the Rx Buffer Descriptor ring - */ - for (i = 0; i < NRXBD; ++i) - { - /* Grab a network buffer from the free list */ - nbuf = nbuf_alloc(); - ASSERT(nbuf); - - /* Initialize the BD */ - RxBD(ch,i).status = RX_BD_E | RX_BD_INTERRUPT; - RxBD(ch,i).length = RX_BUF_SZ; - RxBD(ch,i).data = nbuf->data; - - /* Add the network buffer to the Rx queue */ - nbuf_add(NBUF_RX_RING, nbuf); - } - - /* - * Set the WRAP bit on the last one - */ - RxBD(ch,i-1).status |= RX_BD_W; - - /* - * Initialize the Tx Buffer Descriptor ring - */ - for (i = 0; i < NTXBD; ++i) - { - TxBD(ch,i).status = TX_BD_INTERRUPT; - TxBD(ch,i).length = 0; - TxBD(ch,i).data = NULL; - } - - /* - * Set the WRAP bit on the last one - */ - TxBD(ch,i-1).status |= TX_BD_W; - - /* - * Initialize the buffer descriptor indexes - */ - iTxbd_new = iTxbd_old = iRxbd = 0; -} - -void -fecbd_dump(uint8_t ch) -{ - #ifdef CONFIG_DRIVER_NET_MCF54XX_DEBUG - int i; - - printf("\n------------ FEC%d BDs -----------\n",ch); - printf("RxBD Ring\n"); - for (i=0; i<NRXBD; i++) - { - printf("%02d: BD Addr=0x%08x, Ctrl=0x%04x, Lgth=%04d, DataPtr=0x%08x\n", - i, &RxBD(ch,i), - RxBD(ch,i).status, - RxBD(ch,i).length, - RxBD(ch,i).data); - } - printf("TxBD Ring\n"); - for (i=0; i<NTXBD; i++) - { - printf("%02d: BD Addr=0x%08x, Ctrl=0x%04x, Lgth=%04d, DataPtr=0x%08x\n", - i, &TxBD(ch,i), - TxBD(ch,i).status, - TxBD(ch,i).length, - TxBD(ch,i).data); - } - printf("--------------------------------\n\n"); - #endif -} - -/* - * Return the address of the first buffer descriptor in the ring. - * - * Parameters: - * ch FEC channel - * direction Rx or Tx Macro - * - * Return Value: - * The start address of the selected Buffer Descriptor ring - */ -uint32_t -fecbd_get_start(uint8_t ch, uint8_t direction) -{ - switch (direction) - { - case Rx: - return (uint32_t)((int)RxBD + (ch * sizeof(FECBD) * NRXBD)); - case Tx: - default: - return (uint32_t)((int)TxBD + (ch * sizeof(FECBD) * NTXBD)); - } -} - -FECBD * -fecbd_rx_alloc(uint8_t ch) -{ - int i = iRxbd; - - /* Check to see if the ring of BDs is full */ - if (RxBD(ch,i).status & RX_BD_E) - return NULL; - - /* Increment the circular index */ - iRxbd = (uint8_t)((iRxbd + 1) % NRXBD); - - return &RxBD(ch,i); -} - -/* - * This function keeps track of the next available Tx BD in the ring - * - * Parameters: - * ch FEC channel - * - * Return Value: - * Pointer to next available buffer descriptor. - * NULL if the BD ring is full - */ -FECBD * -fecbd_tx_alloc(uint8_t ch) -{ - int i = iTxbd_new; - - /* Check to see if the ring of BDs is full */ - if (TxBD(ch,i).status & TX_BD_R) - return NULL; - - /* Increment the circular index */ - iTxbd_new = (uint8_t)((iTxbd_new + 1) % NTXBD); - - return &TxBD(ch,i); -} - -/* - * This function keeps track of the Tx BDs that have already been - * processed by the FEC - * - * Parameters: - * ch FEC channel - * - * Return Value: - * Pointer to the oldest buffer descriptor that has already been sent - * by the FEC, NULL if the BD ring is empty - */ -FECBD * -fecbd_tx_free(uint8_t ch) -{ - int i = iTxbd_old; - - /* Check to see if the ring of BDs is empty */ - if ((TxBD(ch,i).data == NULL) || (TxBD(ch,i).status & TX_BD_R)) - return NULL; - - /* Increment the circular index */ - iTxbd_old = (uint8_t)((iTxbd_old + 1) % NTXBD); - - return &TxBD(ch,i); -} diff --git a/arch/m68k/mach-mcfv4e/include/mach/clocks.h b/arch/m68k/mach-mcfv4e/include/mach/clocks.h deleted file mode 100644 index daedb7aebe..0000000000 --- a/arch/m68k/mach-mcfv4e/include/mach/clocks.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * This File contains functions to query clock settings for the actual - * board. - */ -#ifndef __ASM_ARCH_CLOCKS_H -#define __ASM_ARCH_CLOCKS_H - -ulong mcfv4e_get_bus_clk(void); - -#endif /* __ASM_ARCH_CLOCKS_H */ diff --git a/arch/m68k/mach-mcfv4e/include/mach/debug_ll.h b/arch/m68k/mach-mcfv4e/include/mach/debug_ll.h deleted file mode 100644 index c58be70334..0000000000 --- a/arch/m68k/mach-mcfv4e/include/mach/debug_ll.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * This File contains declaration for early output support - */ -#ifndef __INCLUDE_ARCH_DEBUG_LL_H__ -#define __INCLUDE_ARCH_DEBUG_LL_H__ - -extern __inline__ void putc( char ch ) -{ - //extern int early_console_putc( char ch); - early_console_putc(NULL,ch); -} - -#endif /* __INCLUDE_ARCH_DEBUG_LL_H__ */ diff --git a/arch/m68k/mach-mcfv4e/include/mach/hardware.h b/arch/m68k/mach-mcfv4e/include/mach/hardware.h deleted file mode 100644 index 118afa63ab..0000000000 --- a/arch/m68k/mach-mcfv4e/include/mach/hardware.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * This File contains declaration for early output support - */ -#ifndef __ASM_ARCH_HARDWARE_H__ -#define __ASM_ARCH_HARDWARE_H__ - -#include <sizes.h> - -#ifdef CONFIG_ARCH_MCF54xx -#include "mcf54xx-regs.h" -#endif - -#endif /* __ASM_ARCH_HARDWARE_H__ */ diff --git a/arch/m68k/mach-mcfv4e/include/mach/mcf54xx-regs.h b/arch/m68k/mach-mcfv4e/include/mach/mcf54xx-regs.h deleted file mode 100644 index 8dd5ed2c15..0000000000 --- a/arch/m68k/mach-mcfv4e/include/mach/mcf54xx-regs.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * This File contains declaration for early output support - */ -#ifndef __MCF54xx_REGS_H__ -#define __MCF54xx_REGS_H__ - -/* System Registers for V4E cores (MCF547x and MCF548x) */ -#include <asm/coldfire/mcf5xxx.h> - -#endif /* __MCF54xx_REGS_H__ */ diff --git a/arch/m68k/mach-mcfv4e/include/proc/dma_utils.h b/arch/m68k/mach-mcfv4e/include/proc/dma_utils.h deleted file mode 100644 index 1cb27822ba..0000000000 --- a/arch/m68k/mach-mcfv4e/include/proc/dma_utils.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Declaration of support function used with the MultiChannel DMA - */ -#ifndef _DMA_UTILS_H_ -#define _DMA_UTILS_H_ - - -void dma_irq_enable(uint8_t, uint8_t); -void dma_irq_disable(void); -int dma_set_initiator(int); -uint32_t dma_get_initiator(int); -void dma_free_initiator(int); -int dma_set_channel(int, void (*)(void)); -int dma_get_channel(int); -void dma_free_channel(int); -int dma_interrupt_handler(void *, void *); - -/* - * Create identifiers for each initiator/requestor - */ -#define DMA_ALWAYS (0) -#define DMA_DSPI_RX (1) -#define DMA_DSPI_TX (2) -#define DMA_DREQ0 (3) -#define DMA_PSC0_RX (4) -#define DMA_PSC0_TX (5) -#define DMA_USBEP0 (6) -#define DMA_USBEP1 (7) -#define DMA_USBEP2 (8) -#define DMA_USBEP3 (9) -#define DMA_PCI_TX (10) -#define DMA_PCI_RX (11) -#define DMA_PSC1_RX (12) -#define DMA_PSC1_TX (13) -#define DMA_I2C_RX (14) -#define DMA_I2C_TX (15) -#define DMA_FEC0_RX (16) -#define DMA_FEC0_TX (17) -#define DMA_FEC1_RX (18) -#define DMA_FEC1_TX (19) -#define DMA_DREQ1 (20) -#define DMA_CTM0 (21) -#define DMA_CTM1 (22) -#define DMA_CTM2 (23) -#define DMA_CTM3 (24) -#define DMA_CTM4 (25) -#define DMA_CTM5 (26) -#define DMA_CTM6 (27) -#define DMA_CTM7 (28) -#define DMA_USBEP4 (29) -#define DMA_USBEP5 (30) -#define DMA_USBEP6 (31) -#define DMA_PSC2_RX (32) -#define DMA_PSC2_TX (33) -#define DMA_PSC3_RX (34) -#define DMA_PSC3_TX (35) -#define DMA_FEC_RX(x) ((x == 0) ? DMA_FEC0_RX : DMA_FEC1_RX) -#define DMA_FEC_TX(x) ((x == 0) ? DMA_FEC0_TX : DMA_FEC1_TX) - -#endif /* _DMA_UTILS_H_ */ diff --git a/arch/m68k/mach-mcfv4e/include/proc/fec.h b/arch/m68k/mach-mcfv4e/include/proc/fec.h deleted file mode 100644 index 16bfaa6ded..0000000000 --- a/arch/m68k/mach-mcfv4e/include/proc/fec.h +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Declaration for the Fast Ethernet Controller (FEC) - */ -#ifndef _FEC_H_ -#define _FEC_H_ - -// FIXME -#define NIF void - -/********************************************************************/ -/* MII Speed Settings */ -#define FEC_MII_10BASE_T 0 -#define FEC_MII_100BASE_TX 1 - -/* MII Duplex Settings */ -#define FEC_MII_HALF_DUPLEX 0 -#define FEC_MII_FULL_DUPLEX 1 - -/* Timeout for MII communications */ -#define FEC_MII_TIMEOUT 0x10000 - -/* External Interface Modes */ -#define FEC_MODE_7WIRE 0 -#define FEC_MODE_MII 1 -#define FEC_MODE_LOOPBACK 2 /* Internal Loopback */ - -/* - * FEC Event Log - */ -typedef struct { - int total; /* total count of errors */ - int hberr; /* heartbeat error */ - int babr; /* babbling receiver */ - int babt; /* babbling transmitter */ - int gra; /* graceful stop complete */ - int txf; /* transmit frame */ - int mii; /* MII */ - int lc; /* late collision */ - int rl; /* collision retry limit */ - int xfun; /* transmit FIFO underrrun */ - int xferr; /* transmit FIFO error */ - int rferr; /* receive FIFO error */ - int dtxf; /* DMA transmit frame */ - int drxf; /* DMA receive frame */ - int rfsw_inv; /* Invalid bit in RFSW */ - int rfsw_l; /* RFSW Last in Frame */ - int rfsw_m; /* RFSW Miss */ - int rfsw_bc; /* RFSW Broadcast */ - int rfsw_mc; /* RFSW Multicast */ - int rfsw_lg; /* RFSW Length Violation */ - int rfsw_no; /* RFSW Non-octet */ - int rfsw_cr; /* RFSW Bad CRC */ - int rfsw_ov; /* RFSW Overflow */ - int rfsw_tr; /* RFSW Truncated */ -} FEC_EVENT_LOG; - - -int fec_mii_write(uint8_t , uint8_t , uint8_t , uint16_t ); -int fec_mii_read(uint8_t , uint8_t , uint8_t , uint16_t *x); -void fec_mii_init(uint8_t, uint32_t); - -void fec_mib_init(uint8_t); -void fec_mib_dump(uint8_t); - -void fec_log_init(uint8_t); -void fec_log_dump(uint8_t); - -void fec_debug_dump(uint8_t); -void fec_duplex (uint8_t, uint8_t); - -uint8_t fec_hash_address(const uint8_t *); -void fec_set_address (uint8_t ch, const uint8_t *); - -void fec_reset (uint8_t); -void fec_init (uint8_t, uint8_t, const uint8_t *); - -void fec_rx_start(uint8_t, int8_t *); -void fec_rx_restart(uint8_t); -void fec_rx_stop (uint8_t); - -NBUF * fec_rx_frame(uint8_t ch, NIF *nif); - -void fec0_rx_frame(void); -void fec1_rx_frame(void); - -void fec_tx_start(uint8_t, int8_t *); -void fec_tx_restart(uint8_t); -void fec_tx_stop (uint8_t); - -void fec0_tx_frame(void); -void fec1_tx_frame(void); - -int fec_send(uint8_t, NIF *, uint8_t *, uint8_t *, uint16_t , NBUF *); -int fec0_send(NIF *, uint8_t *, uint8_t *, uint16_t , NBUF *); -int fec1_send(NIF *, uint8_t *, uint8_t *, uint16_t , NBUF *); - -void fec_irq_enable(uint8_t, uint8_t, uint8_t); -void fec_irq_disable(uint8_t); - -void fec_interrupt_handler(uint8_t); -int fec0_interrupt_handler(void *, void *); -int fec1_interrupt_handler(void *, void *); - -void fec_eth_setup(uint8_t, uint8_t, uint8_t, uint8_t, const uint8_t *); - -void fec_eth_reset(uint8_t); - -void fec_eth_stop(uint8_t); - -#endif /* _FEC_H_ */ diff --git a/arch/m68k/mach-mcfv4e/include/proc/fecbd.h b/arch/m68k/mach-mcfv4e/include/proc/fecbd.h deleted file mode 100644 index d7551c6587..0000000000 --- a/arch/m68k/mach-mcfv4e/include/proc/fecbd.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Provide a simple buffer management driver - */ - -#ifndef _FECBD_H_ -#define _FECBD_H_ - -/********************************************************************/ - -#define Rx 1 -#define Tx 0 - -/* - * Buffer sizes in bytes - */ -#ifndef RX_BUF_SZ -#define RX_BUF_SZ NBUF_SZ -#endif -#ifndef TX_BUF_SZ -#define TX_BUF_SZ NBUF_SZ -#endif - -/* - * Number of Rx and Tx Buffers and Buffer Descriptors - */ -#ifndef NRXBD -#define NRXBD 10 -#endif -#ifndef NTXBD -#define NTXBD 4 -#endif - -/* - * Buffer Descriptor Format - */ -typedef struct -{ - uint16_t status; /* control and status */ - uint16_t length; /* transfer length */ - uint8_t *data; /* buffer address */ -} FECBD; - -/* - * Bit level definitions for status field of buffer descriptors - */ -#define TX_BD_R 0x8000 -#define TX_BD_TO1 0x4000 -#define TX_BD_W 0x2000 -#define TX_BD_TO2 0x1000 -#define TX_BD_INTERRUPT 0x1000 /* MCF547x/8x Only */ -#define TX_BD_L 0x0800 -#define TX_BD_TC 0x0400 -#define TX_BD_DEF 0x0200 /* MCF5272 Only */ -#define TX_BD_ABC 0x0200 -#define TX_BD_HB 0x0100 /* MCF5272 Only */ -#define TX_BD_LC 0x0080 /* MCF5272 Only */ -#define TX_BD_RL 0x0040 /* MCF5272 Only */ -#define TX_BD_UN 0x0002 /* MCF5272 Only */ -#define TX_BD_CSL 0x0001 /* MCF5272 Only */ - -#define RX_BD_E 0x8000 -#define RX_BD_R01 0x4000 -#define RX_BD_W 0x2000 -#define RX_BD_R02 0x1000 -#define RX_BD_INTERRUPT 0x1000 /* MCF547x/8x Only */ -#define RX_BD_L 0x0800 -#define RX_BD_M 0x0100 -#define RX_BD_BC 0x0080 -#define RX_BD_MC 0x0040 -#define RX_BD_LG 0x0020 -#define RX_BD_NO 0x0010 -#define RX_BD_CR 0x0004 -#define RX_BD_OV 0x0002 -#define RX_BD_TR 0x0001 -#define RX_BD_ERROR (RX_BD_NO | RX_BD_CR | RX_BD_OV | RX_BD_TR) - -/* - * Functions provided in fec_bd.c - */ -void -fecbd_init(uint8_t); - -uint32_t -fecbd_get_start(uint8_t, uint8_t); - -FECBD * -fecbd_rx_alloc(uint8_t); - -FECBD * -fecbd_tx_alloc(uint8_t); - -FECBD * -fecbd_tx_free(uint8_t); - -#endif /* _FECBD_H_ */ diff --git a/arch/m68k/mach-mcfv4e/include/proc/mcdapi/MCD_dma.h b/arch/m68k/mach-mcfv4e/include/proc/mcdapi/MCD_dma.h deleted file mode 100644 index ad7f1393c1..0000000000 --- a/arch/m68k/mach-mcfv4e/include/proc/mcdapi/MCD_dma.h +++ /dev/null @@ -1,379 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Main header file for multi-channel DMA API. - */ -#ifndef _MCD_API_H -#define _MCD_API_H - -/* - * Turn Execution Unit tasks ON (#define) or OFF (#undef) - */ -#undef MCD_INCLUDE_EU - -/* - * Number of DMA channels - */ -#define NCHANNELS 16 - -/* - * Total number of variants - */ -#ifdef MCD_INCLUDE_EU -#define NUMOFVARIANTS 6 -#else -#define NUMOFVARIANTS 4 -#endif - -/* - * Define sizes of the various tables - */ -#define TASK_TABLE_SIZE (NCHANNELS*32) -#define VAR_TAB_SIZE (128) -#define CONTEXT_SAVE_SIZE (128) -#define FUNCDESC_TAB_SIZE (256) - -#ifdef MCD_INCLUDE_EU -#define FUNCDESC_TAB_NUM 16 -#else -#define FUNCDESC_TAB_NUM 1 -#endif - - -#ifndef DEFINESONLY - -/* - * Portability typedefs - */ -//typedef signed int s32; -//typedef unsigned int u32; -//typedef signed short s16; -//typedef unsigned short u16; -//typedef signed char s8; -//typedef unsigned char u8; -// -/* - * These structures represent the internal registers of the - * multi-channel DMA - */ -struct dmaRegs_s { - u32 taskbar; /* task table base address register */ - u32 currPtr; - u32 endPtr; - u32 varTablePtr; - u16 dma_rsvd0; - u16 ptdControl; /* ptd control */ - u32 intPending; /* interrupt pending register */ - u32 intMask; /* interrupt mask register */ - u16 taskControl[16]; /* task control registers */ - u8 priority[32]; /* priority registers */ - u32 initiatorMux; /* initiator mux control */ - u32 taskSize0; /* task size control register 0. */ - u32 taskSize1; /* task size control register 1. */ - u32 dma_rsvd1; /* reserved */ - u32 dma_rsvd2; /* reserved */ - u32 debugComp1; /* debug comparator 1 */ - u32 debugComp2; /* debug comparator 2 */ - u32 debugControl; /* debug control */ - u32 debugStatus; /* debug status */ - u32 ptdDebug; /* priority task decode debug */ - u32 dma_rsvd3[31]; /* reserved */ -}; -typedef volatile struct dmaRegs_s dmaRegs; - -#endif - -/* - * PTD contrl reg bits - */ -#define PTD_CTL_TSK_PRI 0x8000 -#define PTD_CTL_COMM_PREFETCH 0x0001 - -/* - * Task Control reg bits and field masks - */ -#define TASK_CTL_EN 0x8000 -#define TASK_CTL_VALID 0x4000 -#define TASK_CTL_ALWAYS 0x2000 -#define TASK_CTL_INIT_MASK 0x1f00 -#define TASK_CTL_ASTRT 0x0080 -#define TASK_CTL_HIPRITSKEN 0x0040 -#define TASK_CTL_HLDINITNUM 0x0020 -#define TASK_CTL_ASTSKNUM_MASK 0x000f - -/* - * Priority reg bits and field masks - */ -#define PRIORITY_HLD 0x80 -#define PRIORITY_PRI_MASK 0x07 - -/* - * Debug Control reg bits and field masks - */ -#define DBG_CTL_BLOCK_TASKS_MASK 0xffff0000 -#define DBG_CTL_AUTO_ARM 0x00008000 -#define DBG_CTL_BREAK 0x00004000 -#define DBG_CTL_COMP1_TYP_MASK 0x00003800 -#define DBG_CTL_COMP2_TYP_MASK 0x00000070 -#define DBG_CTL_EXT_BREAK 0x00000004 -#define DBG_CTL_INT_BREAK 0x00000002 - -/* - * PTD Debug reg selector addresses - * This reg must be written with a value to show the contents of - * one of the desired internal register. - */ -#define PTD_DBG_REQ 0x00 /* shows the state of 31 initiators */ -#define PTD_DBG_TSK_VLD_INIT 0x01 /* shows which 16 tasks are valid and - have initiators asserted */ - - -/* - * General return values - */ -#define MCD_OK 0 -#define MCD_ERROR -1 -#define MCD_TABLE_UNALIGNED -2 -#define MCD_CHANNEL_INVALID -3 - -/* - * MCD_initDma input flags - */ -#define MCD_RELOC_TASKS 0x00000001 -#define MCD_NO_RELOC_TASKS 0x00000000 -#define MCD_COMM_PREFETCH_EN 0x00000002 /* Commbus Prefetching - MCF547x/548x ONLY */ - -/* - * MCD_dmaStatus Status Values for each channel - */ -#define MCD_NO_DMA 1 /* No DMA has been requested since reset */ -#define MCD_IDLE 2 /* DMA active, but the initiator is currently inactive */ -#define MCD_RUNNING 3 /* DMA active, and the initiator is currently active */ -#define MCD_PAUSED 4 /* DMA active but it is currently paused */ -#define MCD_HALTED 5 /* the most recent DMA has been killed with MCD_killTask() */ -#define MCD_DONE 6 /* the most recent DMA has completed. */ - - -/* - * MCD_startDma parameter defines - */ - -/* - * Constants for the funcDesc parameter - */ -/* Byte swapping: */ -#define MCD_NO_BYTE_SWAP 0x00045670 /* to disable byte swapping. */ -#define MCD_BYTE_REVERSE 0x00076540 /* to reverse the bytes of each u32 of the DMAed data. */ -#define MCD_U16_REVERSE 0x00067450 /* to reverse the 16-bit halves of - each 32-bit data value being DMAed.*/ -#define MCD_U16_BYTE_REVERSE 0x00054760 /* to reverse the byte halves of each - 16-bit half of each 32-bit data value DMAed */ -#define MCD_NO_BIT_REV 0x00000000 /* do not reverse the bits of each byte DMAed. */ -#define MCD_BIT_REV 0x00088880 /* reverse the bits of each byte DMAed */ -/* CRCing: */ -#define MCD_CRC16 0xc0100000 /* to perform CRC-16 on DMAed data. */ -#define MCD_CRCCCITT 0xc0200000 /* to perform CRC-CCITT on DMAed data. */ -#define MCD_CRC32 0xc0300000 /* to perform CRC-32 on DMAed data. */ -#define MCD_CSUMINET 0xc0400000 /* to perform internet checksums on DMAed data.*/ -#define MCD_NO_CSUM 0xa0000000 /* to perform no checksumming. */ - -#define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | MCD_NO_CSUM) -#define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM) - -/* - * Constants for the flags parameter - */ -#define MCD_TT_FLAGS_RL 0x00000001 /* Read line */ -#define MCD_TT_FLAGS_CW 0x00000002 /* Combine Writes */ -#define MCD_TT_FLAGS_SP 0x00000004 /* Speculative prefetch(XLB) MCF547x/548x ONLY */ -#define MCD_TT_FLAGS_MASK 0x000000ff -#define MCD_TT_FLAGS_DEF (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW) - -#define MCD_SINGLE_DMA 0x00000100 /* Unchained DMA */ -#define MCD_CHAIN_DMA /* TBD */ -#define MCD_EU_DMA /* TBD */ -#define MCD_FECTX_DMA 0x00001000 /* FEC TX ring DMA */ -#define MCD_FECRX_DMA 0x00002000 /* FEC RX ring DMA */ - - -/* these flags are valid for MCD_startDma and the chained buffer descriptors */ -#define MCD_BUF_READY 0x80000000 /* indicates that this buffer is now under the DMA's control */ -#define MCD_WRAP 0x20000000 /* to tell the FEC Dmas to wrap to the first BD */ -#define MCD_INTERRUPT 0x10000000 /* to generate an interrupt after completion of the DMA. */ -#define MCD_END_FRAME 0x08000000 /* tell the DMA to end the frame when transferring - last byte of data in buffer */ -#define MCD_CRC_RESTART 0x40000000 /* to empty out the accumulated checksum - prior to performing the DMA. */ - -/* Defines for the FEC buffer descriptor control/status word*/ -#define MCD_FEC_BUF_READY 0x8000 -#define MCD_FEC_WRAP 0x2000 -#define MCD_FEC_INTERRUPT 0x1000 -#define MCD_FEC_END_FRAME 0x0800 - - -/* - * Defines for general intuitiveness - */ - -#define MCD_TRUE 1 -#define MCD_FALSE 0 - -/* - * Three different cases for destination and source. - */ -#define MINUS1 -1 -#define ZERO 0 -#define PLUS1 1 - -#ifndef DEFINESONLY - -/* Task Table Entry struct*/ -typedef struct { - u32 TDTstart; /* task descriptor table start */ - u32 TDTend; /* task descriptor table end */ - u32 varTab; /* variable table start */ - u32 FDTandFlags; /* function descriptor table start and flags */ - volatile u32 descAddrAndStatus; - volatile u32 modifiedVarTab; - u32 contextSaveSpace; /* context save space start */ - u32 literalBases; -} TaskTableEntry; - - -/* Chained buffer descriptor */ -typedef volatile struct MCD_bufDesc_struct MCD_bufDesc; -struct MCD_bufDesc_struct { - u32 flags; /* flags describing the DMA */ - u32 csumResult; /* checksum from checksumming performed since last checksum reset */ - s8 *srcAddr; /* the address to move data from */ - s8 *destAddr; /* the address to move data to */ - s8 *lastDestAddr; /* the last address written to */ - u32 dmaSize; /* the number of bytes to transfer independent of the transfer size */ - MCD_bufDesc *next; /* next buffer descriptor in chain */ - u32 info; /* private information about this descriptor; DMA does not affect it */ -}; - -/* Progress Query struct */ -typedef volatile struct MCD_XferProg_struct { - s8 *lastSrcAddr; /* the most-recent or last, post-increment source address */ - s8 *lastDestAddr; /* the most-recent or last, post-increment destination address */ - u32 dmaSize; /* the amount of data transferred for the current buffer */ - MCD_bufDesc *currBufDesc;/* pointer to the current buffer descriptor being DMAed */ -} MCD_XferProg; - - -/* FEC buffer descriptor */ -typedef volatile struct MCD_bufDescFec_struct { - u16 statCtrl; - u16 length; - u32 dataPointer; -} MCD_bufDescFec; - - -/*************************************************************************/ -/* - * API function Prototypes - see MCD_dmaApi.c for further notes - */ - -/* - * MCD_startDma starts a particular kind of DMA . - */ -int MCD_startDma ( - int channel, /* the channel on which to run the DMA */ - s8 *srcAddr, /* the address to move data from, or buffer-descriptor address */ - s16 srcIncr, /* the amount to increment the source address per transfer */ - s8 *destAddr, /* the address to move data to */ - s16 destIncr, /* the amount to increment the destination address per transfer */ - u32 dmaSize, /* the number of bytes to transfer independent of the transfer size */ - u32 xferSize, /* the number bytes in of each data movement (1, 2, or 4) */ - u32 initiator, /* what device initiates the DMA */ - int priority, /* priority of the DMA */ - u32 flags, /* flags describing the DMA */ - u32 funcDesc /* a description of byte swapping, bit swapping, and CRC actions */ -); - -/* - * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA - * registers, relocating and creating the appropriate task structures, and - * setting up some global settings - */ -int MCD_initDma (dmaRegs *sDmaBarAddr, void *taskTableDest, u32 flags); - -/* - * MCD_dmaStatus() returns the status of the DMA on the requested channel. - */ -int MCD_dmaStatus (int channel); - -/* - * MCD_XferProgrQuery() returns progress of DMA on requested channel - */ -int MCD_XferProgrQuery (int channel, MCD_XferProg *progRep); - -/* - * MCD_killDma() halts the DMA on the requested channel, without any - * intention of resuming the DMA. - */ -int MCD_killDma (int channel); - -/* - * MCD_continDma() continues a DMA which as stopped due to encountering an - * unready buffer descriptor. - */ -int MCD_continDma (int channel); - -/* - * MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is - * running on that channel). - */ -int MCD_pauseDma (int channel); - -/* - * MCD_resumeDma() resumes the DMA on a given channel (if any DMA is - * running on that channel). - */ -int MCD_resumeDma (int channel); - -/* - * MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA - */ -int MCD_csumQuery (int channel, u32 *csum); - -/* - * MCD_getCodeSize provides the packed size required by the microcoded task - * and structures. - */ -int MCD_getCodeSize(void); - -/* - * MCD_getVersion provides a pointer to a version string and returns a - * version number. - */ -int MCD_getVersion(char **longVersion); - -/* macro for setting a location in the variable table */ -#define MCD_SET_VAR(taskTab,idx,value) ((u32 *)(taskTab)->varTab)[idx] = value - /* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function, - so I'm avoiding surrounding it with "do {} while(0)" */ - -#endif /* DEFINESONLY */ - -#endif /* _MCD_API_H */ diff --git a/arch/m68k/mach-mcfv4e/include/proc/mcdapi/MCD_progCheck.h b/arch/m68k/mach-mcfv4e/include/proc/mcdapi/MCD_progCheck.h deleted file mode 100644 index a536f147c1..0000000000 --- a/arch/m68k/mach-mcfv4e/include/proc/mcdapi/MCD_progCheck.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * This file is autogenerated. Do not change . - */ -#define CURRBD 4 -#define DCOUNT 6 -#define DESTPTR 5 -#define SRCPTR 7 diff --git a/arch/m68k/mach-mcfv4e/include/proc/mcdapi/MCD_tasksInit.h b/arch/m68k/mach-mcfv4e/include/proc/mcdapi/MCD_tasksInit.h deleted file mode 100644 index 6b19d0262b..0000000000 --- a/arch/m68k/mach-mcfv4e/include/proc/mcdapi/MCD_tasksInit.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Declaration for the MCD tasks. Do not edit. - */ -#ifndef MCD_TSK_INIT_H -#define MCD_TSK_INIT_H 1 - -/* - * Do not edit! - */ - -/* - * Task 0 - */ -void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel); - - -/* - * Task 1 - */ -void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel); - - -/* - * Task 2 - */ -void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel); - - -/* - * Task 3 - */ -void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel); - - -/* - * Task 4 - */ -void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel); - - -/* - * Task 5 - */ -void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel); - -#endif /* MCD_TSK_INIT_H */ diff --git a/arch/m68k/mach-mcfv4e/include/proc/net/eth.h b/arch/m68k/mach-mcfv4e/include/proc/net/eth.h deleted file mode 100644 index e86d0646c4..0000000000 --- a/arch/m68k/mach-mcfv4e/include/proc/net/eth.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Declaration for for Ethernet Frames. - */ - -#ifndef _ETH_H -#define _ETH_H - - -/* Ethernet standard lengths in bytes*/ -#define ETH_ADDR_LEN (6) -#define ETH_TYPE_LEN (2) -#define ETH_CRC_LEN (4) -#define ETH_MAX_DATA (1500) -#define ETH_MIN_DATA (46) -#define ETH_HDR_LEN (ETH_ADDR_LEN * 2 + ETH_TYPE_LEN) - -/* Defined Ethernet Frame Types */ -#define ETH_FRM_IP (0x0800) -#define ETH_FRM_ARP (0x0806) -#define ETH_FRM_RARP (0x8035) -#define ETH_FRM_TEST (0xA5A5) - -/* Maximum and Minimum Ethernet Frame Sizes */ -#define ETH_MAX_FRM (ETH_HDR_LEN + ETH_MAX_DATA + ETH_CRC_LEN) -#define ETH_MIN_FRM (ETH_HDR_LEN + ETH_MIN_DATA + ETH_CRC_LEN) -#define ETH_MTU (ETH_HDR_LEN + ETH_MAX_DATA) - -/* Ethernet Addresses */ -typedef uint8_t ETH_ADDR[ETH_ADDR_LEN]; - -/* 16-bit Ethernet Frame Type, ie. Protocol */ -typedef uint16_t ETH_FRM_TYPE; - -/* Ethernet Frame Header definition */ -typedef struct -{ - ETH_ADDR dest; - ETH_ADDR src; - ETH_FRM_TYPE type; -} ETH_HDR; - -/* Ethernet Frame definition */ -typedef struct -{ - ETH_HDR head; - uint8_t* data; -} ETH_FRAME; - - -#endif /* _ETH_H */ diff --git a/arch/m68k/mach-mcfv4e/include/proc/net/nbuf.h b/arch/m68k/mach-mcfv4e/include/proc/net/nbuf.h deleted file mode 100644 index 8b6a89c27d..0000000000 --- a/arch/m68k/mach-mcfv4e/include/proc/net/nbuf.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Definitions for network buffer management - */ - -#ifndef _MCFV4E_NBUF_H_ -#define _MCFV4E_NBUF_H_ - -/* - * Include the Queue structure definitions - */ -#include "queue.h" - -/* - * Number of network buffers to use - */ -#define NBUF_MAX 30 - -/* - * Size of each buffer in bytes - */ -#ifndef NBUF_SZ -#define NBUF_SZ 1520 -#endif - -/* - * Defines to identify all the buffer queues - * - FREE must always be defined as 0 - */ -#define NBUF_FREE 0 /* available buffers */ -#define NBUF_TX_RING 1 /* buffers in the Tx BD ring */ -#define NBUF_RX_RING 2 /* buffers in the Rx BD ring */ -#define NBUF_SCRATCH 3 /* misc */ -#define NBUF_MAXQ 4 /* total number of queueus */ - -/* - * Buffer Descriptor Format - * - * Fields: - * next Pointer to next node in the queue - * data Pointer to the data buffer - * offset Index into buffer - * length Remaining bytes in buffer from (data + offset) - */ -typedef struct -{ - QNODE node; - uint8_t *data; - uint16_t offset; - uint16_t length; -} NBUF; - -/* - * Functions to manipulate the network buffers. - */ -int nbuf_init(void); -void nbuf_flush(void); - -NBUF * nbuf_alloc (void); -void nbuf_free(NBUF *); - -NBUF *nbuf_remove(int); -void nbuf_add(int, NBUF *); - -void nbuf_reset(void); -void nbuf_debug_dump(void); - - -#endif /* _MCFV4E_NBUF_H_ */ diff --git a/arch/m68k/mach-mcfv4e/include/proc/net/net.h b/arch/m68k/mach-mcfv4e/include/proc/net/net.h deleted file mode 100644 index d6877596b6..0000000000 --- a/arch/m68k/mach-mcfv4e/include/proc/net/net.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Network definitions and prototypes for dBUG. - */ - -#ifndef _MCFV4E_NET_H -#define _MCFV4E_NET_H - -/* - * Include information and prototypes for all protocols - */ -#include "eth.h" -#include "nbuf.h" - -int netif_init(int channel); -int netif_setup(int channel); -int netif_done(int channel); - -#endif /* _MCFV4E_NET_H */ - diff --git a/arch/m68k/mach-mcfv4e/include/proc/net/queue.h b/arch/m68k/mach-mcfv4e/include/proc/net/queue.h deleted file mode 100644 index d5c13f8a50..0000000000 --- a/arch/m68k/mach-mcfv4e/include/proc/net/queue.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Implement a first in, first out linked list - */ -#ifndef _QUEUE_H_ -#define _QUEUE_H_ - -/* - * Individual queue node - */ -typedef struct NODE -{ - struct NODE *next; -} QNODE; - -/* - * Queue Struture - linked list of qentry items - */ -typedef struct -{ - QNODE *head; - QNODE *tail; -} QUEUE; - -/* - * Functions provided by queue.c - */ -void queue_init(QUEUE *); -int queue_isempty(QUEUE *); -void queue_add(QUEUE *, QNODE *); -QNODE* queue_remove(QUEUE *); -QNODE* queue_peek(QUEUE *); -void queue_move(QUEUE *, QUEUE *); - -#endif /* _QUEUE_H_ */ diff --git a/arch/m68k/mach-mcfv4e/include/proc/processor.h b/arch/m68k/mach-mcfv4e/include/proc/processor.h deleted file mode 100644 index 4f196bda9b..0000000000 --- a/arch/m68k/mach-mcfv4e/include/proc/processor.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Coldfire V4e processor specific defines - */ - -/* Empty dummy FIXME */ - -/* interrupt management */ - -void mcf_interrupts_initialize (void); -int mcf_interrupts_register_handler (int vector, int (*handler)(void *, void *), void *hdev, void *harg); -void mcf_interrupts_remove_handler (int (*handler)(void *, void *)); -int mcf_execute_irq_handler (struct pt_regs *pt_regs,int); - diff --git a/arch/m68k/mach-mcfv4e/include/proc/ptrace.h b/arch/m68k/mach-mcfv4e/include/proc/ptrace.h deleted file mode 100644 index 5e120596d2..0000000000 --- a/arch/m68k/mach-mcfv4e/include/proc/ptrace.h +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Declaration and defines for M68k register frames - */ -#ifndef __ASM_PROC_PTRACE_H -#define __ASM_PROC_PTRACE_H - -#define TRACE_FLAG 0x8000 -#define SVR_MODE 0x2000 -#define MODE_MASK 0x2000 -#define MASTER_FLAG 0x1000 -#define IRQ_MASK 0x0700 -#define CC_MASK 0x00FF - -#define CC_X_BIT 0x0010 -#define CC_N_BIT 0x0008 -#define CC_Z_BIT 0x0004 -#define CC_V_BIT 0x0002 -#define CC_C_BIT 0x0001 - -#define PCMASK 0x0 - -#ifndef __ASSEMBLY__ - -/* this struct defines the way the registers are stored on the - stack during a system call. */ - -struct pt_regs { - long uregs[37]; -}; -#define M68K_sp uregs[37] -#define M68K_sr uregs[36] -#define M68K_pc uregs[35] -#define M68K_fpiar uregs[34] -#define M68K_fpsr uregs[33] -#define M68K_fpcr uregs[32] - -#define M68K_fp7 uregs[30] -#define M68K_fp6 uregs[28] -#define M68K_fp5 uregs[26] -#define M68K_fp4 uregs[24] -#define M68K_fp3 uregs[22] -#define M68K_fp2 uregs[20] -#define M68K_fp1 uregs[18] -#define M68K_fp0 uregs[16] - -#define M68K_a7 uregs[15] -#define M68K_a6 uregs[14] -#define M68K_a5 uregs[13] -#define M68K_a4 uregs[12] -#define M68K_a3 uregs[11] -#define M68K_a2 uregs[10] -#define M68K_a1 uregs[ 9] -#define M68K_a0 uregs[ 8] -#define M68K_d7 uregs[ 7] -#define M68K_d6 uregs[ 6] -#define M68K_d5 uregs[ 5] -#define M68K_d4 uregs[ 4] -#define M68K_d3 uregs[ 3] -#define M68K_d2 uregs[ 2] -#define M68K_d1 uregs[ 1] -#define M68K_d0 uregs[ 0] - - -#ifdef __KERNEL__ - -#define user_mode(regs) \ - (((regs)->M68K_sr & SVR_MODE) == 0) - -#define processor_mode(regs) \ - ((regs)->M68K_sr & SVR_MODE) - -#define interrupts_enabled(regs) \ - (!((regs)->M68K_sr & IRQ_MASK)) - -#define condition_codes(regs) \ - ((regs)->M68K_sr & CC_MASK) - -/* Are the current registers suitable for user mode? - * (used to maintain security in signal handlers) - */ -static inline int valid_user_regs(struct pt_regs *regs) -{ - if ((regs->M68K_sr & SVR_MODE) == 0 && - (regs->M68K_sr & IRQ_MASK) == 7) - return 1; - - /* - * Force SR to something logical... - */ - regs->M68K_sr &= ~(CC_MASK); - - return 0; -} - -#endif /* __KERNEL__ */ - -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/arch/m68k/mach-mcfv4e/mcdapi/MCD_dmaApi.c b/arch/m68k/mach-mcfv4e/mcdapi/MCD_dmaApi.c deleted file mode 100644 index 60e2b6dd76..0000000000 --- a/arch/m68k/mach-mcfv4e/mcdapi/MCD_dmaApi.c +++ /dev/null @@ -1,907 +0,0 @@ -/* - * File: MCD_dmaApi.c - * Purpose: Main C file for multi-channel DMA API. - * - * Notes: - */ - -#include <asm/types.h> -#include <proc/mcdapi/MCD_dma.h> -#include <proc/mcdapi/MCD_tasksInit.h> -#include <proc/mcdapi/MCD_progCheck.h> - -/* - * This is an API-internal pointer to the DMA's registers - */ -dmaRegs *MCD_dmaBar; - -/* - * These are the real and model task tables as generated by the - * build process - */ -extern TaskTableEntry MCD_realTaskTableSrc[NCHANNELS]; -extern TaskTableEntry MCD_modelTaskTableSrc[NUMOFVARIANTS]; - -/* - * However, this (usually) gets relocated to on-chip SRAM, at which - * point we access them as these tables - */ -volatile TaskTableEntry *MCD_taskTable; -TaskTableEntry *MCD_modelTaskTable; - - -/* - * MCD_chStatus[] is an array of status indicators for remembering - * whether a DMA has ever been attempted on each channel, pausing - * status, etc. - */ -static int MCD_chStatus[NCHANNELS] = -{ - MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, - MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, - MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, - MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA -}; - -/* - * Prototypes for local functions - */ -static void MCD_memcpy (int *dest, int *src, u32 size); -static void MCD_resmActions (int channel); - -/* - * Buffer descriptors used for storage of progress info for single Dmas - * Also used as storage for the DMA for CRCs for single DMAs - * Otherwise, the DMA does not parse these buffer descriptors - */ -#ifdef MCD_INCLUDE_EU -extern MCD_bufDesc MCD_singleBufDescs[NCHANNELS]; -#else -MCD_bufDesc MCD_singleBufDescs[NCHANNELS]; -#endif -MCD_bufDesc *MCD_relocBuffDesc; - - -/* - * Defines for the debug control register's functions - */ -#define DBG_CTL_COMP1_TASK (0x00002000) /* have comparator 1 look for a task # */ -#define DBG_CTL_ENABLE (DBG_CTL_AUTO_ARM | \ - DBG_CTL_BREAK | \ - DBG_CTL_INT_BREAK | \ - DBG_CTL_COMP1_TASK) -#define DBG_CTL_DISABLE (DBG_CTL_AUTO_ARM | \ - DBG_CTL_INT_BREAK | \ - DBG_CTL_COMP1_TASK) -#define DBG_KILL_ALL_STAT (0xFFFFFFFF) - -/* - * Offset to context save area where progress info is stored - */ -#define CSAVE_OFFSET 10 - -/* - * Defines for Byte Swapping - */ -#define MCD_BYTE_SWAP_KILLER 0xFFF8888F -#define MCD_NO_BYTE_SWAP_ATALL 0x00040000 - -/* - * Execution Unit Identifiers - */ -#define MAC 0 /* legacy - not used */ -#define LUAC 1 /* legacy - not used */ -#define CRC 2 /* legacy - not used */ -#define LURC 3 /* Logic Unit with CRC */ - -/* - * Task Identifiers - */ -#define TASK_CHAINNOEU 0 -#define TASK_SINGLENOEU 1 -#ifdef MCD_INCLUDE_EU -#define TASK_CHAINEU 2 -#define TASK_SINGLEEU 3 -#define TASK_FECRX 4 -#define TASK_FECTX 5 -#else -#define TASK_CHAINEU 0 -#define TASK_SINGLEEU 1 -#define TASK_FECRX 2 -#define TASK_FECTX 3 -#endif - -/* - * Structure to remember which variant is on which channel - * TBD- need this? - */ -typedef struct MCD_remVariants_struct MCD_remVariant; -struct MCD_remVariants_struct -{ - int remDestRsdIncr[NCHANNELS]; /* -1,0,1 */ - int remSrcRsdIncr[NCHANNELS]; /* -1,0,1 */ - s16 remDestIncr[NCHANNELS]; /* DestIncr */ - s16 remSrcIncr[NCHANNELS]; /* srcIncr */ - u32 remXferSize[NCHANNELS]; /* xferSize */ -}; - -/* - * Structure to remember the startDma parameters for each channel - */ -MCD_remVariant MCD_remVariants; - -/* - * Function: MCD_initDma - * Purpose: Initializes the DMA API by setting up a pointer to the DMA - * registers, relocating and creating the appropriate task - * structures, and setting up some global settings - * Arguments: - * dmaBarAddr - pointer to the multichannel DMA registers - * taskTableDest - location to move DMA task code and structs to - * flags - operational parameters - * Return Value: - * MCD_TABLE_UNALIGNED if taskTableDest is not 512-byte aligned - * MCD_OK otherwise - */ -extern u32 MCD_funcDescTab0[]; - -int MCD_initDma (dmaRegs *dmaBarAddr, void *taskTableDest, u32 flags) -{ - int i; - TaskTableEntry *entryPtr; - - /* setup the local pointer to register set */ - MCD_dmaBar = dmaBarAddr; - - /* do we need to move/create a task table */ - if ((flags & MCD_RELOC_TASKS) != 0) - { - int fixedSize; - u32 *fixedPtr; - /*int *tablePtr = taskTableDest;TBD*/ - int varTabsOffset, funcDescTabsOffset, contextSavesOffset; - int taskDescTabsOffset; - int taskTableSize, varTabsSize, funcDescTabsSize, contextSavesSize; - int taskDescTabSize; - - int i; - - /* check if physical address is aligned on 512 byte boundary */ - if (((u32)taskTableDest & 0x000001ff) != 0) - return(MCD_TABLE_UNALIGNED); - - MCD_taskTable = taskTableDest; /* set up local pointer to task Table */ - - /* - * Create a task table: - * - compute aligned base offsets for variable tables and - * function descriptor tables, then - * - loop through the task table and setup the pointers - * - copy over model task table with the the actual task descriptor - * tables - */ - - taskTableSize = NCHANNELS * sizeof(TaskTableEntry); - /* align variable tables to size */ - varTabsOffset = taskTableSize + (u32)taskTableDest; - if ((varTabsOffset & (VAR_TAB_SIZE - 1)) != 0) - varTabsOffset = (varTabsOffset + VAR_TAB_SIZE) & (~VAR_TAB_SIZE); - /* align function descriptor tables */ - varTabsSize = NCHANNELS * VAR_TAB_SIZE; - funcDescTabsOffset = varTabsOffset + varTabsSize; - - if ((funcDescTabsOffset & (FUNCDESC_TAB_SIZE - 1)) != 0) - funcDescTabsOffset = (funcDescTabsOffset + FUNCDESC_TAB_SIZE) & - (~FUNCDESC_TAB_SIZE); - - funcDescTabsSize = FUNCDESC_TAB_NUM * FUNCDESC_TAB_SIZE; - contextSavesOffset = funcDescTabsOffset + funcDescTabsSize; - contextSavesSize = (NCHANNELS * CONTEXT_SAVE_SIZE); - fixedSize = taskTableSize + varTabsSize + funcDescTabsSize + - contextSavesSize; - - /* zero the thing out */ - fixedPtr = (u32 *)taskTableDest; - for (i = 0;i<(fixedSize/4);i++) - fixedPtr[i] = 0; - - entryPtr = (TaskTableEntry*)MCD_taskTable; - /* set up fixed pointers */ - for (i = 0; i < NCHANNELS; i++) - { - entryPtr[i].varTab = (u32)varTabsOffset; /* update ptr to local value */ - entryPtr[i].FDTandFlags = (u32)funcDescTabsOffset | MCD_TT_FLAGS_DEF; - entryPtr[i].contextSaveSpace = (u32)contextSavesOffset; - varTabsOffset += VAR_TAB_SIZE; -#ifdef MCD_INCLUDE_EU /* if not there is only one, just point to the same one */ - funcDescTabsOffset += FUNCDESC_TAB_SIZE; -#endif - contextSavesOffset += CONTEXT_SAVE_SIZE; - } - /* copy over the function descriptor table */ - for ( i = 0; i < FUNCDESC_TAB_NUM; i++) - { - MCD_memcpy((void*)(entryPtr[i].FDTandFlags & ~MCD_TT_FLAGS_MASK), - (void*)MCD_funcDescTab0, FUNCDESC_TAB_SIZE); - } - - /* copy model task table to where the context saves stuff leaves off*/ - MCD_modelTaskTable = (TaskTableEntry*)contextSavesOffset; - - MCD_memcpy ((void*)MCD_modelTaskTable, (void*)MCD_modelTaskTableSrc, - NUMOFVARIANTS * sizeof(TaskTableEntry)); - - entryPtr = MCD_modelTaskTable; /* point to local version of - model task table */ - taskDescTabsOffset = (u32)MCD_modelTaskTable + - (NUMOFVARIANTS * sizeof(TaskTableEntry)); - - /* copy actual task code and update TDT ptrs in local model task table */ - for (i = 0; i < NUMOFVARIANTS; i++) - { - taskDescTabSize = entryPtr[i].TDTend - entryPtr[i].TDTstart + 4; - MCD_memcpy ((void*)taskDescTabsOffset, (void*)entryPtr[i].TDTstart, taskDescTabSize); - entryPtr[i].TDTstart = (u32)taskDescTabsOffset; - taskDescTabsOffset += taskDescTabSize; - entryPtr[i].TDTend = (u32)taskDescTabsOffset - 4; - } -#ifdef MCD_INCLUDE_EU /* Tack single DMA BDs onto end of code so API controls - where they are since DMA might write to them */ - MCD_relocBuffDesc = (MCD_bufDesc*)(entryPtr[NUMOFVARIANTS - 1].TDTend + 4); -#else /* DMA does not touch them so they can be wherever and we don't need to - waste SRAM on them */ - MCD_relocBuffDesc = MCD_singleBufDescs; -#endif - } - else - { - /* point the would-be relocated task tables and the - buffer descriptors to the ones the linker generated */ - - if (((u32)MCD_realTaskTableSrc & 0x000001ff) != 0) - return(MCD_TABLE_UNALIGNED); - - /* need to add code to make sure that every thing else is aligned properly TBD*/ - /* this is problematic if we init more than once or after running tasks, - need to add variable to see if we have aleady init'd */ - entryPtr = MCD_realTaskTableSrc; - for (i = 0; i < NCHANNELS; i++) - { - if (((entryPtr[i].varTab & (VAR_TAB_SIZE - 1)) != 0) || - ((entryPtr[i].FDTandFlags & (FUNCDESC_TAB_SIZE - 1)) != 0)) - return(MCD_TABLE_UNALIGNED); - } - - MCD_taskTable = MCD_realTaskTableSrc; - MCD_modelTaskTable = MCD_modelTaskTableSrc; - MCD_relocBuffDesc = MCD_singleBufDescs; - } - - - /* Make all channels as totally inactive, and remember them as such: */ - - MCD_dmaBar->taskbar = (u32) MCD_taskTable; - for (i = 0; i < NCHANNELS; i++) - { - MCD_dmaBar->taskControl[i] = 0x0; - MCD_chStatus[i] = MCD_NO_DMA; - } - - /* Set up pausing mechanism to inactive state: */ - MCD_dmaBar->debugComp1 = 0; /* no particular values yet for either comparator registers */ - MCD_dmaBar->debugComp2 = 0; - MCD_dmaBar->debugControl = DBG_CTL_DISABLE; - MCD_dmaBar->debugStatus = DBG_KILL_ALL_STAT; - - /* enable or disable commbus prefetch, really need an ifdef or - something to keep from trying to set this in the 8220 */ - if ((flags & MCD_COMM_PREFETCH_EN) != 0) - MCD_dmaBar->ptdControl &= ~PTD_CTL_COMM_PREFETCH; - else - MCD_dmaBar->ptdControl |= PTD_CTL_COMM_PREFETCH; - - return(MCD_OK); -} - -/* Function: MCD_dmaStatus - * Purpose: Returns the status of the DMA on the requested channel - * Arguments: channel - channel number - * Returns: Predefined status indicators - */ -int MCD_dmaStatus (int channel) -{ - u16 tcrValue; - - if((channel < 0) || (channel >= NCHANNELS)) - return(MCD_CHANNEL_INVALID); - - tcrValue = MCD_dmaBar->taskControl[channel]; - if ((tcrValue & TASK_CTL_EN) == 0) - { /* nothing running */ - /* if last reported with task enabled */ - if ( MCD_chStatus[channel] == MCD_RUNNING - || MCD_chStatus[channel] == MCD_IDLE) - MCD_chStatus[channel] = MCD_DONE; - } - else /* something is running */ - { - /* There are three possibilities: paused, running or idle. */ - if ( MCD_chStatus[channel] == MCD_RUNNING - || MCD_chStatus[channel] == MCD_IDLE) - { - MCD_dmaBar->ptdDebug = PTD_DBG_TSK_VLD_INIT; - /* This register is selected to know which initiator is - actually asserted. */ - if ((MCD_dmaBar->ptdDebug >> channel ) & 0x1 ) - MCD_chStatus[channel] = MCD_RUNNING; - else - MCD_chStatus[channel] = MCD_IDLE; - /* do not change the status if it is already paused. */ - } - } - return MCD_chStatus[channel]; -} - -/* Function: MCD_startDma - * Ppurpose: Starts a particular kind of DMA - * Arguments: see below - * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK - */ - -int MCD_startDma ( - int channel, /* the channel on which to run the DMA */ - s8 *srcAddr, /* the address to move data from, or physical buffer-descriptor address */ - s16 srcIncr, /* the amount to increment the source address per transfer */ - s8 *destAddr, /* the address to move data to */ - s16 destIncr, /* the amount to increment the destination address per transfer */ - u32 dmaSize, /* the number of bytes to transfer independent of the transfer size */ - u32 xferSize, /* the number bytes in of each data movement (1, 2, or 4) */ - u32 initiator, /* what device initiates the DMA */ - int priority, /* priority of the DMA */ - u32 flags, /* flags describing the DMA */ - u32 funcDesc /* a description of byte swapping, bit swapping, and CRC actions */ -#ifdef MCD_NEED_ADDR_TRANS - s8 *srcAddrVirt /* virtual buffer descriptor address TBD*/ -#endif -) -{ - int srcRsdIncr, destRsdIncr; - int *cSave; - short xferSizeIncr; - int tcrCount = 0; -#ifdef MCD_INCLUDE_EU - u32 *realFuncArray; -#endif - - if((channel < 0) || (channel >= NCHANNELS)) - return(MCD_CHANNEL_INVALID); - - /* tbd - need to determine the proper response to a bad funcDesc when not - including EU functions, for now, assign a benign funcDesc, but maybe - should return an error */ -#ifndef MCD_INCLUDE_EU - funcDesc = MCD_FUNC_NOEU1; -#endif - -#ifdef MCD_DEBUG -printf("startDma:Setting up params\n"); -#endif - /* Set us up for task-wise priority. We don't technically need to do this on every start, but - since the register involved is in the same longword as other registers that users are in control - of, setting it more than once is probably preferable. That since the documentation doesn't seem - to be completely consistent about the nature of the PTD control register. */ - MCD_dmaBar->ptdControl |= (u16) 0x8000; -#if 1 /* Not sure what we need to keep here rtm TBD */ - /* Calculate additional parameters to the regular DMA calls. */ - srcRsdIncr = srcIncr < 0 ? -1 : (srcIncr > 0 ? 1 : 0); - destRsdIncr = destIncr < 0 ? -1 : (destIncr > 0 ? 1 : 0); - - xferSizeIncr = (xferSize & 0xffff) | 0x20000000; - - /* Remember for each channel which variant is running. */ - MCD_remVariants.remSrcRsdIncr[channel] = srcRsdIncr; - MCD_remVariants.remDestRsdIncr[channel] = destRsdIncr; - MCD_remVariants.remDestIncr[channel] = destIncr; - MCD_remVariants.remSrcIncr[channel] = srcIncr; - MCD_remVariants.remXferSize[channel] = xferSize; -#endif - - cSave = (int*)(MCD_taskTable[channel].contextSaveSpace) + CSAVE_OFFSET + CURRBD; - -#ifdef MCD_INCLUDE_EU /* may move this to EU specific calls */ - realFuncArray = (u32 *) (MCD_taskTable[channel].FDTandFlags & 0xffffff00); - /* Modify the LURC's normal and byte-residue-loop functions according to parameter. */ - realFuncArray[(LURC*16)] = xferSize == 4 ? - funcDesc : xferSize == 2 ? - funcDesc & 0xfffff00f : funcDesc & 0xffff000f; - realFuncArray[(LURC*16+1)] = (funcDesc & MCD_BYTE_SWAP_KILLER) | MCD_NO_BYTE_SWAP_ATALL; -#endif - /* Write the initiator field in the TCR, and also set the initiator-hold - bit. Note that,due to a hardware quirk, this could collide with an - MDE access to the initiator-register file, so we have to verify that the write - reads back correctly. */ - - MCD_dmaBar->taskControl[channel] = - (initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM; - - while(((MCD_dmaBar->taskControl[channel] & 0x1fff) != - ((initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM)) && - (tcrCount < 1000)) - { - tcrCount++; - /*MCD_dmaBar->ptd_tcr[channel] = (initiator << 8) | 0x0020;*/ - MCD_dmaBar->taskControl[channel] = - (initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM; - } - - MCD_dmaBar->priority[channel] = (u8)priority & PRIORITY_PRI_MASK; - /* should be albe to handle this stuff with only one write to ts reg - tbd */ - if (channel < 8 && channel >= 0) - { - MCD_dmaBar->taskSize0 &= ~(0xf << (7-channel)*4); - MCD_dmaBar->taskSize0 |= (xferSize & 3) << (((7 - channel)*4) + 2); - MCD_dmaBar->taskSize0 |= (xferSize & 3) << ((7 - channel)*4); - } - else - { - MCD_dmaBar->taskSize1 &= ~(0xf << (15-channel)*4); - MCD_dmaBar->taskSize1 |= (xferSize & 3) << (((15 - channel)*4) + 2); - MCD_dmaBar->taskSize1 |= (xferSize & 3) << ((15 - channel)*4); - } - - /* setup task table flags/options which mostly control the line buffers */ - MCD_taskTable[channel].FDTandFlags &= ~MCD_TT_FLAGS_MASK; - MCD_taskTable[channel].FDTandFlags |= (MCD_TT_FLAGS_MASK & flags); - - if (flags & MCD_FECTX_DMA) - { - /* TDTStart and TDTEnd */ - MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_FECTX].TDTstart; - MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_FECTX].TDTend; - MCD_startDmaENetXmit(srcAddr, srcAddr, destAddr, MCD_taskTable, channel); - } - else if (flags & MCD_FECRX_DMA) - { - /* TDTStart and TDTEnd */ - MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_FECRX].TDTstart; - MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_FECRX].TDTend; - MCD_startDmaENetRcv(srcAddr, srcAddr, destAddr, MCD_taskTable, channel); - } - else if(flags & MCD_SINGLE_DMA) - { - /* this buffer descriptor is used for storing off initial parameters for later - progress query calculation and for the DMA to write the resulting checksum - The DMA does not use this to determine how to operate, that info is passed - with the init routine*/ - MCD_relocBuffDesc[channel].srcAddr = srcAddr; - MCD_relocBuffDesc[channel].destAddr = destAddr; - MCD_relocBuffDesc[channel].lastDestAddr = destAddr; /* definitely not its final value */ - MCD_relocBuffDesc[channel].dmaSize = dmaSize; - MCD_relocBuffDesc[channel].flags = 0; /* not used */ - MCD_relocBuffDesc[channel].csumResult = 0; /* not used */ - MCD_relocBuffDesc[channel].next = 0; /* not used */ - - /* Initialize the progress-querying stuff to show no progress:*/ - ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET] = (int)srcAddr; - ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET] = (int)destAddr; - ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DCOUNT + CSAVE_OFFSET] = 0; - ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[CURRBD + CSAVE_OFFSET] = - (u32) &(MCD_relocBuffDesc[channel]); - /* tbd - need to keep the user from trying to call the EU routine - when MCD_INCLUDE_EU is not defined */ - if( funcDesc == MCD_FUNC_NOEU1 || funcDesc == MCD_FUNC_NOEU2) - { - /* TDTStart and TDTEnd */ - MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_SINGLENOEU].TDTstart; - MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_SINGLENOEU].TDTend; - MCD_startDmaSingleNoEu(srcAddr, srcIncr, destAddr, destIncr, dmaSize, - xferSizeIncr, flags, (int *)&(MCD_relocBuffDesc[channel]), cSave, - MCD_taskTable, channel); - } - else - { - /* TDTStart and TDTEnd */ - MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_SINGLEEU].TDTstart; - MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_SINGLEEU].TDTend; - MCD_startDmaSingleEu(srcAddr, srcIncr, destAddr, destIncr, dmaSize, - xferSizeIncr, flags, (int *)&(MCD_relocBuffDesc[channel]), cSave, - MCD_taskTable, channel); - } - } - else - { /* chained DMAS */ - /* Initialize the progress-querying stuff to show no progress:*/ -#if 1 /* (!defined(MCD_NEED_ADDR_TRANS)) */ - ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET] - = (int)((MCD_bufDesc*) srcAddr)->srcAddr; - ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET] - = (int)((MCD_bufDesc*) srcAddr)->destAddr; -#else /* if using address translation, need the virtual addr of the first buffdesc */ - ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET] - = (int)((MCD_bufDesc*) srcAddrVirt)->srcAddr; - ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET] - = (int)((MCD_bufDesc*) srcAddrVirt)->destAddr; -#endif - ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DCOUNT + CSAVE_OFFSET] = 0; - ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[CURRBD + CSAVE_OFFSET] = (u32) srcAddr; - - if( funcDesc == MCD_FUNC_NOEU1 || funcDesc == MCD_FUNC_NOEU2) - { - /*TDTStart and TDTEnd*/ - MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_CHAINNOEU].TDTstart; - MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_CHAINNOEU].TDTend; - MCD_startDmaChainNoEu((int *)srcAddr, srcIncr, destIncr, xferSize, - xferSizeIncr, cSave, MCD_taskTable, channel); - } - else - { - /*TDTStart and TDTEnd*/ - MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_CHAINEU].TDTstart; - MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_CHAINEU].TDTend; - MCD_startDmaChainEu((int *)srcAddr, srcIncr, destIncr, xferSize, - xferSizeIncr, cSave, MCD_taskTable, channel); - } - } - MCD_chStatus[channel] = MCD_IDLE; - return(MCD_OK); -} - -/* Function: MCD_XferProgrQuery - * Purpose: Returns progress of DMA on requested channel - * Arguments: channel - channel to retrieve progress for - * progRep - pointer to user supplied MCD_XferProg struct - * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK - * - * Notes: - * MCD_XferProgrQuery() upon completing or after aborting a DMA, or - * while the DMA is in progress, this function returns the first - * DMA-destination address not (or not yet) used in the DMA. When - * encountering a non-ready buffer descriptor, the information for - * the last completed descriptor is returned. - * - * MCD_XferProgQuery() has to avoid the possibility of getting - * partially-updated information in the event that we should happen - * to query DMA progress just as the DMA is updating it. It does that - * by taking advantage of the fact context is not saved frequently for - * the most part. We therefore read it at least twice until we get the - * same information twice in a row. - * - * Because a small, but not insignificant, amount of time is required - * to write out the progress-query information, especially upon - * completion of the DMA, it would be wise to guarantee some time lag - * between successive readings of the progress-query information. - */ - -/* - * How many iterations of the loop below to execute to stabilize values - */ -#define STABTIME 0 - -int MCD_XferProgrQuery (int channel, MCD_XferProg *progRep) -{ - MCD_XferProg prevRep; - int again; /* true if we are to try again to get consistent results */ - int i; /* used as a time-waste counter */ - int destDiffBytes; /* Total number of bytes that we think actually got xfered. */ - int numIterations; /* number of iterations */ - int bytesNotXfered; /* bytes that did not get xfered. */ - s8 *LWAlignedInitDestAddr, *LWAlignedCurrDestAddr; - int subModVal, addModVal; /* Mode values to added and subtracted from the - final destAddr */ - - if((channel < 0) || (channel >= NCHANNELS)) - return(MCD_CHANNEL_INVALID); - - /* Read a trial value for the progress-reporting values*/ - prevRep.lastSrcAddr = - (s8 *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET]; - prevRep.lastDestAddr = - (s8 *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET]; - prevRep.dmaSize = ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DCOUNT + CSAVE_OFFSET]; - prevRep.currBufDesc = - (MCD_bufDesc*) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[CURRBD + CSAVE_OFFSET]; - /* Repeatedly reread those values until they match previous values: */ - do { - /* Waste a little bit of time to ensure stability: */ - for (i = 0; i < STABTIME; i++) - i += i >> 2; /* make sure this loop does something so that it doesn't get optimized out */ - /* Check them again: */ - progRep->lastSrcAddr = - (s8 *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET]; - progRep->lastDestAddr = - (s8 *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET]; - progRep->dmaSize = ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DCOUNT + CSAVE_OFFSET]; - progRep->currBufDesc = - (MCD_bufDesc*) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[CURRBD + CSAVE_OFFSET]; - /* See if they match: */ - if ( prevRep.lastSrcAddr != progRep->lastSrcAddr - || prevRep.lastDestAddr != progRep->lastDestAddr - || prevRep.dmaSize != progRep->dmaSize - || prevRep.currBufDesc != progRep->currBufDesc) - { - /* If they don't match, remember previous values and try again:*/ - prevRep.lastSrcAddr = progRep->lastSrcAddr; - prevRep.lastDestAddr = progRep->lastDestAddr; - prevRep.dmaSize = progRep->dmaSize; - prevRep.currBufDesc = progRep->currBufDesc; - again = MCD_TRUE; - } - else - again = MCD_FALSE; - } while (again == MCD_TRUE); - - - /* Update the dCount, srcAddr and destAddr */ - /* To calculate dmaCount, we consider destination address. C - overs M1,P1,Z for destination */ - switch(MCD_remVariants.remDestRsdIncr[channel]) { - case MINUS1: - subModVal = ((int)progRep->lastDestAddr) & ((MCD_remVariants.remXferSize[channel]) - 1); - addModVal = ((int)progRep->currBufDesc->destAddr) & ((MCD_remVariants.remXferSize[channel]) - 1); - LWAlignedInitDestAddr = (progRep->currBufDesc->destAddr) - addModVal; - LWAlignedCurrDestAddr = (progRep->lastDestAddr) - subModVal; - destDiffBytes = LWAlignedInitDestAddr - LWAlignedCurrDestAddr; - bytesNotXfered = (destDiffBytes/MCD_remVariants.remDestIncr[channel]) * - ( MCD_remVariants.remDestIncr[channel] - + MCD_remVariants.remXferSize[channel]); - progRep->dmaSize = destDiffBytes - bytesNotXfered + addModVal - subModVal; - break; - case ZERO: - progRep->lastDestAddr = progRep->currBufDesc->destAddr; - break; - case PLUS1: - /* This value has to be subtracted from the final calculated dCount. */ - subModVal = ((int)progRep->currBufDesc->destAddr) & ((MCD_remVariants.remXferSize[channel]) - 1); - /* These bytes are already in lastDestAddr. */ - addModVal = ((int)progRep->lastDestAddr) & ((MCD_remVariants.remXferSize[channel]) - 1); - LWAlignedInitDestAddr = (progRep->currBufDesc->destAddr) - subModVal; - LWAlignedCurrDestAddr = (progRep->lastDestAddr) - addModVal; - destDiffBytes = (progRep->lastDestAddr - LWAlignedInitDestAddr); - numIterations = ( LWAlignedCurrDestAddr - LWAlignedInitDestAddr)/MCD_remVariants.remDestIncr[channel]; - bytesNotXfered = numIterations * - ( MCD_remVariants.remDestIncr[channel] - - MCD_remVariants.remXferSize[channel]); - progRep->dmaSize = destDiffBytes - bytesNotXfered - subModVal; - break; - default: - break; - } - - /* This covers M1,P1,Z for source */ - switch(MCD_remVariants.remSrcRsdIncr[channel]) { - case MINUS1: - progRep->lastSrcAddr = - progRep->currBufDesc->srcAddr + - ( MCD_remVariants.remSrcIncr[channel] * - (progRep->dmaSize/MCD_remVariants.remXferSize[channel])); - break; - case ZERO: - progRep->lastSrcAddr = progRep->currBufDesc->srcAddr; - break; - case PLUS1: - progRep->lastSrcAddr = - progRep->currBufDesc->srcAddr + - ( MCD_remVariants.remSrcIncr[channel] * - (progRep->dmaSize/MCD_remVariants.remXferSize[channel])); - break; - default: break; - } - - return(MCD_OK); -} - -/* MCD_resmActions() does the majority of the actions of a DMA resume. - * It is called from MCD_killDma() and MCD_resumeDma(). It has to be - * a separate function because the kill function has to negate the task - * enable before resuming it, but the resume function has to do nothing - * if there is no DMA on that channel (i.e., if the enable bit is 0). - */ -static void MCD_resmActions (int channel) -{ - MCD_dmaBar->debugControl = DBG_CTL_DISABLE; - MCD_dmaBar->debugStatus = MCD_dmaBar->debugStatus; - MCD_dmaBar->ptdDebug = PTD_DBG_TSK_VLD_INIT; /* This register is selected to know - which initiator is actually asserted. */ - if((MCD_dmaBar->ptdDebug >> channel ) & 0x1) - MCD_chStatus[channel] = MCD_RUNNING; - else - MCD_chStatus[channel] = MCD_IDLE; -} - -/* Function: MCD_killDma - * Purpose: Halt the DMA on the requested channel, without any - * intention of resuming the DMA. - * Arguments: channel - requested channel - * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK - * - * Notes: - * A DMA may be killed from any state, including paused state, and it - * always goes to the MCD_HALTED state even if it is killed while in - * the MCD_NO_DMA or MCD_IDLE states. - */ -int MCD_killDma (int channel) -{ - /* MCD_XferProg progRep; */ - - if((channel < 0) || (channel >= NCHANNELS)) - return(MCD_CHANNEL_INVALID); - - MCD_dmaBar->taskControl[channel] = 0x0; - MCD_resumeDma (channel); - /* - * This must be after the write to the TCR so that the task doesn't - * start up again momentarily, and before the status assignment so - * as to override whatever MCD_resumeDma() may do to the channel - * status. - */ - MCD_chStatus[channel] = MCD_HALTED; - - /* - * Update the current buffer descriptor's lastDestAddr field - * - * MCD_XferProgrQuery (channel, &progRep); - * progRep.currBufDesc->lastDestAddr = progRep.lastDestAddr; - */ - return(MCD_OK); -} - -/* Function: MCD_continDma - * Purpose: Continue a DMA which as stopped due to encountering an - * unready buffer descriptor. - * Arguments: channel - channel to continue the DMA on - * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK - * - * Notes: - * This routine does not check to see if there is a task which can - * be continued. Also this routine should not be used with single DMAs. - */ -int MCD_continDma (int channel) -{ - if((channel < 0) || (channel >= NCHANNELS)) - return(MCD_CHANNEL_INVALID); - - MCD_dmaBar->taskControl[channel] |= TASK_CTL_EN; - MCD_chStatus[channel] = MCD_RUNNING; - - return(MCD_OK); -} - -/* - * MCD_pauseDma() and MCD_resumeDma() below use the DMA's debug unit - * to freeze a task and resume it. We freeze a task by breakpointing - * on the stated task. That is, not any specific place in the task, - * but any time that task executes. In particular, when that task - * executes, we want to freeze that task and only that task. - * - * The bits of the debug control register influence interrupts vs. - * breakpoints as follows: - * - Bits 14 and 0 enable or disable debug functions. If enabled, you - * will get the interrupt but you may or may not get a breakpoint. - * - Bits 2 and 1 decide whether you also get a breakpoint in addition - * to an interrupt. - * - * The debug unit can do these actions in response to either internally - * detected breakpoint conditions from the comparators, or in response - * to the external breakpoint pin, or both. - * - Bits 14 and 1 perform the above-described functions for - * internally-generated conditions, i.e., the debug comparators. - * - Bits 0 and 2 perform the above-described functions for external - * conditions, i.e., the breakpoint external pin. - * - * Note that, although you "always" get the interrupt when you turn - * the debug functions, the interrupt can nevertheless, if desired, be - * masked by the corresponding bit in the PTD's IMR. Note also that - * this means that bits 14 and 0 must enable debug functions before - * bits 1 and 2, respectively, have any effect. - * - * NOTE: It's extremely important to not pause more than one DMA channel - * at a time. - ********************************************************************/ - -/* Function: MCD_pauseDma - * Purpose: Pauses the DMA on a given channel (if any DMA is running - * on that channel). - * Arguments: channel - * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK - */ -int MCD_pauseDma (int channel) -{ - /* MCD_XferProg progRep; */ - - if((channel < 0) || (channel >= NCHANNELS)) - return(MCD_CHANNEL_INVALID); - - if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN) - { - MCD_dmaBar->debugComp1 = channel; - MCD_dmaBar->debugControl = DBG_CTL_ENABLE | (1 << (channel + 16)); - MCD_chStatus[channel] = MCD_PAUSED; - - /* - * Update the current buffer descriptor's lastDestAddr field - * - * MCD_XferProgrQuery (channel, &progRep); - * progRep.currBufDesc->lastDestAddr = progRep.lastDestAddr; - */ - } - return(MCD_OK); -} - -/* Function: MCD_resumeDma - * Purpose: Resumes the DMA on a given channel (if any DMA is - * running on that channel). - * Arguments: channel - channel on which to resume DMA - * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK - */ -int MCD_resumeDma (int channel) -{ - if((channel < 0) || (channel >= NCHANNELS)) - return(MCD_CHANNEL_INVALID); - - if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN) - MCD_resmActions (channel); - - return(MCD_OK); -} - -/* Function: MCD_csumQuery - * Purpose: Provide the checksum after performing a non-chained DMA - * Arguments: channel - channel to report on - * csum - pointer to where to write the checksum/CRC - * Returns: MCD_ERROR if the channel is invalid, else MCD_OK - * - * Notes: - * - */ -int MCD_csumQuery (int channel, u32 *csum) -{ -#ifdef MCD_INCLUDE_EU - if((channel < 0) || (channel >= NCHANNELS)) - return(MCD_CHANNEL_INVALID); - - *csum = MCD_relocBuffDesc[channel].csumResult; - return(MCD_OK); -#else - return(MCD_ERROR); -#endif -} - -/* Function: MCD_getCodeSize - * Purpose: Provide the size requirements of the microcoded tasks - * Returns: Size in bytes - */ -int MCD_getCodeSize(void) -{ -#ifdef MCD_INCLUDE_EU - return(0x2b5c); -#else - return(0x173c); -#endif -} - -/* Function: MCD_getVersion - * Purpose: Provide the version string and number - * Arguments: longVersion - user supplied pointer to a pointer to a char - * which points to the version string - * Returns: Version number and version string (by reference) - */ -char MCD_versionString[] = "Multi-channel DMA API Alpha v0.3 (2004-04-26)"; -#define MCD_REV_MAJOR 0x00 -#define MCD_REV_MINOR 0x03 - -int MCD_getVersion(char **longVersion) -{ - *longVersion = MCD_versionString; - return((MCD_REV_MAJOR << 8) | MCD_REV_MINOR); -} - -/* Private version of memcpy() - * Note that everything this is used for is longword-aligned. - */ -static void MCD_memcpy (int *dest, int *src, u32 size) -{ - u32 i; - - for (i = 0; i < size; i += sizeof(int), dest++, src++) - *dest = *src; -} diff --git a/arch/m68k/mach-mcfv4e/mcdapi/MCD_library.dox b/arch/m68k/mach-mcfv4e/mcdapi/MCD_library.dox deleted file mode 100644 index ec3a730730..0000000000 --- a/arch/m68k/mach-mcfv4e/mcdapi/MCD_library.dox +++ /dev/null @@ -1,10 +0,0 @@ -/** @page mcfv4e_MCDlib MultiChannelDMA library for Coldfire V4e - * - * The MCD library is taken as is from sources publically available from - * FreeScale Semiconductors az http://www.freescale.com - * - * It is slight reformatted and cleaned up, but otherwise unchanged to support - * later merged with updated MCD library releases. - * - * See the PDF document supplied with the library for API documentation - */ diff --git a/arch/m68k/mach-mcfv4e/mcdapi/MCD_tasks.c b/arch/m68k/mach-mcfv4e/mcdapi/MCD_tasks.c deleted file mode 100644 index 812120dd7a..0000000000 --- a/arch/m68k/mach-mcfv4e/mcdapi/MCD_tasks.c +++ /dev/null @@ -1,2449 +0,0 @@ -/* - * File: MCD_tasks.c - * Purpose: Contains task code and structures for Multi-channel DMA - * - * Notes: - */ -#include <asm/types.h> -#include <proc/mcdapi/MCD_dma.h> - -u32 MCD_varTab0[]; -u32 MCD_varTab1[]; -u32 MCD_varTab2[]; -u32 MCD_varTab3[]; -u32 MCD_varTab4[]; -u32 MCD_varTab5[]; -u32 MCD_varTab6[]; -u32 MCD_varTab7[]; -u32 MCD_varTab8[]; -u32 MCD_varTab9[]; -u32 MCD_varTab10[]; -u32 MCD_varTab11[]; -u32 MCD_varTab12[]; -u32 MCD_varTab13[]; -u32 MCD_varTab14[]; -u32 MCD_varTab15[]; - -u32 MCD_funcDescTab0[]; -#ifdef MCD_INCLUDE_EU -u32 MCD_funcDescTab1[]; -u32 MCD_funcDescTab2[]; -u32 MCD_funcDescTab3[]; -u32 MCD_funcDescTab4[]; -u32 MCD_funcDescTab5[]; -u32 MCD_funcDescTab6[]; -u32 MCD_funcDescTab7[]; -u32 MCD_funcDescTab8[]; -u32 MCD_funcDescTab9[]; -u32 MCD_funcDescTab10[]; -u32 MCD_funcDescTab11[]; -u32 MCD_funcDescTab12[]; -u32 MCD_funcDescTab13[]; -u32 MCD_funcDescTab14[]; -u32 MCD_funcDescTab15[]; -#endif - -u32 MCD_contextSave0[]; -u32 MCD_contextSave1[]; -u32 MCD_contextSave2[]; -u32 MCD_contextSave3[]; -u32 MCD_contextSave4[]; -u32 MCD_contextSave5[]; -u32 MCD_contextSave6[]; -u32 MCD_contextSave7[]; -u32 MCD_contextSave8[]; -u32 MCD_contextSave9[]; -u32 MCD_contextSave10[]; -u32 MCD_contextSave11[]; -u32 MCD_contextSave12[]; -u32 MCD_contextSave13[]; -u32 MCD_contextSave14[]; -u32 MCD_contextSave15[]; - -u32 MCD_realTaskTableSrc[] = -{ - 0x00000000, - 0x00000000, - (u32)MCD_varTab0, /* Task 0 Variable Table */ - (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ - 0x00000000, - 0x00000000, - (u32)MCD_contextSave0, /* Task 0 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32)MCD_varTab1, /* Task 1 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32)MCD_funcDescTab1, /* Task 1 Function Descriptor Table & Flags */ -#else - (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32)MCD_contextSave1, /* Task 1 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32)MCD_varTab2, /* Task 2 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32)MCD_funcDescTab2, /* Task 2 Function Descriptor Table & Flags */ -#else - (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32)MCD_contextSave2, /* Task 2 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32)MCD_varTab3, /* Task 3 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32)MCD_funcDescTab3, /* Task 3 Function Descriptor Table & Flags */ -#else - (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32)MCD_contextSave3, /* Task 3 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32)MCD_varTab4, /* Task 4 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32)MCD_funcDescTab4, /* Task 4 Function Descriptor Table & Flags */ -#else - (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32)MCD_contextSave4, /* Task 4 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32)MCD_varTab5, /* Task 5 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32)MCD_funcDescTab5, /* Task 5 Function Descriptor Table & Flags */ -#else - (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32)MCD_contextSave5, /* Task 5 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32)MCD_varTab6, /* Task 6 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32)MCD_funcDescTab6, /* Task 6 Function Descriptor Table & Flags */ -#else - (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32)MCD_contextSave6, /* Task 6 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32)MCD_varTab7, /* Task 7 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32)MCD_funcDescTab7, /* Task 7 Function Descriptor Table & Flags */ -#else - (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32)MCD_contextSave7, /* Task 7 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32)MCD_varTab8, /* Task 8 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32)MCD_funcDescTab8, /* Task 8 Function Descriptor Table & Flags */ -#else - (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32)MCD_contextSave8, /* Task 8 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32)MCD_varTab9, /* Task 9 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32)MCD_funcDescTab9, /* Task 9 Function Descriptor Table & Flags */ -#else - (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32)MCD_contextSave9, /* Task 9 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32)MCD_varTab10, /* Task 10 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32)MCD_funcDescTab10, /* Task 10 Function Descriptor Table & Flags */ -#else - (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32)MCD_contextSave10, /* Task 10 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32)MCD_varTab11, /* Task 11 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32)MCD_funcDescTab11, /* Task 11 Function Descriptor Table & Flags */ -#else - (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32)MCD_contextSave11, /* Task 11 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32)MCD_varTab12, /* Task 12 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32)MCD_funcDescTab12, /* Task 12 Function Descriptor Table & Flags */ -#else - (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32)MCD_contextSave12, /* Task 12 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32)MCD_varTab13, /* Task 13 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32)MCD_funcDescTab13, /* Task 13 Function Descriptor Table & Flags */ -#else - (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32)MCD_contextSave13, /* Task 13 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32)MCD_varTab14, /* Task 14 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32)MCD_funcDescTab14, /* Task 14 Function Descriptor Table & Flags */ -#else - (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32)MCD_contextSave14, /* Task 14 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32)MCD_varTab15, /* Task 15 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32)MCD_funcDescTab15, /* Task 15 Function Descriptor Table & Flags */ -#else - (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32)MCD_contextSave15, /* Task 15 context save space */ - 0x00000000, -}; - - -u32 MCD_varTab0[] = -{ /* Task 0 Variable Table */ - 0x00000000, /* var[0] */ - 0x00000000, /* var[1] */ - 0x00000000, /* var[2] */ - 0x00000000, /* var[3] */ - 0x00000000, /* var[4] */ - 0x00000000, /* var[5] */ - 0x00000000, /* var[6] */ - 0x00000000, /* var[7] */ - 0x00000000, /* var[8] */ - 0x00000000, /* var[9] */ - 0x00000000, /* var[10] */ - 0x00000000, /* var[11] */ - 0x00000000, /* var[12] */ - 0x00000000, /* var[13] */ - 0x00000000, /* var[14] */ - 0x00000000, /* var[15] */ - 0x00000000, /* var[16] */ - 0x00000000, /* var[17] */ - 0x00000000, /* var[18] */ - 0x00000000, /* var[19] */ - 0x00000000, /* var[20] */ - 0x00000000, /* var[21] */ - 0x00000000, /* var[22] */ - 0x00000000, /* var[23] */ - 0xe0000000, /* inc[0] */ - 0x20000000, /* inc[1] */ - 0x2000ffff, /* inc[2] */ - 0x00000000, /* inc[3] */ - 0x00000000, /* inc[4] */ - 0x00000000, /* inc[5] */ - 0x00000000, /* inc[6] */ - 0x00000000, /* inc[7] */ -}; - - -u32 MCD_varTab1[] = -{ /* Task 1 Variable Table */ - 0x00000000, /* var[0] */ - 0x00000000, /* var[1] */ - 0x00000000, /* var[2] */ - 0x00000000, /* var[3] */ - 0x00000000, /* var[4] */ - 0x00000000, /* var[5] */ - 0x00000000, /* var[6] */ - 0x00000000, /* var[7] */ - 0x00000000, /* var[8] */ - 0x00000000, /* var[9] */ - 0x00000000, /* var[10] */ - 0x00000000, /* var[11] */ - 0x00000000, /* var[12] */ - 0x00000000, /* var[13] */ - 0x00000000, /* var[14] */ - 0x00000000, /* var[15] */ - 0x00000000, /* var[16] */ - 0x00000000, /* var[17] */ - 0x00000000, /* var[18] */ - 0x00000000, /* var[19] */ - 0x00000000, /* var[20] */ - 0x00000000, /* var[21] */ - 0x00000000, /* var[22] */ - 0x00000000, /* var[23] */ - 0xe0000000, /* inc[0] */ - 0x20000000, /* inc[1] */ - 0x2000ffff, /* inc[2] */ - 0x00000000, /* inc[3] */ - 0x00000000, /* inc[4] */ - 0x00000000, /* inc[5] */ - 0x00000000, /* inc[6] */ - 0x00000000, /* inc[7] */ -}; - -u32 MCD_varTab2[]= -{ /* Task 2 Variable Table */ - 0x00000000, /* var[0] */ - 0x00000000, /* var[1] */ - 0x00000000, /* var[2] */ - 0x00000000, /* var[3] */ - 0x00000000, /* var[4] */ - 0x00000000, /* var[5] */ - 0x00000000, /* var[6] */ - 0x00000000, /* var[7] */ - 0x00000000, /* var[8] */ - 0x00000000, /* var[9] */ - 0x00000000, /* var[10] */ - 0x00000000, /* var[11] */ - 0x00000000, /* var[12] */ - 0x00000000, /* var[13] */ - 0x00000000, /* var[14] */ - 0x00000000, /* var[15] */ - 0x00000000, /* var[16] */ - 0x00000000, /* var[17] */ - 0x00000000, /* var[18] */ - 0x00000000, /* var[19] */ - 0x00000000, /* var[20] */ - 0x00000000, /* var[21] */ - 0x00000000, /* var[22] */ - 0x00000000, /* var[23] */ - 0xe0000000, /* inc[0] */ - 0x20000000, /* inc[1] */ - 0x2000ffff, /* inc[2] */ - 0x00000000, /* inc[3] */ - 0x00000000, /* inc[4] */ - 0x00000000, /* inc[5] */ - 0x00000000, /* inc[6] */ - 0x00000000, /* inc[7] */ -}; - -u32 MCD_varTab3[]= -{ /* Task 3 Variable Table */ - 0x00000000, /* var[0] */ - 0x00000000, /* var[1] */ - 0x00000000, /* var[2] */ - 0x00000000, /* var[3] */ - 0x00000000, /* var[4] */ - 0x00000000, /* var[5] */ - 0x00000000, /* var[6] */ - 0x00000000, /* var[7] */ - 0x00000000, /* var[8] */ - 0x00000000, /* var[9] */ - 0x00000000, /* var[10] */ - 0x00000000, /* var[11] */ - 0x00000000, /* var[12] */ - 0x00000000, /* var[13] */ - 0x00000000, /* var[14] */ - 0x00000000, /* var[15] */ - 0x00000000, /* var[16] */ - 0x00000000, /* var[17] */ - 0x00000000, /* var[18] */ - 0x00000000, /* var[19] */ - 0x00000000, /* var[20] */ - 0x00000000, /* var[21] */ - 0x00000000, /* var[22] */ - 0x00000000, /* var[23] */ - 0xe0000000, /* inc[0] */ - 0x20000000, /* inc[1] */ - 0x2000ffff, /* inc[2] */ - 0x00000000, /* inc[3] */ - 0x00000000, /* inc[4] */ - 0x00000000, /* inc[5] */ - 0x00000000, /* inc[6] */ - 0x00000000, /* inc[7] */ -}; - -u32 MCD_varTab4[]= -{ /* Task 4 Variable Table */ - 0x00000000, /* var[0] */ - 0x00000000, /* var[1] */ - 0x00000000, /* var[2] */ - 0x00000000, /* var[3] */ - 0x00000000, /* var[4] */ - 0x00000000, /* var[5] */ - 0x00000000, /* var[6] */ - 0x00000000, /* var[7] */ - 0x00000000, /* var[8] */ - 0x00000000, /* var[9] */ - 0x00000000, /* var[10] */ - 0x00000000, /* var[11] */ - 0x00000000, /* var[12] */ - 0x00000000, /* var[13] */ - 0x00000000, /* var[14] */ - 0x00000000, /* var[15] */ - 0x00000000, /* var[16] */ - 0x00000000, /* var[17] */ - 0x00000000, /* var[18] */ - 0x00000000, /* var[19] */ - 0x00000000, /* var[20] */ - 0x00000000, /* var[21] */ - 0x00000000, /* var[22] */ - 0x00000000, /* var[23] */ - 0xe0000000, /* inc[0] */ - 0x20000000, /* inc[1] */ - 0x2000ffff, /* inc[2] */ - 0x00000000, /* inc[3] */ - 0x00000000, /* inc[4] */ - 0x00000000, /* inc[5] */ - 0x00000000, /* inc[6] */ - 0x00000000, /* inc[7] */ -}; - -u32 MCD_varTab5[]= -{ /* Task 5 Variable Table */ - 0x00000000, /* var[0] */ - 0x00000000, /* var[1] */ - 0x00000000, /* var[2] */ - 0x00000000, /* var[3] */ - 0x00000000, /* var[4] */ - 0x00000000, /* var[5] */ - 0x00000000, /* var[6] */ - 0x00000000, /* var[7] */ - 0x00000000, /* var[8] */ - 0x00000000, /* var[9] */ - 0x00000000, /* var[10] */ - 0x00000000, /* var[11] */ - 0x00000000, /* var[12] */ - 0x00000000, /* var[13] */ - 0x00000000, /* var[14] */ - 0x00000000, /* var[15] */ - 0x00000000, /* var[16] */ - 0x00000000, /* var[17] */ - 0x00000000, /* var[18] */ - 0x00000000, /* var[19] */ - 0x00000000, /* var[20] */ - 0x00000000, /* var[21] */ - 0x00000000, /* var[22] */ - 0x00000000, /* var[23] */ - 0xe0000000, /* inc[0] */ - 0x20000000, /* inc[1] */ - 0x2000ffff, /* inc[2] */ - 0x00000000, /* inc[3] */ - 0x00000000, /* inc[4] */ - 0x00000000, /* inc[5] */ - 0x00000000, /* inc[6] */ - 0x00000000, /* inc[7] */ -}; - -u32 MCD_varTab6[]= -{ /* Task 6 Variable Table */ - 0x00000000, /* var[0] */ - 0x00000000, /* var[1] */ - 0x00000000, /* var[2] */ - 0x00000000, /* var[3] */ - 0x00000000, /* var[4] */ - 0x00000000, /* var[5] */ - 0x00000000, /* var[6] */ - 0x00000000, /* var[7] */ - 0x00000000, /* var[8] */ - 0x00000000, /* var[9] */ - 0x00000000, /* var[10] */ - 0x00000000, /* var[11] */ - 0x00000000, /* var[12] */ - 0x00000000, /* var[13] */ - 0x00000000, /* var[14] */ - 0x00000000, /* var[15] */ - 0x00000000, /* var[16] */ - 0x00000000, /* var[17] */ - 0x00000000, /* var[18] */ - 0x00000000, /* var[19] */ - 0x00000000, /* var[20] */ - 0x00000000, /* var[21] */ - 0x00000000, /* var[22] */ - 0x00000000, /* var[23] */ - 0xe0000000, /* inc[0] */ - 0x20000000, /* inc[1] */ - 0x2000ffff, /* inc[2] */ - 0x00000000, /* inc[3] */ - 0x00000000, /* inc[4] */ - 0x00000000, /* inc[5] */ - 0x00000000, /* inc[6] */ - 0x00000000, /* inc[7] */ -}; - -u32 MCD_varTab7[]= -{ /* Task 7 Variable Table */ - 0x00000000, /* var[0] */ - 0x00000000, /* var[1] */ - 0x00000000, /* var[2] */ - 0x00000000, /* var[3] */ - 0x00000000, /* var[4] */ - 0x00000000, /* var[5] */ - 0x00000000, /* var[6] */ - 0x00000000, /* var[7] */ - 0x00000000, /* var[8] */ - 0x00000000, /* var[9] */ - 0x00000000, /* var[10] */ - 0x00000000, /* var[11] */ - 0x00000000, /* var[12] */ - 0x00000000, /* var[13] */ - 0x00000000, /* var[14] */ - 0x00000000, /* var[15] */ - 0x00000000, /* var[16] */ - 0x00000000, /* var[17] */ - 0x00000000, /* var[18] */ - 0x00000000, /* var[19] */ - 0x00000000, /* var[20] */ - 0x00000000, /* var[21] */ - 0x00000000, /* var[22] */ - 0x00000000, /* var[23] */ - 0xe0000000, /* inc[0] */ - 0x20000000, /* inc[1] */ - 0x2000ffff, /* inc[2] */ - 0x00000000, /* inc[3] */ - 0x00000000, /* inc[4] */ - 0x00000000, /* inc[5] */ - 0x00000000, /* inc[6] */ - 0x00000000, /* inc[7] */ -}; - -u32 MCD_varTab8[]= -{ /* Task 8 Variable Table */ - 0x00000000, /* var[0] */ - 0x00000000, /* var[1] */ - 0x00000000, /* var[2] */ - 0x00000000, /* var[3] */ - 0x00000000, /* var[4] */ - 0x00000000, /* var[5] */ - 0x00000000, /* var[6] */ - 0x00000000, /* var[7] */ - 0x00000000, /* var[8] */ - 0x00000000, /* var[9] */ - 0x00000000, /* var[10] */ - 0x00000000, /* var[11] */ - 0x00000000, /* var[12] */ - 0x00000000, /* var[13] */ - 0x00000000, /* var[14] */ - 0x00000000, /* var[15] */ - 0x00000000, /* var[16] */ - 0x00000000, /* var[17] */ - 0x00000000, /* var[18] */ - 0x00000000, /* var[19] */ - 0x00000000, /* var[20] */ - 0x00000000, /* var[21] */ - 0x00000000, /* var[22] */ - 0x00000000, /* var[23] */ - 0xe0000000, /* inc[0] */ - 0x20000000, /* inc[1] */ - 0x2000ffff, /* inc[2] */ - 0x00000000, /* inc[3] */ - 0x00000000, /* inc[4] */ - 0x00000000, /* inc[5] */ - 0x00000000, /* inc[6] */ - 0x00000000, /* inc[7] */ -}; - -u32 MCD_varTab9[]= -{ /* Task 9 Variable Table */ - 0x00000000, /* var[0] */ - 0x00000000, /* var[1] */ - 0x00000000, /* var[2] */ - 0x00000000, /* var[3] */ - 0x00000000, /* var[4] */ - 0x00000000, /* var[5] */ - 0x00000000, /* var[6] */ - 0x00000000, /* var[7] */ - 0x00000000, /* var[8] */ - 0x00000000, /* var[9] */ - 0x00000000, /* var[10] */ - 0x00000000, /* var[11] */ - 0x00000000, /* var[12] */ - 0x00000000, /* var[13] */ - 0x00000000, /* var[14] */ - 0x00000000, /* var[15] */ - 0x00000000, /* var[16] */ - 0x00000000, /* var[17] */ - 0x00000000, /* var[18] */ - 0x00000000, /* var[19] */ - 0x00000000, /* var[20] */ - 0x00000000, /* var[21] */ - 0x00000000, /* var[22] */ - 0x00000000, /* var[23] */ - 0xe0000000, /* inc[0] */ - 0x20000000, /* inc[1] */ - 0x2000ffff, /* inc[2] */ - 0x00000000, /* inc[3] */ - 0x00000000, /* inc[4] */ - 0x00000000, /* inc[5] */ - 0x00000000, /* inc[6] */ - 0x00000000, /* inc[7] */ -}; - -u32 MCD_varTab10[]= -{ /* Task 10 Variable Table */ - 0x00000000, /* var[0] */ - 0x00000000, /* var[1] */ - 0x00000000, /* var[2] */ - 0x00000000, /* var[3] */ - 0x00000000, /* var[4] */ - 0x00000000, /* var[5] */ - 0x00000000, /* var[6] */ - 0x00000000, /* var[7] */ - 0x00000000, /* var[8] */ - 0x00000000, /* var[9] */ - 0x00000000, /* var[10] */ - 0x00000000, /* var[11] */ - 0x00000000, /* var[12] */ - 0x00000000, /* var[13] */ - 0x00000000, /* var[14] */ - 0x00000000, /* var[15] */ - 0x00000000, /* var[16] */ - 0x00000000, /* var[17] */ - 0x00000000, /* var[18] */ - 0x00000000, /* var[19] */ - 0x00000000, /* var[20] */ - 0x00000000, /* var[21] */ - 0x00000000, /* var[22] */ - 0x00000000, /* var[23] */ - 0xe0000000, /* inc[0] */ - 0x20000000, /* inc[1] */ - 0x2000ffff, /* inc[2] */ - 0x00000000, /* inc[3] */ - 0x00000000, /* inc[4] */ - 0x00000000, /* inc[5] */ - 0x00000000, /* inc[6] */ - 0x00000000, /* inc[7] */ -}; - -u32 MCD_varTab11[]= -{ /* Task 11 Variable Table */ - 0x00000000, /* var[0] */ - 0x00000000, /* var[1] */ - 0x00000000, /* var[2] */ - 0x00000000, /* var[3] */ - 0x00000000, /* var[4] */ - 0x00000000, /* var[5] */ - 0x00000000, /* var[6] */ - 0x00000000, /* var[7] */ - 0x00000000, /* var[8] */ - 0x00000000, /* var[9] */ - 0x00000000, /* var[10] */ - 0x00000000, /* var[11] */ - 0x00000000, /* var[12] */ - 0x00000000, /* var[13] */ - 0x00000000, /* var[14] */ - 0x00000000, /* var[15] */ - 0x00000000, /* var[16] */ - 0x00000000, /* var[17] */ - 0x00000000, /* var[18] */ - 0x00000000, /* var[19] */ - 0x00000000, /* var[20] */ - 0x00000000, /* var[21] */ - 0x00000000, /* var[22] */ - 0x00000000, /* var[23] */ - 0xe0000000, /* inc[0] */ - 0x20000000, /* inc[1] */ - 0x2000ffff, /* inc[2] */ - 0x00000000, /* inc[3] */ - 0x00000000, /* inc[4] */ - 0x00000000, /* inc[5] */ - 0x00000000, /* inc[6] */ - 0x00000000, /* inc[7] */ -}; - -u32 MCD_varTab12[]= -{ /* Task 12 Variable Table */ - 0x00000000, /* var[0] */ - 0x00000000, /* var[1] */ - 0x00000000, /* var[2] */ - 0x00000000, /* var[3] */ - 0x00000000, /* var[4] */ - 0x00000000, /* var[5] */ - 0x00000000, /* var[6] */ - 0x00000000, /* var[7] */ - 0x00000000, /* var[8] */ - 0x00000000, /* var[9] */ - 0x00000000, /* var[10] */ - 0x00000000, /* var[11] */ - 0x00000000, /* var[12] */ - 0x00000000, /* var[13] */ - 0x00000000, /* var[14] */ - 0x00000000, /* var[15] */ - 0x00000000, /* var[16] */ - 0x00000000, /* var[17] */ - 0x00000000, /* var[18] */ - 0x00000000, /* var[19] */ - 0x00000000, /* var[20] */ - 0x00000000, /* var[21] */ - 0x00000000, /* var[22] */ - 0x00000000, /* var[23] */ - 0xe0000000, /* inc[0] */ - 0x20000000, /* inc[1] */ - 0x2000ffff, /* inc[2] */ - 0x00000000, /* inc[3] */ - 0x00000000, /* inc[4] */ - 0x00000000, /* inc[5] */ - 0x00000000, /* inc[6] */ - 0x00000000, /* inc[7] */ -}; - -u32 MCD_varTab13[]= -{ /* Task 13 Variable Table */ - 0x00000000, /* var[0] */ - 0x00000000, /* var[1] */ - 0x00000000, /* var[2] */ - 0x00000000, /* var[3] */ - 0x00000000, /* var[4] */ - 0x00000000, /* var[5] */ - 0x00000000, /* var[6] */ - 0x00000000, /* var[7] */ - 0x00000000, /* var[8] */ - 0x00000000, /* var[9] */ - 0x00000000, /* var[10] */ - 0x00000000, /* var[11] */ - 0x00000000, /* var[12] */ - 0x00000000, /* var[13] */ - 0x00000000, /* var[14] */ - 0x00000000, /* var[15] */ - 0x00000000, /* var[16] */ - 0x00000000, /* var[17] */ - 0x00000000, /* var[18] */ - 0x00000000, /* var[19] */ - 0x00000000, /* var[20] */ - 0x00000000, /* var[21] */ - 0x00000000, /* var[22] */ - 0x00000000, /* var[23] */ - 0xe0000000, /* inc[0] */ - 0x20000000, /* inc[1] */ - 0x2000ffff, /* inc[2] */ - 0x00000000, /* inc[3] */ - 0x00000000, /* inc[4] */ - 0x00000000, /* inc[5] */ - 0x00000000, /* inc[6] */ - 0x00000000, /* inc[7] */ -}; - -u32 MCD_varTab14[]= -{ /* Task 14 Variable Table */ - 0x00000000, /* var[0] */ - 0x00000000, /* var[1] */ - 0x00000000, /* var[2] */ - 0x00000000, /* var[3] */ - 0x00000000, /* var[4] */ - 0x00000000, /* var[5] */ - 0x00000000, /* var[6] */ - 0x00000000, /* var[7] */ - 0x00000000, /* var[8] */ - 0x00000000, /* var[9] */ - 0x00000000, /* var[10] */ - 0x00000000, /* var[11] */ - 0x00000000, /* var[12] */ - 0x00000000, /* var[13] */ - 0x00000000, /* var[14] */ - 0x00000000, /* var[15] */ - 0x00000000, /* var[16] */ - 0x00000000, /* var[17] */ - 0x00000000, /* var[18] */ - 0x00000000, /* var[19] */ - 0x00000000, /* var[20] */ - 0x00000000, /* var[21] */ - 0x00000000, /* var[22] */ - 0x00000000, /* var[23] */ - 0xe0000000, /* inc[0] */ - 0x20000000, /* inc[1] */ - 0x2000ffff, /* inc[2] */ - 0x00000000, /* inc[3] */ - 0x00000000, /* inc[4] */ - 0x00000000, /* inc[5] */ - 0x00000000, /* inc[6] */ - 0x00000000, /* inc[7] */ -}; - -u32 MCD_varTab15[]= -{ /* Task 15 Variable Table */ - 0x00000000, /* var[0] */ - 0x00000000, /* var[1] */ - 0x00000000, /* var[2] */ - 0x00000000, /* var[3] */ - 0x00000000, /* var[4] */ - 0x00000000, /* var[5] */ - 0x00000000, /* var[6] */ - 0x00000000, /* var[7] */ - 0x00000000, /* var[8] */ - 0x00000000, /* var[9] */ - 0x00000000, /* var[10] */ - 0x00000000, /* var[11] */ - 0x00000000, /* var[12] */ - 0x00000000, /* var[13] */ - 0x00000000, /* var[14] */ - 0x00000000, /* var[15] */ - 0x00000000, /* var[16] */ - 0x00000000, /* var[17] */ - 0x00000000, /* var[18] */ - 0x00000000, /* var[19] */ - 0x00000000, /* var[20] */ - 0x00000000, /* var[21] */ - 0x00000000, /* var[22] */ - 0x00000000, /* var[23] */ - 0xe0000000, /* inc[0] */ - 0x20000000, /* inc[1] */ - 0x2000ffff, /* inc[2] */ - 0x00000000, /* inc[3] */ - 0x00000000, /* inc[4] */ - 0x00000000, /* inc[5] */ - 0x00000000, /* inc[6] */ - 0x00000000, /* inc[7] */ -}; - -u32 MCD_funcDescTab0[]= -{ /* Task 0 Function Descriptor Table */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, /* mainFunc(), EU# 3 */ - 0xa0000000, /* rsduFunc(), EU# 3 */ - 0xa0000000, /* crcAccumVal(), EU# 3 */ - 0x20000000, /* setCrcAccum(), EU# 3 */ - 0x21800000, /* and(), EU# 3 */ - 0x21e00000, /* or(), EU# 3 */ - 0x20400000, /* add(), EU# 3 */ - 0x20500000, /* sub(), EU# 3 */ - 0x205a0000, /* andNot(), EU# 3 */ - 0x20a00000, /* shiftR(), EU# 3 */ - 0x202fa000, /* andReadyBit(), EU# 3 */ - 0x202f9000, /* andNotReadyBit(), EU# 3 */ - 0x202ea000, /* andWrapBit(), EU# 3 */ - 0x202da000, /* andLastBit(), EU# 3 */ - 0x202e2000, /* andInterruptBit(), EU# 3 */ - 0x202f2000, /* andCrcRestartBit(), EU# 3 */ -}; - -#ifdef MCD_INCLUDE_EU -u32 MCD_funcDescTab1[]= -{ /* Task 1 Function Descriptor Table */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, /* mainFunc(), EU# 3 */ - 0xa0000000, /* rsduFunc(), EU# 3 */ - 0xa0000000, /* crcAccumVal(), EU# 3 */ - 0x20000000, /* setCrcAccum(), EU# 3 */ - 0x21800000, /* and(), EU# 3 */ - 0x21e00000, /* or(), EU# 3 */ - 0x20400000, /* add(), EU# 3 */ - 0x20500000, /* sub(), EU# 3 */ - 0x205a0000, /* andNot(), EU# 3 */ - 0x20a00000, /* shiftR(), EU# 3 */ - 0x202fa000, /* andReadyBit(), EU# 3 */ - 0x202f9000, /* andNotReadyBit(), EU# 3 */ - 0x202ea000, /* andWrapBit(), EU# 3 */ - 0x202da000, /* andLastBit(), EU# 3 */ - 0x202e2000, /* andInterruptBit(), EU# 3 */ - 0x202f2000, /* andCrcRestartBit(), EU# 3 */ -}; - -u32 MCD_funcDescTab2[]= -{ /* Task 2 Function Descriptor Table */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, /* mainFunc(), EU# 3 */ - 0xa0000000, /* rsduFunc(), EU# 3 */ - 0xa0000000, /* crcAccumVal(), EU# 3 */ - 0x20000000, /* setCrcAccum(), EU# 3 */ - 0x21800000, /* and(), EU# 3 */ - 0x21e00000, /* or(), EU# 3 */ - 0x20400000, /* add(), EU# 3 */ - 0x20500000, /* sub(), EU# 3 */ - 0x205a0000, /* andNot(), EU# 3 */ - 0x20a00000, /* shiftR(), EU# 3 */ - 0x202fa000, /* andReadyBit(), EU# 3 */ - 0x202f9000, /* andNotReadyBit(), EU# 3 */ - 0x202ea000, /* andWrapBit(), EU# 3 */ - 0x202da000, /* andLastBit(), EU# 3 */ - 0x202e2000, /* andInterruptBit(), EU# 3 */ - 0x202f2000, /* andCrcRestartBit(), EU# 3 */ -}; - -u32 MCD_funcDescTab3[]= -{ /* Task 3 Function Descriptor Table */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, /* mainFunc(), EU# 3 */ - 0xa0000000, /* rsduFunc(), EU# 3 */ - 0xa0000000, /* crcAccumVal(), EU# 3 */ - 0x20000000, /* setCrcAccum(), EU# 3 */ - 0x21800000, /* and(), EU# 3 */ - 0x21e00000, /* or(), EU# 3 */ - 0x20400000, /* add(), EU# 3 */ - 0x20500000, /* sub(), EU# 3 */ - 0x205a0000, /* andNot(), EU# 3 */ - 0x20a00000, /* shiftR(), EU# 3 */ - 0x202fa000, /* andReadyBit(), EU# 3 */ - 0x202f9000, /* andNotReadyBit(), EU# 3 */ - 0x202ea000, /* andWrapBit(), EU# 3 */ - 0x202da000, /* andLastBit(), EU# 3 */ - 0x202e2000, /* andInterruptBit(), EU# 3 */ - 0x202f2000, /* andCrcRestartBit(), EU# 3 */ -}; - -u32 MCD_funcDescTab4[]= -{ /* Task 4 Function Descriptor Table */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, /* mainFunc(), EU# 3 */ - 0xa0000000, /* rsduFunc(), EU# 3 */ - 0xa0000000, /* crcAccumVal(), EU# 3 */ - 0x20000000, /* setCrcAccum(), EU# 3 */ - 0x21800000, /* and(), EU# 3 */ - 0x21e00000, /* or(), EU# 3 */ - 0x20400000, /* add(), EU# 3 */ - 0x20500000, /* sub(), EU# 3 */ - 0x205a0000, /* andNot(), EU# 3 */ - 0x20a00000, /* shiftR(), EU# 3 */ - 0x202fa000, /* andReadyBit(), EU# 3 */ - 0x202f9000, /* andNotReadyBit(), EU# 3 */ - 0x202ea000, /* andWrapBit(), EU# 3 */ - 0x202da000, /* andLastBit(), EU# 3 */ - 0x202e2000, /* andInterruptBit(), EU# 3 */ - 0x202f2000, /* andCrcRestartBit(), EU# 3 */ -}; - -u32 MCD_funcDescTab5[]= -{ /* Task 5 Function Descriptor Table */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, /* mainFunc(), EU# 3 */ - 0xa0000000, /* rsduFunc(), EU# 3 */ - 0xa0000000, /* crcAccumVal(), EU# 3 */ - 0x20000000, /* setCrcAccum(), EU# 3 */ - 0x21800000, /* and(), EU# 3 */ - 0x21e00000, /* or(), EU# 3 */ - 0x20400000, /* add(), EU# 3 */ - 0x20500000, /* sub(), EU# 3 */ - 0x205a0000, /* andNot(), EU# 3 */ - 0x20a00000, /* shiftR(), EU# 3 */ - 0x202fa000, /* andReadyBit(), EU# 3 */ - 0x202f9000, /* andNotReadyBit(), EU# 3 */ - 0x202ea000, /* andWrapBit(), EU# 3 */ - 0x202da000, /* andLastBit(), EU# 3 */ - 0x202e2000, /* andInterruptBit(), EU# 3 */ - 0x202f2000, /* andCrcRestartBit(), EU# 3 */ -}; - -u32 MCD_funcDescTab6[]= -{ /* Task 6 Function Descriptor Table */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, /* mainFunc(), EU# 3 */ - 0xa0000000, /* rsduFunc(), EU# 3 */ - 0xa0000000, /* crcAccumVal(), EU# 3 */ - 0x20000000, /* setCrcAccum(), EU# 3 */ - 0x21800000, /* and(), EU# 3 */ - 0x21e00000, /* or(), EU# 3 */ - 0x20400000, /* add(), EU# 3 */ - 0x20500000, /* sub(), EU# 3 */ - 0x205a0000, /* andNot(), EU# 3 */ - 0x20a00000, /* shiftR(), EU# 3 */ - 0x202fa000, /* andReadyBit(), EU# 3 */ - 0x202f9000, /* andNotReadyBit(), EU# 3 */ - 0x202ea000, /* andWrapBit(), EU# 3 */ - 0x202da000, /* andLastBit(), EU# 3 */ - 0x202e2000, /* andInterruptBit(), EU# 3 */ - 0x202f2000, /* andCrcRestartBit(), EU# 3 */ -}; - -u32 MCD_funcDescTab7[]= -{ /* Task 7 Function Descriptor Table */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, /* mainFunc(), EU# 3 */ - 0xa0000000, /* rsduFunc(), EU# 3 */ - 0xa0000000, /* crcAccumVal(), EU# 3 */ - 0x20000000, /* setCrcAccum(), EU# 3 */ - 0x21800000, /* and(), EU# 3 */ - 0x21e00000, /* or(), EU# 3 */ - 0x20400000, /* add(), EU# 3 */ - 0x20500000, /* sub(), EU# 3 */ - 0x205a0000, /* andNot(), EU# 3 */ - 0x20a00000, /* shiftR(), EU# 3 */ - 0x202fa000, /* andReadyBit(), EU# 3 */ - 0x202f9000, /* andNotReadyBit(), EU# 3 */ - 0x202ea000, /* andWrapBit(), EU# 3 */ - 0x202da000, /* andLastBit(), EU# 3 */ - 0x202e2000, /* andInterruptBit(), EU# 3 */ - 0x202f2000, /* andCrcRestartBit(), EU# 3 */ -}; - -u32 MCD_funcDescTab8[]= -{ /* Task 8 Function Descriptor Table */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, /* mainFunc(), EU# 3 */ - 0xa0000000, /* rsduFunc(), EU# 3 */ - 0xa0000000, /* crcAccumVal(), EU# 3 */ - 0x20000000, /* setCrcAccum(), EU# 3 */ - 0x21800000, /* and(), EU# 3 */ - 0x21e00000, /* or(), EU# 3 */ - 0x20400000, /* add(), EU# 3 */ - 0x20500000, /* sub(), EU# 3 */ - 0x205a0000, /* andNot(), EU# 3 */ - 0x20a00000, /* shiftR(), EU# 3 */ - 0x202fa000, /* andReadyBit(), EU# 3 */ - 0x202f9000, /* andNotReadyBit(), EU# 3 */ - 0x202ea000, /* andWrapBit(), EU# 3 */ - 0x202da000, /* andLastBit(), EU# 3 */ - 0x202e2000, /* andInterruptBit(), EU# 3 */ - 0x202f2000, /* andCrcRestartBit(), EU# 3 */ -}; - -u32 MCD_funcDescTab9[]= -{ /* Task 9 Function Descriptor Table */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, /* mainFunc(), EU# 3 */ - 0xa0000000, /* rsduFunc(), EU# 3 */ - 0xa0000000, /* crcAccumVal(), EU# 3 */ - 0x20000000, /* setCrcAccum(), EU# 3 */ - 0x21800000, /* and(), EU# 3 */ - 0x21e00000, /* or(), EU# 3 */ - 0x20400000, /* add(), EU# 3 */ - 0x20500000, /* sub(), EU# 3 */ - 0x205a0000, /* andNot(), EU# 3 */ - 0x20a00000, /* shiftR(), EU# 3 */ - 0x202fa000, /* andReadyBit(), EU# 3 */ - 0x202f9000, /* andNotReadyBit(), EU# 3 */ - 0x202ea000, /* andWrapBit(), EU# 3 */ - 0x202da000, /* andLastBit(), EU# 3 */ - 0x202e2000, /* andInterruptBit(), EU# 3 */ - 0x202f2000, /* andCrcRestartBit(), EU# 3 */ -}; - -u32 MCD_funcDescTab10[]= -{ /* Task 10 Function Descriptor Table */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, /* mainFunc(), EU# 3 */ - 0xa0000000, /* rsduFunc(), EU# 3 */ - 0xa0000000, /* crcAccumVal(), EU# 3 */ - 0x20000000, /* setCrcAccum(), EU# 3 */ - 0x21800000, /* and(), EU# 3 */ - 0x21e00000, /* or(), EU# 3 */ - 0x20400000, /* add(), EU# 3 */ - 0x20500000, /* sub(), EU# 3 */ - 0x205a0000, /* andNot(), EU# 3 */ - 0x20a00000, /* shiftR(), EU# 3 */ - 0x202fa000, /* andReadyBit(), EU# 3 */ - 0x202f9000, /* andNotReadyBit(), EU# 3 */ - 0x202ea000, /* andWrapBit(), EU# 3 */ - 0x202da000, /* andLastBit(), EU# 3 */ - 0x202e2000, /* andInterruptBit(), EU# 3 */ - 0x202f2000, /* andCrcRestartBit(), EU# 3 */ -}; - -u32 MCD_funcDescTab11[]= -{ /* Task 11 Function Descriptor Table */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, /* mainFunc(), EU# 3 */ - 0xa0000000, /* rsduFunc(), EU# 3 */ - 0xa0000000, /* crcAccumVal(), EU# 3 */ - 0x20000000, /* setCrcAccum(), EU# 3 */ - 0x21800000, /* and(), EU# 3 */ - 0x21e00000, /* or(), EU# 3 */ - 0x20400000, /* add(), EU# 3 */ - 0x20500000, /* sub(), EU# 3 */ - 0x205a0000, /* andNot(), EU# 3 */ - 0x20a00000, /* shiftR(), EU# 3 */ - 0x202fa000, /* andReadyBit(), EU# 3 */ - 0x202f9000, /* andNotReadyBit(), EU# 3 */ - 0x202ea000, /* andWrapBit(), EU# 3 */ - 0x202da000, /* andLastBit(), EU# 3 */ - 0x202e2000, /* andInterruptBit(), EU# 3 */ - 0x202f2000, /* andCrcRestartBit(), EU# 3 */ -}; - -u32 MCD_funcDescTab12[]= -{ /* Task 12 Function Descriptor Table */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, /* mainFunc(), EU# 3 */ - 0xa0000000, /* rsduFunc(), EU# 3 */ - 0xa0000000, /* crcAccumVal(), EU# 3 */ - 0x20000000, /* setCrcAccum(), EU# 3 */ - 0x21800000, /* and(), EU# 3 */ - 0x21e00000, /* or(), EU# 3 */ - 0x20400000, /* add(), EU# 3 */ - 0x20500000, /* sub(), EU# 3 */ - 0x205a0000, /* andNot(), EU# 3 */ - 0x20a00000, /* shiftR(), EU# 3 */ - 0x202fa000, /* andReadyBit(), EU# 3 */ - 0x202f9000, /* andNotReadyBit(), EU# 3 */ - 0x202ea000, /* andWrapBit(), EU# 3 */ - 0x202da000, /* andLastBit(), EU# 3 */ - 0x202e2000, /* andInterruptBit(), EU# 3 */ - 0x202f2000, /* andCrcRestartBit(), EU# 3 */ -}; - -u32 MCD_funcDescTab13[]= -{ /* Task 13 Function Descriptor Table */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, /* mainFunc(), EU# 3 */ - 0xa0000000, /* rsduFunc(), EU# 3 */ - 0xa0000000, /* crcAccumVal(), EU# 3 */ - 0x20000000, /* setCrcAccum(), EU# 3 */ - 0x21800000, /* and(), EU# 3 */ - 0x21e00000, /* or(), EU# 3 */ - 0x20400000, /* add(), EU# 3 */ - 0x20500000, /* sub(), EU# 3 */ - 0x205a0000, /* andNot(), EU# 3 */ - 0x20a00000, /* shiftR(), EU# 3 */ - 0x202fa000, /* andReadyBit(), EU# 3 */ - 0x202f9000, /* andNotReadyBit(), EU# 3 */ - 0x202ea000, /* andWrapBit(), EU# 3 */ - 0x202da000, /* andLastBit(), EU# 3 */ - 0x202e2000, /* andInterruptBit(), EU# 3 */ - 0x202f2000, /* andCrcRestartBit(), EU# 3 */ -}; - -u32 MCD_funcDescTab14[]= -{ /* Task 14 Function Descriptor Table */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, /* mainFunc(), EU# 3 */ - 0xa0000000, /* rsduFunc(), EU# 3 */ - 0xa0000000, /* crcAccumVal(), EU# 3 */ - 0x20000000, /* setCrcAccum(), EU# 3 */ - 0x21800000, /* and(), EU# 3 */ - 0x21e00000, /* or(), EU# 3 */ - 0x20400000, /* add(), EU# 3 */ - 0x20500000, /* sub(), EU# 3 */ - 0x205a0000, /* andNot(), EU# 3 */ - 0x20a00000, /* shiftR(), EU# 3 */ - 0x202fa000, /* andReadyBit(), EU# 3 */ - 0x202f9000, /* andNotReadyBit(), EU# 3 */ - 0x202ea000, /* andWrapBit(), EU# 3 */ - 0x202da000, /* andLastBit(), EU# 3 */ - 0x202e2000, /* andInterruptBit(), EU# 3 */ - 0x202f2000, /* andCrcRestartBit(), EU# 3 */ -}; - -u32 MCD_funcDescTab15[]= -{ /* Task 15 Function Descriptor Table */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, /* mainFunc(), EU# 3 */ - 0xa0000000, /* rsduFunc(), EU# 3 */ - 0xa0000000, /* crcAccumVal(), EU# 3 */ - 0x20000000, /* setCrcAccum(), EU# 3 */ - 0x21800000, /* and(), EU# 3 */ - 0x21e00000, /* or(), EU# 3 */ - 0x20400000, /* add(), EU# 3 */ - 0x20500000, /* sub(), EU# 3 */ - 0x205a0000, /* andNot(), EU# 3 */ - 0x20a00000, /* shiftR(), EU# 3 */ - 0x202fa000, /* andReadyBit(), EU# 3 */ - 0x202f9000, /* andNotReadyBit(), EU# 3 */ - 0x202ea000, /* andWrapBit(), EU# 3 */ - 0x202da000, /* andLastBit(), EU# 3 */ - 0x202e2000, /* andInterruptBit(), EU# 3 */ - 0x202f2000, /* andCrcRestartBit(), EU# 3 */ -}; -#endif /*MCD_INCLUDE_EU*/ - -u32 MCD_contextSave0[128]; /* Task 0 context save space */ -u32 MCD_contextSave1[128]; /* Task 1 context save space */ -u32 MCD_contextSave2[128]; /* Task 2 context save space */ -u32 MCD_contextSave3[128]; /* Task 3 context save space */ -u32 MCD_contextSave4[128]; /* Task 4 context save space */ -u32 MCD_contextSave5[128]; /* Task 5 context save space */ -u32 MCD_contextSave6[128]; /* Task 6 context save space */ -u32 MCD_contextSave7[128]; /* Task 7 context save space */ -u32 MCD_contextSave8[128]; /* Task 8 context save space */ -u32 MCD_contextSave9[128]; /* Task 9 context save space */ -u32 MCD_contextSave10[128]; /* Task 10 context save space */ -u32 MCD_contextSave11[128]; /* Task 11 context save space */ -u32 MCD_contextSave12[128]; /* Task 12 context save space */ -u32 MCD_contextSave13[128]; /* Task 13 context save space */ -u32 MCD_contextSave14[128]; /* Task 14 context save space */ -u32 MCD_contextSave15[128]; /* Task 15 context save space */ - - -u32 MCD_ChainNoEu_TDT[]; -u32 MCD_SingleNoEu_TDT[]; -#ifdef MCD_INCLUDE_EU -u32 MCD_ChainEu_TDT[]; -u32 MCD_SingleEu_TDT[]; -#endif -u32 MCD_ENetRcv_TDT[]; -u32 MCD_ENetXmit_TDT[]; - -u32 MCD_modelTaskTableSrc[]= -{ - (u32)MCD_ChainNoEu_TDT, - (u32)&((u8*)MCD_ChainNoEu_TDT)[0x0000016c], - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - (u32)MCD_SingleNoEu_TDT, - (u32)&((u8*)MCD_SingleNoEu_TDT)[0x000000d4], - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -#ifdef MCD_INCLUDE_EU - (u32)MCD_ChainEu_TDT, - (u32)&((u8*)MCD_ChainEu_TDT)[0x000001b4], - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - (u32)MCD_SingleEu_TDT, - (u32)&((u8*)MCD_SingleEu_TDT)[0x00000124], - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -#endif - (u32)MCD_ENetRcv_TDT, - (u32)&((u8*)MCD_ENetRcv_TDT)[0x0000009c], - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - (u32)MCD_ENetXmit_TDT, - (u32)&((u8*)MCD_ENetXmit_TDT)[0x000000d0], - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; -u32 MCD_ChainNoEu_TDT[]= -{ - 0x80004000, /* 0000(:370): LCDEXT: idx0 = 0x00000000; ; */ - 0x8118801b, /* 0004(:370): LCD: idx1 = var2; idx1 once var0; idx1 += inc3 */ - 0xb8c60018, /* 0008(:371): LCD: idx2 = *(idx1 + var12); idx2 once var0; idx2 += inc3 */ - 0x10002b10, /* 000C(:372): DRD1A: var10 = idx2; FN=0 MORE init=0 WS=0 RS=0 */ - 0x7000000d, /* 0010(:373): DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT MORE init=0 WS=0 RS=0 */ - 0x018cf89f, /* 0014(:373): DRD2B1: var6 = EU3(); EU3(idx2) */ - 0x6000000a, /* 0018(:374): DRD2A: EU0=0 EU1=0 EU2=0 EU3=10 EXT init=0 WS=0 RS=0 */ - 0x080cf89f, /* 001C(:374): DRD2B1: idx0 = EU3(); EU3(idx2) */ - 0x000001f8, /* 0020(:0): NOP */ - 0x98180364, /* 0024(:378): LCD: idx0 = idx0; idx0 == var13; idx0 += inc4 */ - 0x8118801b, /* 0028(:380): LCD: idx1 = var2; idx1 once var0; idx1 += inc3 */ - 0xf8c6001a, /* 002C(:381): LCDEXT: idx2 = *(idx1 + var12 + 8); idx2 once var0; idx2 += inc3 */ - 0xb8c6601b, /* 0030(:382): LCD: idx3 = *(idx1 + var12 + 12); ; idx3 += inc3 */ - 0x10002710, /* 0034(:384): DRD1A: var9 = idx2; FN=0 MORE init=0 WS=0 RS=0 */ - 0x00000f18, /* 0038(:385): DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */ - 0xb8c6001d, /* 003C(:387): LCD: idx2 = *(idx1 + var12 + 20); idx2 once var0; idx2 += inc3 */ - 0x10001310, /* 0040(:388): DRD1A: var4 = idx2; FN=0 MORE init=0 WS=0 RS=0 */ - 0x60000007, /* 0044(:389): DRD2A: EU0=0 EU1=0 EU2=0 EU3=7 EXT init=0 WS=0 RS=0 */ - 0x014cf88b, /* 0048(:389): DRD2B1: var5 = EU3(); EU3(idx2,var11) */ - 0x98c6001c, /* 004C(:391): LCD: idx2 = idx1 + var12 + 4; idx2 once var0; idx2 += inc3 */ - 0x00000710, /* 0050(:392): DRD1A: var1 = idx2; FN=0 init=0 WS=0 RS=0 */ - 0x98c70018, /* 0054(:393): LCD: idx2 = idx1 + var14; idx2 once var0; idx2 += inc3 */ - 0x10001f10, /* 0058(:394): DRD1A: var7 = idx2; FN=0 MORE init=0 WS=0 RS=0 */ - 0x0000c818, /* 005C(:395): DRD1A: *idx2 = var3; FN=0 init=0 WS=0 RS=0 */ - 0x000001f8, /* 0060(:0): NOP */ - 0xc1476018, /* 0064(:399): LCDEXT: idx1 = var2 + var14; ; idx1 += inc3 */ - 0xc003231d, /* 0068(:399): LCDEXT: idx2 = var0, idx3 = var6; idx3 == var12; idx2 += inc3, idx3 += inc5 */ - 0x811a601b, /* 006C(:400): LCD: idx4 = var2; ; idx4 += inc3 */ - 0xc1862102, /* 0070(:403): LCDEXT: idx5 = var3, idx6 = var12; idx6 < var4; idx5 += inc0, idx6 += inc2 */ - 0x849be009, /* 0074(:403): LCD: idx7 = var9; ; idx7 += inc1 */ - 0x03fed7b8, /* 0078(:406): DRD1A: *idx7; FN=0 init=31 WS=3 RS=3 */ - 0xda9b001b, /* 007C(:408): LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */ - 0x9b9be01b, /* 0080(:408): LCD: idx7 = idx7; ; idx7 += inc3 */ - 0x1000cb20, /* 0084(:409): DRD1A: *idx2 = idx4; FN=0 MORE init=0 WS=0 RS=0 */ - 0x70000006, /* 0088(:410): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ - 0x088cf88f, /* 008C(:410): DRD2B1: idx2 = EU3(); EU3(idx2,var15) */ - 0x1000cb28, /* 0090(:411): DRD1A: *idx2 = idx5; FN=0 MORE init=0 WS=0 RS=0 */ - 0x70000006, /* 0094(:412): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ - 0x088cf88f, /* 0098(:412): DRD2B1: idx2 = EU3(); EU3(idx2,var15) */ - 0x1000cb30, /* 009C(:413): DRD1A: *idx2 = idx6; FN=0 MORE init=0 WS=0 RS=0 */ - 0x70000006, /* 00A0(:414): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ - 0x088cf88f, /* 00A4(:414): DRD2B1: idx2 = EU3(); EU3(idx2,var15) */ - 0x1000cb38, /* 00A8(:415): DRD1A: *idx2 = idx7; FN=0 MORE init=0 WS=0 RS=0 */ - 0x0000c728, /* 00AC(:416): DRD1A: *idx1 = idx5; FN=0 init=0 WS=0 RS=0 */ - 0x000001f8, /* 00B0(:0): NOP */ - 0xc1476018, /* 00B4(:420): LCDEXT: idx1 = var2 + var14; ; idx1 += inc3 */ - 0xc003241d, /* 00B8(:420): LCDEXT: idx2 = var0, idx3 = var6; idx3 == var16; idx2 += inc3, idx3 += inc5 */ - 0x811a601b, /* 00BC(:421): LCD: idx4 = var2; ; idx4 += inc3 */ - 0xda9b001b, /* 00C0(:424): LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */ - 0x9b9be01b, /* 00C4(:424): LCD: idx7 = idx7; ; idx7 += inc3 */ - 0x0000d3a0, /* 00C8(:425): DRD1A: *idx4; FN=0 init=0 WS=0 RS=0 */ - 0xc1862102, /* 00CC(:427): LCDEXT: idx5 = var3, idx6 = var12; idx6 < var4; idx5 += inc0, idx6 += inc2 */ - 0x849be009, /* 00D0(:427): LCD: idx7 = var9; ; idx7 += inc1 */ - 0x0bfed7b8, /* 00D4(:430): DRD1A: *idx7; FN=0 TFD init=31 WS=3 RS=3 */ - 0xda9b001b, /* 00D8(:432): LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */ - 0x9b9be01b, /* 00DC(:432): LCD: idx7 = idx7; ; idx7 += inc3 */ - 0x1000cb20, /* 00E0(:433): DRD1A: *idx2 = idx4; FN=0 MORE init=0 WS=0 RS=0 */ - 0x70000006, /* 00E4(:434): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ - 0x088cf88f, /* 00E8(:434): DRD2B1: idx2 = EU3(); EU3(idx2,var15) */ - 0x1000cb28, /* 00EC(:435): DRD1A: *idx2 = idx5; FN=0 MORE init=0 WS=0 RS=0 */ - 0x70000006, /* 00F0(:436): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ - 0x088cf88f, /* 00F4(:436): DRD2B1: idx2 = EU3(); EU3(idx2,var15) */ - 0x1000cb30, /* 00F8(:437): DRD1A: *idx2 = idx6; FN=0 MORE init=0 WS=0 RS=0 */ - 0x70000006, /* 00FC(:438): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ - 0x088cf88f, /* 0100(:438): DRD2B1: idx2 = EU3(); EU3(idx2,var15) */ - 0x1000cb38, /* 0104(:439): DRD1A: *idx2 = idx7; FN=0 MORE init=0 WS=0 RS=0 */ - 0x0000c728, /* 0108(:440): DRD1A: *idx1 = idx5; FN=0 init=0 WS=0 RS=0 */ - 0x000001f8, /* 010C(:0): NOP */ - 0x8118801b, /* 0110(:444): LCD: idx1 = var2; idx1 once var0; idx1 += inc3 */ - 0xd8c60018, /* 0114(:446): LCDEXT: idx2 = idx1 + var12; idx2 once var0; idx2 += inc3 */ - 0x98c6601c, /* 0118(:446): LCD: idx3 = idx1 + var12 + 4; ; idx3 += inc3 */ - 0x6000000b, /* 011C(:447): DRD2A: EU0=0 EU1=0 EU2=0 EU3=11 EXT init=0 WS=0 RS=0 */ - 0x0c8cfc9f, /* 0120(:447): DRD2B1: *idx2 = EU3(); EU3(*idx2) */ - 0x000001f8, /* 0124(:0): NOP */ - 0xa146001e, /* 0128(:450): LCD: idx1 = *(var2 + var12 + 24); idx1 once var0; idx1 += inc3 */ - 0x10000b08, /* 012C(:451): DRD1A: var2 = idx1; FN=0 MORE init=0 WS=0 RS=0 */ - 0x10002050, /* 0130(:452): DRD1A: var8 = var10; FN=0 MORE init=0 WS=0 RS=0 */ - 0xb8c60018, /* 0134(:453): LCD: idx2 = *(idx1 + var12); idx2 once var0; idx2 += inc3 */ - 0x10002b10, /* 0138(:454): DRD1A: var10 = idx2; FN=0 MORE init=0 WS=0 RS=0 */ - 0x7000000a, /* 013C(:455): DRD2A: EU0=0 EU1=0 EU2=0 EU3=10 EXT MORE init=0 WS=0 RS=0 */ - 0x080cf89f, /* 0140(:455): DRD2B1: idx0 = EU3(); EU3(idx2) */ - 0x6000000d, /* 0144(:456): DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT init=0 WS=0 RS=0 */ - 0x018cf89f, /* 0148(:456): DRD2B1: var6 = EU3(); EU3(idx2) */ - 0x000001f8, /* 014C(:0): NOP */ - 0x8618801b, /* 0150(:462): LCD: idx1 = var12; idx1 once var0; idx1 += inc3 */ - 0x7000000e, /* 0154(:463): DRD2A: EU0=0 EU1=0 EU2=0 EU3=14 EXT MORE init=0 WS=0 RS=0 */ - 0x084cf21f, /* 0158(:463): DRD2B1: idx1 = EU3(); EU3(var8) */ - 0xd8990336, /* 015C(:464): LCDEXT: idx2 = idx1; idx2 > var12; idx2 += inc6 */ - 0x8019801b, /* 0160(:464): LCD: idx3 = var0; idx3 once var0; idx3 += inc3 */ - 0x040001f8, /* 0164(:465): DRD1A: FN=0 INT init=0 WS=0 RS=0 */ - 0x000001f8, /* 0168(:0): NOP */ - 0x000001f8, /* 016C(:0): NOP */ -}; -u32 MCD_SingleNoEu_TDT[]= -{ - 0x8198001b, /* 0000(:657): LCD: idx0 = var3; idx0 once var0; idx0 += inc3 */ - 0x7000000d, /* 0004(:658): DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT MORE init=0 WS=0 RS=0 */ - 0x080cf81f, /* 0008(:658): DRD2B1: idx0 = EU3(); EU3(idx0) */ - 0x8198801b, /* 000C(:659): LCD: idx1 = var3; idx1 once var0; idx1 += inc3 */ - 0x6000000e, /* 0010(:660): DRD2A: EU0=0 EU1=0 EU2=0 EU3=14 EXT init=0 WS=0 RS=0 */ - 0x084cf85f, /* 0014(:660): DRD2B1: idx1 = EU3(); EU3(idx1) */ - 0x000001f8, /* 0018(:0): NOP */ - 0x8298001b, /* 001C(:664): LCD: idx0 = var5; idx0 once var0; idx0 += inc3 */ - 0x7000000d, /* 0020(:665): DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT MORE init=0 WS=0 RS=0 */ - 0x010cf81f, /* 0024(:665): DRD2B1: var4 = EU3(); EU3(idx0) */ - 0x6000000e, /* 0028(:666): DRD2A: EU0=0 EU1=0 EU2=0 EU3=14 EXT init=0 WS=0 RS=0 */ - 0x018cf81f, /* 002C(:666): DRD2B1: var6 = EU3(); EU3(idx0) */ - 0xc202601b, /* 0030(:669): LCDEXT: idx0 = var4, idx1 = var4; ; idx0 += inc3, idx1 += inc3 */ - 0xc002221c, /* 0034(:669): LCDEXT: idx2 = var0, idx3 = var4; idx3 == var8; idx2 += inc3, idx3 += inc4 */ - 0x809a601b, /* 0038(:670): LCD: idx4 = var1; ; idx4 += inc3 */ - 0xc10420c2, /* 003C(:673): LCDEXT: idx5 = var2, idx6 = var8; idx6 < var3; idx5 += inc0, idx6 += inc2 */ - 0x839be009, /* 0040(:673): LCD: idx7 = var7; ; idx7 += inc1 */ - 0x03fed7b8, /* 0044(:676): DRD1A: *idx7; FN=0 init=31 WS=3 RS=3 */ - 0xda9b001b, /* 0048(:678): LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */ - 0x9b9be01b, /* 004C(:678): LCD: idx7 = idx7; ; idx7 += inc3 */ - 0x70000006, /* 0050(:680): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ - 0x088cf889, /* 0054(:680): DRD2B1: idx2 = EU3(); EU3(idx2,var9) */ - 0x1000cb28, /* 0058(:681): DRD1A: *idx2 = idx5; FN=0 MORE init=0 WS=0 RS=0 */ - 0x70000006, /* 005C(:682): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ - 0x088cf889, /* 0060(:682): DRD2B1: idx2 = EU3(); EU3(idx2,var9) */ - 0x1000cb30, /* 0064(:683): DRD1A: *idx2 = idx6; FN=0 MORE init=0 WS=0 RS=0 */ - 0x70000006, /* 0068(:684): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ - 0x088cf889, /* 006C(:684): DRD2B1: idx2 = EU3(); EU3(idx2,var9) */ - 0x0000cb38, /* 0070(:685): DRD1A: *idx2 = idx7; FN=0 init=0 WS=0 RS=0 */ - 0x000001f8, /* 0074(:0): NOP */ - 0xc202601b, /* 0078(:689): LCDEXT: idx0 = var4, idx1 = var4; ; idx0 += inc3, idx1 += inc3 */ - 0xc002229c, /* 007C(:689): LCDEXT: idx2 = var0, idx3 = var4; idx3 == var10; idx2 += inc3, idx3 += inc4 */ - 0x809a601b, /* 0080(:690): LCD: idx4 = var1; ; idx4 += inc3 */ - 0xda9b001b, /* 0084(:693): LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */ - 0x9b9be01b, /* 0088(:693): LCD: idx7 = idx7; ; idx7 += inc3 */ - 0x0000d3a0, /* 008C(:694): DRD1A: *idx4; FN=0 init=0 WS=0 RS=0 */ - 0xc10420c2, /* 0090(:696): LCDEXT: idx5 = var2, idx6 = var8; idx6 < var3; idx5 += inc0, idx6 += inc2 */ - 0x839be009, /* 0094(:696): LCD: idx7 = var7; ; idx7 += inc1 */ - 0x0bfed7b8, /* 0098(:699): DRD1A: *idx7; FN=0 TFD init=31 WS=3 RS=3 */ - 0xda9b001b, /* 009C(:701): LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */ - 0x9b9be01b, /* 00A0(:701): LCD: idx7 = idx7; ; idx7 += inc3 */ - 0x70000006, /* 00A4(:703): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ - 0x088cf889, /* 00A8(:703): DRD2B1: idx2 = EU3(); EU3(idx2,var9) */ - 0x1000cb28, /* 00AC(:704): DRD1A: *idx2 = idx5; FN=0 MORE init=0 WS=0 RS=0 */ - 0x70000006, /* 00B0(:705): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ - 0x088cf889, /* 00B4(:705): DRD2B1: idx2 = EU3(); EU3(idx2,var9) */ - 0x1000cb30, /* 00B8(:706): DRD1A: *idx2 = idx6; FN=0 MORE init=0 WS=0 RS=0 */ - 0x70000006, /* 00BC(:707): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ - 0x088cf889, /* 00C0(:707): DRD2B1: idx2 = EU3(); EU3(idx2,var9) */ - 0x0000cb38, /* 00C4(:708): DRD1A: *idx2 = idx7; FN=0 init=0 WS=0 RS=0 */ - 0x000001f8, /* 00C8(:0): NOP */ - 0xc318022d, /* 00CC(:712): LCDEXT: idx0 = var6; idx0 > var8; idx0 += inc5 */ - 0x8018801b, /* 00D0(:712): LCD: idx1 = var0; idx1 once var0; idx1 += inc3 */ - 0x040001f8, /* 00D4(:713): DRD1A: FN=0 INT init=0 WS=0 RS=0 */ -}; -#ifdef MCD_INCLUDE_EU -u32 MCD_ChainEu_TDT[]= -{ - 0x80004000, /* 0000(:947): LCDEXT: idx0 = 0x00000000; ; */ - 0x8198801b, /* 0004(:947): LCD: idx1 = var3; idx1 once var0; idx1 += inc3 */ - 0xb8c68018, /* 0008(:948): LCD: idx2 = *(idx1 + var13); idx2 once var0; idx2 += inc3 */ - 0x10002f10, /* 000C(:949): DRD1A: var11 = idx2; FN=0 MORE init=0 WS=0 RS=0 */ - 0x7000000d, /* 0010(:950): DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT MORE init=0 WS=0 RS=0 */ - 0x01ccf89f, /* 0014(:950): DRD2B1: var7 = EU3(); EU3(idx2) */ - 0x6000000a, /* 0018(:951): DRD2A: EU0=0 EU1=0 EU2=0 EU3=10 EXT init=0 WS=0 RS=0 */ - 0x080cf89f, /* 001C(:951): DRD2B1: idx0 = EU3(); EU3(idx2) */ - 0x000001f8, /* 0020(:0): NOP */ - 0x981803a4, /* 0024(:955): LCD: idx0 = idx0; idx0 == var14; idx0 += inc4 */ - 0x8198801b, /* 0028(:957): LCD: idx1 = var3; idx1 once var0; idx1 += inc3 */ - 0xf8c6801a, /* 002C(:958): LCDEXT: idx2 = *(idx1 + var13 + 8); idx2 once var0; idx2 += inc3 */ - 0xb8c6e01b, /* 0030(:959): LCD: idx3 = *(idx1 + var13 + 12); ; idx3 += inc3 */ - 0x10002b10, /* 0034(:961): DRD1A: var10 = idx2; FN=0 MORE init=0 WS=0 RS=0 */ - 0x00001318, /* 0038(:962): DRD1A: var4 = idx3; FN=0 init=0 WS=0 RS=0 */ - 0xb8c6801d, /* 003C(:964): LCD: idx2 = *(idx1 + var13 + 20); idx2 once var0; idx2 += inc3 */ - 0x10001710, /* 0040(:965): DRD1A: var5 = idx2; FN=0 MORE init=0 WS=0 RS=0 */ - 0x60000007, /* 0044(:966): DRD2A: EU0=0 EU1=0 EU2=0 EU3=7 EXT init=0 WS=0 RS=0 */ - 0x018cf88c, /* 0048(:966): DRD2B1: var6 = EU3(); EU3(idx2,var12) */ - 0x98c6801c, /* 004C(:968): LCD: idx2 = idx1 + var13 + 4; idx2 once var0; idx2 += inc3 */ - 0x00000b10, /* 0050(:969): DRD1A: var2 = idx2; FN=0 init=0 WS=0 RS=0 */ - 0x98c78018, /* 0054(:970): LCD: idx2 = idx1 + var15; idx2 once var0; idx2 += inc3 */ - 0x10002310, /* 0058(:971): DRD1A: var8 = idx2; FN=0 MORE init=0 WS=0 RS=0 */ - 0x0000c820, /* 005C(:972): DRD1A: *idx2 = var4; FN=0 init=0 WS=0 RS=0 */ - 0x000001f8, /* 0060(:0): NOP */ - 0x8698801b, /* 0064(:976): LCD: idx1 = var13; idx1 once var0; idx1 += inc3 */ - 0x7000000f, /* 0068(:977): DRD2A: EU0=0 EU1=0 EU2=0 EU3=15 EXT MORE init=0 WS=0 RS=0 */ - 0x084cf2df, /* 006C(:977): DRD2B1: idx1 = EU3(); EU3(var11) */ - 0xd899042d, /* 0070(:978): LCDEXT: idx2 = idx1; idx2 >= var16; idx2 += inc5 */ - 0x8019801b, /* 0074(:978): LCD: idx3 = var0; idx3 once var0; idx3 += inc3 */ - 0x60000003, /* 0078(:979): DRD2A: EU0=0 EU1=0 EU2=0 EU3=3 EXT init=0 WS=0 RS=0 */ - 0x2cd7c7df, /* 007C(:979): DRD2B2: EU3(var13) */ - 0xd8990364, /* 0080(:980): LCDEXT: idx2 = idx1; idx2 == var13; idx2 += inc4 */ - 0x8019801b, /* 0084(:980): LCD: idx3 = var0; idx3 once var0; idx3 += inc3 */ - 0x60000003, /* 0088(:981): DRD2A: EU0=0 EU1=0 EU2=0 EU3=3 EXT init=0 WS=0 RS=0 */ - 0x2c17c7df, /* 008C(:981): DRD2B2: EU3(var1) */ - 0x000001f8, /* 0090(:0): NOP */ - 0xc1c7e018, /* 0094(:984): LCDEXT: idx1 = var3 + var15; ; idx1 += inc3 */ - 0xc003a35e, /* 0098(:984): LCDEXT: idx2 = var0, idx3 = var7; idx3 == var13; idx2 += inc3, idx3 += inc6 */ - 0x819a601b, /* 009C(:985): LCD: idx4 = var3; ; idx4 += inc3 */ - 0xc206a142, /* 00A0(:988): LCDEXT: idx5 = var4, idx6 = var13; idx6 < var5; idx5 += inc0, idx6 += inc2 */ - 0x851be009, /* 00A4(:988): LCD: idx7 = var10; ; idx7 += inc1 */ - 0x63fe0000, /* 00A8(:991): DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=31 WS=3 RS=3 */ - 0x0d4cfddf, /* 00AC(:991): DRD2B1: *idx5 = EU3(); EU3(*idx7) */ - 0xda9b001b, /* 00B0(:993): LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */ - 0x9b9be01b, /* 00B4(:993): LCD: idx7 = idx7; ; idx7 += inc3 */ - 0x70000002, /* 00B8(:994): DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT MORE init=0 WS=0 RS=0 */ - 0x004cf81f, /* 00BC(:994): DRD2B1: var1 = EU3(); EU3(idx0) */ - 0x1000cb20, /* 00C0(:995): DRD1A: *idx2 = idx4; FN=0 MORE init=0 WS=0 RS=0 */ - 0x70000006, /* 00C4(:996): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ - 0x088cf891, /* 00C8(:996): DRD2B1: idx2 = EU3(); EU3(idx2,var17) */ - 0x1000cb28, /* 00CC(:997): DRD1A: *idx2 = idx5; FN=0 MORE init=0 WS=0 RS=0 */ - 0x70000006, /* 00D0(:998): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ - 0x088cf891, /* 00D4(:998): DRD2B1: idx2 = EU3(); EU3(idx2,var17) */ - 0x1000cb30, /* 00D8(:999): DRD1A: *idx2 = idx6; FN=0 MORE init=0 WS=0 RS=0 */ - 0x70000006, /* 00DC(:1000): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ - 0x088cf891, /* 00E0(:1000): DRD2B1: idx2 = EU3(); EU3(idx2,var17) */ - 0x1000cb38, /* 00E4(:1001): DRD1A: *idx2 = idx7; FN=0 MORE init=0 WS=0 RS=0 */ - 0x0000c728, /* 00E8(:1002): DRD1A: *idx1 = idx5; FN=0 init=0 WS=0 RS=0 */ - 0x000001f8, /* 00EC(:0): NOP */ - 0xc1c7e018, /* 00F0(:1006): LCDEXT: idx1 = var3 + var15; ; idx1 += inc3 */ - 0xc003a49e, /* 00F4(:1006): LCDEXT: idx2 = var0, idx3 = var7; idx3 == var18; idx2 += inc3, idx3 += inc6 */ - 0x819a601b, /* 00F8(:1007): LCD: idx4 = var3; ; idx4 += inc3 */ - 0xda9b001b, /* 00FC(:1010): LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */ - 0x9b9be01b, /* 0100(:1010): LCD: idx7 = idx7; ; idx7 += inc3 */ - 0x0000d3a0, /* 0104(:1011): DRD1A: *idx4; FN=0 init=0 WS=0 RS=0 */ - 0xc206a142, /* 0108(:1013): LCDEXT: idx5 = var4, idx6 = var13; idx6 < var5; idx5 += inc0, idx6 += inc2 */ - 0x851be009, /* 010C(:1013): LCD: idx7 = var10; ; idx7 += inc1 */ - 0x6bfe0000, /* 0110(:1016): DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 TFD EXT init=31 WS=3 RS=3 */ - 0x0d4cfddf, /* 0114(:1016): DRD2B1: *idx5 = EU3(); EU3(*idx7) */ - 0xda9b001b, /* 0118(:1018): LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */ - 0x9b9be01b, /* 011C(:1018): LCD: idx7 = idx7; ; idx7 += inc3 */ - 0x70000002, /* 0120(:1019): DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT MORE init=0 WS=0 RS=0 */ - 0x004cf81f, /* 0124(:1019): DRD2B1: var1 = EU3(); EU3(idx0) */ - 0x1000cb20, /* 0128(:1020): DRD1A: *idx2 = idx4; FN=0 MORE init=0 WS=0 RS=0 */ - 0x70000006, /* 012C(:1021): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ - 0x088cf891, /* 0130(:1021): DRD2B1: idx2 = EU3(); EU3(idx2,var17) */ - 0x1000cb28, /* 0134(:1022): DRD1A: *idx2 = idx5; FN=0 MORE init=0 WS=0 RS=0 */ - 0x70000006, /* 0138(:1023): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ - 0x088cf891, /* 013C(:1023): DRD2B1: idx2 = EU3(); EU3(idx2,var17) */ - 0x1000cb30, /* 0140(:1024): DRD1A: *idx2 = idx6; FN=0 MORE init=0 WS=0 RS=0 */ - 0x70000006, /* 0144(:1025): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ - 0x088cf891, /* 0148(:1025): DRD2B1: idx2 = EU3(); EU3(idx2,var17) */ - 0x1000cb38, /* 014C(:1026): DRD1A: *idx2 = idx7; FN=0 MORE init=0 WS=0 RS=0 */ - 0x0000c728, /* 0150(:1027): DRD1A: *idx1 = idx5; FN=0 init=0 WS=0 RS=0 */ - 0x000001f8, /* 0154(:0): NOP */ - 0x8198801b, /* 0158(:1031): LCD: idx1 = var3; idx1 once var0; idx1 += inc3 */ - 0xd8c68018, /* 015C(:1033): LCDEXT: idx2 = idx1 + var13; idx2 once var0; idx2 += inc3 */ - 0x98c6e01c, /* 0160(:1033): LCD: idx3 = idx1 + var13 + 4; ; idx3 += inc3 */ - 0x6000000b, /* 0164(:1034): DRD2A: EU0=0 EU1=0 EU2=0 EU3=11 EXT init=0 WS=0 RS=0 */ - 0x0c8cfc9f, /* 0168(:1034): DRD2B1: *idx2 = EU3(); EU3(*idx2) */ - 0x0000cc08, /* 016C(:1035): DRD1A: *idx3 = var1; FN=0 init=0 WS=0 RS=0 */ - 0xa1c6801e, /* 0170(:1038): LCD: idx1 = *(var3 + var13 + 24); idx1 once var0; idx1 += inc3 */ - 0x10000f08, /* 0174(:1039): DRD1A: var3 = idx1; FN=0 MORE init=0 WS=0 RS=0 */ - 0x10002458, /* 0178(:1040): DRD1A: var9 = var11; FN=0 MORE init=0 WS=0 RS=0 */ - 0xb8c68018, /* 017C(:1041): LCD: idx2 = *(idx1 + var13); idx2 once var0; idx2 += inc3 */ - 0x10002f10, /* 0180(:1042): DRD1A: var11 = idx2; FN=0 MORE init=0 WS=0 RS=0 */ - 0x7000000a, /* 0184(:1043): DRD2A: EU0=0 EU1=0 EU2=0 EU3=10 EXT MORE init=0 WS=0 RS=0 */ - 0x080cf89f, /* 0188(:1043): DRD2B1: idx0 = EU3(); EU3(idx2) */ - 0x6000000d, /* 018C(:1044): DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT init=0 WS=0 RS=0 */ - 0x01ccf89f, /* 0190(:1044): DRD2B1: var7 = EU3(); EU3(idx2) */ - 0x000001f8, /* 0194(:0): NOP */ - 0x8698801b, /* 0198(:1050): LCD: idx1 = var13; idx1 once var0; idx1 += inc3 */ - 0x7000000e, /* 019C(:1051): DRD2A: EU0=0 EU1=0 EU2=0 EU3=14 EXT MORE init=0 WS=0 RS=0 */ - 0x084cf25f, /* 01A0(:1051): DRD2B1: idx1 = EU3(); EU3(var9) */ - 0xd899037f, /* 01A4(:1052): LCDEXT: idx2 = idx1; idx2 > var13; idx2 += inc7 */ - 0x8019801b, /* 01A8(:1052): LCD: idx3 = var0; idx3 once var0; idx3 += inc3 */ - 0x040001f8, /* 01AC(:1053): DRD1A: FN=0 INT init=0 WS=0 RS=0 */ - 0x000001f8, /* 01B0(:0): NOP */ - 0x000001f8, /* 01B4(:0): NOP */ -}; -u32 MCD_SingleEu_TDT[]= -{ - 0x8218001b, /* 0000(:1248): LCD: idx0 = var4; idx0 once var0; idx0 += inc3 */ - 0x7000000d, /* 0004(:1249): DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT MORE init=0 WS=0 RS=0 */ - 0x080cf81f, /* 0008(:1249): DRD2B1: idx0 = EU3(); EU3(idx0) */ - 0x8218801b, /* 000C(:1250): LCD: idx1 = var4; idx1 once var0; idx1 += inc3 */ - 0x6000000e, /* 0010(:1251): DRD2A: EU0=0 EU1=0 EU2=0 EU3=14 EXT init=0 WS=0 RS=0 */ - 0x084cf85f, /* 0014(:1251): DRD2B1: idx1 = EU3(); EU3(idx1) */ - 0x000001f8, /* 0018(:0): NOP */ - 0x8318001b, /* 001C(:1255): LCD: idx0 = var6; idx0 once var0; idx0 += inc3 */ - 0x7000000d, /* 0020(:1256): DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT MORE init=0 WS=0 RS=0 */ - 0x014cf81f, /* 0024(:1256): DRD2B1: var5 = EU3(); EU3(idx0) */ - 0x6000000e, /* 0028(:1257): DRD2A: EU0=0 EU1=0 EU2=0 EU3=14 EXT init=0 WS=0 RS=0 */ - 0x01ccf81f, /* 002C(:1257): DRD2B1: var7 = EU3(); EU3(idx0) */ - 0x8498001b, /* 0030(:1260): LCD: idx0 = var9; idx0 once var0; idx0 += inc3 */ - 0x7000000f, /* 0034(:1261): DRD2A: EU0=0 EU1=0 EU2=0 EU3=15 EXT MORE init=0 WS=0 RS=0 */ - 0x080cf19f, /* 0038(:1261): DRD2B1: idx0 = EU3(); EU3(var6) */ - 0xd81882a4, /* 003C(:1262): LCDEXT: idx1 = idx0; idx1 >= var10; idx1 += inc4 */ - 0x8019001b, /* 0040(:1262): LCD: idx2 = var0; idx2 once var0; idx2 += inc3 */ - 0x60000003, /* 0044(:1263): DRD2A: EU0=0 EU1=0 EU2=0 EU3=3 EXT init=0 WS=0 RS=0 */ - 0x2c97c7df, /* 0048(:1263): DRD2B2: EU3(var9) */ - 0xd818826d, /* 004C(:1264): LCDEXT: idx1 = idx0; idx1 == var9; idx1 += inc5 */ - 0x8019001b, /* 0050(:1264): LCD: idx2 = var0; idx2 once var0; idx2 += inc3 */ - 0x60000003, /* 0054(:1265): DRD2A: EU0=0 EU1=0 EU2=0 EU3=3 EXT init=0 WS=0 RS=0 */ - 0x2c17c7df, /* 0058(:1265): DRD2B2: EU3(var1) */ - 0x000001f8, /* 005C(:0): NOP */ - 0xc282e01b, /* 0060(:1268): LCDEXT: idx0 = var5, idx1 = var5; ; idx0 += inc3, idx1 += inc3 */ - 0xc002a25e, /* 0064(:1268): LCDEXT: idx2 = var0, idx3 = var5; idx3 == var9; idx2 += inc3, idx3 += inc6 */ - 0x811a601b, /* 0068(:1269): LCD: idx4 = var2; ; idx4 += inc3 */ - 0xc184a102, /* 006C(:1272): LCDEXT: idx5 = var3, idx6 = var9; idx6 < var4; idx5 += inc0, idx6 += inc2 */ - 0x841be009, /* 0070(:1272): LCD: idx7 = var8; ; idx7 += inc1 */ - 0x63fe0000, /* 0074(:1275): DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=31 WS=3 RS=3 */ - 0x0d4cfddf, /* 0078(:1275): DRD2B1: *idx5 = EU3(); EU3(*idx7) */ - 0xda9b001b, /* 007C(:1277): LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */ - 0x9b9be01b, /* 0080(:1277): LCD: idx7 = idx7; ; idx7 += inc3 */ - 0x70000002, /* 0084(:1279): DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT MORE init=0 WS=0 RS=0 */ - 0x004cf99f, /* 0088(:1279): DRD2B1: var1 = EU3(); EU3(idx6) */ - 0x70000006, /* 008C(:1280): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ - 0x088cf88b, /* 0090(:1280): DRD2B1: idx2 = EU3(); EU3(idx2,var11) */ - 0x1000cb28, /* 0094(:1281): DRD1A: *idx2 = idx5; FN=0 MORE init=0 WS=0 RS=0 */ - 0x70000006, /* 0098(:1282): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ - 0x088cf88b, /* 009C(:1282): DRD2B1: idx2 = EU3(); EU3(idx2,var11) */ - 0x1000cb30, /* 00A0(:1283): DRD1A: *idx2 = idx6; FN=0 MORE init=0 WS=0 RS=0 */ - 0x70000006, /* 00A4(:1284): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ - 0x088cf88b, /* 00A8(:1284): DRD2B1: idx2 = EU3(); EU3(idx2,var11) */ - 0x0000cb38, /* 00AC(:1285): DRD1A: *idx2 = idx7; FN=0 init=0 WS=0 RS=0 */ - 0x000001f8, /* 00B0(:0): NOP */ - 0xc282e01b, /* 00B4(:1289): LCDEXT: idx0 = var5, idx1 = var5; ; idx0 += inc3, idx1 += inc3 */ - 0xc002a31e, /* 00B8(:1289): LCDEXT: idx2 = var0, idx3 = var5; idx3 == var12; idx2 += inc3, idx3 += inc6 */ - 0x811a601b, /* 00BC(:1290): LCD: idx4 = var2; ; idx4 += inc3 */ - 0xda9b001b, /* 00C0(:1293): LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */ - 0x9b9be01b, /* 00C4(:1293): LCD: idx7 = idx7; ; idx7 += inc3 */ - 0x0000d3a0, /* 00C8(:1294): DRD1A: *idx4; FN=0 init=0 WS=0 RS=0 */ - 0xc184a102, /* 00CC(:1296): LCDEXT: idx5 = var3, idx6 = var9; idx6 < var4; idx5 += inc0, idx6 += inc2 */ - 0x841be009, /* 00D0(:1296): LCD: idx7 = var8; ; idx7 += inc1 */ - 0x6bfe0000, /* 00D4(:1299): DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 TFD EXT init=31 WS=3 RS=3 */ - 0x0d4cfddf, /* 00D8(:1299): DRD2B1: *idx5 = EU3(); EU3(*idx7) */ - 0xda9b001b, /* 00DC(:1301): LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */ - 0x9b9be01b, /* 00E0(:1301): LCD: idx7 = idx7; ; idx7 += inc3 */ - 0x70000002, /* 00E4(:1303): DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT MORE init=0 WS=0 RS=0 */ - 0x004cf99f, /* 00E8(:1303): DRD2B1: var1 = EU3(); EU3(idx6) */ - 0x70000006, /* 00EC(:1304): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ - 0x088cf88b, /* 00F0(:1304): DRD2B1: idx2 = EU3(); EU3(idx2,var11) */ - 0x1000cb28, /* 00F4(:1305): DRD1A: *idx2 = idx5; FN=0 MORE init=0 WS=0 RS=0 */ - 0x70000006, /* 00F8(:1306): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ - 0x088cf88b, /* 00FC(:1306): DRD2B1: idx2 = EU3(); EU3(idx2,var11) */ - 0x1000cb30, /* 0100(:1307): DRD1A: *idx2 = idx6; FN=0 MORE init=0 WS=0 RS=0 */ - 0x70000006, /* 0104(:1308): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ - 0x088cf88b, /* 0108(:1308): DRD2B1: idx2 = EU3(); EU3(idx2,var11) */ - 0x0000cb38, /* 010C(:1309): DRD1A: *idx2 = idx7; FN=0 init=0 WS=0 RS=0 */ - 0x000001f8, /* 0110(:0): NOP */ - 0x8144801c, /* 0114(:1312): LCD: idx0 = var2 + var9 + 4; idx0 once var0; idx0 += inc3 */ - 0x0000c008, /* 0118(:1313): DRD1A: *idx0 = var1; FN=0 init=0 WS=0 RS=0 */ - 0xc398027f, /* 011C(:1315): LCDEXT: idx0 = var7; idx0 > var9; idx0 += inc7 */ - 0x8018801b, /* 0120(:1315): LCD: idx1 = var0; idx1 once var0; idx1 += inc3 */ - 0x040001f8, /* 0124(:1316): DRD1A: FN=0 INT init=0 WS=0 RS=0 */ -}; -#endif -u32 MCD_ENetRcv_TDT[]= -{ - 0x80004000, /* 0000(:1389): LCDEXT: idx0 = 0x00000000; ; */ - 0x81988000, /* 0004(:1389): LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ - 0x10000788, /* 0008(:1390): DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ - 0x6000000a, /* 000C(:1391): DRD2A: EU0=0 EU1=0 EU2=0 EU3=10 EXT init=0 WS=0 RS=0 */ - 0x080cf05f, /* 0010(:1391): DRD2B1: idx0 = EU3(); EU3(var1) */ - 0x98180209, /* 0014(:1394): LCD: idx0 = idx0; idx0 != var8; idx0 += inc1 */ - 0x81c40004, /* 0018(:1396): LCD: idx1 = var3 + var8 + 4; idx1 once var0; idx1 += inc0 */ - 0x7000000e, /* 001C(:1397): DRD2A: EU0=0 EU1=0 EU2=0 EU3=14 EXT MORE init=0 WS=0 RS=0 */ - 0x010cf05f, /* 0020(:1397): DRD2B1: var4 = EU3(); EU3(var1) */ - 0x7000000c, /* 0024(:1398): DRD2A: EU0=0 EU1=0 EU2=0 EU3=12 EXT MORE init=0 WS=0 RS=0 */ - 0x01ccf05f, /* 0028(:1398): DRD2B1: var7 = EU3(); EU3(var1) */ - 0x70000004, /* 002C(:1399): DRD2A: EU0=0 EU1=0 EU2=0 EU3=4 EXT MORE init=0 WS=0 RS=0 */ - 0x014cf049, /* 0030(:1399): DRD2B1: var5 = EU3(); EU3(var1,var9) */ - 0x70000004, /* 0034(:1400): DRD2A: EU0=0 EU1=0 EU2=0 EU3=4 EXT MORE init=0 WS=0 RS=0 */ - 0x004cf04a, /* 0038(:1400): DRD2B1: var1 = EU3(); EU3(var1,var10) */ - 0x00000b88, /* 003C(:1403): DRD1A: var2 = *idx1; FN=0 init=0 WS=0 RS=0 */ - 0xc4030150, /* 0040(:1406): LCDEXT: idx1 = var8, idx2 = var6; idx1 < var5; idx1 += inc2, idx2 += inc0 */ - 0x8119e012, /* 0044(:1406): LCD: idx3 = var2; ; idx3 += inc2 */ - 0x03e0cf90, /* 0048(:1409): DRD1A: *idx3 = *idx2; FN=0 init=31 WS=0 RS=0 */ - 0x81188000, /* 004C(:1412): LCD: idx1 = var2; idx1 once var0; idx1 += inc0 */ - 0x000ac788, /* 0050(:1413): DRD1A: *idx1 = *idx1; FN=0 init=0 WS=1 RS=1 */ - 0xc4030000, /* 0054(:1415): LCDEXT: idx1 = var8, idx2 = var6; idx1 once var0; idx1 += inc0, idx2 += inc0 */ - 0x8199e000, /* 0058(:1415): LCD: idx3 = var3; ; idx3 += inc0 */ - 0x70000004, /* 005C(:1421): DRD2A: EU0=0 EU1=0 EU2=0 EU3=4 EXT MORE init=0 WS=0 RS=0 */ - 0x084cfc8b, /* 0060(:1421): DRD2B1: idx1 = EU3(); EU3(*idx2,var11) */ - 0x60000005, /* 0064(:1422): DRD2A: EU0=0 EU1=0 EU2=0 EU3=5 EXT init=0 WS=0 RS=0 */ - 0x0cccf841, /* 0068(:1422): DRD2B1: *idx3 = EU3(); EU3(idx1,var1) */ - 0x81c60000, /* 006C(:1428): LCD: idx1 = var3 + var12; idx1 once var0; idx1 += inc0 */ - 0xc399021b, /* 0070(:1430): LCDEXT: idx2 = var7; idx2 > var8; idx2 += inc3 */ - 0x80198000, /* 0074(:1430): LCD: idx3 = var0; idx3 once var0; idx3 += inc0 */ - 0x00008400, /* 0078(:1431): DRD1A: idx1 = var0; FN=0 init=0 WS=0 RS=0 */ - 0x00000f08, /* 007C(:1432): DRD1A: var3 = idx1; FN=0 init=0 WS=0 RS=0 */ - 0x81988000, /* 0080(:1435): LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ - 0x10000788, /* 0084(:1436): DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ - 0x6000000a, /* 0088(:1437): DRD2A: EU0=0 EU1=0 EU2=0 EU3=10 EXT init=0 WS=0 RS=0 */ - 0x080cf05f, /* 008C(:1437): DRD2B1: idx0 = EU3(); EU3(var1) */ - 0xc2188209, /* 0090(:1440): LCDEXT: idx1 = var4; idx1 != var8; idx1 += inc1 */ - 0x80190000, /* 0094(:1440): LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */ - 0x040001f8, /* 0098(:1441): DRD1A: FN=0 INT init=0 WS=0 RS=0 */ - 0x000001f8, /* 009C(:0): NOP */ -}; -u32 MCD_ENetXmit_TDT[]= -{ - 0x80004000, /* 0000(:1516): LCDEXT: idx0 = 0x00000000; ; */ - 0x81988000, /* 0004(:1516): LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ - 0x10000788, /* 0008(:1517): DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ - 0x6000000a, /* 000C(:1518): DRD2A: EU0=0 EU1=0 EU2=0 EU3=10 EXT init=0 WS=0 RS=0 */ - 0x080cf05f, /* 0010(:1518): DRD2B1: idx0 = EU3(); EU3(var1) */ - 0x98180309, /* 0014(:1521): LCD: idx0 = idx0; idx0 != var12; idx0 += inc1 */ - 0x80004003, /* 0018(:1523): LCDEXT: idx1 = 0x00000003; ; */ - 0x81c60004, /* 001C(:1523): LCD: idx2 = var3 + var12 + 4; idx2 once var0; idx2 += inc0 */ - 0x7000000e, /* 0020(:1524): DRD2A: EU0=0 EU1=0 EU2=0 EU3=14 EXT MORE init=0 WS=0 RS=0 */ - 0x014cf05f, /* 0024(:1524): DRD2B1: var5 = EU3(); EU3(var1) */ - 0x7000000c, /* 0028(:1525): DRD2A: EU0=0 EU1=0 EU2=0 EU3=12 EXT MORE init=0 WS=0 RS=0 */ - 0x028cf05f, /* 002C(:1525): DRD2B1: var10 = EU3(); EU3(var1) */ - 0x7000000d, /* 0030(:1526): DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT MORE init=0 WS=0 RS=0 */ - 0x018cf05f, /* 0034(:1526): DRD2B1: var6 = EU3(); EU3(var1) */ - 0x70000004, /* 0038(:1527): DRD2A: EU0=0 EU1=0 EU2=0 EU3=4 EXT MORE init=0 WS=0 RS=0 */ - 0x01ccf04d, /* 003C(:1527): DRD2B1: var7 = EU3(); EU3(var1,var13) */ - 0x10000b90, /* 0040(:1528): DRD1A: var2 = *idx2; FN=0 MORE init=0 WS=0 RS=0 */ - 0x60000004, /* 0044(:1529): DRD2A: EU0=0 EU1=0 EU2=0 EU3=4 EXT init=0 WS=0 RS=0 */ - 0x020cf0a1, /* 0048(:1529): DRD2B1: var8 = EU3(); EU3(var2,idx1) */ - 0xc3188312, /* 004C(:1532): LCDEXT: idx1 = var6; idx1 > var12; idx1 += inc2 */ - 0x83c70000, /* 0050(:1532): LCD: idx2 = var7 + var14; idx2 once var0; idx2 += inc0 */ - 0x00001f10, /* 0054(:1533): DRD1A: var7 = idx2; FN=0 init=0 WS=0 RS=0 */ - 0xc583a3c3, /* 0058(:1535): LCDEXT: idx1 = var11, idx2 = var7; idx2 >= var15; idx1 += inc0, idx2 += inc3 */ - 0x81042325, /* 005C(:1535): LCD: idx3 = var2, idx4 = var8; idx4 == var12; idx3 += inc4, idx4 += inc5 */ - 0x03e0c798, /* 0060(:1540): DRD1A: *idx1 = *idx3; FN=0 init=31 WS=0 RS=0 */ - 0xd8990000, /* 0064(:1543): LCDEXT: idx1 = idx1, idx2 = idx2; idx1 once var0; idx1 += inc0, idx2 += inc0 */ - 0x9999e000, /* 0068(:1543): LCD: idx3 = idx3; ; idx3 += inc0 */ - 0x000acf98, /* 006C(:1544): DRD1A: *idx3 = *idx3; FN=0 init=0 WS=1 RS=1 */ - 0xd8992306, /* 0070(:1546): LCDEXT: idx1 = idx1, idx2 = idx2; idx2 > var12; idx1 += inc0, idx2 += inc6 */ - 0x9999e03f, /* 0074(:1546): LCD: idx3 = idx3; ; idx3 += inc7 */ - 0x03eac798, /* 0078(:1549): DRD1A: *idx1 = *idx3; FN=0 init=31 WS=1 RS=1 */ - 0xd8990000, /* 007C(:1552): LCDEXT: idx1 = idx1, idx2 = idx2; idx1 once var0; idx1 += inc0, idx2 += inc0 */ - 0x9999e000, /* 0080(:1552): LCD: idx3 = idx3; ; idx3 += inc0 */ - 0x000acf98, /* 0084(:1553): DRD1A: *idx3 = *idx3; FN=0 init=0 WS=1 RS=1 */ - 0xd8990000, /* 0088(:1555): LCDEXT: idx1 = idx1, idx2 = idx2; idx1 once var0; idx1 += inc0, idx2 += inc0 */ - 0x99832302, /* 008C(:1555): LCD: idx3 = idx3, idx4 = var6; idx4 > var12; idx3 += inc0, idx4 += inc2 */ - 0x0beac798, /* 0090(:1558): DRD1A: *idx1 = *idx3; FN=0 TFD init=31 WS=1 RS=1 */ - 0x81988000, /* 0094(:1560): LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ - 0x6000000b, /* 0098(:1561): DRD2A: EU0=0 EU1=0 EU2=0 EU3=11 EXT init=0 WS=0 RS=0 */ - 0x0c4cfc5f, /* 009C(:1561): DRD2B1: *idx1 = EU3(); EU3(*idx1) */ - 0x81c80000, /* 00A0(:1563): LCD: idx1 = var3 + var16; idx1 once var0; idx1 += inc0 */ - 0xc5190312, /* 00A4(:1565): LCDEXT: idx2 = var10; idx2 > var12; idx2 += inc2 */ - 0x80198000, /* 00A8(:1565): LCD: idx3 = var0; idx3 once var0; idx3 += inc0 */ - 0x00008400, /* 00AC(:1566): DRD1A: idx1 = var0; FN=0 init=0 WS=0 RS=0 */ - 0x00000f08, /* 00B0(:1567): DRD1A: var3 = idx1; FN=0 init=0 WS=0 RS=0 */ - 0x81988000, /* 00B4(:1570): LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ - 0x10000788, /* 00B8(:1571): DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ - 0x6000000a, /* 00BC(:1572): DRD2A: EU0=0 EU1=0 EU2=0 EU3=10 EXT init=0 WS=0 RS=0 */ - 0x080cf05f, /* 00C0(:1572): DRD2B1: idx0 = EU3(); EU3(var1) */ - 0xc2988309, /* 00C4(:1575): LCDEXT: idx1 = var5; idx1 != var12; idx1 += inc1 */ - 0x80190000, /* 00C8(:1575): LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */ - 0x040001f8, /* 00CC(:1576): DRD1A: FN=0 INT init=0 WS=0 RS=0 */ - 0x000001f8, /* 00D0(:0): NOP */ -}; - -#ifdef MCD_INCLUDE_EU -MCD_bufDesc MCD_singleBufDescs[NCHANNELS]; -#endif diff --git a/arch/m68k/mach-mcfv4e/mcdapi/MCD_tasksInit.c b/arch/m68k/mach-mcfv4e/mcdapi/MCD_tasksInit.c deleted file mode 100644 index 8d82b471f9..0000000000 --- a/arch/m68k/mach-mcfv4e/mcdapi/MCD_tasksInit.c +++ /dev/null @@ -1,225 +0,0 @@ -/* - * File: MCD_tasksInit.c - * Purpose: Functions for initializing variable tables of different - * types of tasks. - * - * Notes: - */ - -/* - * Do not edit! - */ - -#include <asm/types.h> -#include <proc/mcdapi/MCD_dma.h> - -extern dmaRegs *MCD_dmaBar; - - -/* - * Task 0 - */ - -void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel) -{ - - MCD_SET_VAR(taskTable+channel, 2, (u32)currBD); /* var[2] */ - MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */ - MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */ - MCD_SET_VAR(taskTable+channel, 11, (u32)xferSize); /* var[11] */ - MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */ - MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */ - MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */ - MCD_SET_VAR(taskTable+channel, 3, (u32)0x00000000); /* var[3] */ - MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */ - MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */ - MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */ - MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */ - MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */ - MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */ - MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000); /* var[10] */ - MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000000); /* var[12] */ - MCD_SET_VAR(taskTable+channel, 13, (u32)0x80000000); /* var[13] */ - MCD_SET_VAR(taskTable+channel, 14, (u32)0x00000010); /* var[14] */ - MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000004); /* var[15] */ - MCD_SET_VAR(taskTable+channel, 16, (u32)0x08000000); /* var[16] */ - MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */ - MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000000); /* inc[4] */ - MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000001); /* inc[5] */ - MCD_SET_VAR(taskTable+channel, 30, (u32)0x40000000); /* inc[6] */ - - /* Set the task's Enable bit in its Task Control Register */ - MCD_dmaBar->taskControl[channel] |= (u16)0x8000; -} - - -/* - * Task 1 - */ - -void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel) -{ - - MCD_SET_VAR(taskTable+channel, 7, (u32)srcAddr); /* var[7] */ - MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */ - MCD_SET_VAR(taskTable+channel, 2, (u32)destAddr); /* var[2] */ - MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */ - MCD_SET_VAR(taskTable+channel, 3, (u32)dmaSize); /* var[3] */ - MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */ - MCD_SET_VAR(taskTable+channel, 5, (u32)flags); /* var[5] */ - MCD_SET_VAR(taskTable+channel, 1, (u32)currBD); /* var[1] */ - MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */ - MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */ - MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */ - MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */ - MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000004); /* var[9] */ - MCD_SET_VAR(taskTable+channel, 10, (u32)0x08000000); /* var[10] */ - MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */ - MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000001); /* inc[4] */ - MCD_SET_VAR(taskTable+channel, 29, (u32)0x40000000); /* inc[5] */ - - /* Set the task's Enable bit in its Task Control Register */ - MCD_dmaBar->taskControl[channel] |= (u16)0x8000; -} - - -/* - * Task 2 - */ - -void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel) -{ - - MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */ - MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */ - MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */ - MCD_SET_VAR(taskTable+channel, 12, (u32)xferSize); /* var[12] */ - MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */ - MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */ - MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */ - MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */ - MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */ - MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */ - MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */ - MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */ - MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */ - MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */ - MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000); /* var[10] */ - MCD_SET_VAR(taskTable+channel, 11, (u32)0x00000000); /* var[11] */ - MCD_SET_VAR(taskTable+channel, 13, (u32)0x00000000); /* var[13] */ - MCD_SET_VAR(taskTable+channel, 14, (u32)0x80000000); /* var[14] */ - MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000010); /* var[15] */ - MCD_SET_VAR(taskTable+channel, 16, (u32)0x00000001); /* var[16] */ - MCD_SET_VAR(taskTable+channel, 17, (u32)0x00000004); /* var[17] */ - MCD_SET_VAR(taskTable+channel, 18, (u32)0x08000000); /* var[18] */ - MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */ - MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000000); /* inc[4] */ - MCD_SET_VAR(taskTable+channel, 29, (u32)0xc0000000); /* inc[5] */ - MCD_SET_VAR(taskTable+channel, 30, (u32)0x80000001); /* inc[6] */ - MCD_SET_VAR(taskTable+channel, 31, (u32)0x40000000); /* inc[7] */ - - /* Set the task's Enable bit in its Task Control Register */ - MCD_dmaBar->taskControl[channel] |= (u16)0x8000; -} - - -/* - * Task 3 - */ - -void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel) -{ - - MCD_SET_VAR(taskTable+channel, 8, (u32)srcAddr); /* var[8] */ - MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */ - MCD_SET_VAR(taskTable+channel, 3, (u32)destAddr); /* var[3] */ - MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */ - MCD_SET_VAR(taskTable+channel, 4, (u32)dmaSize); /* var[4] */ - MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */ - MCD_SET_VAR(taskTable+channel, 6, (u32)flags); /* var[6] */ - MCD_SET_VAR(taskTable+channel, 2, (u32)currBD); /* var[2] */ - MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */ - MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */ - MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */ - MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */ - MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */ - MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000001); /* var[10] */ - MCD_SET_VAR(taskTable+channel, 11, (u32)0x00000004); /* var[11] */ - MCD_SET_VAR(taskTable+channel, 12, (u32)0x08000000); /* var[12] */ - MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */ - MCD_SET_VAR(taskTable+channel, 28, (u32)0xc0000000); /* inc[4] */ - MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000000); /* inc[5] */ - MCD_SET_VAR(taskTable+channel, 30, (u32)0x80000001); /* inc[6] */ - MCD_SET_VAR(taskTable+channel, 31, (u32)0x40000000); /* inc[7] */ - - /* Set the task's Enable bit in its Task Control Register */ - MCD_dmaBar->taskControl[channel] |= (u16)0x8000; -} - - -/* - * Task 4 - */ - -void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel) -{ - - MCD_SET_VAR(taskTable+channel, 0, (u32)bDBase); /* var[0] */ - MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */ - MCD_SET_VAR(taskTable+channel, 6, (u32)rcvFifoPtr); /* var[6] */ - MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */ - MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */ - MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */ - MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */ - MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */ - MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */ - MCD_SET_VAR(taskTable+channel, 9, (u32)0x0000ffff); /* var[9] */ - MCD_SET_VAR(taskTable+channel, 10, (u32)0x30000000); /* var[10] */ - MCD_SET_VAR(taskTable+channel, 11, (u32)0x0fffffff); /* var[11] */ - MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000008); /* var[12] */ - MCD_SET_VAR(taskTable+channel, 24, (u32)0x00000000); /* inc[0] */ - MCD_SET_VAR(taskTable+channel, 25, (u32)0x60000000); /* inc[1] */ - MCD_SET_VAR(taskTable+channel, 26, (u32)0x20000004); /* inc[2] */ - MCD_SET_VAR(taskTable+channel, 27, (u32)0x40000000); /* inc[3] */ - - /* Set the task's Enable bit in its Task Control Register */ - MCD_dmaBar->taskControl[channel] |= (u16)0x8000; -} - - -/* - * Task 5 - */ - -void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel) -{ - - MCD_SET_VAR(taskTable+channel, 0, (u32)bDBase); /* var[0] */ - MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */ - MCD_SET_VAR(taskTable+channel, 11, (u32)xmitFifoPtr); /* var[11] */ - MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */ - MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */ - MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */ - MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */ - MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */ - MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */ - MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */ - MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */ - MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000); /* var[10] */ - MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000000); /* var[12] */ - MCD_SET_VAR(taskTable+channel, 13, (u32)0x0000ffff); /* var[13] */ - MCD_SET_VAR(taskTable+channel, 14, (u32)0xffffffff); /* var[14] */ - MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000004); /* var[15] */ - MCD_SET_VAR(taskTable+channel, 16, (u32)0x00000008); /* var[16] */ - MCD_SET_VAR(taskTable+channel, 24, (u32)0x00000000); /* inc[0] */ - MCD_SET_VAR(taskTable+channel, 25, (u32)0x60000000); /* inc[1] */ - MCD_SET_VAR(taskTable+channel, 26, (u32)0x40000000); /* inc[2] */ - MCD_SET_VAR(taskTable+channel, 27, (u32)0xc000fffc); /* inc[3] */ - MCD_SET_VAR(taskTable+channel, 28, (u32)0xe0000004); /* inc[4] */ - MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000000); /* inc[5] */ - MCD_SET_VAR(taskTable+channel, 30, (u32)0x4000ffff); /* inc[6] */ - MCD_SET_VAR(taskTable+channel, 31, (u32)0xe0000001); /* inc[7] */ - - /* Set the task's Enable bit in its Task Control Register */ - MCD_dmaBar->taskControl[channel] |= (u16)0x8000; -} diff --git a/arch/m68k/mach-mcfv4e/mcdapi/Makefile b/arch/m68k/mach-mcfv4e/mcdapi/Makefile deleted file mode 100644 index 52ddaf8581..0000000000 --- a/arch/m68k/mach-mcfv4e/mcdapi/Makefile +++ /dev/null @@ -1,26 +0,0 @@ -# -# (C) Copyright 2007 Carsten Schlote <schlote@vahanus.net> -# See file CREDITS for list of people who contributed to this project. -# -# This file is part of barebox. -# -# barebox is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# barebox is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with barebox. If not, see <http://www.gnu.org/licenses/>. -# - -# -# FreeScale MultiDMA Library -# -obj-y += MCD_dmaApi.o MCD_tasks.o MCD_tasksInit.o - - diff --git a/arch/m68k/mach-mcfv4e/mcdapi/ReleaseNotes.txt b/arch/m68k/mach-mcfv4e/mcdapi/ReleaseNotes.txt deleted file mode 100644 index bc10e713f9..0000000000 --- a/arch/m68k/mach-mcfv4e/mcdapi/ReleaseNotes.txt +++ /dev/null @@ -1,27 +0,0 @@ - -Multi-channel DMA API Release Notes - -Version 0.3 - -* MCD_INCLUDE_EU functionality supported(microcode changes for all tasks -except ethernet). -* Fixed bug when using MCD_END_FRAME which would cause the DMA to transfer -zero bytes and then complete. -* Code cleanup. - - -Version 0.2 (Slight Update) - -* Modified casts and task table implementations that were causing -warnings (and even errors on certain compilers) -* Cosmetic changes to clean up MCD_dmaApi.c and MCD_dma.h -* Fixed table declarations so that MCD_tasks.c will compile if - MCD_INCLUDE_EU is defined (Note: EU functionality still not supported) - -Version 0.1 (Initial release) - -Alpha version -MCD_INCLUDE_EU functionality not supported. -MCD_INCLUDE_JBIG not supported. - - diff --git a/arch/m68k/mach-mcfv4e/mcf_clocksource.c b/arch/m68k/mach-mcfv4e/mcf_clocksource.c deleted file mode 100644 index 8fb2fba2ec..0000000000 --- a/arch/m68k/mach-mcfv4e/mcf_clocksource.c +++ /dev/null @@ -1,138 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Implements the clocksource for Coldfire V4E - */ -#include <common.h> -#include <init.h> -#include <clock.h> -#include <mach/mcf54xx-regs.h> -#include <mach/clocks.h> -#include <proc/processor.h> //FIXME - move to other file - -#ifdef CONFIG_USE_IRQ - -static uint32_t mcf_sltirq_hits; // FIXME: test code - -static int slt_timer_default_isr(void *not_used, void *t) -{ - struct mcf5xxx_slt *slt = MCF_SLT_Address(0); - if ( MCF_INTC_IPRH | MCF_INTC_IPRH_INT54 ) - { - if (slt->SSR & MCF_SLT_SSR_ST) - { - slt->SSR = 0UL - | MCF_SLT_SSR_ST; - } - mcf_sltirq_hits++; - return 1; - } - return 0; -} -#endif - - -static uint64_t mcf_clocksource_read(void) -{ - struct mcf5xxx_slt *slt = MCF_SLT_Address(0); - uint32_t sltcnt; - uint64_t rc = 0; - - if (slt->SSR & MCF_SLT_SSR_ST) - { -#ifndef CONFIG_USE_IRQ - slt->SSR = 0UL - | MCF_SLT_SSR_ST; -#endif - - rc = 0xffffffffULL + 1; - } - - sltcnt = 0xffffffffUL - slt->SCNT; - - rc += sltcnt; - - return rc; -} - - -static struct clocksource cs = { - .read = mcf_clocksource_read, - .mask = 0xffffffff, - .mult = 1, - .shift = 0, -}; - -static int clocksource_init (void) -{ - struct mcf5xxx_slt *slt = MCF_SLT_Address(0); - uint32_t sltclk = mcfv4e_get_bus_clk() * 1000000; - - /* Setup a slice timer terminal count */ - slt->STCNT = 0xffffffff; - - /* Reset status bits */ - slt->SSR = 0UL - | MCF_SLT_SSR_ST - | MCF_SLT_SSR_BE; - - /* Start timer to run continously */ - slt->SCR = 0UL - | MCF_SLT_SCR_TEN - | MCF_SLT_SCR_RUN - | MCF_SLT_SCR_IEN; // FIXME - add irq handler - - /* Setup up multiplier */ - cs.mult = clocksource_hz2mult(sltclk, cs.shift); - - /* - * Register the timer interrupt handler - */ - init_clock(&cs); - - return 0; -} - -core_initcall(clocksource_init); - -#ifdef CONFIG_USE_IRQ - -static int clocksource_irq_init(void) -{ - if (!mcf_interrupts_register_handler( - 118, // FIXME! - (int (*)(void*,void*))slt_timer_default_isr, - NULL, - NULL) - ) - { - return 1; - } - // Setup ICR - MCF_INTC_ICR54 = MCF_INTC_ICRn_IL(1) | MCF_INTC_ICRn_IP(0); - // Enable IRQ source - MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK54; - return 0; -} - -postcore_initcall(clocksource_irq_init); - -#endif diff --git a/arch/m68k/mach-mcfv4e/mcf_reset_cpu.c b/arch/m68k/mach-mcfv4e/mcf_reset_cpu.c deleted file mode 100644 index d4659d22aa..0000000000 --- a/arch/m68k/mach-mcfv4e/mcf_reset_cpu.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Implements a watchdog triggered reset for V4e Coldfire cores - */ -#include <common.h> -#include <mach/mcf54xx-regs.h> - -/** - * Reset the cpu by setting up the watchdog timer and let it time out - */ -void __noreturn reset_cpu (unsigned long addr) -{ - while ( ignored ) { ; }; - - /* Disable watchdog and set Time-Out field to minimum timeout value */ - MCF_GPT_GMS0 = 0; - MCF_GPT_GCIR0 = MCF_GPT_GCIR_PRE(1) | MCF_GPT_GCIR_CNT(0xffff); - - /* Enable watchdog */ - MCF_GPT_GMS0 = MCF_GPT_GMS_OCPW(0xA5) | MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS_GPIO; - - while (1); - /*NOTREACHED*/ -} -EXPORT_SYMBOL(reset_cpu); - diff --git a/arch/m68k/mach-mcfv4e/multichannel_dma.c b/arch/m68k/mach-mcfv4e/multichannel_dma.c deleted file mode 100644 index acc104e4af..0000000000 --- a/arch/m68k/mach-mcfv4e/multichannel_dma.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * barebox Header File - * - * Generic Clocksource for V4E - * - * Copyright (c) 2007 Carsten Schlote <c.schlote\@konzeptpark.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include <common.h> -#include <init.h> -#include <mach/mcf54xx-regs.h> -#include <proc/mcdapi/MCD_dma.h> -#include <proc/dma_utils.h> - - -static int mcdapi_init(void) -{ - /* - * Initialize the Multi-channel DMA - */ - MCD_initDma ((dmaRegs*)(__MBAR+0x8000), - (void *)CFG_SYS_SRAM_ADDRESS, - MCD_COMM_PREFETCH_EN | MCD_RELOC_TASKS); - - /* - * Enable interrupts in DMA and INTC - */ - dma_irq_enable(DMA_INTC_LVL, DMA_INTC_PRI); - - return 0; -} - -postcore_initcall(mcdapi_init); - diff --git a/arch/m68k/mach-mcfv4e/net/Makefile b/arch/m68k/mach-mcfv4e/net/Makefile deleted file mode 100644 index 78c528f259..0000000000 --- a/arch/m68k/mach-mcfv4e/net/Makefile +++ /dev/null @@ -1,26 +0,0 @@ -# -# (C) Copyright 2007 Carsten Schlote <schlote@vahanus.net> -# See file CREDITS for list of people who contributed to this project. -# -# This file is part of barebox. -# -# barebox is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# barebox is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with barebox. If not, see <http://www.gnu.org/licenses/>. -# - -# -# Support code for current FEC driver code - must be eliminated later... -# -obj-y += nbuf.o queue.o net.o - - diff --git a/arch/m68k/mach-mcfv4e/net/nbuf.c b/arch/m68k/mach-mcfv4e/net/nbuf.c deleted file mode 100644 index 234e75821a..0000000000 --- a/arch/m68k/mach-mcfv4e/net/nbuf.c +++ /dev/null @@ -1,239 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Implementation of network buffer scheme. - * @todo Obsolete this file - */ -#include <common.h> -#include <malloc.h> -#include <linux/types.h> - -#include <proc/net/queue.h> -#include <proc/net/net.h> - -#include <mach/mcf54xx-regs.h> - - -#define ASSERT(x) - -/** - * Queues used for network buffer storage - */ -QUEUE nbuf_queue[NBUF_MAXQ]; - -/* - * Some devices require line-aligned buffers. In order to accomplish - * this, the nbuf data is over-allocated and adjusted. The following - * array keeps track of the original data pointer returned by malloc - */ -ADDRESS unaligned_buffers[NBUF_MAX]; - -/** - * Initialize all the network buffer queues - * - * Return Value: - * 0 success - * 1 failure - */ -int -nbuf_init(void) -{ - int i; - NBUF *nbuf; - - for (i=0; i<NBUF_MAXQ; ++i) - { - /* Initialize all the queues */ - queue_init(&nbuf_queue[i]); - } - - #ifdef CONFIG_DRIVER_NET_MCF54XX_DEBUG - printf("Creating %d net buffers of %d bytes\n",NBUF_MAX,NBUF_SZ); - #endif - - for (i=0; i<NBUF_MAX; ++i) - { - /* Allocate memory for the network buffer structure */ - nbuf = (NBUF *)malloc(sizeof(NBUF)); - if (!nbuf) - { - ASSERT(nbuf); - return 1; - } - - /* Allocate memory for the actual data */ - unaligned_buffers[i] = (ADDRESS)malloc(NBUF_SZ + 16); - nbuf->data = (uint8_t *)((uint32_t)(unaligned_buffers[i] + 15) & 0xFFFFFFF0); - if (!nbuf->data) - { - ASSERT(nbuf->data); - return 1; - } - - /* Initialize the network buffer */ - nbuf->offset = 0; - nbuf->length = 0; - - /* Add the network buffer to the free list */ - queue_add(&nbuf_queue[NBUF_FREE], (QNODE *)nbuf); - } - - #ifdef CONFIG_DRIVER_NET_MCF54XX_DEBUG - printf("NBUF allocation complete\n"); - nbuf_debug_dump(); - #endif - - return 0; -} -/** - * Return all the allocated memory to the heap - */ -void -nbuf_flush(void) -{ - NBUF *nbuf; - int i, level = asm_set_ipl(7); - int n = 0; - - for (i=0; i<NBUF_MAX; ++i) - free((uint8_t*)unaligned_buffers[i]); - - for (i=0; i<NBUF_MAXQ; ++i) - { - while ((nbuf = (NBUF *)queue_remove(&nbuf_queue[i])) != NULL) - { - free(nbuf); - ++n; - } - } - ASSERT(n == NBUF_MAX); - asm_set_ipl(level); -} -/** - * Allocate a network buffer from the free list - * - * Return Value: - * Pointer to a free network buffer - * NULL if none are available - */ -NBUF * -nbuf_alloc(void) -{ - NBUF *nbuf; - int level = asm_set_ipl(7); - - nbuf = (NBUF *)queue_remove(&nbuf_queue[NBUF_FREE]); - asm_set_ipl(level); - return nbuf; -} -/** - * Add the specified network buffer back to the free list - * - * Parameters: - * nbuf Buffer to add back to the free list - */ -void -nbuf_free(NBUF *nbuf) -{ - int level = asm_set_ipl(7); - - nbuf->offset = 0; - nbuf->length = NBUF_SZ; - queue_add(&nbuf_queue[NBUF_FREE],(QNODE *)nbuf); - - asm_set_ipl(level); -} -/** - * Remove a network buffer from the specified queue - * - * Parameters: - * q The index that identifies the queue to pull the buffer from - */ -NBUF * -nbuf_remove(int q) -{ - NBUF *nbuf; - int level = asm_set_ipl(7); - - nbuf = (NBUF *)queue_remove(&nbuf_queue[q]); - asm_set_ipl(level); - return nbuf; -} -/** - * Add a network buffer to the specified queue - * - * Parameters: - * q The index that identifies the queue to add the buffer to - */ -void -nbuf_add(int q, NBUF *nbuf) -{ - int level = asm_set_ipl(7); - queue_add(&nbuf_queue[q],(QNODE *)nbuf); - asm_set_ipl(level); -} -/** - * Put all the network buffers back into the free list - */ -void -nbuf_reset(void) -{ - NBUF *nbuf; - int i, level = asm_set_ipl(7); - - for (i=1; i<NBUF_MAXQ; ++i) - { - while ((nbuf = nbuf_remove(i)) != NULL) - nbuf_free(nbuf); - } - asm_set_ipl(level); -} -/** - * Display all the nbuf queues - */ -void -nbuf_debug_dump(void) -{ -#ifdef CONFIG_DRIVER_NET_MCF54XX_DEBUG - NBUF *nbuf; - int i, j, level; - - level = asm_set_ipl(7); - - for (i=0; i<NBUF_MAXQ; ++i) - { - printf("\n\nQueue #%d\n\n",i); - printf("\tBuffer Location\tOffset\tLength\n"); - printf("--------------------------------------\n"); - j = 0; - nbuf = (NBUF *)queue_peek(&nbuf_queue[i]); - while (nbuf != NULL) - { - printf("%d\t 0x%08x\t0x%04x\t0x%04x\n",j++,nbuf->data, - nbuf->offset, - nbuf->length); - nbuf = (NBUF *)nbuf->node.next; - } - } - - asm_set_ipl(level); -#endif -} diff --git a/arch/m68k/mach-mcfv4e/net/net.c b/arch/m68k/mach-mcfv4e/net/net.c deleted file mode 100644 index febabfeda0..0000000000 --- a/arch/m68k/mach-mcfv4e/net/net.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Network initialization for MCF V4E FEC support code - * @todo Obsolete this file - */ -#include <common.h> -#include <malloc.h> -#include <linux/types.h> - -#include <mach/mcf54xx-regs.h> -#include <proc/mcdapi/MCD_dma.h> -#include <proc/net/net.h> -#include <proc/fecbd.h> -#include <proc/fec.h> -#include <proc/dma_utils.h> - -#include <proc/processor.h> //FIXME - move to other file - -int netif_init(int channel) -{ - uint8_t* board_get_ethaddr(uint8_t*); - -#ifdef CONFIG_USE_IRQ - int vector; - int (*handler)(void *, void *); - - disable_interrupts(); - - /* - * Register the FEC0 interrupt handler - */ - handler = (channel == 0) ? fec0_interrupt_handler - : fec1_interrupt_handler; - vector = (channel == 0) ? 103 : 102; - - if (!mcf_interrupts_register_handler( - vector,handler, NULL,(void *)0xdeadbeef)) - { - printf("Error: Unable to register handler\n"); - return 0; - } - - /* - * Register the DMA interrupt handler - */ - handler = dma_interrupt_handler; - vector = 112; - - if (!mcf_interrupts_register_handler( - vector,handler, NULL,NULL)) - { - printf("Error: Unable to register handler\n"); - return 0; - } -#endif - /* - * Enable interrupts - */ - enable_interrupts(); - - return 1; -} - -int netif_setup(int channel) -{ - uint8_t mac[6]; - /* - * Get user programmed MAC address - */ -// board_get_ethaddr(mac); - - - /* - * Initialize the network interface structure - */ -// nif_init(&nif1); -// nif1.mtu = ETH_MTU; -// nif1.send = (DBUG_ETHERNET_PORT == 0) ? fec0_send : fec1_send; - - /* - * Initialize the dBUG Ethernet port - */ - fec_eth_setup(channel, /* Which FEC to use */ - FEC_MODE_MII, /* Use MII mode */ - FEC_MII_100BASE_TX, /* Allow 10 and 100Mbps */ - FEC_MII_FULL_DUPLEX, /* Allow Full and Half Duplex */ - mac); - - /* - * Copy the Ethernet address to the NIF structure - */ -// memcpy(nif1.hwa, mac, 6); - - #ifdef DEBUG - printf("Ethernet Address is %02X:%02X:%02X:%02X:%02X:%02X\n",\ - mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); - #endif - - return 1; -} - -int netif_done(int channel) -{ - /* - * Download complete, clean up - */ -#ifdef CONFIG_USE_IRQ - int (*handler)(void *, void *); -#endif - /* - * Disable interrupts - */ - disable_interrupts(); - - /* - * Disable the Instruction Cache - */ - mcf5xxx_wr_cacr(MCF5XXX_CACR_ICINVA); - - /* - * Disable the dBUG Ethernet port - */ - fec_eth_stop(channel); - - /* - * Remove the interrupt handlers - */ -#ifdef CONFIG_USE_IRQ - handler = (channel == 0) ? fec0_interrupt_handler - : fec1_interrupt_handler; - mcf_interrupts_remove_handler(handler); - mcf_interrupts_remove_handler(dma_interrupt_handler); -#endif - return 1; -} - - diff --git a/arch/m68k/mach-mcfv4e/net/queue.c b/arch/m68k/mach-mcfv4e/net/queue.c deleted file mode 100644 index 9f779474ea..0000000000 --- a/arch/m68k/mach-mcfv4e/net/queue.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> - * See file CREDITS for list of people who contributed to this project. - * - * This file is part of barebox. - * - * barebox is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * barebox is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with barebox. If not, see <http://www.gnu.org/licenses/>. - */ - -/** @file - * Implements a first in, first out linked list - * - * @note Simple selfcontaining basic code - * @todo Replace by barebox standard list functions - */ -#include <linux/types.h> -#include <proc/net/queue.h> - -/** Initialize the specified queue to an empty state - * - * @param[in] - * q Pointer to queue structure - */ -void queue_init(QUEUE *q) -{ - q->head = NULL; -} - -/** - * Check for an empty queue - * - * @param[in] q Pointer to queue structure - * @return - * 1 if Queue is empty - * 0 otherwise - */ -int -queue_isempty(QUEUE *q) -{ - return (q->head == NULL); -} - -/** - * Add an item to the end of the queue - * - * @param[in] q Pointer to queue structure - * @param[in] node New node to add to the queue - */ -void queue_add(QUEUE *q, QNODE *node) -{ - if (queue_isempty(q)) - { - q->head = q->tail = node; - } - else - { - q->tail->next = node; - q->tail = node; - } - - node->next = NULL; -} - -/** Remove and return first (oldest) entry from the specified queue - * - * @param[in] q Pointer to queue structure - * @return - * Node at head of queue - NULL if queue is empty - */ -QNODE* -queue_remove(QUEUE *q) -{ - QNODE *oldest; - - if (queue_isempty(q)) - return NULL; - - oldest = q->head; - q->head = oldest->next; - return oldest; -} - -/** Peek into the queue and return pointer to first (oldest) entry. - * - * The queue is not modified - * - * @param[in] q Pointer to queue structure - * @return - * Node at head of queue - NULL if queue is empty - */ -QNODE* -queue_peek(QUEUE *q) -{ - return q->head; -} - -/** Move entire contents of one queue to the other - * - * @param[in] src Pointer to source queue - * @param[in] dst Pointer to destination queue - */ -void -queue_move(QUEUE *dst, QUEUE *src) -{ - if (queue_isempty(src)) - return; - - if (queue_isempty(dst)) - dst->head = src->head; - else - dst->tail->next = src->head; - - dst->tail = src->tail; - src->head = NULL; - return; -} - diff --git a/arch/ppc/lib/time.c b/arch/ppc/lib/time.c index ee6cbdf676..04c71dfcc6 100644 --- a/arch/ppc/lib/time.c +++ b/arch/ppc/lib/time.c @@ -56,7 +56,7 @@ uint64_t ppc_clocksource_read(void) static struct clocksource cs = { .read = ppc_clocksource_read, - .mask = 0xffffffff, + .mask = CLOCKSOURCE_MASK(32), .shift = 15, }; diff --git a/arch/sandbox/board/clock.c b/arch/sandbox/board/clock.c index b15086432c..3afbc8d681 100644 --- a/arch/sandbox/board/clock.c +++ b/arch/sandbox/board/clock.c @@ -32,7 +32,7 @@ static uint64_t linux_clocksource_read(void) static struct clocksource cs = { .read = linux_clocksource_read, - .mask = 0xffffffff, + .mask = CLOCKSOURCE_MASK(32), .shift = 10, }; diff --git a/arch/x86/mach-i386/pit_timer.c b/arch/x86/mach-i386/pit_timer.c index b9f805e61f..ec97cee49b 100644 --- a/arch/x86/mach-i386/pit_timer.c +++ b/arch/x86/mach-i386/pit_timer.c @@ -56,7 +56,7 @@ static uint64_t pit_clocksource_read(void) static struct clocksource cs = { .read = pit_clocksource_read, - .mask = 0x0000ffff, + .mask = CLOCKSOURCE_MASK(16), .shift = 10, }; diff --git a/commands/bootm.c b/commands/bootm.c index 991431bf77..34164bcf08 100644 --- a/commands/bootm.c +++ b/commands/bootm.c @@ -481,5 +481,4 @@ void bz_internal_error(int errcode) * - @subpage arm_boot_preparation * - @subpage ppc_boot_preparation * - @subpage x86_boot_preparation - * - @subpage m68k_boot_preparation */ diff --git a/defaultenv/bin/_update b/defaultenv/bin/_update index 87e6922326..f736acc744 100644 --- a/defaultenv/bin/_update +++ b/defaultenv/bin/_update @@ -22,6 +22,14 @@ if [ x$mode = xtftp ]; then fi fi +if [ x$mode = xxmodem ]; then + loadb -f $image -c + if [ $? -ne 0 ] ; then + echo "loadb failed or cancelled! Update aborted." + exit 1 + fi +fi + unprotect $part echo @@ -36,7 +44,6 @@ echo if [ x$mode = xtftp ]; then tftp $image $part else - loadb -f $image -c cp $image $part fi diff --git a/defaultenv/bin/update b/defaultenv/bin/update index 3601177308..29c240b784 100644 --- a/defaultenv/bin/update +++ b/defaultenv/bin/update @@ -33,7 +33,7 @@ elif [ x${type} = xrootfs ]; then elif [ x${type} = xbarebox ]; then image=$bareboximage if [ x${image} = x ]; then - imamge=barebox.bin + image=barebox.bin fi else . /env/bin/_update_help diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index bc95195116..034bb6fe49 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -11,12 +11,12 @@ if NAND config NAND_IMX bool prompt "i.MX NAND driver" - depends on ARCH_IMX21 || ARCH_IMX27 || ARCH_IMX31 || ARCH_IMX35 || ARCH_IMX25 + depends on ARCH_IMX21 || ARCH_IMX27 || ARCH_IMX31 || ARCH_IMX35 || ARCH_IMX25 || ARCH_IMX51 config NAND_IMX_BOOT bool prompt "Support Starting barebox from NAND" - depends on NAND_IMX || NAND_IMX_V2 + depends on NAND_IMX && !ARCH_IMX51 choice depends on NAND_IMX_BOOT diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index b75a450278..56fafb035f 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2215,6 +2215,12 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, /* Select the device */ chip->select_chip(mtd, 0); + /* + * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) + * after power-up + */ + chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); + /* Send the command for reading device ID */ chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); diff --git a/drivers/mtd/nand/nand_imx.c b/drivers/mtd/nand/nand_imx.c index 63ba188789..9a15ab2c98 100644 --- a/drivers/mtd/nand/nand_imx.c +++ b/drivers/mtd/nand/nand_imx.c @@ -30,103 +30,107 @@ #include <asm/io.h> #include <errno.h> -#define DVR_VER "2.0" - #define nfc_is_v21() (cpu_is_mx25() || cpu_is_mx35()) #define nfc_is_v1() (cpu_is_mx31() || cpu_is_mx27() || cpu_is_mx21()) +#define nfc_is_v3_2() cpu_is_mx51() +#define nfc_is_v3() nfc_is_v3_2() + +#define NFC_V1_ECC_STATUS_RESULT 0x0c +#define NFC_V1_RSLTMAIN_AREA 0x0e +#define NFC_V1_RSLTSPARE_AREA 0x10 + +#define NFC_V2_ECC_STATUS_RESULT1 0x0c +#define NFC_V2_ECC_STATUS_RESULT2 0x0e +#define NFC_V2_SPAS 0x10 + +#define NFC_V1_V2_BUF_SIZE 0x00 +#define NFC_V1_V2_BUF_ADDR 0x04 +#define NFC_V1_V2_FLASH_ADDR 0x06 +#define NFC_V1_V2_FLASH_CMD 0x08 +#define NFC_V1_V2_CONFIG 0x0a + +#define NFC_V1_V2_WRPROT 0x12 +#define NFC_V1_UNLOCKSTART_BLKADDR 0x14 +#define NFC_V1_UNLOCKEND_BLKADDR 0x16 +#define NFC_V21_UNLOCKSTART_BLKADDR 0x20 +#define NFC_V21_UNLOCKEND_BLKADDR 0x22 +#define NFC_V1_V2_NF_WRPRST 0x18 +#define NFC_V1_V2_CONFIG1 0x1a +#define NFC_V1_V2_CONFIG2 0x1c + +#define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0) +#define NFC_V1_V2_CONFIG1_SP_EN (1 << 2) +#define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3) +#define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4) +#define NFC_V1_V2_CONFIG1_BIG (1 << 5) +#define NFC_V1_V2_CONFIG1_RST (1 << 6) +#define NFC_V1_V2_CONFIG1_CE (1 << 7) +#define NFC_V1_V2_CONFIG1_ONE_CYCLE (1 << 8) +#define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9) +#define NFC_V2_CONFIG1_FP_INT (1 << 11) + +#define NFC_V1_V2_CONFIG2_INT (1 << 15) + +#define NFC_V2_SPAS_SPARESIZE(spas) ((spas) >> 1) /* - * Addresses for NFC registers - */ -#define NFC_BUF_SIZE 0xE00 -#define NFC_BUF_ADDR 0xE04 -#define NFC_FLASH_ADDR 0xE06 -#define NFC_FLASH_CMD 0xE08 -#define NFC_CONFIG 0xE0A -#define NFC_ECC_STATUS_RESULT 0xE0C -#define NFC_RSLTMAIN_AREA 0xE0E -#define NFC_RSLTSPARE_AREA 0xE10 -#define NFC_SPAS 0xe10 -#define NFC_WRPROT 0xE12 -#define NFC_V1_UNLOCKSTART_BLKADDR 0xe14 -#define NFC_V1_UNLOCKEND_BLKADDR 0xe16 -#define NFC_V21_UNLOCKSTART_BLKADDR 0xe20 -#define NFC_V21_UNLOCKEND_BLKADDR 0xe22 -#define NFC_NF_WRPRST 0xE18 -#define NFC_CONFIG1 0xE1A -#define NFC_CONFIG2 0xE1C - -/* - * Addresses for NFC RAM BUFFER Main area 0 - */ -#define MAIN_AREA0 0x000 -#define MAIN_AREA1 0x200 -#define MAIN_AREA2 0x400 -#define MAIN_AREA3 0x600 - -/* - * Addresses for NFC SPARE BUFFER Spare area 0 - */ -#define SPARE_AREA0 0x800 -#define SPARE_AREA1 0x810 -#define SPARE_AREA2 0x820 -#define SPARE_AREA3 0x830 - -/* - * Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register for Command - * operation - */ -#define NFC_CMD 0x1 - -/* - * Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register for Address - * operation - */ -#define NFC_ADDR 0x2 - -/* - * Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register for Input - * operation - */ -#define NFC_INPUT 0x4 - -/* - * Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register for Data Output - * operation - */ -#define NFC_OUTPUT 0x8 - -/* - * Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register for Read ID - * operation - */ -#define NFC_ID 0x10 - -/* - * Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register for Read Status - * operation - */ -#define NFC_STATUS 0x20 - -/* - * Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read Status - * operation + * Operation modes for the NFC. Valid for v1, v2 and v3 + * type controllers. */ -#define NFC_INT 0x8000 - -#define NFC_ECC_MODE (1 << 0) -#define NFC_SP_EN (1 << 2) -#define NFC_ECC_EN (1 << 3) -#define NFC_INT_MSK (1 << 4) -#define NFC_BIG (1 << 5) -#define NFC_RST (1 << 6) -#define NFC_CE (1 << 7) -#define NFC_ONE_CYCLE (1 << 8) - -#define NFC_SPAS_16 8 -#define NFC_SPAS_64 32 -#define NFC_SPAS_128 64 -#define NFC_SPAS_218 109 +#define NFC_CMD (1 << 0) +#define NFC_ADDR (1 << 1) +#define NFC_INPUT (1 << 2) +#define NFC_OUTPUT (1 << 3) +#define NFC_ID (1 << 4) +#define NFC_STATUS (1 << 5) + +#define NFC_V3_FLASH_CMD (host->regs_axi + 0x00) +#define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04) + +#define NFC_V3_CONFIG1 (host->regs_axi + 0x34) +#define NFC_V3_CONFIG1_SP_EN (1 << 0) +#define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4) + +#define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38) + +#define NFC_V3_LAUNCH (host->regs_axi + 0x40) + +#define NFC_V3_WRPROT (host->regs_ip + 0x0) +#define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0) +#define NFC_V3_WRPROT_LOCK (1 << 1) +#define NFC_V3_WRPROT_UNLOCK (1 << 2) +#define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6) + +#define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04) + +#define NFC_V3_CONFIG2 (host->regs_ip + 0x24) +#define NFC_V3_CONFIG2_PS_512 (0 << 0) +#define NFC_V3_CONFIG2_PS_2048 (1 << 0) +#define NFC_V3_CONFIG2_PS_4096 (2 << 0) +#define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2) +#define NFC_V3_CONFIG2_ECC_EN (1 << 3) +#define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4) +#define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5) +#define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6) +#define NFC_V3_CONFIG2_PPB(x) (((x) & 0x3) << 7) +#define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12) +#define NFC_V3_CONFIG2_INT_MSK (1 << 15) +#define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24) +#define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16) + +#define NFC_V3_CONFIG3 (host->regs_ip + 0x28) +#define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0) +#define NFC_V3_CONFIG3_FW8 (1 << 3) +#define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8) +#define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12) +#define NFC_V3_CONFIG3_RBB_MODE (1 << 15) +#define NFC_V3_CONFIG3_NO_SDMA (1 << 20) + +#define NFC_V3_IPC (host->regs_ip + 0x2C) +#define NFC_V3_IPC_CREQ (1 << 0) +#define NFC_V3_IPC_INT (1 << 31) + +#define NFC_V3_DELAY_LINE (host->regs_ip + 0x34) #ifdef CONFIG_NAND_IMX_BOOT #define __nand_boot_init __bare_init @@ -142,10 +146,11 @@ struct imx_nand_host { void *spare0; void *main_area0; - void *main_area1; void __iomem *base; void __iomem *regs; + void __iomem *regs_axi; + void __iomem *regs_ip; int status_request; struct clk *clk; @@ -153,7 +158,15 @@ struct imx_nand_host { uint8_t *data_buf; unsigned int buf_start; int spare_len; - + int eccsize; + + void (*preset)(struct mtd_info *); + void (*send_cmd)(struct imx_nand_host *, uint16_t); + void (*send_addr)(struct imx_nand_host *, uint16_t); + void (*send_page)(struct imx_nand_host *, unsigned int); + void (*send_read_id)(struct imx_nand_host *); + uint16_t (*get_dev_status)(struct imx_nand_host *); + int (*check_int)(struct imx_nand_host *); }; /* @@ -215,16 +228,35 @@ static void memcpy32(void *trg, const void *src, int size) *t++ = *s++; } -/* - * This function polls the NANDFC to wait for the basic operation to complete by - * checking the INT bit of config2 register. - * - * @param max_retries number of retry attempts (separated by 1 us) - * @param param parameter for debug - */ +static int check_int_v3(struct imx_nand_host *host) +{ + uint32_t tmp; + + tmp = readl(NFC_V3_IPC); + if (!(tmp & NFC_V3_IPC_INT)) + return 0; + + tmp &= ~NFC_V3_IPC_INT; + writel(tmp, NFC_V3_IPC); + + return 1; +} + +static int check_int_v1_v2(struct imx_nand_host *host) +{ + uint32_t tmp; + + tmp = readw(host->regs + NFC_V1_V2_CONFIG2); + if (!(tmp & NFC_V1_V2_CONFIG2_INT)) + return 0; + + writew(tmp & ~NFC_V1_V2_CONFIG2_INT, host->regs + NFC_V1_V2_CONFIG2); + + return 1; +} + static void wait_op_done(struct imx_nand_host *host) { - u32 tmp; int i; /* This is a timeout of roughly 15ms on my system. We @@ -232,12 +264,8 @@ static void wait_op_done(struct imx_nand_host *host) * here as we might be here from nand booting. */ for (i = 0; i < 100000; i++) { - if (readw(host->regs + NFC_CONFIG2) & NFC_INT) { - tmp = readw(host->regs + NFC_CONFIG2); - tmp &= ~NFC_INT; - writew(tmp, host->regs + NFC_CONFIG2); + if (host->check_int(host)) return; - } } } @@ -247,19 +275,31 @@ static void wait_op_done(struct imx_nand_host *host) * * @param cmd command for NAND Flash */ -static void send_cmd(struct imx_nand_host *host, u16 cmd) +static void send_cmd_v3(struct imx_nand_host *host, uint16_t cmd) +{ + /* fill command */ + writel(cmd, NFC_V3_FLASH_CMD); + + /* send out command */ + writel(NFC_CMD, NFC_V3_LAUNCH); + + /* Wait for operation to complete */ + wait_op_done(host); +} + +static void send_cmd_v1_v2(struct imx_nand_host *host, u16 cmd) { MTD_DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd); - writew(cmd, host->regs + NFC_FLASH_CMD); - writew(NFC_CMD, host->regs + NFC_CONFIG2); + writew(cmd, host->regs + NFC_V1_V2_FLASH_CMD); + writew(NFC_CMD, host->regs + NFC_V1_V2_CONFIG2); if (cpu_is_mx21() && (cmd == NAND_CMD_RESET)) { /* Reset completion is indicated by NFC_CONFIG2 */ /* being set to 0 */ int i; for (i = 0; i < 100000; i++) { - if (readw(host->regs + NFC_CONFIG2) == 0) { + if (readw(host->regs + NFC_V1_V2_CONFIG2) == 0) { break; } } @@ -276,12 +316,23 @@ static void send_cmd(struct imx_nand_host *host, u16 cmd) * @param addr address to be written to NFC. * @param islast True if this is the last address cycle for command */ -static void send_addr(struct imx_nand_host *host, u16 addr) +static void send_addr_v3(struct imx_nand_host *host, uint16_t addr) +{ + /* fill address */ + writel(addr, NFC_V3_FLASH_ADDR0); + + /* send out address */ + writel(NFC_ADDR, NFC_V3_LAUNCH); + + wait_op_done(host); +} + +static void send_addr_v1_v2(struct imx_nand_host *host, u16 addr) { MTD_DEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x %d)\n", addr, islast); - writew(addr, host->regs + NFC_FLASH_ADDR); - writew(NFC_ADDR, host->regs + NFC_CONFIG2); + writew(addr, host->regs + NFC_V1_V2_FLASH_ADDR); + writew(NFC_ADDR, host->regs + NFC_V1_V2_CONFIG2); /* Wait for operation to complete */ wait_op_done(host); @@ -294,7 +345,21 @@ static void send_addr(struct imx_nand_host *host, u16 addr) * @param buf_id Specify Internal RAM Buffer number (0-3) * @param spare_only set true if only the spare area is transferred */ -static void send_page(struct imx_nand_host *host, +static void send_page_v3(struct imx_nand_host *host, unsigned int ops) +{ + uint32_t tmp; + + tmp = readl(NFC_V3_CONFIG1); + tmp &= ~(7 << 4); + writel(tmp, NFC_V3_CONFIG1); + + /* transfer data from NFC ram to nand */ + writel(ops, NFC_V3_LAUNCH); + + wait_op_done(host); +} + +static void send_page_v1_v2(struct imx_nand_host *host, unsigned int ops) { int bufs, i; @@ -306,9 +371,9 @@ static void send_page(struct imx_nand_host *host, for (i = 0; i < bufs; i++) { /* NANDFC buffer 0 is used for page read/write */ - writew(i, host->regs + NFC_BUF_ADDR); + writew(i, host->regs + NFC_V1_V2_BUF_ADDR); - writew(ops, host->regs + NFC_CONFIG2); + writew(ops, host->regs + NFC_V1_V2_CONFIG2); /* Wait for operation to complete */ wait_op_done(host); @@ -319,20 +384,24 @@ static void send_page(struct imx_nand_host *host, * This function requests the NANDFC to perform a read of the * NAND device ID. */ -static void send_read_id(struct imx_nand_host *host) +static void send_read_id_v3(struct imx_nand_host *host) +{ + /* Read ID into main buffer */ + writel(NFC_ID, NFC_V3_LAUNCH); + + wait_op_done(host); + + memcpy(host->data_buf, host->main_area0, 16); +} + +static void send_read_id_v1_v2(struct imx_nand_host *host) { struct nand_chip *this = &host->nand; - u16 tmp; /* NANDFC buffer 0 is used for device ID output */ - writew(0x0, host->regs + NFC_BUF_ADDR); - - /* Read ID into main buffer */ - tmp = readw(host->regs + NFC_CONFIG1); - tmp &= ~NFC_SP_EN; - writew(tmp, host->regs + NFC_CONFIG1); + writew(0x0, host->regs + NFC_V1_V2_BUF_ADDR); - writew(NFC_ID, host->regs + NFC_CONFIG2); + writew(NFC_ID, host->regs + NFC_V1_V2_CONFIG2); /* Wait for operation to complete */ wait_op_done(host); @@ -359,35 +428,39 @@ static void send_read_id(struct imx_nand_host *host) * * @return device status */ -static u16 get_dev_status(struct imx_nand_host *host) +static uint16_t get_dev_status_v3(struct imx_nand_host *host) { - volatile u16 *mainbuf = host->main_area1; + writew(NFC_STATUS, NFC_V3_LAUNCH); + wait_op_done(host); + + return readl(NFC_V3_CONFIG1) >> 16; +} + +static u16 get_dev_status_v1_v2(struct imx_nand_host *host) +{ + void *main_buf = host->main_area0; u32 store; - u16 ret, tmp; - /* Issue status request to NAND device */ + u16 ret; + + writew(0x0, host->regs + NFC_V1_V2_BUF_ADDR); - /* store the main area1 first word, later do recovery */ - store = *((u32 *) mainbuf); /* - * NANDFC buffer 1 is used for device status to prevent - * corruption of read/write buffer on status requests. + * The device status is stored in main_area0. To + * prevent corruption of the buffer save the value + * and restore it afterwards. */ - writew(1, host->regs + NFC_BUF_ADDR); - - /* Read status into main buffer */ - tmp = readw(host->regs + NFC_CONFIG1); - tmp &= ~NFC_SP_EN; - writew(tmp, host->regs + NFC_CONFIG1); + store = readl(main_buf); - writew(NFC_STATUS, host->regs + NFC_CONFIG2); + writew(NFC_STATUS, host->regs + NFC_V1_V2_CONFIG2); /* Wait for operation to complete */ wait_op_done(host); /* Status is placed in first word of main buffer */ /* get status, then recovery area 1 data */ - ret = mainbuf[0]; - *((u32 *) mainbuf) = store; + ret = readw(main_buf); + + writel(store, main_buf); return ret; } @@ -416,7 +489,7 @@ static void imx_nand_enable_hwecc(struct mtd_info *mtd, int mode) */ } -static int imx_nand_correct_data(struct mtd_info *mtd, u_char * dat, +static int imx_nand_correct_data_v1(struct mtd_info *mtd, u_char * dat, u_char * read_ecc, u_char * calc_ecc) { struct nand_chip *nand_chip = mtd->priv; @@ -427,7 +500,7 @@ static int imx_nand_correct_data(struct mtd_info *mtd, u_char * dat, * additional correction. 2-Bit errors cannot be corrected by * HW ECC, so we need to return failure */ - u16 ecc_status = readw(host->regs + NFC_ECC_STATUS_RESULT); + u16 ecc_status = readw(host->regs + NFC_V1_ECC_STATUS_RESULT); if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) { MTD_DEBUG(MTD_DEBUG_LEVEL0, @@ -438,6 +511,43 @@ static int imx_nand_correct_data(struct mtd_info *mtd, u_char * dat, return 0; } +static int imx_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat, + u_char *read_ecc, u_char *calc_ecc) +{ + struct nand_chip *nand_chip = mtd->priv; + struct imx_nand_host *host = nand_chip->priv; + u32 ecc_stat, err; + int no_subpages = 1; + int ret = 0; + u8 ecc_bit_mask, err_limit; + + ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf; + err_limit = (host->eccsize == 4) ? 0x4 : 0x8; + + no_subpages = mtd->writesize >> 9; + + if (nfc_is_v21()) + ecc_stat = readl(host->regs + NFC_V2_ECC_STATUS_RESULT1); + else + ecc_stat = readl(NFC_V3_ECC_STATUS_RESULT); + + do { + err = ecc_stat & ecc_bit_mask; + if (err > err_limit) { + printk(KERN_WARNING "UnCorrectable RS-ECC Error\n"); + return -1; + } else { + ret += err; + } + ecc_stat >>= 4; + } while (--no_subpages); + + mtd->ecc_stats.corrected += ret; + pr_debug("%d Symbol Correctable RS-ECC Error\n", ret); + + return ret; +} + static int imx_nand_calculate_ecc(struct mtd_info *mtd, const u_char * dat, u_char * ecc_code) { @@ -459,7 +569,7 @@ static u_char imx_nand_read_byte(struct mtd_info *mtd) /* Check for status request */ if (host->status_request) - return get_dev_status(host) & 0xFF; + return host->get_dev_status(host) & 0xFF; ret = *(uint8_t *)(host->data_buf + host->buf_start); host->buf_start++; @@ -627,37 +737,164 @@ static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr) * we will used the saved column adress to index into * the full page. */ - send_addr(host, 0); + host->send_addr(host, 0); if (host->pagesize_2k) /* another col addr cycle for 2k page */ - send_addr(host, 0); + host->send_addr(host, 0); } /* * Write out page address, if necessary */ if (page_addr != -1) { - send_addr(host, (page_addr & 0xff)); /* paddr_0 - p_addr_7 */ + host->send_addr(host, (page_addr & 0xff)); /* paddr_0 - p_addr_7 */ if (host->pagesize_2k) { - send_addr(host, (page_addr >> 8) & 0xFF); + host->send_addr(host, (page_addr >> 8) & 0xFF); if (mtd->size >= 0x10000000) { - send_addr(host, (page_addr >> 16) & 0xff); + host->send_addr(host, (page_addr >> 16) & 0xff); } } else { /* One more address cycle for higher density devices */ if (mtd->size >= 0x4000000) { /* paddr_8 - paddr_15 */ - send_addr(host, (page_addr >> 8) & 0xff); - send_addr(host, (page_addr >> 16) & 0xff); + host->send_addr(host, (page_addr >> 8) & 0xff); + host->send_addr(host, (page_addr >> 16) & 0xff); } else /* paddr_8 - paddr_15 */ - send_addr(host, (page_addr >> 8) & 0xff); + host->send_addr(host, (page_addr >> 8) & 0xff); } } } /* + * v2 and v3 type controllers can do 4bit or 8bit ecc depending + * on how much oob the nand chip has. For 8bit ecc we need at least + * 26 bytes of oob data per 512 byte block. + */ +static int get_eccsize(struct mtd_info *mtd) +{ + int oobbytes_per_512 = 0; + + oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize; + + if (oobbytes_per_512 < 26) + return 4; + else + return 8; +} + +static void preset_v1_v2(struct mtd_info *mtd) +{ + struct nand_chip *nand_chip = mtd->priv; + struct imx_nand_host *host = nand_chip->priv; + uint16_t config1 = 0; + + if (nand_chip->ecc.mode == NAND_ECC_HW) + config1 |= NFC_V1_V2_CONFIG1_ECC_EN; + + if (nfc_is_v21()) + config1 |= NFC_V2_CONFIG1_FP_INT; + + if (nfc_is_v21() && mtd->writesize) { + uint16_t pages_per_block = mtd->erasesize / mtd->writesize; + + host->eccsize = get_eccsize(mtd); + if (host->eccsize == 4) + config1 |= NFC_V2_CONFIG1_ECC_MODE_4; + + config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6); + } else { + host->eccsize = 1; + } + + writew(config1, host->regs + NFC_V1_V2_CONFIG1); + /* preset operation */ + + /* Unlock the internal RAM Buffer */ + writew(0x2, host->regs + NFC_V1_V2_CONFIG); + + /* Blocks to be unlocked */ + if (nfc_is_v21()) { + writew(0x0, host->regs + NFC_V21_UNLOCKSTART_BLKADDR); + writew(0xffff, host->regs + NFC_V21_UNLOCKEND_BLKADDR); + } else if (nfc_is_v1()) { + writew(0x0, host->regs + NFC_V1_UNLOCKSTART_BLKADDR); + writew(0x4000, host->regs + NFC_V1_UNLOCKEND_BLKADDR); + } else + BUG(); + + /* Unlock Block Command for given address range */ + writew(0x4, host->regs + NFC_V1_V2_WRPROT); +} + +static void preset_v3(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + struct imx_nand_host *host = chip->priv; + uint32_t config2, config3; + int i, addr_phases; + + writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1); + writel(NFC_V3_IPC_CREQ, NFC_V3_IPC); + + /* Unlock the internal RAM Buffer */ + writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK, + NFC_V3_WRPROT); + + /* Blocks to be unlocked */ + for (i = 0; i < NAND_MAX_CHIPS; i++) + writel(0x0 | (0xffff << 16), + NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2)); + + writel(0, NFC_V3_IPC); + + config2 = NFC_V3_CONFIG2_ONE_CYCLE | + NFC_V3_CONFIG2_2CMD_PHASES | + NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) | + NFC_V3_CONFIG2_ST_CMD(0x70) | + NFC_V3_CONFIG2_NUM_ADDR_PHASE0; + + if (chip->ecc.mode == NAND_ECC_HW) + config2 |= NFC_V3_CONFIG2_ECC_EN; + + addr_phases = fls(chip->pagemask) >> 3; + + if (mtd->writesize == 2048) { + config2 |= NFC_V3_CONFIG2_PS_2048; + config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases); + } else if (mtd->writesize == 4096) { + config2 |= NFC_V3_CONFIG2_PS_4096; + config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases); + } else { + config2 |= NFC_V3_CONFIG2_PS_512; + config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1); + } + + if (mtd->writesize) { + config2 |= NFC_V3_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6); + host->eccsize = get_eccsize(mtd); + if (host->eccsize == 8) + config2 |= NFC_V3_CONFIG2_ECC_MODE_8; + } + + writel(config2, NFC_V3_CONFIG2); + + config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) | + NFC_V3_CONFIG3_NO_SDMA | + NFC_V3_CONFIG3_RBB_MODE | + NFC_V3_CONFIG3_SBB(6) | /* Reset default */ + NFC_V3_CONFIG3_ADD_OP(0); + + if (!(chip->options & NAND_BUSWIDTH_16)) + config3 |= NFC_V3_CONFIG3_FW8; + + writel(config3, NFC_V3_CONFIG3); + + writel(0, NFC_V3_DELAY_LINE); +} + +/* * This function is used by the upper layer to write command to NAND Flash for * different operations to be carried out on NAND Flash * @@ -685,11 +922,15 @@ static void imx_nand_command(struct mtd_info *mtd, unsigned command, * Command pre-processing step */ switch (command) { + case NAND_CMD_RESET: + host->preset(mtd); + host->send_cmd(host, command); + break; case NAND_CMD_STATUS: host->buf_start = 0; host->status_request = 1; - send_cmd(host, command); + host->send_cmd(host, command); mxc_do_addr_cycle(mtd, column, page_addr); break; @@ -702,14 +943,14 @@ static void imx_nand_command(struct mtd_info *mtd, unsigned command, command = NAND_CMD_READ0; - send_cmd(host, command); + host->send_cmd(host, command); mxc_do_addr_cycle(mtd, column, page_addr); if (host->pagesize_2k) /* send read confirm command */ - send_cmd(host, NAND_CMD_READSTART); + host->send_cmd(host, NAND_CMD_READSTART); - send_page(host, NFC_OUTPUT); + host->send_page(host, NFC_OUTPUT); memcpy32(host->data_buf, host->main_area0, mtd->writesize); copy_spare(mtd, 1); @@ -733,15 +974,15 @@ static void imx_nand_command(struct mtd_info *mtd, unsigned command, /* Set program pointer to spare region */ if (!host->pagesize_2k) - send_cmd(host, NAND_CMD_READOOB); + host->send_cmd(host, NAND_CMD_READOOB); } else { host->buf_start = column; /* Set program pointer to page start */ if (!host->pagesize_2k) - send_cmd(host, NAND_CMD_READ0); + host->send_cmd(host, NAND_CMD_READ0); } - send_cmd(host, command); + host->send_cmd(host, command); mxc_do_addr_cycle(mtd, column, page_addr); break; @@ -749,22 +990,21 @@ static void imx_nand_command(struct mtd_info *mtd, unsigned command, case NAND_CMD_PAGEPROG: memcpy32(host->main_area0, host->data_buf, mtd->writesize); copy_spare(mtd, 0); - send_page(host, NFC_INPUT); - send_cmd(host, command); + host->send_page(host, NFC_INPUT); + host->send_cmd(host, command); mxc_do_addr_cycle(mtd, column, page_addr); break; case NAND_CMD_READID: - send_cmd(host, command); + host->send_cmd(host, command); mxc_do_addr_cycle(mtd, column, page_addr); host->buf_start = 0; - send_read_id(host); + host->send_read_id(host); break; case NAND_CMD_ERASE1: case NAND_CMD_ERASE2: - case NAND_CMD_RESET: - send_cmd(host, command); + host->send_cmd(host, command); mxc_do_addr_cycle(mtd, column, page_addr); break; } @@ -839,7 +1079,6 @@ static int __init imxnd_probe(struct device_d *dev) struct imx_nand_platform_data *pdata = dev->platform_data; struct imx_nand_host *host; struct nand_ecclayout *oob_smallpage, *oob_largepage; - u16 tmp; int err = 0; #ifdef CONFIG_ARCH_IMX27 @@ -858,20 +1097,45 @@ static int __init imxnd_probe(struct device_d *dev) host->base = (void __iomem *)dev->map_base; host->main_area0 = host->base; - host->main_area1 = host->base + 0x200; + + if (nfc_is_v1() || nfc_is_v21()) { + host->preset = preset_v1_v2; + host->send_cmd = send_cmd_v1_v2; + host->send_addr = send_addr_v1_v2; + host->send_page = send_page_v1_v2; + host->send_read_id = send_read_id_v1_v2; + host->get_dev_status = get_dev_status_v1_v2; + host->check_int = check_int_v1_v2; + } if (nfc_is_v21()) { - host->regs = host->base + 0x1000; + host->regs = host->base + 0x1e00; host->spare0 = host->base + 0x1000; host->spare_len = 64; oob_smallpage = &nandv2_hw_eccoob_smallpage; oob_largepage = &nandv2_hw_eccoob_largepage; } else if (nfc_is_v1()) { - host->regs = host->base; + host->regs = host->base + 0xe00; host->spare0 = host->base + 0x800; host->spare_len = 16; oob_smallpage = &nandv1_hw_eccoob_smallpage; oob_largepage = &nandv1_hw_eccoob_largepage; + } else if (nfc_is_v3_2()) { +#ifdef CONFIG_ARCH_IMX51 + host->regs_ip = (void *)MX51_NFC_BASE_ADDR; +#endif + host->regs_axi = host->base + 0x1e00; + host->spare0 = host->base + 0x1000; + host->spare_len = 64; + host->preset = preset_v3; + host->send_cmd = send_cmd_v3; + host->send_addr = send_addr_v3; + host->send_page = send_page_v3; + host->send_read_id = send_read_id_v3; + host->get_dev_status = get_dev_status_v3; + host->check_int = check_int_v3; + oob_smallpage = &nandv2_hw_eccoob_smallpage; + oob_largepage = &nandv2_hw_eccoob_largepage; } host->dev = dev; @@ -900,52 +1164,20 @@ static int __init imxnd_probe(struct device_d *dev) clk_enable(host->clk); #endif - tmp = readw(host->regs + NFC_CONFIG1); - tmp |= NFC_INT_MSK; - tmp &= ~NFC_SP_EN; - if (nfc_is_v21()) - /* currently no support for 218 byte OOB with stronger ECC */ - tmp |= NFC_ECC_MODE; - writew(tmp, host->regs + NFC_CONFIG1); - if (pdata->hw_ecc) { this->ecc.calculate = imx_nand_calculate_ecc; this->ecc.hwctl = imx_nand_enable_hwecc; - this->ecc.correct = imx_nand_correct_data; + if (nfc_is_v1()) + this->ecc.correct = imx_nand_correct_data_v1; + else + this->ecc.correct = imx_nand_correct_data_v2_v3; this->ecc.mode = NAND_ECC_HW; this->ecc.size = 512; - tmp = readw(host->regs + NFC_CONFIG1); - tmp |= NFC_ECC_EN; - writew(tmp, host->regs + NFC_CONFIG1); } else { this->ecc.size = 512; this->ecc.mode = NAND_ECC_SOFT; - tmp = readw(host->regs + NFC_CONFIG1); - tmp &= ~NFC_ECC_EN; - writew(tmp, host->regs + NFC_CONFIG1); - } - - /* Reset NAND */ - this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); - - /* preset operation */ - /* Unlock the internal RAM Buffer */ - writew(0x2, host->regs + NFC_CONFIG); - - /* Blocks to be unlocked */ - if (nfc_is_v21()) { - writew(0x0, host->regs + NFC_V21_UNLOCKSTART_BLKADDR); - writew(0xffff, host->regs + NFC_V21_UNLOCKEND_BLKADDR); - this->ecc.bytes = 9; - } else if (nfc_is_v1()) { - writew(0x0, host->regs + NFC_V1_UNLOCKSTART_BLKADDR); - writew(0x4000, host->regs + NFC_V1_UNLOCKEND_BLKADDR); - this->ecc.bytes = 3; } - /* Unlock Block Command for given address range */ - writew(0x4, host->regs + NFC_WRPROT); - this->ecc.layout = oob_smallpage; /* NAND bus width determines access funtions used by upper layer */ @@ -968,24 +1200,19 @@ static int __init imxnd_probe(struct device_d *dev) goto escan; } + /* Call preset again, with correct writesize this time */ + host->preset(mtd); + imx_nand_set_layout(mtd->writesize, pdata->width == 2 ? 16 : 8); if (mtd->writesize == 2048) { this->ecc.layout = oob_largepage; host->pagesize_2k = 1; - if (nfc_is_v21()) { - tmp = readw(host->regs + NFC_SPAS); - tmp &= 0xff00; - tmp |= NFC_SPAS_64; - writew(tmp, host->regs + NFC_SPAS); - } + if (nfc_is_v21()) + writew(NFC_V2_SPAS_SPARESIZE(64), host->regs + NFC_V2_SPAS); } else { - if (nfc_is_v21()) { - tmp = readw(host->regs + NFC_SPAS); - tmp &= 0xff00; - tmp |= NFC_SPAS_16; - writew(tmp, host->regs + NFC_SPAS); - } + if (nfc_is_v21()) + writew(NFC_V2_SPAS_SPARESIZE(16), host->regs + NFC_V2_SPAS); } /* second phase scan */ @@ -1018,14 +1245,14 @@ static void __nand_boot_init noinline imx_nandboot_wait_op_done(void *regs) u32 r; while (1) { - r = readw(regs + NFC_CONFIG2); - if (r & NFC_INT) + r = readw(regs + NFC_V1_V2_CONFIG2); + if (r & NFC_V1_V2_CONFIG2_INT) break; }; - r &= ~NFC_INT; + r &= ~NFC_V1_V2_CONFIG2_INT; - writew(r, regs + NFC_CONFIG2); + writew(r, regs + NFC_V1_V2_CONFIG2); } /* @@ -1036,8 +1263,8 @@ static void __nand_boot_init noinline imx_nandboot_wait_op_done(void *regs) */ static void __nand_boot_init imx_nandboot_send_cmd(void *regs, u16 cmd) { - writew(cmd, regs + NFC_FLASH_CMD); - writew(NFC_CMD, regs + NFC_CONFIG2); + writew(cmd, regs + NFC_V1_V2_FLASH_CMD); + writew(NFC_CMD, regs + NFC_V1_V2_CONFIG2); imx_nandboot_wait_op_done(regs); } @@ -1052,8 +1279,8 @@ static void __nand_boot_init imx_nandboot_send_cmd(void *regs, u16 cmd) */ static void __nand_boot_init noinline imx_nandboot_send_addr(void *regs, u16 addr) { - writew(addr, regs + NFC_FLASH_ADDR); - writew(NFC_ADDR, regs + NFC_CONFIG2); + writew(addr, regs + NFC_V1_V2_FLASH_ADDR); + writew(NFC_ADDR, regs + NFC_V1_V2_CONFIG2); /* Wait for operation to complete */ imx_nandboot_wait_op_done(regs); @@ -1088,9 +1315,9 @@ static void __nand_boot_init imx_nandboot_send_page(void *regs, for (i = 0; i < bufs; i++) { /* NANDFC buffer 0 is used for page read/write */ - writew(i, regs + NFC_BUF_ADDR); + writew(i, regs + NFC_V1_V2_BUF_ADDR); - writew(ops, regs + NFC_CONFIG2); + writew(ops, regs + NFC_V1_V2_CONFIG2); /* Wait for operation to complete */ imx_nandboot_wait_op_done(regs); @@ -1159,10 +1386,10 @@ void __nand_boot_init imx_nand_load_image(void *dest, int size) base = (void __iomem *)IMX_NFC_BASE; if (nfc_is_v21()) { - regs = base + 0x1000; + regs = base + 0x1e00; spare0 = base + 0x1000; } else if (nfc_is_v1()) { - regs = base; + regs = base + 0xe00; spare0 = base + 0x800; } @@ -1170,31 +1397,24 @@ void __nand_boot_init imx_nand_load_image(void *dest, int size) /* preset operation */ /* Unlock the internal RAM Buffer */ - writew(0x2, regs + NFC_CONFIG); + writew(0x2, regs + NFC_V1_V2_CONFIG); /* Unlock Block Command for given address range */ - writew(0x4, regs + NFC_WRPROT); + writew(0x4, regs + NFC_V1_V2_WRPROT); - tmp = readw(regs + NFC_CONFIG1); - tmp |= NFC_ECC_EN; + tmp = readw(regs + NFC_V1_V2_CONFIG1); + tmp |= NFC_V1_V2_CONFIG1_ECC_EN; if (nfc_is_v21()) /* currently no support for 218 byte OOB with stronger ECC */ - tmp |= NFC_ECC_MODE; - tmp &= ~(NFC_SP_EN | NFC_INT_MSK); - writew(tmp, regs + NFC_CONFIG1); + tmp |= NFC_V2_CONFIG1_ECC_MODE_4; + tmp &= ~(NFC_V1_V2_CONFIG1_SP_EN | NFC_V1_V2_CONFIG1_INT_MSK); + writew(tmp, regs + NFC_V1_V2_CONFIG1); if (nfc_is_v21()) { - if (pagesize_2k) { - tmp = readw(regs + NFC_SPAS); - tmp &= 0xff00; - tmp |= NFC_SPAS_64; - writew(tmp, regs + NFC_SPAS); - } else { - tmp = readw(regs + NFC_SPAS); - tmp &= 0xff00; - tmp |= NFC_SPAS_16; - writew(tmp, regs + NFC_SPAS); - } + if (pagesize_2k) + writew(NFC_V2_SPAS_SPARESIZE(64), regs + NFC_V2_SPAS); + else + writew(NFC_V2_SPAS_SPARESIZE(16), regs + NFC_V2_SPAS); } block = page = 0; diff --git a/drivers/mtd/nand/nand_s3c2410.c b/drivers/mtd/nand/nand_s3c2410.c index b989583050..fa4acf4638 100644 --- a/drivers/mtd/nand/nand_s3c2410.c +++ b/drivers/mtd/nand/nand_s3c2410.c @@ -96,7 +96,7 @@ struct s3c24x0_nand_host { struct mtd_partition *parts; struct device_d *dev; - unsigned long base; + void __iomem *base; }; /** @@ -120,7 +120,7 @@ static struct nand_ecclayout nand_hw_eccoob = { * @param[in] host Base address of the NAND controller * @param[in] cmd Command for NAND flash */ -static void __nand_boot_init send_cmd(unsigned long host, uint8_t cmd) +static void __nand_boot_init send_cmd(void __iomem *host, uint8_t cmd) { writeb(cmd, host + NFCMD); } @@ -130,7 +130,7 @@ static void __nand_boot_init send_cmd(unsigned long host, uint8_t cmd) * @param[in] host Base address of the NAND controller * @param[in] addr Address for the NAND flash */ -static void __nand_boot_init send_addr(unsigned long host, uint8_t addr) +static void __nand_boot_init send_addr(void __iomem *host, uint8_t addr) { writeb(addr, host + NFADDR); } @@ -139,7 +139,7 @@ static void __nand_boot_init send_addr(unsigned long host, uint8_t addr) * Enable the NAND flash access * @param[in] host Base address of the NAND controller */ -static void __nand_boot_init enable_cs(unsigned long host) +static void __nand_boot_init enable_cs(void __iomem *host) { #ifdef CONFIG_CPU_S3C2410 writew(readw(host + NFCONF) & ~NFCONF_nFCE, host + NFCONF); @@ -153,7 +153,7 @@ static void __nand_boot_init enable_cs(unsigned long host) * Disable the NAND flash access * @param[in] host Base address of the NAND controller */ -static void __nand_boot_init disable_cs(unsigned long host) +static void __nand_boot_init disable_cs(void __iomem *host) { #ifdef CONFIG_CPU_S3C2410 writew(readw(host + NFCONF) | NFCONF_nFCE, host + NFCONF); @@ -168,7 +168,7 @@ static void __nand_boot_init disable_cs(unsigned long host) * @param[in] host Base address of the NAND controller * @param[in] timing Timing to access the NAND memory */ -static void __nand_boot_init enable_nand_controller(unsigned long host, uint32_t timing) +static void __nand_boot_init enable_nand_controller(void __iomem *host, uint32_t timing) { #ifdef CONFIG_CPU_S3C2410 writew(timing + NFCONF_EN + NFCONF_nFCE, host + NFCONF); @@ -183,7 +183,7 @@ static void __nand_boot_init enable_nand_controller(unsigned long host, uint32_t * Diable the NAND flash controller * @param[in] host Base address of the NAND controller */ -static void __nand_boot_init disable_nand_controller(unsigned long host) +static void __nand_boot_init disable_nand_controller(void __iomem *host) { #ifdef CONFIG_CPU_S3C2410 writew(NFCONF_nFCE, host + NFCONF); @@ -359,7 +359,7 @@ static int s3c24x0_nand_probe(struct device_d *dev) return -ENOMEM; host->dev = dev; - host->base = dev->map_base; + host->base = IOMEM(dev->map_base); /* structures must be linked */ chip = &host->nand; @@ -375,7 +375,7 @@ static int s3c24x0_nand_probe(struct device_d *dev) chip->chip_delay = 50; chip->priv = host; - chip->IO_ADDR_R = chip->IO_ADDR_W = (void*)(dev->map_base + NFDATA); + chip->IO_ADDR_R = chip->IO_ADDR_W = IOMEM(dev->map_base + NFDATA); chip->cmd_ctrl = s3c24x0_nand_hwcontrol; chip->dev_ready = s3c24x0_nand_devready; @@ -418,13 +418,13 @@ static struct driver_d s3c24x0_nand_driver = { #ifdef CONFIG_S3C24XX_NAND_BOOT -static void __nand_boot_init wait_for_completion(unsigned long host) +static void __nand_boot_init wait_for_completion(void __iomem *host) { while (!(readw(host + NFSTAT) & NFSTAT_BUSY)) ; } -static void __nand_boot_init nfc_addr(unsigned long host, uint32_t offs) +static void __nand_boot_init nfc_addr(void __iomem *host, uint32_t offs) { send_addr(host, offs & 0xff); send_addr(host, (offs >> 9) & 0xff); @@ -447,7 +447,7 @@ static void __nand_boot_init nfc_addr(unsigned long host, uint32_t offs) */ void __nand_boot_init s3c24x0_nand_load_image(void *dest, int size, int page, int pagesize) { - unsigned long host = S3C24X0_NAND_BASE; + void __iomem *host = (void __iomem *)S3C24X0_NAND_BASE; int i; /* @@ -469,7 +469,7 @@ void __nand_boot_init s3c24x0_nand_load_image(void *dest, int size, int page, in wait_for_completion(host); /* copy one page (do *not* use readsb() here!)*/ for (i = 0; i < pagesize; i++) - writeb(readb(host + NFDATA), (unsigned long)(dest + i)); + writeb(readb(host + NFDATA), (void __iomem *)(dest + i)); disable_cs(host); page++; diff --git a/drivers/net/miidev.c b/drivers/net/miidev.c index 343eb406e0..3d552db06a 100644 --- a/drivers/net/miidev.c +++ b/drivers/net/miidev.c @@ -208,6 +208,7 @@ static struct driver_d miidev_drv = { int mii_register(struct mii_device *mdev) { mdev->dev.priv = mdev; + mdev->dev.id = -1; strcpy(mdev->dev.name, "miidev"); return register_device(&mdev->dev); diff --git a/drivers/net/smc91111.c b/drivers/net/smc91111.c index 605a7d8613..535e69a1d9 100644 --- a/drivers/net/smc91111.c +++ b/drivers/net/smc91111.c @@ -440,20 +440,20 @@ #define MEMORY_WAIT_TIME 16 struct accessors { - void (*ob)(unsigned, unsigned long); - void (*ow)(unsigned, unsigned long); - void (*ol)(unsigned long, unsigned long); - void (*osl)(unsigned long, const void*, int); - unsigned (*ib)(unsigned long); - unsigned (*iw)(unsigned long); - unsigned long (*il)(unsigned long); - void (*isl)(unsigned long, void*, int); + void (*ob)(unsigned, void __iomem *); + void (*ow)(unsigned, void __iomem *); + void (*ol)(unsigned long, void __iomem *); + void (*osl)(void __iomem *, const void *, int); + unsigned (*ib)(void __iomem *); + unsigned (*iw)(void __iomem *); + unsigned long (*il)(void __iomem *); + void (*isl)(void __iomem *, void*, int); }; struct smc91c111_priv { struct mii_device miidev; struct accessors a; - unsigned long base; + void __iomem *base; }; #if (SMC_DEBUG > 2 ) @@ -483,44 +483,44 @@ struct smc91c111_priv { #define ETH_ZLEN 60 -static void a_outb(unsigned value, unsigned long offset) +static void a_outb(unsigned value, void __iomem *offset) { writeb(value, offset); } -static void a_outw(unsigned value, unsigned long offset) +static void a_outw(unsigned value, void __iomem *offset) { writew(value, offset); } -static void a_outl(unsigned long value, unsigned long offset) +static void a_outl(unsigned long value, void __iomem *offset) { writel(value, offset); } -static void a_outsl(unsigned long offset, const void *data, int count) +static void a_outsl(void __iomem *offset, const void *data, int count) { - writesl((void*)offset, data, count); + writesl(offset, data, count); } -static unsigned a_inb(unsigned long offset) +static unsigned a_inb(void __iomem *offset) { return readb(offset); } -static unsigned a_inw(unsigned long offset) +static unsigned a_inw(void __iomem *offset) { return readw(offset); } -static unsigned long a_inl(unsigned long offset) +static unsigned long a_inl(void __iomem *offset) { return readl(offset); } -static inline void a_insl(unsigned long offset, void *data, int count) +static inline void a_insl(void __iomem *offset, void *data, int count) { - readsl((void*)offset, data, count); + readsl(offset, data, count); } /* access happens via a 32 bit bus */ @@ -1317,7 +1317,7 @@ static int smc91c111_probe(struct device_d *dev) priv->miidev.address = 0; priv->miidev.flags = 0; priv->miidev.edev = edev; - priv->base = dev->map_base; + priv->base = IOMEM(dev->map_base); smc91c111_reset(edev); diff --git a/drivers/nor/cfi_flash.c b/drivers/nor/cfi_flash.c index fa5e5ee86c..2fa2c6b900 100644 --- a/drivers/nor/cfi_flash.c +++ b/drivers/nor/cfi_flash.c @@ -61,8 +61,6 @@ * */ -#define NUM_ERASE_REGIONS 4 /* max. number of erase regions */ - static uint flash_offset_cfi[2]={FLASH_OFFSET_CFI,FLASH_OFFSET_CFI_ALT}; /* @@ -117,20 +115,20 @@ static void flash_add_byte (struct flash_info *info, cfiword_t * cword, uchar c) static int flash_write_cfiword (struct flash_info *info, ulong dest, cfiword_t cword) { - cfiptr_t cptr; + void *dstaddr; int flag; - cptr.cp = (uchar *) dest; + dstaddr = (uchar *) dest; /* Check if Flash is (sufficiently) erased */ if (bankwidth_is_1(info)) { - flag = ((cptr.cp[0] & cword.c) == cword.c); + flag = ((flash_read8(dstaddr) & cword.c) == cword.c); } else if (bankwidth_is_2(info)) { - flag = ((cptr.wp[0] & cword.w) == cword.w); + flag = ((flash_read16(dstaddr) & cword.w) == cword.w); } else if (bankwidth_is_4(info)) { - flag = ((cptr.lp[0] & cword.l) == cword.l); + flag = ((flash_read32(dstaddr) & cword.l) == cword.l); } else if (bankwidth_is_8(info)) { - flag = ((cptr.llp[0] & cword.ll) == cword.ll); + flag = ((flash_read64(dstaddr) & cword.ll) == cword.ll); } else return 2; @@ -159,61 +157,42 @@ void print_longlong (char *str, unsigned long long data) sprintf (&str[i * 2], "%2.2x", *cp++); } -static void flash_printqry (struct flash_info *info, flash_sect_t sect) +static void flash_printqry (struct cfi_qry *qry) { - cfiptr_t cptr; + u8 *p = (u8 *)qry; int x, y; + unsigned char c; - for (x = 0; x < 0x40; x += 16U / info->portwidth) { - cptr.cp = - flash_make_addr (info, sect, - x + FLASH_OFFSET_CFI_RESP); - debug ("%p : ", cptr.cp); - for (y = 0; y < 16; y++) { - debug ("%2.2x ", cptr.cp[y]); - } - debug (" "); + for (x = 0; x < sizeof(struct cfi_qry); x += 16) { + debug("%02x : ", x); + for (y = 0; y < 16; y++) + debug("%2.2x ", p[x + y]); + debug(" "); for (y = 0; y < 16; y++) { - if (cptr.cp[y] >= 0x20 && cptr.cp[y] <= 0x7e) { - debug ("%c", cptr.cp[y]); - } else { - debug ("."); - } + c = p[x + y]; + if (c >= 0x20 && c <= 0x7e) + debug("%c", c); + else + debug("."); } - debug ("\n"); + debug("\n"); } } #endif /* - * read a short word by swapping for ppc format. + * read a character at a port width address */ -static ushort flash_read_ushort (struct flash_info *info, flash_sect_t sect, uint offset) +uchar flash_read_uchar (struct flash_info *info, uint offset) { - uchar *addr; - ushort retval; - -#ifdef DEBUG - int x; -#endif - addr = flash_make_addr (info, sect, offset); + uchar *cp; -#ifdef DEBUG - debug ("ushort addr is at %p info->portwidth = %d\n", addr, - info->portwidth); - for (x = 0; x < 2 * info->portwidth; x++) { - debug ("addr[%x] = 0x%x\n", x, addr[x]); - } -#endif + cp = flash_make_addr (info, 0, offset); #if defined(__LITTLE_ENDIAN) - retval = ((addr[(info->portwidth)] << 8) | addr[0]); + return flash_read8(cp); #else - retval = ((addr[(2 * info->portwidth) - 1] << 8) | - addr[info->portwidth - 1]); + return flash_read8(cp + info->portwidth - 1); #endif - - debug ("retval = 0x%x\n", retval); - return retval; } /* @@ -234,17 +213,19 @@ static ulong flash_read_long (struct flash_info *info, flash_sect_t sect, uint o debug ("long addr is at %p info->portwidth = %d\n", addr, info->portwidth); for (x = 0; x < 4 * info->portwidth; x++) { - debug ("addr[%x] = 0x%x\n", x, addr[x]); + debug ("addr[%x] = 0x%x\n", x, flash_read8(addr + x)); } #endif #if defined(__LITTLE_ENDIAN) - retval = (addr[0] << 16) | (addr[(info->portwidth)] << 24) | - (addr[(2 * info->portwidth)]) | (addr[(3 * info->portwidth)] << 8); + retval = ((flash_read8(addr) << 16) | + (flash_read8(addr + info->portwidth) << 24) | + (flash_read8(addr + 2 * info->portwidth)) | + (flash_read8(addr + 3 * info->portwidth) << 8)); #else - retval = (addr[(2 * info->portwidth) - 1] << 24) | - (addr[(info->portwidth) - 1] << 16) | - (addr[(4 * info->portwidth) - 1] << 8) | - addr[(3 * info->portwidth) - 1]; + retval = ((flash_read8(addr + 2 * info->portwidth - 1) << 24) | + (flash_read8(addr + info->portwidth - 1) << 16) | + (flash_read8(addr + 4 * info->portwidth - 1) << 8) | + (flash_read8(addr + 3 * info->portwidth - 1))); #endif return retval; } @@ -254,7 +235,35 @@ static ulong flash_read_long (struct flash_info *info, flash_sect_t sect, uint o * http://www.jedec.org/download/search/jesd68.pdf * */ -static int flash_detect_cfi (struct flash_info *info) +u32 jedec_read_mfr(struct flash_info *info) +{ + int bank = 0; + uchar mfr; + + /* According to JEDEC "Standard Manufacturer's Identification Code" + * (http://www.jedec.org/download/search/jep106W.pdf) + * several first banks can contain 0x7f instead of actual ID + */ + do { + mfr = flash_read_uchar (info, + (bank << 8) | FLASH_OFFSET_MANUFACTURER_ID); + bank++; + } while (mfr == FLASH_ID_CONTINUATION); + + return mfr; +} + +static void flash_read_cfi (struct flash_info *info, void *buf, + unsigned int start, size_t len) +{ + u8 *p = buf; + unsigned int i; + + for (i = 0; i < len; i++) + p[i] = flash_read_uchar(info, start + i); +} + +static int flash_detect_cfi (struct flash_info *info, struct cfi_qry *qry) { int cfi_offset; debug ("flash detect cfi\n"); @@ -264,13 +273,17 @@ static int flash_detect_cfi (struct flash_info *info) for (info->chipwidth = FLASH_CFI_BY8; info->chipwidth <= info->portwidth; info->chipwidth <<= 1) { - flash_write_cmd (info, 0, 0, info->cmd_reset); + flash_write_cmd (info, 0, 0, AMD_CMD_RESET); + flash_write_cmd (info, 0, 0, FLASH_CMD_RESET); for (cfi_offset=0; cfi_offset < sizeof(flash_offset_cfi)/sizeof(uint); cfi_offset++) { flash_write_cmd (info, 0, flash_offset_cfi[cfi_offset], FLASH_CMD_CFI); if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q') && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) { - info->interface = flash_read_ushort (info, 0, FLASH_OFFSET_INTERFACE); + flash_read_cfi(info, qry, FLASH_OFFSET_CFI_RESP, + sizeof(struct cfi_qry)); + info->interface = le16_to_cpu(qry->interface_desc); + info->cfi_offset=flash_offset_cfi[cfi_offset]; debug ("device interface is %d\n", info->interface); @@ -301,8 +314,10 @@ static ulong flash_get_size (struct flash_info *info, ulong base) uchar num_erase_regions; int erase_region_size; int erase_region_count; - int geometry_reversed = 0; int cur_offset = 0; + struct cfi_qry qry; + + memset(&qry, 0, sizeof(qry)); info->ext_addr = 0; info->cfi_version = 0; @@ -316,9 +331,22 @@ static ulong flash_get_size (struct flash_info *info, ulong base) info->start[0] = base; info->protect = 0; - if (flash_detect_cfi (info)) { - info->vendor = flash_read_ushort (info, 0, - FLASH_OFFSET_PRIMARY_VENDOR); + if (flash_detect_cfi (info, &qry)) { + info->vendor = le16_to_cpu(qry.p_id); + info->ext_addr = le16_to_cpu(qry.p_adr); + num_erase_regions = qry.num_erase_regions; + + if (info->ext_addr) { + info->cfi_version = (ushort) flash_read_uchar (info, + info->ext_addr + 3) << 8; + info->cfi_version |= (ushort) flash_read_uchar (info, + info->ext_addr + 4); + } + +#ifdef DEBUG + flash_printqry (&qry); +#endif + switch (info->vendor) { #ifdef CONFIG_DRIVER_CFI_INTEL case CFI_CMDSET_INTEL_EXTENDED: @@ -338,53 +366,8 @@ static ulong flash_get_size (struct flash_info *info, ulong base) } info->cfi_cmd_set->flash_read_jedec_ids (info); flash_write_cmd (info, 0, info->cfi_offset, FLASH_CMD_CFI); - num_erase_regions = flash_read_uchar (info, - FLASH_OFFSET_NUM_ERASE_REGIONS); - info->ext_addr = flash_read_ushort (info, 0, - FLASH_OFFSET_EXT_QUERY_T_P_ADDR); - if (info->ext_addr) { - info->cfi_version = (ushort) flash_read_uchar (info, - info->ext_addr + 3) << 8; - info->cfi_version |= (ushort) flash_read_uchar (info, - info->ext_addr + 4); - } -#ifdef DEBUG - flash_printqry (info, 0); -#endif - switch (info->vendor) { - case CFI_CMDSET_INTEL_STANDARD: - case CFI_CMDSET_INTEL_EXTENDED: - default: - info->cmd_reset = FLASH_CMD_RESET; -#ifdef CFG_FLASH_PROTECTION - /* read legacy lock/unlock bit from intel flash */ - if (info->ext_addr) { - info->legacy_unlock = flash_read_uchar (info, - info->ext_addr + 5) & 0x08; - } -#endif - break; - case CFI_CMDSET_AMD_STANDARD: - case CFI_CMDSET_AMD_EXTENDED: - info->cmd_reset = AMD_CMD_RESET; - /* check if flash geometry needs reversal */ - if (num_erase_regions <= 1) - break; - /* reverse geometry if top boot part */ - if (info->cfi_version < 0x3131) { - /* CFI < 1.1, try to guess from device id */ - if ((info->device_id & 0x80) != 0) { - geometry_reversed = 1; - } - break; - } - /* CFI >= 1.1, deduct from top/bottom flag */ - /* note: ext_addr is valid since cfi_version > 0 */ - if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) { - geometry_reversed = 1; - } - break; - } + + info->cfi_cmd_set->flash_fixup (info, &qry); debug ("manufacturer is %d\n", info->vendor); debug ("manufacturer id is 0x%x\n", info->manufacturer_id); @@ -415,18 +398,14 @@ static ulong flash_get_size (struct flash_info *info, ulong base) num_erase_regions, NUM_ERASE_REGIONS); break; } - if (geometry_reversed) - tmp = flash_read_long (info, 0, - FLASH_OFFSET_ERASE_REGIONS + - (num_erase_regions - 1 - i) * 4); - else - tmp = flash_read_long (info, 0, - FLASH_OFFSET_ERASE_REGIONS + - i * 4); + + tmp = le32_to_cpu(qry.erase_region_info[i]); + debug("erase region %u: 0x%08lx\n", i, tmp); + + erase_region_count = (tmp & 0xffff) + 1; + tmp >>= 16; erase_region_size = (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128; - tmp >>= 16; - erase_region_count = (tmp & 0xffff) + 1; debug ("erase_region_count = %d erase_region_size = %d\n", erase_region_count, erase_region_size); @@ -464,23 +443,23 @@ static ulong flash_get_size (struct flash_info *info, ulong base) info->sector_count = sect_cnt; /* multiply the size by the number of chips */ - info->size = (1 << flash_read_uchar (info, FLASH_OFFSET_SIZE)) * size_ratio; - info->buffer_size = (1 << flash_read_ushort (info, 0, FLASH_OFFSET_BUFFER_SIZE)); - tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_ETOUT); - info->erase_blk_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_EMAX_TOUT))); - tmp = (1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT)) * - (1 << flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT)); + info->size = (1 << qry.dev_size) * size_ratio; + info->buffer_size = (1 << le16_to_cpu(qry.max_buf_write_size)); + tmp = 1 << qry.block_erase_timeout_typ; + info->erase_blk_tout = (tmp * (1 << qry.block_erase_timeout_max)); + tmp = (1 << qry.buf_write_timeout_typ) * + (1 << qry.buf_write_timeout_max); info->buffer_write_tout = tmp * 1000; - tmp = (1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT)) * - (1 << flash_read_uchar (info, FLASH_OFFSET_WMAX_TOUT)); + tmp = (1 << qry.word_write_timeout_typ) * + (1 << qry.word_write_timeout_max); info->write_tout = tmp * 1000; info->flash_id = FLASH_MAN_CFI; if ((info->interface == FLASH_CFI_X8X16) && (info->chipwidth == FLASH_CFI_BY8)) { info->portwidth >>= 1; /* XXX - Need to test on x8/x16 in parallel. */ } + flash_write_cmd (info, 0, 0, info->cmd_reset); } - flash_write_cmd (info, 0, 0, info->cmd_reset); return info->size; } @@ -542,7 +521,7 @@ static int cfi_erase(struct cdev *cdev, size_t count, unsigned long offset) static int write_buff (struct flash_info *info, const uchar * src, ulong addr, ulong cnt) { ulong wp; - ulong cp; + uchar *p; int aln; cfiword_t cword; int i, rc; @@ -551,28 +530,27 @@ static int write_buff (struct flash_info *info, const uchar * src, ulong addr, u int buffered_size; #endif /* get lower aligned address */ - /* get lower aligned address */ wp = (addr & ~(info->portwidth - 1)); /* handle unaligned start */ if ((aln = addr - wp) != 0) { cword.l = 0; - cp = wp; - for (i = 0; i < aln; ++i, ++cp) - flash_add_byte (info, &cword, (*(uchar *) cp)); + p = (uchar*)wp; + for (i = 0; i < aln; ++i) + flash_add_byte (info, &cword, flash_read8(p + i)); for (; (i < info->portwidth) && (cnt > 0); i++) { flash_add_byte (info, &cword, *src++); cnt--; - cp++; } - for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp) - flash_add_byte (info, &cword, (*(uchar *) cp)); + for (; (cnt == 0) && (i < info->portwidth); ++i) + flash_add_byte (info, &cword, flash_read8(p + i)); rc = flash_write_cfiword (info, wp, cword); - if (rc) + if (rc != 0) return rc; - wp = cp; + + wp += i; } /* handle the aligned part */ @@ -623,12 +601,13 @@ static int write_buff (struct flash_info *info, const uchar * src, ulong addr, u * handle unaligned tail bytes */ cword.l = 0; - for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) { + p = (uchar*)wp; + for (i = 0; (i < info->portwidth) && (cnt > 0); ++i) { flash_add_byte (info, &cword, *src++); --cnt; } - for (; i < info->portwidth; ++i, ++cp) { - flash_add_byte (info, &cword, (*(uchar *) cp)); + for (; i < info->portwidth; ++i) { + flash_add_byte (info, &cword, flash_read8(p + i)); } return flash_write_cfiword (info, wp, cword); @@ -638,12 +617,10 @@ static int flash_real_protect (struct flash_info *info, long sector, int prot) { int retcode = 0; - flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT); - if (prot) - flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET); - else - flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR); + retcode = info->cfi_cmd_set->flash_real_protect(info, sector, prot); + + if (retcode) + return retcode; if ((retcode = flash_status_check (info, sector, info->erase_blk_tout, @@ -888,35 +865,35 @@ void flash_write_cmd (struct flash_info *info, flash_sect_t sect, uint offset, u int flash_isequal (struct flash_info *info, flash_sect_t sect, uint offset, uchar cmd) { - cfiptr_t cptr; + void *addr; cfiword_t cword; int retval; - cptr.cp = flash_make_addr (info, sect, offset); + addr = flash_make_addr (info, sect, offset); flash_make_cmd (info, cmd, &cword); - debug ("is= cmd %x(%c) addr %p ", cmd, cmd, cptr.cp); + debug ("is= cmd %x(%c) addr %p ", cmd, cmd, addr); if (bankwidth_is_1(info)) { - debug ("is= %x %x\n", cptr.cp[0], cword.c); - retval = (cptr.cp[0] == cword.c); + debug ("is= %x %x\n", flash_read8(addr), cword.c); + retval = (flash_read8(addr) == cword.c); } else if (bankwidth_is_2(info)) { - debug ("is= %4.4x %4.4x\n", cptr.wp[0], cword.w); - retval = (cptr.wp[0] == cword.w); + debug ("is= %4.4x %4.4x\n", flash_read16(addr), cword.w); + retval = (flash_read16(addr) == cword.w); } else if (bankwidth_is_4(info)) { - debug ("is= %8.8lx %8.8lx\n", cptr.lp[0], cword.l); - retval = (cptr.lp[0] == cword.l); + debug ("is= %8.8lx %8.8lx\n", flash_read32(addr), cword.l); + retval = (flash_read32(addr) == cword.l); } else if (bankwidth_is_8(info)) { #ifdef DEBUG { char str1[20]; char str2[20]; - print_longlong (str1, cptr.llp[0]); + print_longlong (str1, flash_read32(addr)); print_longlong (str2, cword.ll); debug ("is= %s %s\n", str1, str2); } #endif - retval = (cptr.llp[0] == cword.ll); + retval = (flash_read32(addr) == cword.ll); } else retval = 0; @@ -925,20 +902,20 @@ int flash_isequal (struct flash_info *info, flash_sect_t sect, uint offset, ucha int flash_isset (struct flash_info *info, flash_sect_t sect, uint offset, uchar cmd) { - cfiptr_t cptr; + void *addr; cfiword_t cword; int retval; - cptr.cp = flash_make_addr (info, sect, offset); + addr = flash_make_addr (info, sect, offset); flash_make_cmd (info, cmd, &cword); if (bankwidth_is_1(info)) { - retval = ((cptr.cp[0] & cword.c) == cword.c); + retval = ((flash_read8(addr) & cword.c) == cword.c); } else if (bankwidth_is_2(info)) { - retval = ((cptr.wp[0] & cword.w) == cword.w); + retval = ((flash_read16(addr) & cword.w) == cword.w); } else if (bankwidth_is_4(info)) { - retval = ((cptr.lp[0] & cword.l) == cword.l); + retval = ((flash_read32(addr) & cword.l) == cword.l); } else if (bankwidth_is_8(info)) { - retval = ((cptr.llp[0] & cword.ll) == cword.ll); + retval = ((flash_read64(addr) & cword.ll) == cword.ll); } else retval = 0; diff --git a/drivers/nor/cfi_flash.h b/drivers/nor/cfi_flash.h index 057e56c6eb..f9023dcafa 100644 --- a/drivers/nor/cfi_flash.h +++ b/drivers/nor/cfi_flash.h @@ -59,6 +59,8 @@ struct flash_info { ushort ext_addr; /* extended query table address */ ushort cfi_version; /* cfi version */ ushort cfi_offset; /* offset for cfi query */ + ulong addr_unlock1; /* unlock address 1 for AMD flash roms */ + ulong addr_unlock2; /* unlock address 2 for AMD flash roms */ struct cfi_cmd_set *cfi_cmd_set; struct cdev cdev; #ifdef CONFIG_PARTITION_NEED_MTD @@ -69,6 +71,41 @@ struct flash_info { void *base; }; +#define NUM_ERASE_REGIONS 4 /* max. number of erase regions */ + +/* CFI standard query structure */ +struct cfi_qry { + u8 qry[3]; + u16 p_id; + u16 p_adr; + u16 a_id; + u16 a_adr; + u8 vcc_min; + u8 vcc_max; + u8 vpp_min; + u8 vpp_max; + u8 word_write_timeout_typ; + u8 buf_write_timeout_typ; + u8 block_erase_timeout_typ; + u8 chip_erase_timeout_typ; + u8 word_write_timeout_max; + u8 buf_write_timeout_max; + u8 block_erase_timeout_max; + u8 chip_erase_timeout_max; + u8 dev_size; + u16 interface_desc; + u16 max_buf_write_size; + u8 num_erase_regions; + u32 erase_region_info[NUM_ERASE_REGIONS]; +} __attribute__((packed)); + +struct cfi_pri_hdr { + u8 pri[3]; + u8 major_version; + u8 minor_version; +} __attribute__((packed)); + + struct cfi_cmd_set { int (*flash_write_cfibuffer) (struct flash_info *info, ulong dest, const uchar * cp, int len); int (*flash_erase_one) (struct flash_info *info, long sect); @@ -76,6 +113,8 @@ struct cfi_cmd_set { void (*flash_read_jedec_ids) (struct flash_info *info); void (*flash_prepare_write) (struct flash_info *info); int (*flash_status_check) (struct flash_info *info, flash_sect_t sector, uint64_t tout, char *prompt); + int (*flash_real_protect) (struct flash_info *info, long sector, int prot); + void (*flash_fixup) (struct flash_info *info, struct cfi_qry *qry); }; extern struct cfi_cmd_set cfi_cmd_set_intel; @@ -104,6 +143,8 @@ extern struct cfi_cmd_set cfi_cmd_set_amd; #define FLASH_STATUS_R 0x01 #define FLASH_STATUS_PROTECT 0x01 +#define FLASH_ID_CONTINUATION 0x7F + #define AMD_CMD_RESET 0xF0 #define AMD_CMD_WRITE 0xA0 #define AMD_CMD_ERASE_START 0x80 @@ -116,9 +157,9 @@ extern struct cfi_cmd_set cfi_cmd_set_amd; #define AMD_STATUS_TOGGLE 0x40 #define AMD_STATUS_ERROR 0x20 -#define AMD_ADDR_ERASE_START ((info->portwidth == FLASH_CFI_8BIT) ? 0xAAA : 0x555) -#define AMD_ADDR_START ((info->portwidth == FLASH_CFI_8BIT) ? 0xAAA : 0x555) -#define AMD_ADDR_ACK ((info->portwidth == FLASH_CFI_8BIT) ? 0x555 : 0x2AA) +#define ATM_CMD_UNLOCK_SECT 0x70 +#define ATM_CMD_SOFTLOCK_START 0x80 +#define ATM_CMD_LOCK_SECT 0x40 #define FLASH_OFFSET_MANUFACTURER_ID 0x00 #define FLASH_OFFSET_DEVICE_ID 0x01 @@ -182,6 +223,7 @@ extern struct cfi_cmd_set cfi_cmd_set_amd; #define FLASH_CFI_X8 0x00 #define FLASH_CFI_X16 0x01 #define FLASH_CFI_X8X16 0x02 +#define FLASH_CFI_X16X32 0x05 /* convert between bit value and numeric value */ #define CFI_FLASH_SHIFT_WIDTH 3 @@ -198,6 +240,47 @@ int flash_generic_status_check (struct flash_info *info, flash_sect_t sector, int flash_isequal (struct flash_info *info, flash_sect_t sect, uint offset, uchar cmd); void flash_make_cmd (struct flash_info *info, uchar cmd, void *cmdbuf); +static inline void flash_write8(u8 value, void *addr) +{ + writeb(value, addr); +} + +static inline void flash_write16(u16 value, void *addr) +{ + writew(value, addr); +} + +static inline void flash_write32(u32 value, void *addr) +{ + writel(value, addr); +} + +static inline void flash_write64(u64 value, void *addr) +{ + memcpy((void *)addr, &value, 8); +} + +static inline u8 flash_read8(void *addr) +{ + return readb(addr); +} + +static inline u16 flash_read16(void *addr) +{ + return readw(addr); +} + +static inline u32 flash_read32(void *addr) +{ + return readl(addr); +} + +static inline u64 flash_read64(void *addr) +{ + /* No architectures currently implement readq() */ + return *(volatile u64 *)addr; +} + /* * create an address based on the offset and the port width */ @@ -206,20 +289,8 @@ static inline uchar *flash_make_addr (struct flash_info *info, flash_sect_t sect return ((uchar *) (info->start[sect] + (offset * info->portwidth))); } -/* - * read a character at a port width address - */ -static inline uchar flash_read_uchar (struct flash_info *info, uint offset) -{ - uchar *cp; - - cp = flash_make_addr (info, 0, offset); -#if defined(__LITTLE_ENDIAN) - return (cp[0]); -#else - return (cp[info->portwidth - 1]); -#endif -} +uchar flash_read_uchar (struct flash_info *info, uint offset); +u32 jedec_read_mfr(struct flash_info *info); #ifdef CONFIG_DRIVER_CFI_BANK_WIDTH_1 #define bankwidth_is_1(info) (info->portwidth == 1) @@ -252,26 +323,19 @@ typedef union { unsigned long long ll; } cfiword_t; -typedef union { - volatile unsigned char *cp; - volatile unsigned short *wp; - volatile unsigned long *lp; - volatile unsigned long long *llp; -} cfiptr_t; - static inline void flash_write_word(struct flash_info *info, cfiword_t datum, void *addr) { if (bankwidth_is_1(info)) { debug("fw addr %p val %02x\n", addr, datum.c); - writeb(datum.c, addr); + flash_write8(datum.c, addr); } else if (bankwidth_is_2(info)) { debug("fw addr %p val %04x\n", addr, datum.w); - writew(datum.w, addr); + flash_write16(datum.w, addr); } else if (bankwidth_is_4(info)) { debug("fw addr %p val %08x\n", addr, datum.l); - writel(datum.l, addr); + flash_write32(datum.l, addr); } else if (bankwidth_is_8(info)) { - memcpy((void *)addr, &datum.ll, 8); + flash_write64(datum.ll, addr); } } diff --git a/drivers/nor/cfi_flash_amd.c b/drivers/nor/cfi_flash_amd.c index 45b7e5ce99..b1d7070b6d 100644 --- a/drivers/nor/cfi_flash_amd.c +++ b/drivers/nor/cfi_flash_amd.c @@ -2,10 +2,27 @@ #include <stdio.h> #include "cfi_flash.h" +/*----------------------------------------------------------------------- + * Reverse the order of the erase regions in the CFI QRY structure. + * This is needed for chips that are either a) correctly detected as + * top-boot, or b) buggy. + */ +static void cfi_reverse_geometry(struct cfi_qry *qry) +{ + unsigned int i, j; + u32 tmp; + + for (i = 0, j = qry->num_erase_regions - 1; i < j; i++, j--) { + tmp = qry->erase_region_info[i]; + qry->erase_region_info[i] = qry->erase_region_info[j]; + qry->erase_region_info[j] = tmp; + } +} + static void flash_unlock_seq (struct flash_info *info) { - flash_write_cmd (info, 0, AMD_ADDR_START, AMD_CMD_UNLOCK_START); - flash_write_cmd (info, 0, AMD_ADDR_ACK, AMD_CMD_UNLOCK_ACK); + flash_write_cmd (info, 0, info->addr_unlock1, AMD_CMD_UNLOCK_START); + flash_write_cmd (info, 0, info->addr_unlock2, AMD_CMD_UNLOCK_ACK); } /* @@ -16,16 +33,35 @@ static void flash_unlock_seq (struct flash_info *info) */ static void amd_read_jedec_ids (struct flash_info *info) { + info->cmd_reset = AMD_CMD_RESET; info->manufacturer_id = 0; info->device_id = 0; info->device_id2 = 0; - flash_write_cmd(info, 0, 0, AMD_CMD_RESET); + /* calculate command offsets as in the Linux driver */ + info->addr_unlock1 = 0x555; + info->addr_unlock2 = 0x2AA; + + /* + * modify the unlock address if we are in compatibility mode + */ + if ( /* x8/x16 in x8 mode */ + ((info->chipwidth == FLASH_CFI_BY8) && + (info->interface == FLASH_CFI_X8X16)) || + /* x16/x32 in x16 mode */ + ((info->chipwidth == FLASH_CFI_BY16) && + (info->interface == FLASH_CFI_X16X32))) + { + info->addr_unlock1 = 0xaaa; + info->addr_unlock2 = 0x555; + } + + flash_write_cmd(info, 0, 0, info->cmd_reset); flash_unlock_seq(info); - flash_write_cmd(info, 0, AMD_ADDR_START, FLASH_CMD_READ_ID); + flash_write_cmd(info, 0, info->addr_unlock1, FLASH_CMD_READ_ID); udelay(1000); /* some flash are slow to respond */ - info->manufacturer_id = flash_read_uchar (info, - FLASH_OFFSET_MANUFACTURER_ID); + + info->manufacturer_id = jedec_read_mfr(info); info->device_id = flash_read_uchar (info, FLASH_OFFSET_DEVICE_ID); if (info->device_id == 0x7E) { @@ -36,26 +72,26 @@ static void amd_read_jedec_ids (struct flash_info *info) info->device_id2 |= flash_read_uchar (info, FLASH_OFFSET_DEVICE_ID3); } - flash_write_cmd(info, 0, 0, AMD_CMD_RESET); + flash_write_cmd(info, 0, 0, info->cmd_reset); } static int flash_toggle (struct flash_info *info, flash_sect_t sect, uint offset, uchar cmd) { - cfiptr_t cptr; + void *addr; cfiword_t cword; int retval; - cptr.cp = flash_make_addr (info, sect, offset); + addr = flash_make_addr (info, sect, offset); flash_make_cmd (info, cmd, &cword); if (bankwidth_is_1(info)) { - retval = ((cptr.cp[0] & cword.c) != (cptr.cp[0] & cword.c)); + retval = flash_read8(addr) != flash_read8(addr); } else if (bankwidth_is_2(info)) { - retval = ((cptr.wp[0] & cword.w) != (cptr.wp[0] & cword.w)); + retval = flash_read16(addr) != flash_read16(addr); } else if (bankwidth_is_4(info)) { - retval = ((cptr.lp[0] & cword.l) != (cptr.lp[0] & cword.l)); + retval = flash_read32(addr) != flash_read32(addr); } else if (bankwidth_is_8(info)) { - retval = ((cptr.llp[0] & cword.ll) != - (cptr.llp[0] & cword.ll)); + retval = ( (flash_read32( addr ) != flash_read32( addr )) || + (flash_read32(addr+4) != flash_read32(addr+4)) ); } else retval = 0; @@ -74,7 +110,7 @@ static int amd_flash_is_busy (struct flash_info *info, flash_sect_t sect) static int amd_flash_erase_one (struct flash_info *info, long sect) { flash_unlock_seq(info); - flash_write_cmd (info, 0, AMD_ADDR_ERASE_START, AMD_CMD_ERASE_START); + flash_write_cmd (info, 0, info->addr_unlock1, AMD_CMD_ERASE_START); flash_unlock_seq(info); flash_write_cmd (info, sect, 0, AMD_CMD_ERASE_SECTOR); @@ -84,7 +120,7 @@ static int amd_flash_erase_one (struct flash_info *info, long sect) static void amd_flash_prepare_write(struct flash_info *info) { flash_unlock_seq(info); - flash_write_cmd (info, 0, AMD_ADDR_START, AMD_CMD_WRITE); + flash_write_cmd (info, 0, info->addr_unlock1, AMD_CMD_WRITE); } #ifdef CONFIG_CFI_BUFFER_WRITE @@ -94,12 +130,10 @@ static int amd_flash_write_cfibuffer (struct flash_info *info, ulong dest, const flash_sect_t sector; int cnt; int retcode; - volatile cfiptr_t src; - volatile cfiptr_t dst; + void *src = (void*)cp; + void *dst = (void *)dest; cfiword_t cword; - src.cp = (uchar *)cp; - dst.cp = (uchar *) dest; sector = find_sector (info, dest); flash_unlock_seq(info); @@ -109,19 +143,31 @@ static int amd_flash_write_cfibuffer (struct flash_info *info, ulong dest, const if (bankwidth_is_1(info)) { cnt = len; flash_write_cmd (info, sector, 0, (uchar) cnt - 1); - while (cnt-- > 0) *dst.cp++ = *src.cp++; + while (cnt-- > 0) { + flash_write8(flash_read8(src), dst); + src += 1, dst += 1; + } } else if (bankwidth_is_2(info)) { cnt = len >> 1; flash_write_cmd (info, sector, 0, (uchar) cnt - 1); - while (cnt-- > 0) *dst.wp++ = *src.wp++; + while (cnt-- > 0) { + flash_write16(flash_read16(src), dst); + src += 2, dst += 2; + } } else if (bankwidth_is_4(info)) { cnt = len >> 2; flash_write_cmd (info, sector, 0, (uchar) cnt - 1); - while (cnt-- > 0) *dst.lp++ = *src.lp++; + while (cnt-- > 0) { + flash_write32(flash_read32(src), dst); + src += 4, dst += 4; + } } else if (bankwidth_is_8(info)) { cnt = len >> 3; flash_write_cmd (info, sector, 0, (uchar) cnt - 1); - while (cnt-- > 0) *dst.llp++ = *src.llp++; + while (cnt-- > 0) { + flash_write64(flash_read64(src), dst); + src += 8, dst += 8; + } } flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM); @@ -133,6 +179,82 @@ static int amd_flash_write_cfibuffer (struct flash_info *info, ulong dest, const #define amd_flash_write_cfibuffer NULL #endif /* CONFIG_CFI_BUFFER_WRITE */ +static int amd_flash_real_protect (struct flash_info *info, long sector, int prot) +{ + if (info->manufacturer_id != (uchar)ATM_MANUFACT) + return 0; + + if (prot) { + flash_unlock_seq (info); + flash_write_cmd (info, 0, info->addr_unlock1, + ATM_CMD_SOFTLOCK_START); + flash_unlock_seq (info); + flash_write_cmd (info, sector, 0, ATM_CMD_LOCK_SECT); + } else { + flash_write_cmd (info, 0, info->addr_unlock1, + AMD_CMD_UNLOCK_START); + if (info->device_id == ATM_ID_BV6416) + flash_write_cmd (info, sector, 0, + ATM_CMD_UNLOCK_SECT); + } + + return 0; +} + +/* + * Manufacturer-specific quirks. Add workarounds for geometry + * reversal, etc. here. + */ +static void flash_fixup_amd (struct flash_info *info, struct cfi_qry *qry) +{ + /* check if flash geometry needs reversal */ + if (qry->num_erase_regions > 1) { + /* reverse geometry if top boot part */ + if (info->cfi_version < 0x3131) { + /* CFI < 1.1, try to guess from device id */ + if ((info->device_id & 0x80) != 0) + cfi_reverse_geometry(qry); + } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) { + /* CFI >= 1.1, deduct from top/bottom flag */ + /* note: ext_addr is valid since cfi_version > 0 */ + cfi_reverse_geometry(qry); + } + } +} + +static void flash_fixup_atmel(struct flash_info *info, struct cfi_qry *qry) +{ + int reverse_geometry = 0; + + /* Check the "top boot" bit in the PRI */ + if (info->ext_addr && !(flash_read_uchar(info, info->ext_addr + 6) & 1)) + reverse_geometry = 1; + + /* AT49BV6416(T) list the erase regions in the wrong order. + * However, the device ID is identical with the non-broken + * AT49BV642D since u-boot only reads the low byte (they + * differ in the high byte.) So leave out this fixup for now. + */ + if (info->device_id == 0xd6 || info->device_id == 0xd2) + reverse_geometry = !reverse_geometry; + + if (reverse_geometry) + cfi_reverse_geometry(qry); +} + +static void amd_flash_fixup(struct flash_info *info, struct cfi_qry *qry) +{ + /* Do manufacturer-specific fixups */ + switch (info->manufacturer_id) { + case 0x0001: + flash_fixup_amd(info, qry); + break; + case 0x001f: + flash_fixup_atmel(info, qry); + break; + } +} + struct cfi_cmd_set cfi_cmd_set_amd = { .flash_write_cfibuffer = amd_flash_write_cfibuffer, .flash_erase_one = amd_flash_erase_one, @@ -140,5 +262,7 @@ struct cfi_cmd_set cfi_cmd_set_amd = { .flash_read_jedec_ids = amd_read_jedec_ids, .flash_prepare_write = amd_flash_prepare_write, .flash_status_check = flash_generic_status_check, + .flash_real_protect = amd_flash_real_protect, + .flash_fixup = amd_flash_fixup, }; diff --git a/drivers/nor/cfi_flash_intel.c b/drivers/nor/cfi_flash_intel.c index 43447609d8..c3cbad55f9 100644 --- a/drivers/nor/cfi_flash_intel.c +++ b/drivers/nor/cfi_flash_intel.c @@ -9,18 +9,19 @@ */ static void intel_read_jedec_ids (struct flash_info *info) { + info->cmd_reset = FLASH_CMD_RESET; info->manufacturer_id = 0; info->device_id = 0; info->device_id2 = 0; - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); + flash_write_cmd(info, 0, 0, info->cmd_reset); flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID); udelay(1000); /* some flash are slow to respond */ - info->manufacturer_id = flash_read_uchar (info, - FLASH_OFFSET_MANUFACTURER_ID); + + info->manufacturer_id = jedec_read_mfr(info); info->device_id = flash_read_uchar (info, FLASH_OFFSET_DEVICE_ID); - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); + flash_write_cmd(info, 0, 0, info->cmd_reset); } /* @@ -54,11 +55,9 @@ static int intel_flash_write_cfibuffer (struct flash_info *info, ulong dest, con flash_sect_t sector; int cnt; int retcode; - volatile cfiptr_t src; - volatile cfiptr_t dst; + void *src = (void*)cp; + void *dst = (void *)dest; - src.cp = (uchar *)cp; - dst.cp = (uchar *) dest; sector = find_sector (info, dest); flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); @@ -74,13 +73,17 @@ static int intel_flash_write_cfibuffer (struct flash_info *info, ulong dest, con flash_write_cmd (info, sector, 0, (uchar) cnt - 1); while (cnt-- > 0) { if (bankwidth_is_1(info)) { - *dst.cp++ = *src.cp++; + flash_write8(flash_read8(src), dst); + src += 1, dst += 1; } else if (bankwidth_is_2(info)) { - *dst.wp++ = *src.wp++; + flash_write16(flash_read16(src), dst); + src += 2, dst += 2; } else if (bankwidth_is_4(info)) { - *dst.lp++ = *src.lp++; + flash_write32(flash_read32(src), dst); + src += 4, dst += 4; } else if (bankwidth_is_8(info)) { - *dst.llp++ = *src.llp++; + flash_write64(flash_read64(src), dst); + src += 8, dst += 8; } } @@ -126,6 +129,29 @@ static int intel_flash_status_check (struct flash_info *info, flash_sect_t secto return retcode; } +static int intel_flash_real_protect (struct flash_info *info, long sector, int prot) +{ + flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); + flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT); + if (prot) + flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET); + else + flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR); + + return 0; +} + +static void intel_flash_fixup (struct flash_info *info, struct cfi_qry *qry) +{ +#ifdef CFG_FLASH_PROTECTION + /* read legacy lock/unlock bit from intel flash */ + if (info->ext_addr) { + info->legacy_unlock = flash_read_uchar (info, + info->ext_addr + 5) & 0x08; + } +#endif +} + struct cfi_cmd_set cfi_cmd_set_intel = { .flash_write_cfibuffer = intel_flash_write_cfibuffer, .flash_erase_one = intel_flash_erase_one, @@ -133,5 +159,7 @@ struct cfi_cmd_set cfi_cmd_set_intel = { .flash_read_jedec_ids = intel_read_jedec_ids, .flash_prepare_write = intel_flash_prepare_write, .flash_status_check = intel_flash_status_check, + .flash_real_protect = intel_flash_real_protect, + .flash_fixup = intel_flash_fixup, }; diff --git a/include/clock.h b/include/clock.h index 278f6e87b2..b9acdb9b69 100644 --- a/include/clock.h +++ b/include/clock.h @@ -3,6 +3,8 @@ #ifndef CLOCK_H #define CLOCK_H +#define CLOCKSOURCE_MASK(bits) (uint64_t)((bits) < 64 ? ((1ULL<<(bits))-1) : -1) + struct clocksource { uint32_t shift; uint32_t mult; diff --git a/include/common.h b/include/common.h index 394542f762..a14bfc10ce 100644 --- a/include/common.h +++ b/include/common.h @@ -220,4 +220,6 @@ int memory_display(char *addr, ulong offs, ulong nbytes, int size); extern const char version_string[]; +#define IOMEM(addr) ((void __force __iomem *)(addr)) + #endif /* __COMMON_H_ */ diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index cb35fd2000..6671a72a58 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -359,10 +359,10 @@ struct nand_buffers { * (determine if errors are correctable) * @write_page: [REPLACEABLE] High-level page write function */ - struct nand_chip { - void *IO_ADDR_R; - void *IO_ADDR_W; + + void __iomem *IO_ADDR_R; + void __iomem *IO_ADDR_W; uint8_t (*read_byte)(struct mtd_info *mtd); u16 (*read_word)(struct mtd_info *mtd); diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl new file mode 100755 index 0000000000..151c53a464 --- /dev/null +++ b/scripts/checkpatch.pl @@ -0,0 +1,2950 @@ +#!/usr/bin/perl -w +# (c) 2001, Dave Jones. (the file handling bit) +# (c) 2005, Joel Schopp <jschopp@austin.ibm.com> (the ugly bit) +# (c) 2007,2008, Andy Whitcroft <apw@uk.ibm.com> (new conditions, test suite) +# (c) 2008-2010 Andy Whitcroft <apw@canonical.com> +# Licensed under the terms of the GNU GPL License version 2 + +use strict; + +my $P = $0; +$P =~ s@.*/@@g; + +my $V = '0.31'; + +use Getopt::Long qw(:config no_auto_abbrev); + +my $quiet = 0; +my $tree = 1; +my $chk_signoff = 1; +my $chk_patch = 1; +my $tst_only; +my $emacs = 0; +my $terse = 0; +my $file = 0; +my $check = 0; +my $summary = 1; +my $mailback = 0; +my $summary_file = 0; +my $root; +my %debug; +my $help = 0; + +sub help { + my ($exitcode) = @_; + + print << "EOM"; +Usage: $P [OPTION]... [FILE]... +Version: $V + +Options: + -q, --quiet quiet + --no-tree run without a kernel tree + --no-signoff do not check for 'Signed-off-by' line + --patch treat FILE as patchfile (default) + --emacs emacs compile window format + --terse one line per report + -f, --file treat FILE as regular source file + --subjective, --strict enable more subjective tests + --root=PATH PATH to the kernel tree root + --no-summary suppress the per-file summary + --mailback only produce a report in case of warnings/errors + --summary-file include the filename in summary + --debug KEY=[0|1] turn on/off debugging of KEY, where KEY is one of + 'values', 'possible', 'type', and 'attr' (default + is all off) + --test-only=WORD report only warnings/errors containing WORD + literally + -h, --help, --version display this help and exit + +When FILE is - read standard input. +EOM + + exit($exitcode); +} + +GetOptions( + 'q|quiet+' => \$quiet, + 'tree!' => \$tree, + 'signoff!' => \$chk_signoff, + 'patch!' => \$chk_patch, + 'emacs!' => \$emacs, + 'terse!' => \$terse, + 'f|file!' => \$file, + 'subjective!' => \$check, + 'strict!' => \$check, + 'root=s' => \$root, + 'summary!' => \$summary, + 'mailback!' => \$mailback, + 'summary-file!' => \$summary_file, + + 'debug=s' => \%debug, + 'test-only=s' => \$tst_only, + 'h|help' => \$help, + 'version' => \$help +) or help(1); + +help(0) if ($help); + +my $exit = 0; + +if ($#ARGV < 0) { + print "$P: no input files\n"; + exit(1); +} + +my $dbg_values = 0; +my $dbg_possible = 0; +my $dbg_type = 0; +my $dbg_attr = 0; +for my $key (keys %debug) { + ## no critic + eval "\${dbg_$key} = '$debug{$key}';"; + die "$@" if ($@); +} + +my $rpt_cleaners = 0; + +if ($terse) { + $emacs = 1; + $quiet++; +} + +if ($tree) { + if (defined $root) { + if (!top_of_kernel_tree($root)) { + die "$P: $root: --root does not point at a valid tree\n"; + } + } else { + if (top_of_kernel_tree('.')) { + $root = '.'; + } elsif ($0 =~ m@(.*)/scripts/[^/]*$@ && + top_of_kernel_tree($1)) { + $root = $1; + } + } + + if (!defined $root) { + print "Must be run from the top-level dir. of a kernel tree\n"; + exit(2); + } +} + +my $emitted_corrupt = 0; + +our $Ident = qr{ + [A-Za-z_][A-Za-z\d_]* + (?:\s*\#\#\s*[A-Za-z_][A-Za-z\d_]*)* + }x; +our $Storage = qr{extern|static|asmlinkage}; +our $Sparse = qr{ + __user| + __kernel| + __force| + __iomem| + __must_check| + __init_refok| + __kprobes| + __ref + }x; + +# Notes to $Attribute: +# We need \b after 'init' otherwise 'initconst' will cause a false positive in a check +our $Attribute = qr{ + const| + __percpu| + __nocast| + __safe| + __bitwise__| + __packed__| + __packed2__| + __naked| + __maybe_unused| + __always_unused| + __noreturn| + __used| + __cold| + __noclone| + __deprecated| + __read_mostly| + __kprobes| + __(?:mem|cpu|dev|)(?:initdata|initconst|init\b)| + ____cacheline_aligned| + ____cacheline_aligned_in_smp| + ____cacheline_internodealigned_in_smp| + __weak + }x; +our $Modifier; +our $Inline = qr{inline|__always_inline|noinline}; +our $Member = qr{->$Ident|\.$Ident|\[[^]]*\]}; +our $Lval = qr{$Ident(?:$Member)*}; + +our $Constant = qr{(?:[0-9]+|0x[0-9a-fA-F]+)[UL]*}; +our $Assignment = qr{(?:\*\=|/=|%=|\+=|-=|<<=|>>=|&=|\^=|\|=|=)}; +our $Compare = qr{<=|>=|==|!=|<|>}; +our $Operators = qr{ + <=|>=|==|!=| + =>|->|<<|>>|<|>|!|~| + &&|\|\||,|\^|\+\+|--|&|\||\+|-|\*|\/|% + }x; + +our $NonptrType; +our $Type; +our $Declare; + +our $UTF8 = qr { + [\x09\x0A\x0D\x20-\x7E] # ASCII + | [\xC2-\xDF][\x80-\xBF] # non-overlong 2-byte + | \xE0[\xA0-\xBF][\x80-\xBF] # excluding overlongs + | [\xE1-\xEC\xEE\xEF][\x80-\xBF]{2} # straight 3-byte + | \xED[\x80-\x9F][\x80-\xBF] # excluding surrogates + | \xF0[\x90-\xBF][\x80-\xBF]{2} # planes 1-3 + | [\xF1-\xF3][\x80-\xBF]{3} # planes 4-15 + | \xF4[\x80-\x8F][\x80-\xBF]{2} # plane 16 +}x; + +our $typeTypedefs = qr{(?x: + (?:__)?(?:u|s|be|le)(?:8|16|32|64)| + atomic_t +)}; + +our $logFunctions = qr{(?x: + printk| + pr_(debug|dbg|vdbg|devel|info|warning|err|notice|alert|crit|emerg|cont)| + (dev|netdev|netif)_(printk|dbg|vdbg|info|warn|err|notice|alert|crit|emerg|WARN)| + WARN| + panic +)}; + +our @typeList = ( + qr{void}, + qr{(?:unsigned\s+)?char}, + qr{(?:unsigned\s+)?short}, + qr{(?:unsigned\s+)?int}, + qr{(?:unsigned\s+)?long}, + qr{(?:unsigned\s+)?long\s+int}, + qr{(?:unsigned\s+)?long\s+long}, + qr{(?:unsigned\s+)?long\s+long\s+int}, + qr{unsigned}, + qr{float}, + qr{double}, + qr{bool}, + qr{struct\s+$Ident}, + qr{union\s+$Ident}, + qr{enum\s+$Ident}, + qr{${Ident}_t}, + qr{${Ident}_handler}, + qr{${Ident}_handler_fn}, +); +our @modifierList = ( + qr{fastcall}, +); + +our $allowed_asm_includes = qr{(?x: + irq| + memory +)}; +# memory.h: ARM has a custom one + +sub build_types { + my $mods = "(?x: \n" . join("|\n ", @modifierList) . "\n)"; + my $all = "(?x: \n" . join("|\n ", @typeList) . "\n)"; + $Modifier = qr{(?:$Attribute|$Sparse|$mods)}; + $NonptrType = qr{ + (?:$Modifier\s+|const\s+)* + (?: + (?:typeof|__typeof__)\s*\(\s*\**\s*$Ident\s*\)| + (?:$typeTypedefs\b)| + (?:${all}\b) + ) + (?:\s+$Modifier|\s+const)* + }x; + $Type = qr{ + $NonptrType + (?:[\s\*]+\s*const|[\s\*]+|(?:\s*\[\s*\])+)? + (?:\s+$Inline|\s+$Modifier)* + }x; + $Declare = qr{(?:$Storage\s+)?$Type}; +} +build_types(); + +$chk_signoff = 0 if ($file); + +my @dep_includes = (); +my @dep_functions = (); +my $removal = "Documentation/feature-removal-schedule.txt"; +if ($tree && -f "$root/$removal") { + open(my $REMOVE, '<', "$root/$removal") || + die "$P: $removal: open failed - $!\n"; + while (<$REMOVE>) { + if (/^Check:\s+(.*\S)/) { + for my $entry (split(/[, ]+/, $1)) { + if ($entry =~ m@include/(.*)@) { + push(@dep_includes, $1); + + } elsif ($entry !~ m@/@) { + push(@dep_functions, $entry); + } + } + } + } + close($REMOVE); +} + +my @rawlines = (); +my @lines = (); +my $vname; +for my $filename (@ARGV) { + my $FILE; + if ($file) { + open($FILE, '-|', "diff -u /dev/null $filename") || + die "$P: $filename: diff failed - $!\n"; + } elsif ($filename eq '-') { + open($FILE, '<&STDIN'); + } else { + open($FILE, '<', "$filename") || + die "$P: $filename: open failed - $!\n"; + } + if ($filename eq '-') { + $vname = 'Your patch'; + } else { + $vname = $filename; + } + while (<$FILE>) { + chomp; + push(@rawlines, $_); + } + close($FILE); + if (!process($filename)) { + $exit = 1; + } + @rawlines = (); + @lines = (); +} + +exit($exit); + +sub top_of_kernel_tree { + my ($root) = @_; + + my @tree_check = ( + "arch", "commands", "common", "COPYING", "CREDITS", "defaultenv", + "Documentation", "Doxyfile", "drivers", "fs", "include", "lib", + "MAKEALL", "Makefile", "net", "README", "scripts", "TODO" + ); + + foreach my $check (@tree_check) { + if (! -e $root . '/' . $check) { + return 0; + } + } + return 1; +} + +sub expand_tabs { + my ($str) = @_; + + my $res = ''; + my $n = 0; + for my $c (split(//, $str)) { + if ($c eq "\t") { + $res .= ' '; + $n++; + for (; ($n % 8) != 0; $n++) { + $res .= ' '; + } + next; + } + $res .= $c; + $n++; + } + + return $res; +} +sub copy_spacing { + (my $res = shift) =~ tr/\t/ /c; + return $res; +} + +sub line_stats { + my ($line) = @_; + + # Drop the diff line leader and expand tabs + $line =~ s/^.//; + $line = expand_tabs($line); + + # Pick the indent from the front of the line. + my ($white) = ($line =~ /^(\s*)/); + + return (length($line), length($white)); +} + +my $sanitise_quote = ''; + +sub sanitise_line_reset { + my ($in_comment) = @_; + + if ($in_comment) { + $sanitise_quote = '*/'; + } else { + $sanitise_quote = ''; + } +} +sub sanitise_line { + my ($line) = @_; + + my $res = ''; + my $l = ''; + + my $qlen = 0; + my $off = 0; + my $c; + + # Always copy over the diff marker. + $res = substr($line, 0, 1); + + for ($off = 1; $off < length($line); $off++) { + $c = substr($line, $off, 1); + + # Comments we are wacking completly including the begin + # and end, all to $;. + if ($sanitise_quote eq '' && substr($line, $off, 2) eq '/*') { + $sanitise_quote = '*/'; + + substr($res, $off, 2, "$;$;"); + $off++; + next; + } + if ($sanitise_quote eq '*/' && substr($line, $off, 2) eq '*/') { + $sanitise_quote = ''; + substr($res, $off, 2, "$;$;"); + $off++; + next; + } + if ($sanitise_quote eq '' && substr($line, $off, 2) eq '//') { + $sanitise_quote = '//'; + + substr($res, $off, 2, $sanitise_quote); + $off++; + next; + } + + # A \ in a string means ignore the next character. + if (($sanitise_quote eq "'" || $sanitise_quote eq '"') && + $c eq "\\") { + substr($res, $off, 2, 'XX'); + $off++; + next; + } + # Regular quotes. + if ($c eq "'" || $c eq '"') { + if ($sanitise_quote eq '') { + $sanitise_quote = $c; + + substr($res, $off, 1, $c); + next; + } elsif ($sanitise_quote eq $c) { + $sanitise_quote = ''; + } + } + + #print "c<$c> SQ<$sanitise_quote>\n"; + if ($off != 0 && $sanitise_quote eq '*/' && $c ne "\t") { + substr($res, $off, 1, $;); + } elsif ($off != 0 && $sanitise_quote eq '//' && $c ne "\t") { + substr($res, $off, 1, $;); + } elsif ($off != 0 && $sanitise_quote && $c ne "\t") { + substr($res, $off, 1, 'X'); + } else { + substr($res, $off, 1, $c); + } + } + + if ($sanitise_quote eq '//') { + $sanitise_quote = ''; + } + + # The pathname on a #include may be surrounded by '<' and '>'. + if ($res =~ /^.\s*\#\s*include\s+\<(.*)\>/) { + my $clean = 'X' x length($1); + $res =~ s@\<.*\>@<$clean>@; + + # The whole of a #error is a string. + } elsif ($res =~ /^.\s*\#\s*(?:error|warning)\s+(.*)\b/) { + my $clean = 'X' x length($1); + $res =~ s@(\#\s*(?:error|warning)\s+).*@$1$clean@; + } + + return $res; +} + +sub ctx_statement_block { + my ($linenr, $remain, $off) = @_; + my $line = $linenr - 1; + my $blk = ''; + my $soff = $off; + my $coff = $off - 1; + my $coff_set = 0; + + my $loff = 0; + + my $type = ''; + my $level = 0; + my @stack = (); + my $p; + my $c; + my $len = 0; + + my $remainder; + while (1) { + @stack = (['', 0]) if ($#stack == -1); + + #warn "CSB: blk<$blk> remain<$remain>\n"; + # If we are about to drop off the end, pull in more + # context. + if ($off >= $len) { + for (; $remain > 0; $line++) { + last if (!defined $lines[$line]); + next if ($lines[$line] =~ /^-/); + $remain--; + $loff = $len; + $blk .= $lines[$line] . "\n"; + $len = length($blk); + $line++; + last; + } + # Bail if there is no further context. + #warn "CSB: blk<$blk> off<$off> len<$len>\n"; + if ($off >= $len) { + last; + } + } + $p = $c; + $c = substr($blk, $off, 1); + $remainder = substr($blk, $off); + + #warn "CSB: c<$c> type<$type> level<$level> remainder<$remainder> coff_set<$coff_set>\n"; + + # Handle nested #if/#else. + if ($remainder =~ /^#\s*(?:ifndef|ifdef|if)\s/) { + push(@stack, [ $type, $level ]); + } elsif ($remainder =~ /^#\s*(?:else|elif)\b/) { + ($type, $level) = @{$stack[$#stack - 1]}; + } elsif ($remainder =~ /^#\s*endif\b/) { + ($type, $level) = @{pop(@stack)}; + } + + # Statement ends at the ';' or a close '}' at the + # outermost level. + if ($level == 0 && $c eq ';') { + last; + } + + # An else is really a conditional as long as its not else if + if ($level == 0 && $coff_set == 0 && + (!defined($p) || $p =~ /(?:\s|\}|\+)/) && + $remainder =~ /^(else)(?:\s|{)/ && + $remainder !~ /^else\s+if\b/) { + $coff = $off + length($1) - 1; + $coff_set = 1; + #warn "CSB: mark coff<$coff> soff<$soff> 1<$1>\n"; + #warn "[" . substr($blk, $soff, $coff - $soff + 1) . "]\n"; + } + + if (($type eq '' || $type eq '(') && $c eq '(') { + $level++; + $type = '('; + } + if ($type eq '(' && $c eq ')') { + $level--; + $type = ($level != 0)? '(' : ''; + + if ($level == 0 && $coff < $soff) { + $coff = $off; + $coff_set = 1; + #warn "CSB: mark coff<$coff>\n"; + } + } + if (($type eq '' || $type eq '{') && $c eq '{') { + $level++; + $type = '{'; + } + if ($type eq '{' && $c eq '}') { + $level--; + $type = ($level != 0)? '{' : ''; + + if ($level == 0) { + if (substr($blk, $off + 1, 1) eq ';') { + $off++; + } + last; + } + } + $off++; + } + # We are truly at the end, so shuffle to the next line. + if ($off == $len) { + $loff = $len + 1; + $line++; + $remain--; + } + + my $statement = substr($blk, $soff, $off - $soff + 1); + my $condition = substr($blk, $soff, $coff - $soff + 1); + + #warn "STATEMENT<$statement>\n"; + #warn "CONDITION<$condition>\n"; + + #print "coff<$coff> soff<$off> loff<$loff>\n"; + + return ($statement, $condition, + $line, $remain + 1, $off - $loff + 1, $level); +} + +sub statement_lines { + my ($stmt) = @_; + + # Strip the diff line prefixes and rip blank lines at start and end. + $stmt =~ s/(^|\n)./$1/g; + $stmt =~ s/^\s*//; + $stmt =~ s/\s*$//; + + my @stmt_lines = ($stmt =~ /\n/g); + + return $#stmt_lines + 2; +} + +sub statement_rawlines { + my ($stmt) = @_; + + my @stmt_lines = ($stmt =~ /\n/g); + + return $#stmt_lines + 2; +} + +sub statement_block_size { + my ($stmt) = @_; + + $stmt =~ s/(^|\n)./$1/g; + $stmt =~ s/^\s*{//; + $stmt =~ s/}\s*$//; + $stmt =~ s/^\s*//; + $stmt =~ s/\s*$//; + + my @stmt_lines = ($stmt =~ /\n/g); + my @stmt_statements = ($stmt =~ /;/g); + + my $stmt_lines = $#stmt_lines + 2; + my $stmt_statements = $#stmt_statements + 1; + + if ($stmt_lines > $stmt_statements) { + return $stmt_lines; + } else { + return $stmt_statements; + } +} + +sub ctx_statement_full { + my ($linenr, $remain, $off) = @_; + my ($statement, $condition, $level); + + my (@chunks); + + # Grab the first conditional/block pair. + ($statement, $condition, $linenr, $remain, $off, $level) = + ctx_statement_block($linenr, $remain, $off); + #print "F: c<$condition> s<$statement> remain<$remain>\n"; + push(@chunks, [ $condition, $statement ]); + if (!($remain > 0 && $condition =~ /^\s*(?:\n[+-])?\s*(?:if|else|do)\b/s)) { + return ($level, $linenr, @chunks); + } + + # Pull in the following conditional/block pairs and see if they + # could continue the statement. + for (;;) { + ($statement, $condition, $linenr, $remain, $off, $level) = + ctx_statement_block($linenr, $remain, $off); + #print "C: c<$condition> s<$statement> remain<$remain>\n"; + last if (!($remain > 0 && $condition =~ /^(?:\s*\n[+-])*\s*(?:else|do)\b/s)); + #print "C: push\n"; + push(@chunks, [ $condition, $statement ]); + } + + return ($level, $linenr, @chunks); +} + +sub ctx_block_get { + my ($linenr, $remain, $outer, $open, $close, $off) = @_; + my $line; + my $start = $linenr - 1; + my $blk = ''; + my @o; + my @c; + my @res = (); + + my $level = 0; + my @stack = ($level); + for ($line = $start; $remain > 0; $line++) { + next if ($rawlines[$line] =~ /^-/); + $remain--; + + $blk .= $rawlines[$line]; + + # Handle nested #if/#else. + if ($lines[$line] =~ /^.\s*#\s*(?:ifndef|ifdef|if)\s/) { + push(@stack, $level); + } elsif ($lines[$line] =~ /^.\s*#\s*(?:else|elif)\b/) { + $level = $stack[$#stack - 1]; + } elsif ($lines[$line] =~ /^.\s*#\s*endif\b/) { + $level = pop(@stack); + } + + foreach my $c (split(//, $lines[$line])) { + ##print "C<$c>L<$level><$open$close>O<$off>\n"; + if ($off > 0) { + $off--; + next; + } + + if ($c eq $close && $level > 0) { + $level--; + last if ($level == 0); + } elsif ($c eq $open) { + $level++; + } + } + + if (!$outer || $level <= 1) { + push(@res, $rawlines[$line]); + } + + last if ($level == 0); + } + + return ($level, @res); +} +sub ctx_block_outer { + my ($linenr, $remain) = @_; + + my ($level, @r) = ctx_block_get($linenr, $remain, 1, '{', '}', 0); + return @r; +} +sub ctx_block { + my ($linenr, $remain) = @_; + + my ($level, @r) = ctx_block_get($linenr, $remain, 0, '{', '}', 0); + return @r; +} +sub ctx_statement { + my ($linenr, $remain, $off) = @_; + + my ($level, @r) = ctx_block_get($linenr, $remain, 0, '(', ')', $off); + return @r; +} +sub ctx_block_level { + my ($linenr, $remain) = @_; + + return ctx_block_get($linenr, $remain, 0, '{', '}', 0); +} +sub ctx_statement_level { + my ($linenr, $remain, $off) = @_; + + return ctx_block_get($linenr, $remain, 0, '(', ')', $off); +} + +sub ctx_locate_comment { + my ($first_line, $end_line) = @_; + + # Catch a comment on the end of the line itself. + my ($current_comment) = ($rawlines[$end_line - 1] =~ m@.*(/\*.*\*/)\s*(?:\\\s*)?$@); + return $current_comment if (defined $current_comment); + + # Look through the context and try and figure out if there is a + # comment. + my $in_comment = 0; + $current_comment = ''; + for (my $linenr = $first_line; $linenr < $end_line; $linenr++) { + my $line = $rawlines[$linenr - 1]; + #warn " $line\n"; + if ($linenr == $first_line and $line =~ m@^.\s*\*@) { + $in_comment = 1; + } + if ($line =~ m@/\*@) { + $in_comment = 1; + } + if (!$in_comment && $current_comment ne '') { + $current_comment = ''; + } + $current_comment .= $line . "\n" if ($in_comment); + if ($line =~ m@\*/@) { + $in_comment = 0; + } + } + + chomp($current_comment); + return($current_comment); +} +sub ctx_has_comment { + my ($first_line, $end_line) = @_; + my $cmt = ctx_locate_comment($first_line, $end_line); + + ##print "LINE: $rawlines[$end_line - 1 ]\n"; + ##print "CMMT: $cmt\n"; + + return ($cmt ne ''); +} + +sub raw_line { + my ($linenr, $cnt) = @_; + + my $offset = $linenr - 1; + $cnt++; + + my $line; + while ($cnt) { + $line = $rawlines[$offset++]; + next if (defined($line) && $line =~ /^-/); + $cnt--; + } + + return $line; +} + +sub cat_vet { + my ($vet) = @_; + my ($res, $coded); + + $res = ''; + while ($vet =~ /([^[:cntrl:]]*)([[:cntrl:]]|$)/g) { + $res .= $1; + if ($2 ne '') { + $coded = sprintf("^%c", unpack('C', $2) + 64); + $res .= $coded; + } + } + $res =~ s/$/\$/; + + return $res; +} + +my $av_preprocessor = 0; +my $av_pending; +my @av_paren_type; +my $av_pend_colon; + +sub annotate_reset { + $av_preprocessor = 0; + $av_pending = '_'; + @av_paren_type = ('E'); + $av_pend_colon = 'O'; +} + +sub annotate_values { + my ($stream, $type) = @_; + + my $res; + my $var = '_' x length($stream); + my $cur = $stream; + + print "$stream\n" if ($dbg_values > 1); + + while (length($cur)) { + @av_paren_type = ('E') if ($#av_paren_type < 0); + print " <" . join('', @av_paren_type) . + "> <$type> <$av_pending>" if ($dbg_values > 1); + if ($cur =~ /^(\s+)/o) { + print "WS($1)\n" if ($dbg_values > 1); + if ($1 =~ /\n/ && $av_preprocessor) { + $type = pop(@av_paren_type); + $av_preprocessor = 0; + } + + } elsif ($cur =~ /^(\(\s*$Type\s*)\)/) { + print "CAST($1)\n" if ($dbg_values > 1); + push(@av_paren_type, $type); + $type = 'C'; + + } elsif ($cur =~ /^($Type)\s*(?:$Ident|,|\)|\(|\s*$)/) { + print "DECLARE($1)\n" if ($dbg_values > 1); + $type = 'T'; + + } elsif ($cur =~ /^($Modifier)\s*/) { + print "MODIFIER($1)\n" if ($dbg_values > 1); + $type = 'T'; + + } elsif ($cur =~ /^(\#\s*define\s*$Ident)(\(?)/o) { + print "DEFINE($1,$2)\n" if ($dbg_values > 1); + $av_preprocessor = 1; + push(@av_paren_type, $type); + if ($2 ne '') { + $av_pending = 'N'; + } + $type = 'E'; + + } elsif ($cur =~ /^(\#\s*(?:undef\s*$Ident|include\b))/o) { + print "UNDEF($1)\n" if ($dbg_values > 1); + $av_preprocessor = 1; + push(@av_paren_type, $type); + + } elsif ($cur =~ /^(\#\s*(?:ifdef|ifndef|if))/o) { + print "PRE_START($1)\n" if ($dbg_values > 1); + $av_preprocessor = 1; + + push(@av_paren_type, $type); + push(@av_paren_type, $type); + $type = 'E'; + + } elsif ($cur =~ /^(\#\s*(?:else|elif))/o) { + print "PRE_RESTART($1)\n" if ($dbg_values > 1); + $av_preprocessor = 1; + + push(@av_paren_type, $av_paren_type[$#av_paren_type]); + + $type = 'E'; + + } elsif ($cur =~ /^(\#\s*(?:endif))/o) { + print "PRE_END($1)\n" if ($dbg_values > 1); + + $av_preprocessor = 1; + + # Assume all arms of the conditional end as this + # one does, and continue as if the #endif was not here. + pop(@av_paren_type); + push(@av_paren_type, $type); + $type = 'E'; + + } elsif ($cur =~ /^(\\\n)/o) { + print "PRECONT($1)\n" if ($dbg_values > 1); + + } elsif ($cur =~ /^(__attribute__)\s*\(?/o) { + print "ATTR($1)\n" if ($dbg_values > 1); + $av_pending = $type; + $type = 'N'; + + } elsif ($cur =~ /^(sizeof)\s*(\()?/o) { + print "SIZEOF($1)\n" if ($dbg_values > 1); + if (defined $2) { + $av_pending = 'V'; + } + $type = 'N'; + + } elsif ($cur =~ /^(if|while|for)\b/o) { + print "COND($1)\n" if ($dbg_values > 1); + $av_pending = 'E'; + $type = 'N'; + + } elsif ($cur =~/^(case)/o) { + print "CASE($1)\n" if ($dbg_values > 1); + $av_pend_colon = 'C'; + $type = 'N'; + + } elsif ($cur =~/^(return|else|goto|typeof|__typeof__)\b/o) { + print "KEYWORD($1)\n" if ($dbg_values > 1); + $type = 'N'; + + } elsif ($cur =~ /^(\()/o) { + print "PAREN('$1')\n" if ($dbg_values > 1); + push(@av_paren_type, $av_pending); + $av_pending = '_'; + $type = 'N'; + + } elsif ($cur =~ /^(\))/o) { + my $new_type = pop(@av_paren_type); + if ($new_type ne '_') { + $type = $new_type; + print "PAREN('$1') -> $type\n" + if ($dbg_values > 1); + } else { + print "PAREN('$1')\n" if ($dbg_values > 1); + } + + } elsif ($cur =~ /^($Ident)\s*\(/o) { + print "FUNC($1)\n" if ($dbg_values > 1); + $type = 'V'; + $av_pending = 'V'; + + } elsif ($cur =~ /^($Ident\s*):(?:\s*\d+\s*(,|=|;))?/) { + if (defined $2 && $type eq 'C' || $type eq 'T') { + $av_pend_colon = 'B'; + } elsif ($type eq 'E') { + $av_pend_colon = 'L'; + } + print "IDENT_COLON($1,$type>$av_pend_colon)\n" if ($dbg_values > 1); + $type = 'V'; + + } elsif ($cur =~ /^($Ident|$Constant)/o) { + print "IDENT($1)\n" if ($dbg_values > 1); + $type = 'V'; + + } elsif ($cur =~ /^($Assignment)/o) { + print "ASSIGN($1)\n" if ($dbg_values > 1); + $type = 'N'; + + } elsif ($cur =~/^(;|{|})/) { + print "END($1)\n" if ($dbg_values > 1); + $type = 'E'; + $av_pend_colon = 'O'; + + } elsif ($cur =~/^(,)/) { + print "COMMA($1)\n" if ($dbg_values > 1); + $type = 'C'; + + } elsif ($cur =~ /^(\?)/o) { + print "QUESTION($1)\n" if ($dbg_values > 1); + $type = 'N'; + + } elsif ($cur =~ /^(:)/o) { + print "COLON($1,$av_pend_colon)\n" if ($dbg_values > 1); + + substr($var, length($res), 1, $av_pend_colon); + if ($av_pend_colon eq 'C' || $av_pend_colon eq 'L') { + $type = 'E'; + } else { + $type = 'N'; + } + $av_pend_colon = 'O'; + + } elsif ($cur =~ /^(\[)/o) { + print "CLOSE($1)\n" if ($dbg_values > 1); + $type = 'N'; + + } elsif ($cur =~ /^(-(?![->])|\+(?!\+)|\*|\&\&|\&)/o) { + my $variant; + + print "OPV($1)\n" if ($dbg_values > 1); + if ($type eq 'V') { + $variant = 'B'; + } else { + $variant = 'U'; + } + + substr($var, length($res), 1, $variant); + $type = 'N'; + + } elsif ($cur =~ /^($Operators)/o) { + print "OP($1)\n" if ($dbg_values > 1); + if ($1 ne '++' && $1 ne '--') { + $type = 'N'; + } + + } elsif ($cur =~ /(^.)/o) { + print "C($1)\n" if ($dbg_values > 1); + } + if (defined $1) { + $cur = substr($cur, length($1)); + $res .= $type x length($1); + } + } + + return ($res, $var); +} + +sub possible { + my ($possible, $line) = @_; + my $notPermitted = qr{(?: + ^(?: + $Modifier| + $Storage| + $Type| + DEFINE_\S+ + )$| + ^(?: + goto| + return| + case| + else| + asm|__asm__| + do + )(?:\s|$)| + ^(?:typedef|struct|enum)\b + )}x; + warn "CHECK<$possible> ($line)\n" if ($dbg_possible > 2); + if ($possible !~ $notPermitted) { + # Check for modifiers. + $possible =~ s/\s*$Storage\s*//g; + $possible =~ s/\s*$Sparse\s*//g; + if ($possible =~ /^\s*$/) { + + } elsif ($possible =~ /\s/) { + $possible =~ s/\s*$Type\s*//g; + for my $modifier (split(' ', $possible)) { + if ($modifier !~ $notPermitted) { + warn "MODIFIER: $modifier ($possible) ($line)\n" if ($dbg_possible); + push(@modifierList, $modifier); + } + } + + } else { + warn "POSSIBLE: $possible ($line)\n" if ($dbg_possible); + push(@typeList, $possible); + } + build_types(); + } else { + warn "NOTPOSS: $possible ($line)\n" if ($dbg_possible > 1); + } +} + +my $prefix = ''; + +sub report { + if (defined $tst_only && $_[0] !~ /\Q$tst_only\E/) { + return 0; + } + my $line = $prefix . $_[0]; + + $line = (split('\n', $line))[0] . "\n" if ($terse); + + push(our @report, $line); + + return 1; +} +sub report_dump { + our @report; +} +sub ERROR { + if (report("ERROR: $_[0]\n")) { + our $clean = 0; + our $cnt_error++; + } +} +sub WARN { + if (report("WARNING: $_[0]\n")) { + our $clean = 0; + our $cnt_warn++; + } +} +sub CHK { + if ($check && report("CHECK: $_[0]\n")) { + our $clean = 0; + our $cnt_chk++; + } +} + +sub check_absolute_file { + my ($absolute, $herecurr) = @_; + my $file = $absolute; + + ##print "absolute<$absolute>\n"; + + # See if any suffix of this path is a path within the tree. + while ($file =~ s@^[^/]*/@@) { + if (-f "$root/$file") { + ##print "file<$file>\n"; + last; + } + } + if (! -f _) { + return 0; + } + + # It is, so see if the prefix is acceptable. + my $prefix = $absolute; + substr($prefix, -length($file)) = ''; + + ##print "prefix<$prefix>\n"; + if ($prefix ne ".../") { + WARN("use relative pathname instead of absolute in changelog text\n" . $herecurr); + } +} + +sub process { + my $filename = shift; + + my $linenr=0; + my $prevline=""; + my $prevrawline=""; + my $stashline=""; + my $stashrawline=""; + + my $length; + my $indent; + my $previndent=0; + my $stashindent=0; + + our $clean = 1; + my $signoff = 0; + my $is_patch = 0; + + our @report = (); + our $cnt_lines = 0; + our $cnt_error = 0; + our $cnt_warn = 0; + our $cnt_chk = 0; + + # Trace the real file/line as we go. + my $realfile = ''; + my $realline = 0; + my $realcnt = 0; + my $here = ''; + my $in_comment = 0; + my $comment_edge = 0; + my $first_line = 0; + my $p1_prefix = ''; + + my $prev_values = 'E'; + + # suppression flags + my %suppress_ifbraces; + my %suppress_whiletrailers; + my %suppress_export; + + # Pre-scan the patch sanitizing the lines. + # Pre-scan the patch looking for any __setup documentation. + # + my @setup_docs = (); + my $setup_docs = 0; + + sanitise_line_reset(); + my $line; + foreach my $rawline (@rawlines) { + $linenr++; + $line = $rawline; + + if ($rawline=~/^\+\+\+\s+(\S+)/) { + $setup_docs = 0; + if ($1 =~ m@Documentation/kernel-parameters.txt$@) { + $setup_docs = 1; + } + #next; + } + if ($rawline=~/^\@\@ -\d+(?:,\d+)? \+(\d+)(,(\d+))? \@\@/) { + $realline=$1-1; + if (defined $2) { + $realcnt=$3+1; + } else { + $realcnt=1+1; + } + $in_comment = 0; + + # Guestimate if this is a continuing comment. Run + # the context looking for a comment "edge". If this + # edge is a close comment then we must be in a comment + # at context start. + my $edge; + my $cnt = $realcnt; + for (my $ln = $linenr + 1; $cnt > 0; $ln++) { + next if (defined $rawlines[$ln - 1] && + $rawlines[$ln - 1] =~ /^-/); + $cnt--; + #print "RAW<$rawlines[$ln - 1]>\n"; + last if (!defined $rawlines[$ln - 1]); + if ($rawlines[$ln - 1] =~ m@(/\*|\*/)@ && + $rawlines[$ln - 1] !~ m@"[^"]*(?:/\*|\*/)[^"]*"@) { + ($edge) = $1; + last; + } + } + if (defined $edge && $edge eq '*/') { + $in_comment = 1; + } + + # Guestimate if this is a continuing comment. If this + # is the start of a diff block and this line starts + # ' *' then it is very likely a comment. + if (!defined $edge && + $rawlines[$linenr] =~ m@^.\s*(?:\*\*+| \*)(?:\s|$)@) + { + $in_comment = 1; + } + + ##print "COMMENT:$in_comment edge<$edge> $rawline\n"; + sanitise_line_reset($in_comment); + + } elsif ($realcnt && $rawline =~ /^(?:\+| |$)/) { + # Standardise the strings and chars within the input to + # simplify matching -- only bother with positive lines. + $line = sanitise_line($rawline); + } + push(@lines, $line); + + if ($realcnt > 1) { + $realcnt-- if ($line =~ /^(?:\+| |$)/); + } else { + $realcnt = 0; + } + + #print "==>$rawline\n"; + #print "-->$line\n"; + + if ($setup_docs && $line =~ /^\+/) { + push(@setup_docs, $line); + } + } + + $prefix = ''; + + $realcnt = 0; + $linenr = 0; + foreach my $line (@lines) { + $linenr++; + + my $rawline = $rawlines[$linenr - 1]; + +#extract the line range in the file after the patch is applied + if ($line=~/^\@\@ -\d+(?:,\d+)? \+(\d+)(,(\d+))? \@\@/) { + $is_patch = 1; + $first_line = $linenr + 1; + $realline=$1-1; + if (defined $2) { + $realcnt=$3+1; + } else { + $realcnt=1+1; + } + annotate_reset(); + $prev_values = 'E'; + + %suppress_ifbraces = (); + %suppress_whiletrailers = (); + %suppress_export = (); + next; + +# track the line number as we move through the hunk, note that +# new versions of GNU diff omit the leading space on completely +# blank context lines so we need to count that too. + } elsif ($line =~ /^( |\+|$)/) { + $realline++; + $realcnt-- if ($realcnt != 0); + + # Measure the line length and indent. + ($length, $indent) = line_stats($rawline); + + # Track the previous line. + ($prevline, $stashline) = ($stashline, $line); + ($previndent, $stashindent) = ($stashindent, $indent); + ($prevrawline, $stashrawline) = ($stashrawline, $rawline); + + #warn "line<$line>\n"; + + } elsif ($realcnt == 1) { + $realcnt--; + } + + my $hunk_line = ($realcnt != 0); + +#make up the handle for any error we report on this line + $prefix = "$filename:$realline: " if ($emacs && $file); + $prefix = "$filename:$linenr: " if ($emacs && !$file); + + $here = "#$linenr: " if (!$file); + $here = "#$realline: " if ($file); + + # extract the filename as it passes + if ($line =~ /^diff --git.*?(\S+)$/) { + $realfile = $1; + $realfile =~ s@^([^/]*)/@@; + + } elsif ($line =~ /^\+\+\+\s+(\S+)/) { + $realfile = $1; + $realfile =~ s@^([^/]*)/@@; + + $p1_prefix = $1; + if (!$file && $tree && $p1_prefix ne '' && + -e "$root/$p1_prefix") { + WARN("patch prefix '$p1_prefix' exists, appears to be a -p0 patch\n"); + } + + if ($realfile =~ m@^include/asm/@) { + ERROR("do not modify files in include/asm, change architecture specific files in include/asm-<architecture>\n" . "$here$rawline\n"); + } + next; + } + + $here .= "FILE: $realfile:$realline:" if ($realcnt != 0); + + my $hereline = "$here\n$rawline\n"; + my $herecurr = "$here\n$rawline\n"; + my $hereprev = "$here\n$prevrawline\n$rawline\n"; + + $cnt_lines++ if ($realcnt != 0); + +# Check for incorrect file permissions + if ($line =~ /^new (file )?mode.*[7531]\d{0,2}$/) { + my $permhere = $here . "FILE: $realfile\n"; + if ($realfile =~ /(Makefile|Kconfig|\.c|\.h|\.S|\.tmpl)$/) { + ERROR("do not set execute permissions for source files\n" . $permhere); + } + } + +#check the patch for a signoff: + if ($line =~ /^\s*signed-off-by:/i) { + # This is a signoff, if ugly, so do not double report. + $signoff++; + if (!($line =~ /^\s*Signed-off-by:/)) { + WARN("Signed-off-by: is the preferred form\n" . + $herecurr); + } + if ($line =~ /^\s*signed-off-by:\S/i) { + WARN("space required after Signed-off-by:\n" . + $herecurr); + } + } + +# Check for wrappage within a valid hunk of the file + if ($realcnt != 0 && $line !~ m{^(?:\+|-| |\\ No newline|$)}) { + ERROR("patch seems to be corrupt (line wrapped?)\n" . + $herecurr) if (!$emitted_corrupt++); + } + +# Check for absolute kernel paths. + if ($tree) { + while ($line =~ m{(?:^|\s)(/\S*)}g) { + my $file = $1; + + if ($file =~ m{^(.*?)(?::\d+)+:?$} && + check_absolute_file($1, $herecurr)) { + # + } else { + check_absolute_file($file, $herecurr); + } + } + } + +# UTF-8 regex found at http://www.w3.org/International/questions/qa-forms-utf-8.en.php + if (($realfile =~ /^$/ || $line =~ /^\+/) && + $rawline !~ m/^$UTF8*$/) { + my ($utf8_prefix) = ($rawline =~ /^($UTF8*)/); + + my $blank = copy_spacing($rawline); + my $ptr = substr($blank, 0, length($utf8_prefix)) . "^"; + my $hereptr = "$hereline$ptr\n"; + + ERROR("Invalid UTF-8, patch and commit message should be encoded in UTF-8\n" . $hereptr); + } + +# ignore non-hunk lines and lines being removed + next if (!$hunk_line || $line =~ /^-/); + +#trailing whitespace + if ($line =~ /^\+.*\015/) { + my $herevet = "$here\n" . cat_vet($rawline) . "\n"; + ERROR("DOS line endings\n" . $herevet); + + } elsif ($rawline =~ /^\+.*\S\s+$/ || $rawline =~ /^\+\s+$/) { + my $herevet = "$here\n" . cat_vet($rawline) . "\n"; + ERROR("trailing whitespace\n" . $herevet); + $rpt_cleaners = 1; + } + +# check for Kconfig help text having a real description +# Only applies when adding the entry originally, after that we do not have +# sufficient context to determine whether it is indeed long enough. + if ($realfile =~ /Kconfig/ && + $line =~ /\+\s*(?:---)?help(?:---)?$/) { + my $length = 0; + my $cnt = $realcnt; + my $ln = $linenr + 1; + my $f; + my $is_end = 0; + while ($cnt > 0 && defined $lines[$ln - 1]) { + $f = $lines[$ln - 1]; + $cnt-- if ($lines[$ln - 1] !~ /^-/); + $is_end = $lines[$ln - 1] =~ /^\+/; + $ln++; + + next if ($f =~ /^-/); + $f =~ s/^.//; + $f =~ s/#.*//; + $f =~ s/^\s+//; + next if ($f =~ /^$/); + if ($f =~ /^\s*config\s/) { + $is_end = 1; + last; + } + $length++; + } + WARN("please write a paragraph that describes the config symbol fully\n" . $herecurr) if ($is_end && $length < 4); + #print "is_end<$is_end> length<$length>\n"; + } + +# check we are in a valid source file if not then ignore this hunk + next if ($realfile !~ /\.(h|c|s|S|pl|sh)$/); + +#80 column limit + if ($line =~ /^\+/ && $prevrawline !~ /\/\*\*/ && + $rawline !~ /^.\s*\*\s*\@$Ident\s/ && + !($line =~ /^\+\s*$logFunctions\s*\(\s*(?:(KERN_\S+\s*|[^"]*))?"[X\t]*"\s*(?:,|\)\s*;)\s*$/ || + $line =~ /^\+\s*"[^"]*"\s*(?:\s*|,|\)\s*;)\s*$/) && + $length > 80) + { + WARN("line over 80 characters\n" . $herecurr); + } + +# check for spaces before a quoted newline + if ($rawline =~ /^.*\".*\s\\n/) { + WARN("unnecessary whitespace before a quoted newline\n" . $herecurr); + } + +# check for adding lines without a newline. + if ($line =~ /^\+/ && defined $lines[$linenr] && $lines[$linenr] =~ /^\\ No newline at end of file/) { + WARN("adding a line without newline at end of file\n" . $herecurr); + } + +# Blackfin: use hi/lo macros + if ($realfile =~ m@arch/blackfin/.*\.S$@) { + if ($line =~ /\.[lL][[:space:]]*=.*&[[:space:]]*0x[fF][fF][fF][fF]/) { + my $herevet = "$here\n" . cat_vet($line) . "\n"; + ERROR("use the LO() macro, not (... & 0xFFFF)\n" . $herevet); + } + if ($line =~ /\.[hH][[:space:]]*=.*>>[[:space:]]*16/) { + my $herevet = "$here\n" . cat_vet($line) . "\n"; + ERROR("use the HI() macro, not (... >> 16)\n" . $herevet); + } + } + +# check we are in a valid source file C or perl if not then ignore this hunk + next if ($realfile !~ /\.(h|c|pl)$/); + +# at the beginning of a line any tabs must come first and anything +# more than 8 must use tabs. + if ($rawline =~ /^\+\s* \t\s*\S/ || + $rawline =~ /^\+\s* \s*/) { + my $herevet = "$here\n" . cat_vet($rawline) . "\n"; + ERROR("code indent should use tabs where possible\n" . $herevet); + $rpt_cleaners = 1; + } + +# check for space before tabs. + if ($rawline =~ /^\+/ && $rawline =~ / \t/) { + my $herevet = "$here\n" . cat_vet($rawline) . "\n"; + WARN("please, no space before tabs\n" . $herevet); + } + +# check for spaces at the beginning of a line. +# Exceptions: +# 1) within comments +# 2) indented preprocessor commands +# 3) hanging labels + if ($rawline =~ /^\+ / && $line !~ /\+ *(?:$;|#|$Ident:)/) { + my $herevet = "$here\n" . cat_vet($rawline) . "\n"; + WARN("please, no spaces at the start of a line\n" . $herevet); + } + +# check we are in a valid C source file if not then ignore this hunk + next if ($realfile !~ /\.(h|c)$/); + +# check for RCS/CVS revision markers + if ($rawline =~ /^\+.*\$(Revision|Log|Id)(?:\$|)/) { + WARN("CVS style keyword markers, these will _not_ be updated\n". $herecurr); + } + +# Blackfin: don't use __builtin_bfin_[cs]sync + if ($line =~ /__builtin_bfin_csync/) { + my $herevet = "$here\n" . cat_vet($line) . "\n"; + ERROR("use the CSYNC() macro in asm/blackfin.h\n" . $herevet); + } + if ($line =~ /__builtin_bfin_ssync/) { + my $herevet = "$here\n" . cat_vet($line) . "\n"; + ERROR("use the SSYNC() macro in asm/blackfin.h\n" . $herevet); + } + +# Check for potential 'bare' types + my ($stat, $cond, $line_nr_next, $remain_next, $off_next, + $realline_next); + if ($realcnt && $line =~ /.\s*\S/) { + ($stat, $cond, $line_nr_next, $remain_next, $off_next) = + ctx_statement_block($linenr, $realcnt, 0); + $stat =~ s/\n./\n /g; + $cond =~ s/\n./\n /g; + + # Find the real next line. + $realline_next = $line_nr_next; + if (defined $realline_next && + (!defined $lines[$realline_next - 1] || + substr($lines[$realline_next - 1], $off_next) =~ /^\s*$/)) { + $realline_next++; + } + + my $s = $stat; + $s =~ s/{.*$//s; + + # Ignore goto labels. + if ($s =~ /$Ident:\*$/s) { + + # Ignore functions being called + } elsif ($s =~ /^.\s*$Ident\s*\(/s) { + + } elsif ($s =~ /^.\s*else\b/s) { + + # declarations always start with types + } elsif ($prev_values eq 'E' && $s =~ /^.\s*(?:$Storage\s+)?(?:$Inline\s+)?(?:const\s+)?((?:\s*$Ident)+?)\b(?:\s+$Sparse)?\s*\**\s*(?:$Ident|\(\*[^\)]*\))(?:\s*$Modifier)?\s*(?:;|=|,|\()/s) { + my $type = $1; + $type =~ s/\s+/ /g; + possible($type, "A:" . $s); + + # definitions in global scope can only start with types + } elsif ($s =~ /^.(?:$Storage\s+)?(?:$Inline\s+)?(?:const\s+)?($Ident)\b\s*(?!:)/s) { + possible($1, "B:" . $s); + } + + # any (foo ... *) is a pointer cast, and foo is a type + while ($s =~ /\(($Ident)(?:\s+$Sparse)*[\s\*]+\s*\)/sg) { + possible($1, "C:" . $s); + } + + # Check for any sort of function declaration. + # int foo(something bar, other baz); + # void (*store_gdt)(x86_descr_ptr *); + if ($prev_values eq 'E' && $s =~ /^(.(?:typedef\s*)?(?:(?:$Storage|$Inline)\s*)*\s*$Type\s*(?:\b$Ident|\(\*\s*$Ident\))\s*)\(/s) { + my ($name_len) = length($1); + + my $ctx = $s; + substr($ctx, 0, $name_len + 1, ''); + $ctx =~ s/\)[^\)]*$//; + + for my $arg (split(/\s*,\s*/, $ctx)) { + if ($arg =~ /^(?:const\s+)?($Ident)(?:\s+$Sparse)*\s*\**\s*(:?\b$Ident)?$/s || $arg =~ /^($Ident)$/s) { + + possible($1, "D:" . $s); + } + } + } + + } + +# +# Checks which may be anchored in the context. +# + +# Check for switch () and associated case and default +# statements should be at the same indent. + if ($line=~/\bswitch\s*\(.*\)/) { + my $err = ''; + my $sep = ''; + my @ctx = ctx_block_outer($linenr, $realcnt); + shift(@ctx); + for my $ctx (@ctx) { + my ($clen, $cindent) = line_stats($ctx); + if ($ctx =~ /^\+\s*(case\s+|default:)/ && + $indent != $cindent) { + $err .= "$sep$ctx\n"; + $sep = ''; + } else { + $sep = "[...]\n"; + } + } + if ($err ne '') { + ERROR("switch and case should be at the same indent\n$hereline$err"); + } + } + +# if/while/etc brace do not go on next line, unless defining a do while loop, +# or if that brace on the next line is for something else + if ($line =~ /(.*)\b((?:if|while|for|switch)\s*\(|do\b|else\b)/ && $line !~ /^.\s*\#/) { + my $pre_ctx = "$1$2"; + + my ($level, @ctx) = ctx_statement_level($linenr, $realcnt, 0); + my $ctx_cnt = $realcnt - $#ctx - 1; + my $ctx = join("\n", @ctx); + + my $ctx_ln = $linenr; + my $ctx_skip = $realcnt; + + while ($ctx_skip > $ctx_cnt || ($ctx_skip == $ctx_cnt && + defined $lines[$ctx_ln - 1] && + $lines[$ctx_ln - 1] =~ /^-/)) { + ##print "SKIP<$ctx_skip> CNT<$ctx_cnt>\n"; + $ctx_skip-- if (!defined $lines[$ctx_ln - 1] || $lines[$ctx_ln - 1] !~ /^-/); + $ctx_ln++; + } + + #print "realcnt<$realcnt> ctx_cnt<$ctx_cnt>\n"; + #print "pre<$pre_ctx>\nline<$line>\nctx<$ctx>\nnext<$lines[$ctx_ln - 1]>\n"; + + if ($ctx !~ /{\s*/ && defined($lines[$ctx_ln -1]) && $lines[$ctx_ln - 1] =~ /^\+\s*{/) { + ERROR("that open brace { should be on the previous line\n" . + "$here\n$ctx\n$rawlines[$ctx_ln - 1]\n"); + } + if ($level == 0 && $pre_ctx !~ /}\s*while\s*\($/ && + $ctx =~ /\)\s*\;\s*$/ && + defined $lines[$ctx_ln - 1]) + { + my ($nlength, $nindent) = line_stats($lines[$ctx_ln - 1]); + if ($nindent > $indent) { + WARN("trailing semicolon indicates no statements, indent implies otherwise\n" . + "$here\n$ctx\n$rawlines[$ctx_ln - 1]\n"); + } + } + } + +# Check relative indent for conditionals and blocks. + if ($line =~ /\b(?:(?:if|while|for)\s*\(|do\b)/ && $line !~ /^.\s*#/ && $line !~ /\}\s*while\s*/) { + my ($s, $c) = ($stat, $cond); + + substr($s, 0, length($c), ''); + + # Make sure we remove the line prefixes as we have + # none on the first line, and are going to readd them + # where necessary. + $s =~ s/\n./\n/gs; + + # Find out how long the conditional actually is. + my @newlines = ($c =~ /\n/gs); + my $cond_lines = 1 + $#newlines; + + # We want to check the first line inside the block + # starting at the end of the conditional, so remove: + # 1) any blank line termination + # 2) any opening brace { on end of the line + # 3) any do (...) { + my $continuation = 0; + my $check = 0; + $s =~ s/^.*\bdo\b//; + $s =~ s/^\s*{//; + if ($s =~ s/^\s*\\//) { + $continuation = 1; + } + if ($s =~ s/^\s*?\n//) { + $check = 1; + $cond_lines++; + } + + # Also ignore a loop construct at the end of a + # preprocessor statement. + if (($prevline =~ /^.\s*#\s*define\s/ || + $prevline =~ /\\\s*$/) && $continuation == 0) { + $check = 0; + } + + my $cond_ptr = -1; + $continuation = 0; + while ($cond_ptr != $cond_lines) { + $cond_ptr = $cond_lines; + + # If we see an #else/#elif then the code + # is not linear. + if ($s =~ /^\s*\#\s*(?:else|elif)/) { + $check = 0; + } + + # Ignore: + # 1) blank lines, they should be at 0, + # 2) preprocessor lines, and + # 3) labels. + if ($continuation || + $s =~ /^\s*?\n/ || + $s =~ /^\s*#\s*?/ || + $s =~ /^\s*$Ident\s*:/) { + $continuation = ($s =~ /^.*?\\\n/) ? 1 : 0; + if ($s =~ s/^.*?\n//) { + $cond_lines++; + } + } + } + + my (undef, $sindent) = line_stats("+" . $s); + my $stat_real = raw_line($linenr, $cond_lines); + + # Check if either of these lines are modified, else + # this is not this patch's fault. + if (!defined($stat_real) || + $stat !~ /^\+/ && $stat_real !~ /^\+/) { + $check = 0; + } + if (defined($stat_real) && $cond_lines > 1) { + $stat_real = "[...]\n$stat_real"; + } + + #print "line<$line> prevline<$prevline> indent<$indent> sindent<$sindent> check<$check> continuation<$continuation> s<$s> cond_lines<$cond_lines> stat_real<$stat_real> stat<$stat>\n"; + + if ($check && (($sindent % 8) != 0 || + ($sindent <= $indent && $s ne ''))) { + WARN("suspect code indent for conditional statements ($indent, $sindent)\n" . $herecurr . "$stat_real\n"); + } + } + + # Track the 'values' across context and added lines. + my $opline = $line; $opline =~ s/^./ /; + my ($curr_values, $curr_vars) = + annotate_values($opline . "\n", $prev_values); + $curr_values = $prev_values . $curr_values; + if ($dbg_values) { + my $outline = $opline; $outline =~ s/\t/ /g; + print "$linenr > .$outline\n"; + print "$linenr > $curr_values\n"; + print "$linenr > $curr_vars\n"; + } + $prev_values = substr($curr_values, -1); + +#ignore lines not being added + if ($line=~/^[^\+]/) {next;} + +# TEST: allow direct testing of the type matcher. + if ($dbg_type) { + if ($line =~ /^.\s*$Declare\s*$/) { + ERROR("TEST: is type\n" . $herecurr); + } elsif ($dbg_type > 1 && $line =~ /^.+($Declare)/) { + ERROR("TEST: is not type ($1 is)\n". $herecurr); + } + next; + } +# TEST: allow direct testing of the attribute matcher. + if ($dbg_attr) { + if ($line =~ /^.\s*$Modifier\s*$/) { + ERROR("TEST: is attr\n" . $herecurr); + } elsif ($dbg_attr > 1 && $line =~ /^.+($Modifier)/) { + ERROR("TEST: is not attr ($1 is)\n". $herecurr); + } + next; + } + +# check for initialisation to aggregates open brace on the next line + if ($line =~ /^.\s*{/ && + $prevline =~ /(?:^|[^=])=\s*$/) { + ERROR("that open brace { should be on the previous line\n" . $hereprev); + } + +# +# Checks which are anchored on the added line. +# + +# check for malformed paths in #include statements (uses RAW line) + if ($rawline =~ m{^.\s*\#\s*include\s+[<"](.*)[">]}) { + my $path = $1; + if ($path =~ m{//}) { + ERROR("malformed #include filename\n" . + $herecurr); + } + } + +# no C99 // comments + if ($line =~ m{//}) { + ERROR("do not use C99 // comments\n" . $herecurr); + } + # Remove C99 comments. + $line =~ s@//.*@@; + $opline =~ s@//.*@@; + +# EXPORT_SYMBOL should immediately follow the thing it is exporting, consider +# the whole statement. +#print "APW <$lines[$realline_next - 1]>\n"; + if (defined $realline_next && + exists $lines[$realline_next - 1] && + !defined $suppress_export{$realline_next} && + ($lines[$realline_next - 1] =~ /EXPORT_SYMBOL.*\((.*)\)/ || + $lines[$realline_next - 1] =~ /EXPORT_UNUSED_SYMBOL.*\((.*)\)/)) { + # Handle definitions which produce identifiers with + # a prefix: + # XXX(foo); + # EXPORT_SYMBOL(something_foo); + my $name = $1; + if ($stat =~ /^.([A-Z_]+)\s*\(\s*($Ident)/ && + $name =~ /^${Ident}_$2/) { +#print "FOO C name<$name>\n"; + $suppress_export{$realline_next} = 1; + + } elsif ($stat !~ /(?: + \n.}\s*$| + ^.DEFINE_$Ident\(\Q$name\E\)| + ^.DECLARE_$Ident\(\Q$name\E\)| + ^.LIST_HEAD\(\Q$name\E\)| + ^.(?:$Storage\s+)?$Type\s*\(\s*\*\s*\Q$name\E\s*\)\s*\(| + \b\Q$name\E(?:\s+$Attribute)*\s*(?:;|=|\[|\() + )/x) { +#print "FOO A<$lines[$realline_next - 1]> stat<$stat> name<$name>\n"; + $suppress_export{$realline_next} = 2; + } else { + $suppress_export{$realline_next} = 1; + } + } + if (!defined $suppress_export{$linenr} && + $prevline =~ /^.\s*$/ && + ($line =~ /EXPORT_SYMBOL.*\((.*)\)/ || + $line =~ /EXPORT_UNUSED_SYMBOL.*\((.*)\)/)) { +#print "FOO B <$lines[$linenr - 1]>\n"; + $suppress_export{$linenr} = 2; + } + if (defined $suppress_export{$linenr} && + $suppress_export{$linenr} == 2) { + WARN("EXPORT_SYMBOL(foo); should immediately follow its function/variable\n" . $herecurr); + } + +# check for global initialisers. + if ($line =~ /^.$Type\s*$Ident\s*(?:\s+$Modifier)*\s*=\s*(0|NULL|false)\s*;/) { + ERROR("do not initialise globals to 0 or NULL\n" . + $herecurr); + } +# check for static initialisers. + if ($line =~ /\bstatic\s.*=\s*(0|NULL|false)\s*;/) { + ERROR("do not initialise statics to 0 or NULL\n" . + $herecurr); + } + +# check for static const char * arrays. + if ($line =~ /\bstatic\s+const\s+char\s*\*\s*(\w+)\s*\[\s*\]\s*=\s*/) { + WARN("static const char * array should probably be static const char * const\n" . + $herecurr); + } + +# check for static char foo[] = "bar" declarations. + if ($line =~ /\bstatic\s+char\s+(\w+)\s*\[\s*\]\s*=\s*"/) { + WARN("static char array declaration should probably be static const char\n" . + $herecurr); + } + +# check for declarations of struct pci_device_id + if ($line =~ /\bstruct\s+pci_device_id\s+\w+\s*\[\s*\]\s*\=\s*\{/) { + WARN("Use DEFINE_PCI_DEVICE_TABLE for struct pci_device_id\n" . $herecurr); + } + +# check for new typedefs, only function parameters and sparse annotations +# make sense. + if ($line =~ /\btypedef\s/ && + $line !~ /\btypedef\s+$Type\s*\(\s*\*?$Ident\s*\)\s*\(/ && + $line !~ /\btypedef\s+$Type\s+$Ident\s*\(/ && + $line !~ /\b$typeTypedefs\b/ && + $line !~ /\b__bitwise(?:__|)\b/) { + WARN("do not add new typedefs\n" . $herecurr); + } + +# * goes on variable not on type + # (char*[ const]) + if ($line =~ m{\($NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)\)}) { + my ($from, $to) = ($1, $1); + + # Should start with a space. + $to =~ s/^(\S)/ $1/; + # Should not end with a space. + $to =~ s/\s+$//; + # '*'s should not have spaces between. + while ($to =~ s/\*\s+\*/\*\*/) { + } + + #print "from<$from> to<$to>\n"; + if ($from ne $to) { + ERROR("\"(foo$from)\" should be \"(foo$to)\"\n" . $herecurr); + } + } elsif ($line =~ m{\b$NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)($Ident)}) { + my ($from, $to, $ident) = ($1, $1, $2); + + # Should start with a space. + $to =~ s/^(\S)/ $1/; + # Should not end with a space. + $to =~ s/\s+$//; + # '*'s should not have spaces between. + while ($to =~ s/\*\s+\*/\*\*/) { + } + # Modifiers should have spaces. + $to =~ s/(\b$Modifier$)/$1 /; + + #print "from<$from> to<$to> ident<$ident>\n"; + if ($from ne $to && $ident !~ /^$Modifier$/) { + ERROR("\"foo${from}bar\" should be \"foo${to}bar\"\n" . $herecurr); + } + } + +# # no BUG() or BUG_ON() +# if ($line =~ /\b(BUG|BUG_ON)\b/) { +# print "Try to use WARN_ON & Recovery code rather than BUG() or BUG_ON()\n"; +# print "$herecurr"; +# $clean = 0; +# } + + if ($line =~ /\bLINUX_VERSION_CODE\b/) { + WARN("LINUX_VERSION_CODE should be avoided, code should be for the version to which it is merged\n" . $herecurr); + } + +# printk should use KERN_* levels. Note that follow on printk's on the +# same line do not need a level, so we use the current block context +# to try and find and validate the current printk. In summary the current +# printk includes all preceeding printk's which have no newline on the end. +# we assume the first bad printk is the one to report. + if ($line =~ /\bprintk\((?!KERN_)\s*"/) { + my $ok = 0; + for (my $ln = $linenr - 1; $ln >= $first_line; $ln--) { + #print "CHECK<$lines[$ln - 1]\n"; + # we have a preceeding printk if it ends + # with "\n" ignore it, else it is to blame + if ($lines[$ln - 1] =~ m{\bprintk\(}) { + if ($rawlines[$ln - 1] !~ m{\\n"}) { + $ok = 1; + } + last; + } + } + if ($ok == 0) { + WARN("printk() should include KERN_ facility level\n" . $herecurr); + } + } + +# function brace can't be on same line, except for #defines of do while, +# or if closed on same line + if (($line=~/$Type\s*$Ident\(.*\).*\s{/) and + !($line=~/\#\s*define.*do\s{/) and !($line=~/}/)) { + ERROR("open brace '{' following function declarations go on the next line\n" . $herecurr); + } + +# open braces for enum, union and struct go on the same line. + if ($line =~ /^.\s*{/ && + $prevline =~ /^.\s*(?:typedef\s+)?(enum|union|struct)(?:\s+$Ident)?\s*$/) { + ERROR("open brace '{' following $1 go on the same line\n" . $hereprev); + } + +# missing space after union, struct or enum definition + if ($line =~ /^.\s*(?:typedef\s+)?(enum|union|struct)(?:\s+$Ident)?(?:\s+$Ident)?[=\{]/) { + WARN("missing space after $1 definition\n" . $herecurr); + } + +# check for spacing round square brackets; allowed: +# 1. with a type on the left -- int [] a; +# 2. at the beginning of a line for slice initialisers -- [0...10] = 5, +# 3. inside a curly brace -- = { [0...10] = 5 } + while ($line =~ /(.*?\s)\[/g) { + my ($where, $prefix) = ($-[1], $1); + if ($prefix !~ /$Type\s+$/ && + ($where != 0 || $prefix !~ /^.\s+$/) && + $prefix !~ /{\s+$/) { + ERROR("space prohibited before open square bracket '['\n" . $herecurr); + } + } + +# check for spaces between functions and their parentheses. + while ($line =~ /($Ident)\s+\(/g) { + my $name = $1; + my $ctx_before = substr($line, 0, $-[1]); + my $ctx = "$ctx_before$name"; + + # Ignore those directives where spaces _are_ permitted. + if ($name =~ /^(?: + if|for|while|switch|return|case| + volatile|__volatile__| + __attribute__|format|__extension__| + asm|__asm__)$/x) + { + + # cpp #define statements have non-optional spaces, ie + # if there is a space between the name and the open + # parenthesis it is simply not a parameter group. + } elsif ($ctx_before =~ /^.\s*\#\s*define\s*$/) { + + # cpp #elif statement condition may start with a ( + } elsif ($ctx =~ /^.\s*\#\s*elif\s*$/) { + + # If this whole things ends with a type its most + # likely a typedef for a function. + } elsif ($ctx =~ /$Type$/) { + + } else { + WARN("space prohibited between function name and open parenthesis '('\n" . $herecurr); + } + } +# Check operator spacing. + if (!($line=~/\#\s*include/)) { + my $ops = qr{ + <<=|>>=|<=|>=|==|!=| + \+=|-=|\*=|\/=|%=|\^=|\|=|&=| + =>|->|<<|>>|<|>|=|!|~| + &&|\|\||,|\^|\+\+|--|&|\||\+|-|\*|\/|%| + \?|: + }x; + my @elements = split(/($ops|;)/, $opline); + my $off = 0; + + my $blank = copy_spacing($opline); + + for (my $n = 0; $n < $#elements; $n += 2) { + $off += length($elements[$n]); + + # Pick up the preceeding and succeeding characters. + my $ca = substr($opline, 0, $off); + my $cc = ''; + if (length($opline) >= ($off + length($elements[$n + 1]))) { + $cc = substr($opline, $off + length($elements[$n + 1])); + } + my $cb = "$ca$;$cc"; + + my $a = ''; + $a = 'V' if ($elements[$n] ne ''); + $a = 'W' if ($elements[$n] =~ /\s$/); + $a = 'C' if ($elements[$n] =~ /$;$/); + $a = 'B' if ($elements[$n] =~ /(\[|\()$/); + $a = 'O' if ($elements[$n] eq ''); + $a = 'E' if ($ca =~ /^\s*$/); + + my $op = $elements[$n + 1]; + + my $c = ''; + if (defined $elements[$n + 2]) { + $c = 'V' if ($elements[$n + 2] ne ''); + $c = 'W' if ($elements[$n + 2] =~ /^\s/); + $c = 'C' if ($elements[$n + 2] =~ /^$;/); + $c = 'B' if ($elements[$n + 2] =~ /^(\)|\]|;)/); + $c = 'O' if ($elements[$n + 2] eq ''); + $c = 'E' if ($elements[$n + 2] =~ /^\s*\\$/); + } else { + $c = 'E'; + } + + my $ctx = "${a}x${c}"; + + my $at = "(ctx:$ctx)"; + + my $ptr = substr($blank, 0, $off) . "^"; + my $hereptr = "$hereline$ptr\n"; + + # Pull out the value of this operator. + my $op_type = substr($curr_values, $off + 1, 1); + + # Get the full operator variant. + my $opv = $op . substr($curr_vars, $off, 1); + + # Ignore operators passed as parameters. + if ($op_type ne 'V' && + $ca =~ /\s$/ && $cc =~ /^\s*,/) { + +# # Ignore comments +# } elsif ($op =~ /^$;+$/) { + + # ; should have either the end of line or a space or \ after it + } elsif ($op eq ';') { + if ($ctx !~ /.x[WEBC]/ && + $cc !~ /^\\/ && $cc !~ /^;/) { + ERROR("space required after that '$op' $at\n" . $hereptr); + } + + # // is a comment + } elsif ($op eq '//') { + + # No spaces for: + # -> + # : when part of a bitfield + } elsif ($op eq '->' || $opv eq ':B') { + if ($ctx =~ /Wx.|.xW/) { + ERROR("spaces prohibited around that '$op' $at\n" . $hereptr); + } + + # , must have a space on the right. + } elsif ($op eq ',') { + if ($ctx !~ /.x[WEC]/ && $cc !~ /^}/) { + ERROR("space required after that '$op' $at\n" . $hereptr); + } + + # '*' as part of a type definition -- reported already. + } elsif ($opv eq '*_') { + #warn "'*' is part of type\n"; + + # unary operators should have a space before and + # none after. May be left adjacent to another + # unary operator, or a cast + } elsif ($op eq '!' || $op eq '~' || + $opv eq '*U' || $opv eq '-U' || + $opv eq '&U' || $opv eq '&&U') { + if ($ctx !~ /[WEBC]x./ && $ca !~ /(?:\)|!|~|\*|-|\&|\||\+\+|\-\-|\{)$/) { + ERROR("space required before that '$op' $at\n" . $hereptr); + } + if ($op eq '*' && $cc =~/\s*$Modifier\b/) { + # A unary '*' may be const + + } elsif ($ctx =~ /.xW/) { + ERROR("space prohibited after that '$op' $at\n" . $hereptr); + } + + # unary ++ and unary -- are allowed no space on one side. + } elsif ($op eq '++' or $op eq '--') { + if ($ctx !~ /[WEOBC]x[^W]/ && $ctx !~ /[^W]x[WOBEC]/) { + ERROR("space required one side of that '$op' $at\n" . $hereptr); + } + if ($ctx =~ /Wx[BE]/ || + ($ctx =~ /Wx./ && $cc =~ /^;/)) { + ERROR("space prohibited before that '$op' $at\n" . $hereptr); + } + if ($ctx =~ /ExW/) { + ERROR("space prohibited after that '$op' $at\n" . $hereptr); + } + + + # << and >> may either have or not have spaces both sides + } elsif ($op eq '<<' or $op eq '>>' or + $op eq '&' or $op eq '^' or $op eq '|' or + $op eq '+' or $op eq '-' or + $op eq '*' or $op eq '/' or + $op eq '%') + { + if ($ctx =~ /Wx[^WCE]|[^WCE]xW/) { + ERROR("need consistent spacing around '$op' $at\n" . + $hereptr); + } + + # A colon needs no spaces before when it is + # terminating a case value or a label. + } elsif ($opv eq ':C' || $opv eq ':L') { + if ($ctx =~ /Wx./) { + ERROR("space prohibited before that '$op' $at\n" . $hereptr); + } + + # All the others need spaces both sides. + } elsif ($ctx !~ /[EWC]x[CWE]/) { + my $ok = 0; + + # Ignore email addresses <foo@bar> + if (($op eq '<' && + $cc =~ /^\S+\@\S+>/) || + ($op eq '>' && + $ca =~ /<\S+\@\S+$/)) + { + $ok = 1; + } + + # Ignore ?: + if (($opv eq ':O' && $ca =~ /\?$/) || + ($op eq '?' && $cc =~ /^:/)) { + $ok = 1; + } + + if ($ok == 0) { + ERROR("spaces required around that '$op' $at\n" . $hereptr); + } + } + $off += length($elements[$n + 1]); + } + } + +# check for multiple assignments + if ($line =~ /^.\s*$Lval\s*=\s*$Lval\s*=(?!=)/) { + CHK("multiple assignments should be avoided\n" . $herecurr); + } + +## # check for multiple declarations, allowing for a function declaration +## # continuation. +## if ($line =~ /^.\s*$Type\s+$Ident(?:\s*=[^,{]*)?\s*,\s*$Ident.*/ && +## $line !~ /^.\s*$Type\s+$Ident(?:\s*=[^,{]*)?\s*,\s*$Type\s*$Ident.*/) { +## +## # Remove any bracketed sections to ensure we do not +## # falsly report the parameters of functions. +## my $ln = $line; +## while ($ln =~ s/\([^\(\)]*\)//g) { +## } +## if ($ln =~ /,/) { +## WARN("declaring multiple variables together should be avoided\n" . $herecurr); +## } +## } + +#need space before brace following if, while, etc + if (($line =~ /\(.*\){/ && $line !~ /\($Type\){/) || + $line =~ /do{/) { + ERROR("space required before the open brace '{'\n" . $herecurr); + } + +# closing brace should have a space following it when it has anything +# on the line + if ($line =~ /}(?!(?:,|;|\)))\S/) { + ERROR("space required after that close brace '}'\n" . $herecurr); + } + +# check spacing on square brackets + if ($line =~ /\[\s/ && $line !~ /\[\s*$/) { + ERROR("space prohibited after that open square bracket '['\n" . $herecurr); + } + if ($line =~ /\s\]/) { + ERROR("space prohibited before that close square bracket ']'\n" . $herecurr); + } + +# check spacing on parentheses + if ($line =~ /\(\s/ && $line !~ /\(\s*(?:\\)?$/ && + $line !~ /for\s*\(\s+;/) { + ERROR("space prohibited after that open parenthesis '('\n" . $herecurr); + } + if ($line =~ /(\s+)\)/ && $line !~ /^.\s*\)/ && + $line !~ /for\s*\(.*;\s+\)/ && + $line !~ /:\s+\)/) { + ERROR("space prohibited before that close parenthesis ')'\n" . $herecurr); + } + +#goto labels aren't indented, allow a single space however + if ($line=~/^.\s+[A-Za-z\d_]+:(?![0-9]+)/ and + !($line=~/^. [A-Za-z\d_]+:/) and !($line=~/^.\s+default:/)) { + WARN("labels should not be indented\n" . $herecurr); + } + +# Return is not a function. + if (defined($stat) && $stat =~ /^.\s*return(\s*)(\(.*);/s) { + my $spacing = $1; + my $value = $2; + + # Flatten any parentheses + $value =~ s/\(/ \(/g; + $value =~ s/\)/\) /g; + while ($value =~ s/\[[^\{\}]*\]/1/ || + $value !~ /(?:$Ident|-?$Constant)\s* + $Compare\s* + (?:$Ident|-?$Constant)/x && + $value =~ s/\([^\(\)]*\)/1/) { + } +#print "value<$value>\n"; + if ($value =~ /^\s*(?:$Ident|-?$Constant)\s*$/) { + ERROR("return is not a function, parentheses are not required\n" . $herecurr); + + } elsif ($spacing !~ /\s+/) { + ERROR("space required before the open parenthesis '('\n" . $herecurr); + } + } +# Return of what appears to be an errno should normally be -'ve + if ($line =~ /^.\s*return\s*(E[A-Z]*)\s*;/) { + my $name = $1; + if ($name ne 'EOF' && $name ne 'ERROR') { + WARN("return of an errno should typically be -ve (return -$1)\n" . $herecurr); + } + } + +# Need a space before open parenthesis after if, while etc + if ($line=~/\b(if|while|for|switch)\(/) { + ERROR("space required before the open parenthesis '('\n" . $herecurr); + } + +# Check for illegal assignment in if conditional -- and check for trailing +# statements after the conditional. + if ($line =~ /do\s*(?!{)/) { + my ($stat_next) = ctx_statement_block($line_nr_next, + $remain_next, $off_next); + $stat_next =~ s/\n./\n /g; + ##print "stat<$stat> stat_next<$stat_next>\n"; + + if ($stat_next =~ /^\s*while\b/) { + # If the statement carries leading newlines, + # then count those as offsets. + my ($whitespace) = + ($stat_next =~ /^((?:\s*\n[+-])*\s*)/s); + my $offset = + statement_rawlines($whitespace) - 1; + + $suppress_whiletrailers{$line_nr_next + + $offset} = 1; + } + } + if (!defined $suppress_whiletrailers{$linenr} && + $line =~ /\b(?:if|while|for)\s*\(/ && $line !~ /^.\s*#/) { + my ($s, $c) = ($stat, $cond); + + if ($c =~ /\bif\s*\(.*[^<>!=]=[^=].*/s) { + ERROR("do not use assignment in if condition\n" . $herecurr); + } + + # Find out what is on the end of the line after the + # conditional. + substr($s, 0, length($c), ''); + $s =~ s/\n.*//g; + $s =~ s/$;//g; # Remove any comments + if (length($c) && $s !~ /^\s*{?\s*\\*\s*$/ && + $c !~ /}\s*while\s*/) + { + # Find out how long the conditional actually is. + my @newlines = ($c =~ /\n/gs); + my $cond_lines = 1 + $#newlines; + my $stat_real = ''; + + $stat_real = raw_line($linenr, $cond_lines) + . "\n" if ($cond_lines); + if (defined($stat_real) && $cond_lines > 1) { + $stat_real = "[...]\n$stat_real"; + } + + ERROR("trailing statements should be on next line\n" . $herecurr . $stat_real); + } + } + +# Check for bitwise tests written as boolean + if ($line =~ / + (?: + (?:\[|\(|\&\&|\|\|) + \s*0[xX][0-9]+\s* + (?:\&\&|\|\|) + | + (?:\&\&|\|\|) + \s*0[xX][0-9]+\s* + (?:\&\&|\|\||\)|\]) + )/x) + { + WARN("boolean test with hexadecimal, perhaps just 1 \& or \|?\n" . $herecurr); + } + +# if and else should not have general statements after it + if ($line =~ /^.\s*(?:}\s*)?else\b(.*)/) { + my $s = $1; + $s =~ s/$;//g; # Remove any comments + if ($s !~ /^\s*(?:\sif|(?:{|)\s*\\?\s*$)/) { + ERROR("trailing statements should be on next line\n" . $herecurr); + } + } +# if should not continue a brace + if ($line =~ /}\s*if\b/) { + ERROR("trailing statements should be on next line\n" . + $herecurr); + } +# case and default should not have general statements after them + if ($line =~ /^.\s*(?:case\s*.*|default\s*):/g && + $line !~ /\G(?: + (?:\s*$;*)(?:\s*{)?(?:\s*$;*)(?:\s*\\)?\s*$| + \s*return\s+ + )/xg) + { + ERROR("trailing statements should be on next line\n" . $herecurr); + } + + # Check for }<nl>else {, these must be at the same + # indent level to be relevant to each other. + if ($prevline=~/}\s*$/ and $line=~/^.\s*else\s*/ and + $previndent == $indent) { + ERROR("else should follow close brace '}'\n" . $hereprev); + } + + if ($prevline=~/}\s*$/ and $line=~/^.\s*while\s*/ and + $previndent == $indent) { + my ($s, $c) = ctx_statement_block($linenr, $realcnt, 0); + + # Find out what is on the end of the line after the + # conditional. + substr($s, 0, length($c), ''); + $s =~ s/\n.*//g; + + if ($s =~ /^\s*;/) { + ERROR("while should follow close brace '}'\n" . $hereprev); + } + } + +#studly caps, commented out until figure out how to distinguish between use of existing and adding new +# if (($line=~/[\w_][a-z\d]+[A-Z]/) and !($line=~/print/)) { +# print "No studly caps, use _\n"; +# print "$herecurr"; +# $clean = 0; +# } + +#no spaces allowed after \ in define + if ($line=~/\#\s*define.*\\\s$/) { + WARN("Whitepspace after \\ makes next lines useless\n" . $herecurr); + } + +#warn if <asm/foo.h> is #included and <linux/foo.h> is available (uses RAW line) + if ($tree && $rawline =~ m{^.\s*\#\s*include\s*\<asm\/(.*)\.h\>}) { + my $file = "$1.h"; + my $checkfile = "include/linux/$file"; + if (-f "$root/$checkfile" && + $realfile ne $checkfile && + $1 !~ /$allowed_asm_includes/) + { + if ($realfile =~ m{^arch/}) { + CHK("Consider using #include <linux/$file> instead of <asm/$file>\n" . $herecurr); + } else { + WARN("Use #include <linux/$file> instead of <asm/$file>\n" . $herecurr); + } + } + } + +# multi-statement macros should be enclosed in a do while loop, grab the +# first statement and ensure its the whole macro if its not enclosed +# in a known good container + if ($realfile !~ m@/vmlinux.lds.h$@ && + $line =~ /^.\s*\#\s*define\s*$Ident(\()?/) { + my $ln = $linenr; + my $cnt = $realcnt; + my ($off, $dstat, $dcond, $rest); + my $ctx = ''; + + my $args = defined($1); + + # Find the end of the macro and limit our statement + # search to that. + while ($cnt > 0 && defined $lines[$ln - 1] && + $lines[$ln - 1] =~ /^(?:-|..*\\$)/) + { + $ctx .= $rawlines[$ln - 1] . "\n"; + $cnt-- if ($lines[$ln - 1] !~ /^-/); + $ln++; + } + $ctx .= $rawlines[$ln - 1]; + + ($dstat, $dcond, $ln, $cnt, $off) = + ctx_statement_block($linenr, $ln - $linenr + 1, 0); + #print "dstat<$dstat> dcond<$dcond> cnt<$cnt> off<$off>\n"; + #print "LINE<$lines[$ln-1]> len<" . length($lines[$ln-1]) . "\n"; + + # Extract the remainder of the define (if any) and + # rip off surrounding spaces, and trailing \'s. + $rest = ''; + while ($off != 0 || ($cnt > 0 && $rest =~ /\\\s*$/)) { + #print "ADDING cnt<$cnt> $off <" . substr($lines[$ln - 1], $off) . "> rest<$rest>\n"; + if ($off != 0 || $lines[$ln - 1] !~ /^-/) { + $rest .= substr($lines[$ln - 1], $off) . "\n"; + $cnt--; + } + $ln++; + $off = 0; + } + $rest =~ s/\\\n.//g; + $rest =~ s/^\s*//s; + $rest =~ s/\s*$//s; + + # Clean up the original statement. + if ($args) { + substr($dstat, 0, length($dcond), ''); + } else { + $dstat =~ s/^.\s*\#\s*define\s+$Ident\s*//; + } + $dstat =~ s/$;//g; + $dstat =~ s/\\\n.//g; + $dstat =~ s/^\s*//s; + $dstat =~ s/\s*$//s; + + # Flatten any parentheses and braces + while ($dstat =~ s/\([^\(\)]*\)/1/ || + $dstat =~ s/\{[^\{\}]*\}/1/ || + $dstat =~ s/\[[^\{\}]*\]/1/) + { + } + + my $exceptions = qr{ + $Declare| + module_param_named| + MODULE_PARAM_DESC| + DECLARE_PER_CPU| + DEFINE_PER_CPU| + __typeof__\(| + union| + struct| + \.$Ident\s*=\s*| + ^\"|\"$ + }x; + #print "REST<$rest> dstat<$dstat> ctx<$ctx>\n"; + if ($rest ne '' && $rest ne ',') { + if ($rest !~ /while\s*\(/ && + $dstat !~ /$exceptions/) + { + ERROR("Macros with multiple statements should be enclosed in a do - while loop\n" . "$here\n$ctx\n"); + } + + } elsif ($ctx !~ /;/) { + if ($dstat ne '' && + $dstat !~ /^(?:$Ident|-?$Constant)$/ && + $dstat !~ /$exceptions/ && + $dstat !~ /^\.$Ident\s*=/ && + $dstat =~ /$Operators/) + { + ERROR("Macros with complex values should be enclosed in parenthesis\n" . "$here\n$ctx\n"); + } + } + } + +# make sure symbols are always wrapped with VMLINUX_SYMBOL() ... +# all assignments may have only one of the following with an assignment: +# . +# ALIGN(...) +# VMLINUX_SYMBOL(...) + if ($realfile eq 'vmlinux.lds.h' && $line =~ /(?:(?:^|\s)$Ident\s*=|=\s*$Ident(?:\s|$))/) { + WARN("vmlinux.lds.h needs VMLINUX_SYMBOL() around C-visible symbols\n" . $herecurr); + } + +# check for redundant bracing round if etc + if ($line =~ /(^.*)\bif\b/ && $1 !~ /else\s*$/) { + my ($level, $endln, @chunks) = + ctx_statement_full($linenr, $realcnt, 1); + #print "chunks<$#chunks> linenr<$linenr> endln<$endln> level<$level>\n"; + #print "APW: <<$chunks[1][0]>><<$chunks[1][1]>>\n"; + if ($#chunks > 0 && $level == 0) { + my $allowed = 0; + my $seen = 0; + my $herectx = $here . "\n"; + my $ln = $linenr - 1; + for my $chunk (@chunks) { + my ($cond, $block) = @{$chunk}; + + # If the condition carries leading newlines, then count those as offsets. + my ($whitespace) = ($cond =~ /^((?:\s*\n[+-])*\s*)/s); + my $offset = statement_rawlines($whitespace) - 1; + + #print "COND<$cond> whitespace<$whitespace> offset<$offset>\n"; + + # We have looked at and allowed this specific line. + $suppress_ifbraces{$ln + $offset} = 1; + + $herectx .= "$rawlines[$ln + $offset]\n[...]\n"; + $ln += statement_rawlines($block) - 1; + + substr($block, 0, length($cond), ''); + + $seen++ if ($block =~ /^\s*{/); + + #print "cond<$cond> block<$block> allowed<$allowed>\n"; + if (statement_lines($cond) > 1) { + #print "APW: ALLOWED: cond<$cond>\n"; + $allowed = 1; + } + if ($block =~/\b(?:if|for|while)\b/) { + #print "APW: ALLOWED: block<$block>\n"; + $allowed = 1; + } + if (statement_block_size($block) > 1) { + #print "APW: ALLOWED: lines block<$block>\n"; + $allowed = 1; + } + } + if ($seen && !$allowed) { + WARN("braces {} are not necessary for any arm of this statement\n" . $herectx); + } + } + } + if (!defined $suppress_ifbraces{$linenr - 1} && + $line =~ /\b(if|while|for|else)\b/) { + my $allowed = 0; + + # Check the pre-context. + if (substr($line, 0, $-[0]) =~ /(\}\s*)$/) { + #print "APW: ALLOWED: pre<$1>\n"; + $allowed = 1; + } + + my ($level, $endln, @chunks) = + ctx_statement_full($linenr, $realcnt, $-[0]); + + # Check the condition. + my ($cond, $block) = @{$chunks[0]}; + #print "CHECKING<$linenr> cond<$cond> block<$block>\n"; + if (defined $cond) { + substr($block, 0, length($cond), ''); + } + if (statement_lines($cond) > 1) { + #print "APW: ALLOWED: cond<$cond>\n"; + $allowed = 1; + } + if ($block =~/\b(?:if|for|while)\b/) { + #print "APW: ALLOWED: block<$block>\n"; + $allowed = 1; + } + if (statement_block_size($block) > 1) { + #print "APW: ALLOWED: lines block<$block>\n"; + $allowed = 1; + } + # Check the post-context. + if (defined $chunks[1]) { + my ($cond, $block) = @{$chunks[1]}; + if (defined $cond) { + substr($block, 0, length($cond), ''); + } + if ($block =~ /^\s*\{/) { + #print "APW: ALLOWED: chunk-1 block<$block>\n"; + $allowed = 1; + } + } + if ($level == 0 && $block =~ /^\s*\{/ && !$allowed) { + my $herectx = $here . "\n";; + my $cnt = statement_rawlines($block); + + for (my $n = 0; $n < $cnt; $n++) { + $herectx .= raw_line($linenr, $n) . "\n";; + } + + WARN("braces {} are not necessary for single statement blocks\n" . $herectx); + } + } + +# don't include deprecated include files (uses RAW line) + for my $inc (@dep_includes) { + if ($rawline =~ m@^.\s*\#\s*include\s*\<$inc>@) { + ERROR("Don't use <$inc>: see Documentation/feature-removal-schedule.txt\n" . $herecurr); + } + } + +# don't use deprecated functions + for my $func (@dep_functions) { + if ($line =~ /\b$func\b/) { + ERROR("Don't use $func(): see Documentation/feature-removal-schedule.txt\n" . $herecurr); + } + } + +# no volatiles please + my $asm_volatile = qr{\b(__asm__|asm)\s+(__volatile__|volatile)\b}; + if ($line =~ /\bvolatile\b/ && $line !~ /$asm_volatile/) { + WARN("Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt\n" . $herecurr); + } + +# SPIN_LOCK_UNLOCKED & RW_LOCK_UNLOCKED are deprecated + if ($line =~ /\b(SPIN_LOCK_UNLOCKED|RW_LOCK_UNLOCKED)/) { + ERROR("Use of $1 is deprecated: see Documentation/spinlocks.txt\n" . $herecurr); + } + +# warn about #if 0 + if ($line =~ /^.\s*\#\s*if\s+0\b/) { + CHK("if this code is redundant consider removing it\n" . + $herecurr); + } + +# check for needless kfree() checks + if ($prevline =~ /\bif\s*\(([^\)]*)\)/) { + my $expr = $1; + if ($line =~ /\bkfree\(\Q$expr\E\);/) { + WARN("kfree(NULL) is safe this check is probably not required\n" . $hereprev); + } + } +# check for needless usb_free_urb() checks + if ($prevline =~ /\bif\s*\(([^\)]*)\)/) { + my $expr = $1; + if ($line =~ /\busb_free_urb\(\Q$expr\E\);/) { + WARN("usb_free_urb(NULL) is safe this check is probably not required\n" . $hereprev); + } + } + +# prefer usleep_range over udelay + if ($line =~ /\budelay\s*\(\s*(\w+)\s*\)/) { + # ignore udelay's < 10, however + if (! (($1 =~ /(\d+)/) && ($1 < 10)) ) { + CHK("usleep_range is preferred over udelay; see Documentation/timers/timers-howto.txt\n" . $line); + } + } + +# warn about unexpectedly long msleep's + if ($line =~ /\bmsleep\s*\((\d+)\);/) { + if ($1 < 20) { + WARN("msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.txt\n" . $line); + } + } + +# warn about #ifdefs in C files +# if ($line =~ /^.\s*\#\s*if(|n)def/ && ($realfile =~ /\.c$/)) { +# print "#ifdef in C files should be avoided\n"; +# print "$herecurr"; +# $clean = 0; +# } + +# warn about spacing in #ifdefs + if ($line =~ /^.\s*\#\s*(ifdef|ifndef|elif)\s\s+/) { + ERROR("exactly one space required after that #$1\n" . $herecurr); + } + +# check for spinlock_t definitions without a comment. + if ($line =~ /^.\s*(struct\s+mutex|spinlock_t)\s+\S+;/ || + $line =~ /^.\s*(DEFINE_MUTEX)\s*\(/) { + my $which = $1; + if (!ctx_has_comment($first_line, $linenr)) { + CHK("$1 definition without comment\n" . $herecurr); + } + } +# check for memory barriers without a comment. + if ($line =~ /\b(mb|rmb|wmb|read_barrier_depends|smp_mb|smp_rmb|smp_wmb|smp_read_barrier_depends)\(/) { + if (!ctx_has_comment($first_line, $linenr)) { + CHK("memory barrier without comment\n" . $herecurr); + } + } +# check of hardware specific defines + if ($line =~ m@^.\s*\#\s*if.*\b(__i386__|__powerpc64__|__sun__|__s390x__)\b@ && $realfile !~ m@include/asm-@) { + CHK("architecture specific defines should be avoided\n" . $herecurr); + } + +# Check that the storage class is at the beginning of a declaration + if ($line =~ /\b$Storage\b/ && $line !~ /^.\s*$Storage\b/) { + WARN("storage class should be at the beginning of the declaration\n" . $herecurr) + } + +# check the location of the inline attribute, that it is between +# storage class and type. + if ($line =~ /\b$Type\s+$Inline\b/ || + $line =~ /\b$Inline\s+$Storage\b/) { + ERROR("inline keyword should sit between storage class and type\n" . $herecurr); + } + +# Check for __inline__ and __inline, prefer inline + if ($line =~ /\b(__inline__|__inline)\b/) { + WARN("plain inline is preferred over $1\n" . $herecurr); + } + +# check for sizeof(&) + if ($line =~ /\bsizeof\s*\(\s*\&/) { + WARN("sizeof(& should be avoided\n" . $herecurr); + } + +# check for new externs in .c files. + if ($realfile =~ /\.c$/ && defined $stat && + $stat =~ /^.\s*(?:extern\s+)?$Type\s+($Ident)(\s*)\(/s) + { + my $function_name = $1; + my $paren_space = $2; + + my $s = $stat; + if (defined $cond) { + substr($s, 0, length($cond), ''); + } + if ($s =~ /^\s*;/ && + $function_name ne 'uninitialized_var') + { + WARN("externs should be avoided in .c files\n" . $herecurr); + } + + if ($paren_space =~ /\n/) { + WARN("arguments for function declarations should follow identifier\n" . $herecurr); + } + + } elsif ($realfile =~ /\.c$/ && defined $stat && + $stat =~ /^.\s*extern\s+/) + { + WARN("externs should be avoided in .c files\n" . $herecurr); + } + +# checks for new __setup's + if ($rawline =~ /\b__setup\("([^"]*)"/) { + my $name = $1; + + if (!grep(/$name/, @setup_docs)) { + CHK("__setup appears un-documented -- check Documentation/kernel-parameters.txt\n" . $herecurr); + } + } + +# check for pointless casting of kmalloc return + if ($line =~ /\*\s*\)\s*k[czm]alloc\b/) { + WARN("unnecessary cast may hide bugs, see http://c-faq.com/malloc/mallocnocast.html\n" . $herecurr); + } + +# check for gcc specific __FUNCTION__ + if ($line =~ /__FUNCTION__/) { + WARN("__func__ should be used instead of gcc specific __FUNCTION__\n" . $herecurr); + } + +# check for semaphores initialized locked + if ($line =~ /^.\s*sema_init.+,\W?0\W?\)/) { + WARN("consider using a completion\n" . $herecurr); + + } +# recommend strict_strto* over simple_strto* + if ($line =~ /\bsimple_(strto.*?)\s*\(/) { + WARN("consider using strict_$1 in preference to simple_$1\n" . $herecurr); + } +# check for __initcall(), use device_initcall() explicitly please + if ($line =~ /^.\s*__initcall\s*\(/) { + WARN("please use device_initcall() instead of __initcall()\n" . $herecurr); + } +# check for various ops structs, ensure they are const. + my $struct_ops = qr{acpi_dock_ops| + address_space_operations| + backlight_ops| + block_device_operations| + dentry_operations| + dev_pm_ops| + dma_map_ops| + extent_io_ops| + file_lock_operations| + file_operations| + hv_ops| + ide_dma_ops| + intel_dvo_dev_ops| + item_operations| + iwl_ops| + kgdb_arch| + kgdb_io| + kset_uevent_ops| + lock_manager_operations| + microcode_ops| + mtrr_ops| + neigh_ops| + nlmsvc_binding| + pci_raw_ops| + pipe_buf_operations| + platform_hibernation_ops| + platform_suspend_ops| + proto_ops| + rpc_pipe_ops| + seq_operations| + snd_ac97_build_ops| + soc_pcmcia_socket_ops| + stacktrace_ops| + sysfs_ops| + tty_operations| + usb_mon_operations| + wd_ops}x; + if ($line !~ /\bconst\b/ && + $line =~ /\bstruct\s+($struct_ops)\b/) { + WARN("struct $1 should normally be const\n" . + $herecurr); + } + +# use of NR_CPUS is usually wrong +# ignore definitions of NR_CPUS and usage to define arrays as likely right + if ($line =~ /\bNR_CPUS\b/ && + $line !~ /^.\s*\s*#\s*if\b.*\bNR_CPUS\b/ && + $line !~ /^.\s*\s*#\s*define\b.*\bNR_CPUS\b/ && + $line !~ /^.\s*$Declare\s.*\[[^\]]*NR_CPUS[^\]]*\]/ && + $line !~ /\[[^\]]*\.\.\.[^\]]*NR_CPUS[^\]]*\]/ && + $line !~ /\[[^\]]*NR_CPUS[^\]]*\.\.\.[^\]]*\]/) + { + WARN("usage of NR_CPUS is often wrong - consider using cpu_possible(), num_possible_cpus(), for_each_possible_cpu(), etc\n" . $herecurr); + } + +# check for %L{u,d,i} in strings + my $string; + while ($line =~ /(?:^|")([X\t]*)(?:"|$)/g) { + $string = substr($rawline, $-[1], $+[1] - $-[1]); + $string =~ s/%%/__/g; + if ($string =~ /(?<!%)%L[udi]/) { + WARN("\%Ld/%Lu are not-standard C, use %lld/%llu\n" . $herecurr); + last; + } + } + +# whine mightly about in_atomic + if ($line =~ /\bin_atomic\s*\(/) { + if ($realfile =~ m@^drivers/@) { + ERROR("do not use in_atomic in drivers\n" . $herecurr); + } elsif ($realfile !~ m@^kernel/@) { + WARN("use of in_atomic() is incorrect outside core kernel code\n" . $herecurr); + } + } + +# check for lockdep_set_novalidate_class + if ($line =~ /^.\s*lockdep_set_novalidate_class\s*\(/ || + $line =~ /__lockdep_no_validate__\s*\)/ ) { + if ($realfile !~ m@^kernel/lockdep@ && + $realfile !~ m@^include/linux/lockdep@ && + $realfile !~ m@^drivers/base/core@) { + ERROR("lockdep_no_validate class is reserved for device->mutex.\n" . $herecurr); + } + } + } + + # If we have no input at all, then there is nothing to report on + # so just keep quiet. + if ($#rawlines == -1) { + exit(0); + } + + # In mailback mode only produce a report in the negative, for + # things that appear to be patches. + if ($mailback && ($clean == 1 || !$is_patch)) { + exit(0); + } + + # This is not a patch, and we are are in 'no-patch' mode so + # just keep quiet. + if (!$chk_patch && !$is_patch) { + exit(0); + } + + if (!$is_patch) { + ERROR("Does not appear to be a unified-diff format patch\n"); + } + if ($is_patch && $chk_signoff && $signoff == 0) { + ERROR("Missing Signed-off-by: line(s)\n"); + } + + print report_dump(); + if ($summary && !($clean == 1 && $quiet == 1)) { + print "$filename " if ($summary_file); + print "total: $cnt_error errors, $cnt_warn warnings, " . + (($check)? "$cnt_chk checks, " : "") . + "$cnt_lines lines checked\n"; + print "\n" if ($quiet == 0); + } + + if ($quiet == 0) { + # If there were whitespace errors which cleanpatch can fix + # then suggest that. + if ($rpt_cleaners) { + print "NOTE: whitespace errors detected, you may wish to use scripts/cleanpatch or\n"; + print " scripts/cleanfile\n\n"; + } + } + + if ($clean == 1 && $quiet == 0) { + print "$vname has no obvious style problems and is ready for submission.\n" + } + if ($clean == 0 && $quiet == 0) { + print "$vname has style problems, please review. If any of these errors\n"; + print "are false positives report them to the maintainer, see\n"; + print "CHECKPATCH in MAINTAINERS.\n"; + } + + return $clean; +} |