diff options
| author | Sanjeev Premi <premi@ti.com> | 2011-01-03 19:54:55 +0530 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2011-01-05 11:05:25 +0100 |
| commit | d4d7a192587bb25051dbc845aab45301d22e6ed3 (patch) | |
| tree | 12fa12cc7ff8b56d8f6d9968e56b9dc831d3aa5b | |
| parent | f2fccf6473d08d15c05c0d2d55742b26eff946c8 (diff) | |
| download | barebox-d4d7a192587bb25051dbc845aab45301d22e6ed3.tar.gz barebox-d4d7a192587bb25051dbc845aab45301d22e6ed3.tar.xz | |
omap3: Define GFX_DIV values for OMAP34xx and OMAP36xx
This patch updates the clock dividers for the graphics
processor.
It is based on commit:
c4e1d9b718b65436e30422506f43fa4eb21069d3
at http://arago-project.org/git/projects/?p=u-boot-omap3.git
Signed-off-by: Sanjeev Premi <premi@ti.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| -rw-r--r-- | arch/arm/mach-omap/include/mach/omap3-clock.h | 3 | ||||
| -rw-r--r-- | arch/arm/mach-omap/omap3_clock.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-omap/omap3_clock_core.S | 2 |
3 files changed, 4 insertions, 3 deletions
diff --git a/arch/arm/mach-omap/include/mach/omap3-clock.h b/arch/arm/mach-omap/include/mach/omap3-clock.h index cccb0da156..10566e11cc 100644 --- a/arch/arm/mach-omap/include/mach/omap3-clock.h +++ b/arch/arm/mach-omap/include/mach/omap3-clock.h @@ -108,7 +108,8 @@ #define CORE_FUSB_DIV 2 /* 41.5MHz: */ #define CORE_L4_DIV 2 /* 83MHz : L4 */ #define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */ -#define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */ +#define GFX_DIV_34X 3 /* 96MHz : CM_CLKSEL_GFX (OMAP34XX) */ +#define GFX_DIV_36X 5 /* 200MHz : CM_CLKSEL_GFX (OMAP36XX) */ #define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */ /* PER DPLL */ diff --git a/arch/arm/mach-omap/omap3_clock.c b/arch/arm/mach-omap/omap3_clock.c index 16cbae9fb5..3a0ab24e58 100644 --- a/arch/arm/mach-omap/omap3_clock.c +++ b/arch/arm/mach-omap/omap3_clock.c @@ -192,7 +192,7 @@ static void init_core_dpll_34x(u32 cpu_rev, u32 clk_sel) sr32(CM_REG(CLKSEL_CORE), 4, 2, CORE_FUSB_DIV); sr32(CM_REG(CLKSEL_CORE), 2, 2, CORE_L4_DIV); sr32(CM_REG(CLKSEL_CORE), 0, 2, CORE_L3_DIV); - sr32(CM_REG(CLKSEL_GFX), 0, 3, GFX_DIV); + sr32(CM_REG(CLKSEL_GFX), 0, 3, GFX_DIV_34X); sr32(CM_REG(CLKSEL_WKUP), 1, 2, WKUP_RSM); /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */ diff --git a/arch/arm/mach-omap/omap3_clock_core.S b/arch/arm/mach-omap/omap3_clock_core.S index eb13c2ff90..c8d04bbc29 100644 --- a/arch/arm/mach-omap/omap3_clock_core.S +++ b/arch/arm/mach-omap/omap3_clock_core.S @@ -194,7 +194,7 @@ pll_div_val3: pll_div_add4: .word CM_CLKSEL_GFX pll_div_val4: - .word (GFX_DIV << 0) + .word GFX_DIV_34X pll_div_add5: .word CM_CLKSEL1_EMU pll_div_val5: |