diff options
| author | Sanjeev Premi <premi@ti.com> | 2011-01-03 19:54:54 +0530 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2011-01-05 11:05:25 +0100 |
| commit | f2fccf6473d08d15c05c0d2d55742b26eff946c8 (patch) | |
| tree | ba123070762b629d4bad948ab847174f2d17ec63 | |
| parent | d03d53f9d503f0d2f0f30a7720739def773158fd (diff) | |
| download | barebox-f2fccf6473d08d15c05c0d2d55742b26eff946c8.tar.gz barebox-f2fccf6473d08d15c05c0d2d55742b26eff946c8.tar.xz | |
omap3: Avoid sudden change to SYS_CLK divider
In function get_osc_clk_speed(), the SYS_CLK divider
was being changed 'suddenly'.
This change has cascading effect on the derived clocks,
leading to inconsistent behavior - often a crash.
Signed-off-by: Sanjeev Premi <premi@ti.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| -rw-r--r-- | arch/arm/mach-omap/include/mach/omap3-clock.h | 6 | ||||
| -rw-r--r-- | arch/arm/mach-omap/omap3_clock.c | 19 |
2 files changed, 21 insertions, 4 deletions
diff --git a/arch/arm/mach-omap/include/mach/omap3-clock.h b/arch/arm/mach-omap/include/mach/omap3-clock.h index b9e2714387..cccb0da156 100644 --- a/arch/arm/mach-omap/include/mach/omap3-clock.h +++ b/arch/arm/mach-omap/include/mach/omap3-clock.h @@ -92,6 +92,12 @@ #define PLL_FAST_RELOCK_BYPASS 6 /* CORE */ #define PLL_LOCK 7 /* MPU, IVA, CORE & PER */ +/* + * Bit positions indicating current SYSCLK divider + */ +#define SYSCLK_DIV_1 (1 << 6) +#define SYSCLK_DIV_2 (1 << 7) + /* The following configurations are OPP and SysClk value independant * and hence are defined here. */ diff --git a/arch/arm/mach-omap/omap3_clock.c b/arch/arm/mach-omap/omap3_clock.c index 1668369d5b..16cbae9fb5 100644 --- a/arch/arm/mach-omap/omap3_clock.c +++ b/arch/arm/mach-omap/omap3_clock.c @@ -65,12 +65,20 @@ static void per_clocks_enable(void); */ static u32 get_osc_clk_speed(void) { - u32 start, cstart, cend, cdiff, val; + u32 start, cstart, cend, cdiff, cdiv, val; val = readl(PRM_REG(CLKSRC_CTRL)); - /* If SYS_CLK is being divided by 2, remove for now */ - val = (val & (~(0x1 << 7))) | (0x1 << 6); - writel(val, PRM_REG(CLKSRC_CTRL)); + + if (val & SYSCLK_DIV_2) + cdiv = 2; + else if (val & SYSCLK_DIV_1) + cdiv = 1; + else + /* + * Should never reach here! + * To proceed, assume divider as 1. + */ + cdiv = 1; /* enable timer2 */ val = readl(CM_REG(CLKSEL_WKUP)) | (0x1 << 0); @@ -97,6 +105,9 @@ static u32 get_osc_clk_speed(void) cend = readl(OMAP_GPTIMER1_BASE + TCRR); cdiff = cend - cstart; /* get elapsed ticks */ + if (cdiv == 2) + cdiff *= 2; + /* based on number of ticks assign speed */ if (cdiff > 19000) return S38_4M; |