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authorSascha Hauer <s.hauer@pengutronix.de>2011-04-08 14:31:38 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2011-04-12 09:54:55 +0200
commit2053e35f20d087de61d57c1a807a479cddc4bd7b (patch)
treeab495444a65a34428b3b42d29345de75990ba3fd
parentf800f73cb8a9b8fd17e4ce73f398dd0b7f729b49 (diff)
downloadbarebox-2053e35f20d087de61d57c1a807a479cddc4bd7b.tar.gz
barebox-2053e35f20d087de61d57c1a807a479cddc4bd7b.tar.xz
nand omap: fix hamming romcode ecc code
This got broken in commit: 6943635 mtd nand omap: make ecc mode runtime configurable Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--drivers/mtd/nand/nand_omap_gpmc.c18
1 files changed, 14 insertions, 4 deletions
diff --git a/drivers/mtd/nand/nand_omap_gpmc.c b/drivers/mtd/nand/nand_omap_gpmc.c
index 15996039e6..74ef1ac59a 100644
--- a/drivers/mtd/nand/nand_omap_gpmc.c
+++ b/drivers/mtd/nand/nand_omap_gpmc.c
@@ -470,7 +470,7 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
struct gpmc_nand_info *oinfo = (struct gpmc_nand_info *)(nand->priv);
unsigned int bch_mod = 0, bch_wrapmode = 0, eccsize1 = 0, eccsize0 = 0;
unsigned int ecc_conf_val = 0, ecc_size_conf_val = 0;
- int dev_width = 0;
+ int dev_width = nand->options & NAND_BUSWIDTH_16 ? 0 : 1;
int ecc_size = nand->ecc.size;
int cs = 0;
@@ -508,7 +508,11 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
/* clear ecc and enable bits */
if (oinfo->ecc_mode == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) {
writel(0x00000101, oinfo->gpmc_base + GPMC_ECC_CONTROL);
- ecc_size_conf_val = (eccsize1 << 22) | 0x0000000F;
+ /* Size 0 = 0xFF, Size1 is 0xFF - both are 512 bytes
+ * tell all regs to generate size0 sized regs
+ * we just have a single ECC engine for all CS
+ */
+ ecc_size_conf_val = 0x3FCFF000;
ecc_conf_val = (dev_width << 7) | (cs << 1) | (0x1);
} else {
writel(0x1, oinfo->gpmc_base + GPMC_ECC_CONTROL);
@@ -557,6 +561,14 @@ static int omap_gpmc_eccmode(struct gpmc_nand_info *oinfo,
case OMAP_ECC_HAMMING_CODE_HW_ROMCODE:
oinfo->nand.ecc.bytes = 3;
oinfo->nand.ecc.size = 512;
+ oinfo->ecc_parity_pairs = 12;
+ if (oinfo->nand.options & NAND_BUSWIDTH_16) {
+ offset = 2;
+ } else {
+ offset = 1;
+ oinfo->nand.badblock_pattern = &bb_descrip_flashbased;
+ }
+ omap_oobinfo.eccbytes = 3 * (minfo->oobsize / 16);
for (i = 0; i < omap_oobinfo.eccbytes; i++)
omap_oobinfo.eccpos[i] = i + offset;
omap_oobinfo.oobfree->offset = offset + omap_oobinfo.eccbytes;
@@ -613,8 +625,6 @@ static int omap_gpmc_eccmode(struct gpmc_nand_info *oinfo,
return -EINVAL;
}
- omap_oobinfo.eccbytes = oinfo->nand.ecc.bytes;
-
oinfo->ecc_mode = mode;
if (nand->buffers)