Merge branch 'pu-mmu' into next

24 files changed, 210 insertions, 262 deletions

diff --git a/arch/arm/boards/chumby_falconwing/falconwing.c b/arch/arm/boards/chumby_falconwing/falconwing.c
index b20dd743a9..1c66eb231a 100644
--- a/arch/arm/boards/chumby_falconwing/falconwing.c
+++ b/arch/arm/boards/chumby_falconwing/falconwing.c
@@ -265,16 +265,6 @@ static int falconwing_mem_init(void)
 {
 	arm_add_mem_device("ram0", IMX_MEMORY_BASE, 64 * 1024 * 1024);
 
-#ifdef CONFIG_MMU
-	mmu_init();
-
-	arm_create_section(0x40000000, 0x40000000, 64, PMD_SECT_DEF_CACHED);
-	arm_create_section(0x50000000, 0x40000000, 64, PMD_SECT_DEF_UNCACHED);
-
-	setup_dma_coherent(0x10000000);
-
-	mmu_enable();
-#endif
 	return 0;
 }
 mem_initcall(falconwing_mem_init);
diff --git a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
index 5c07597efa..1c54202dfa 100644
--- a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
+++ b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
@@ -160,16 +160,6 @@ static int eukrea_cpuimx25_mem_init(void)
 {
 	arm_add_mem_device("ram0", IMX_SDRAM_CS0, 64 * 1024 * 1024);
 
-#ifdef CONFIG_MMU
-	mmu_init();
-
-	arm_create_section(0x80000000, 0x80000000, 128, PMD_SECT_DEF_CACHED);
-	arm_create_section(0x90000000, 0x80000000, 128, PMD_SECT_DEF_UNCACHED);
-
-	setup_dma_coherent(0x10000000);
-
-	mmu_enable();
-#endif
 	return 0;
 }
 mem_initcall(eukrea_cpuimx25_mem_init);
diff --git a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
index ac886fa303..a5aadac0d9 100644
--- a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
+++ b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
@@ -92,16 +92,6 @@ static int eukrea_cpuimx27_mem_init(void)
 {
 	arm_add_mem_device("ram0", 0xa0000000, SDRAM0 * 1024 * 1024);
 
-#ifdef CONFIG_MMU
-	mmu_init();
-
-	arm_create_section(0xa0000000, 0xa0000000, 128, PMD_SECT_DEF_CACHED);
-	arm_create_section(0xb0000000, 0xa0000000, 128, PMD_SECT_DEF_UNCACHED);
-
-	setup_dma_coherent(0x10000000);
-
-	mmu_enable();
-#endif
 	return 0;
 }
 mem_initcall(eukrea_cpuimx27_mem_init);
diff --git a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
index 02df444e39..426445f59d 100644
--- a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
+++ b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
@@ -130,23 +130,17 @@ static int eukrea_cpuimx35_mem_init(void)
 {
 	arm_add_mem_device("ram0", IMX_SDRAM_CS0, 128 * 1024 * 1024);
 
-#ifdef CONFIG_MMU
-	mmu_init();
-
-	arm_create_section(0x80000000, 0x80000000, 128, PMD_SECT_DEF_CACHED);
-	arm_create_section(0x90000000, 0x80000000, 128, PMD_SECT_DEF_UNCACHED);
-
-	setup_dma_coherent(0x10000000);
-
-	mmu_enable();
+	return 0;
+}
+mem_initcall(eukrea_cpuimx35_mem_init);
 
-#ifdef CONFIG_CACHE_L2X0
+static int eukrea_cpuimx35_mmu_init(void)
+{
 	l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000);
-#endif
-#endif
+
 	return 0;
 }
-mem_initcall(eukrea_cpuimx35_mem_init);
+postmmu_initcall(eukrea_cpuimx35_mmu_init);
 
 static int eukrea_cpuimx35_devices_init(void)
 {
diff --git a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c
index b6fce93289..727db29241 100644
--- a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c
+++ b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c
@@ -97,22 +97,6 @@ static int eukrea_cpuimx51_mem_init(void)
 {
 	arm_add_mem_device("ram0", 0x90000000, 256 * 1024 * 1024);
 
-#ifdef CONFIG_MMU
-	mmu_init();
-
-	arm_create_section(0x90000000, 0x90000000, 256, PMD_SECT_DEF_CACHED);
-	arm_create_section(0xa0000000, 0x90000000, 256, PMD_SECT_DEF_UNCACHED);
-
-	setup_dma_coherent(0x10000000);
-
-#if TEXT_BASE & (0x100000 - 1)
-#warning cannot create vector section. Adjust TEXT_BASE to a 1M boundary
-#else
-	arm_create_section(0x0,        TEXT_BASE,   1, PMD_SECT_DEF_UNCACHED);
-#endif
-
-	mmu_enable();
-#endif
 	return 0;
 }
 mem_initcall(eukrea_cpuimx51_mem_init);
diff --git a/arch/arm/boards/freescale-mx51-pdk/board.c b/arch/arm/boards/freescale-mx51-pdk/board.c
index f34765737b..d6472df69f 100644
--- a/arch/arm/boards/freescale-mx51-pdk/board.c
+++ b/arch/arm/boards/freescale-mx51-pdk/board.c
@@ -77,16 +77,6 @@ static int babbage_mem_init(void)
 {
 	arm_add_mem_device("ram0", 0x90000000, 512 * 1024 * 1024);
 
-#ifdef CONFIG_MMU
-	mmu_init();
-
-	arm_create_section(0x90000000, 0x90000000, 512, PMD_SECT_DEF_CACHED);
-	arm_create_section(0xb0000000, 0x90000000, 512, PMD_SECT_DEF_UNCACHED);
-
-	setup_dma_coherent(0x20000000);
-
-	mmu_enable();
-#endif
 	return 0;
 }
 mem_initcall(babbage_mem_init);
diff --git a/arch/arm/boards/freescale-mx53-loco/board.c b/arch/arm/boards/freescale-mx53-loco/board.c
index 92cff017fb..b5240f4f3a 100644
--- a/arch/arm/boards/freescale-mx53-loco/board.c
+++ b/arch/arm/boards/freescale-mx53-loco/board.c
@@ -78,18 +78,6 @@ static int loco_mem_init(void)
 	arm_add_mem_device("ram0", 0x70000000, SZ_512M);
 	arm_add_mem_device("ram1", 0xb0000000, SZ_512M);
 
-#ifdef CONFIG_MMU
-	mmu_init();
-
-	arm_create_section(0x70000000, 0x70000000, 512, PMD_SECT_DEF_CACHED);
-	arm_create_section(0x90000000, 0x70000000, 512, PMD_SECT_DEF_UNCACHED);
-	arm_create_section(0xb0000000, 0xb0000000, 512, PMD_SECT_DEF_CACHED);
-	arm_create_section(0xd0000000, 0xb0000000, 512, PMD_SECT_DEF_UNCACHED);
-
-	setup_dma_coherent(0x20000000);
-
-	mmu_enable();
-#endif
 	return 0;
 }
 mem_initcall(loco_mem_init);
diff --git a/arch/arm/boards/guf-cupid/board.c b/arch/arm/boards/guf-cupid/board.c
index 134f377165..706707d0bb 100644
--- a/arch/arm/boards/guf-cupid/board.c
+++ b/arch/arm/boards/guf-cupid/board.c
@@ -100,23 +100,17 @@ static int cupid_mem_init(void)
 {
 	arm_add_mem_device("ram0", IMX_SDRAM_CS0, 128 * 1024 * 1024);
 
-#ifdef CONFIG_MMU
-	mmu_init();
-
-	arm_create_section(0x80000000, 0x80000000, 128, PMD_SECT_DEF_CACHED);
-	arm_create_section(0x90000000, 0x80000000, 128, PMD_SECT_DEF_UNCACHED);
-
-	setup_dma_coherent(0x10000000);
-
-	mmu_enable();
+	return 0;
+}
+mem_initcall(cupid_mem_init);
 
-#ifdef CONFIG_CACHE_L2X0
+static int cupid_mmu_init(void)
+{
 	l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000);
-#endif
-#endif
+
 	return 0;
 }
-mem_initcall(cupid_mem_init);
+postmmu_initcall(cupid_mmu_init);
 
 static int cupid_devices_init(void)
 {
diff --git a/arch/arm/boards/guf-neso/board.c b/arch/arm/boards/guf-neso/board.c
index 3517a5dfa0..446b333f1f 100644
--- a/arch/arm/boards/guf-neso/board.c
+++ b/arch/arm/boards/guf-neso/board.c
@@ -140,16 +140,6 @@ static int neso_mem_init(void)
 {
 	arm_add_mem_device("ram0", 0xa0000000, 128 * 1024 * 1024);
 
-#ifdef CONFIG_MMU
-	mmu_init();
-
-	arm_create_section(0xa0000000, 0xa0000000, 128, PMD_SECT_DEF_CACHED);
-	arm_create_section(0xb0000000, 0xa0000000, 128, PMD_SECT_DEF_UNCACHED);
-
-	setup_dma_coherent(0x10000000);
-
-	mmu_enable();
-#endif
 	return 0;
 }
 mem_initcall(neso_mem_init);
diff --git a/arch/arm/boards/karo-tx25/board.c b/arch/arm/boards/karo-tx25/board.c
index a01fa3c25d..22bc27a291 100644
--- a/arch/arm/boards/karo-tx25/board.c
+++ b/arch/arm/boards/karo-tx25/board.c
@@ -59,18 +59,6 @@ static int tx25_mem_init(void)
 	add_mem_device("ram0", 0x78000000, 128 * 1024,
 				   IORESOURCE_MEM_WRITEABLE);
 
-#ifdef CONFIG_MMU
-	mmu_init();
-
-	arm_create_section(0x80000000, 0x80000000, 32, PMD_SECT_DEF_CACHED);
-	arm_create_section(0x82000000, 0x80000000, 32, PMD_SECT_DEF_UNCACHED);
-	arm_create_section(0x90000000, 0x90000000, 32, PMD_SECT_DEF_CACHED);
-	arm_create_section(0x92000000, 0x90000000, 32, PMD_SECT_DEF_UNCACHED);
-
-	setup_dma_coherent(0x02000000);
-
-	mmu_enable();
-#endif
 	return 0;
 }
 mem_initcall(tx25_mem_init);
diff --git a/arch/arm/boards/karo-tx28/tx28.c b/arch/arm/boards/karo-tx28/tx28.c
index d6e3f9c25c..def388a8d9 100644
--- a/arch/arm/boards/karo-tx28/tx28.c
+++ b/arch/arm/boards/karo-tx28/tx28.c
@@ -74,16 +74,6 @@ static int tx28_mem_init(void)
 {
 	arm_add_mem_device("ram0", IMX_MEMORY_BASE, 128 * 1024 * 1024);
 
-#ifdef CONFIG_MMU
-	mmu_init();
-
-	arm_create_section(0x40000000, 0x40000000, 128, PMD_SECT_DEF_CACHED);
-	arm_create_section(0x50000000, 0x40000000, 128, PMD_SECT_DEF_UNCACHED);
-
-	setup_dma_coherent(0x10000000);
-
-	mmu_enable();
-#endif
 	return 0;
 }
 mem_initcall(tx28_mem_init);
diff --git a/arch/arm/boards/panda/board.c b/arch/arm/boards/panda/board.c
index 696d44a819..1303c47233 100644
--- a/arch/arm/boards/panda/board.c
+++ b/arch/arm/boards/panda/board.c
@@ -48,14 +48,6 @@ static int panda_mem_init(void)
 {
 	arm_add_mem_device("ram0", 0x80000000, SZ_1G);
 
-#ifdef CONFIG_MMU
-	mmu_init();
-
-	arm_create_section(0x80000000, 0x80000000, 256, PMD_SECT_DEF_CACHED);
-	arm_create_section(0x90000000, 0x80000000, 256, PMD_SECT_DEF_UNCACHED);
-
-	mmu_enable();
-#endif
 	return 0;
 }
 mem_initcall(panda_mem_init);
diff --git a/arch/arm/boards/pcm037/pcm037.c b/arch/arm/boards/pcm037/pcm037.c
index a026f2367d..85f004fe48 100644
--- a/arch/arm/boards/pcm037/pcm037.c
+++ b/arch/arm/boards/pcm037/pcm037.c
@@ -153,23 +153,17 @@ static int pcm037_mem_init(void)
 	arm_add_mem_device("ram1", IMX_SDRAM_CS1, SDRAM1 * 1024 * 1024);
 #endif
 
-#ifdef CONFIG_MMU
-	mmu_init();
-
-	arm_create_section(0x80000000, 0x80000000, 128, PMD_SECT_DEF_CACHED);
-	arm_create_section(0x90000000, 0x80000000, 128, PMD_SECT_DEF_UNCACHED);
-
-	setup_dma_coherent(0x10000000);
-
-	mmu_enable();
+	return 0;
+}
+mem_initcall(pcm037_mem_init);
 
-#ifdef CONFIG_CACHE_L2X0
+static int pcm037_mmu_init(void)
+{
 	l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000);
-#endif
-#endif
+
 	return 0;
 }
-mem_initcall(pcm037_mem_init);
+postmmu_initcall(pcm037_mmu_init);
 
 static int imx31_devices_init(void)
 {
diff --git a/arch/arm/boards/pcm038/pcm038.c b/arch/arm/boards/pcm038/pcm038.c
index 9588b9be67..4db50fe8c0 100644
--- a/arch/arm/boards/pcm038/pcm038.c
+++ b/arch/arm/boards/pcm038/pcm038.c
@@ -135,16 +135,6 @@ static int pcm038_mem_init(void)
 
 	add_mem_device("ram0", 0xc8000000, 512 * 1024, /* Can be up to 2MiB */
 				   IORESOURCE_MEM_WRITEABLE);
-#ifdef CONFIG_MMU
-	mmu_init();
-
-	arm_create_section(0xa0000000, 0xa0000000, 128, PMD_SECT_DEF_CACHED);
-	arm_create_section(0xb0000000, 0xa0000000, 128, PMD_SECT_DEF_UNCACHED);
-
-	setup_dma_coherent(0x10000000);
-
-	mmu_enable();
-#endif
 	return 0;
 }
 mem_initcall(pcm038_mem_init);
diff --git a/arch/arm/boards/pcm043/pcm043.c b/arch/arm/boards/pcm043/pcm043.c
index 10d319fa1d..966899a5ba 100644
--- a/arch/arm/boards/pcm043/pcm043.c
+++ b/arch/arm/boards/pcm043/pcm043.c
@@ -103,24 +103,17 @@ static int pcm043_mem_init(void)
 {
 	arm_add_mem_device("ram0", IMX_SDRAM_CS0, 128 * 1024 * 1024);
 
-#ifdef CONFIG_MMU
-	mmu_init();
-
-	arm_create_section(0x80000000, 0x80000000, 128, PMD_SECT_DEF_CACHED);
-	arm_create_section(0x90000000, 0x80000000, 128, PMD_SECT_DEF_UNCACHED);
-
-	setup_dma_coherent(0x10000000);
-
-	mmu_enable();
-
-#ifdef CONFIG_CACHE_L2X0
-	l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000);
-#endif
-#endif
 	return 0;
 }
 mem_initcall(pcm043_mem_init);
 
+static int pcm043_mmu_init(void)
+{
+	l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000);
+
+	return 0;
+}
+postmmu_initcall(pcm043_mmu_init);
 
 struct gpio_led led0 = {
 	.gpio = 1 * 32 + 6,
diff --git a/arch/arm/boards/pcm049/board.c b/arch/arm/boards/pcm049/board.c
index 83eb9be3ef..502e121b45 100644
--- a/arch/arm/boards/pcm049/board.c
+++ b/arch/arm/boards/pcm049/board.c
@@ -60,15 +60,6 @@ static int pcm049_mem_init(void)
 
 	add_mem_device("sram0", 0x40300000, 48 * 1024,
 				   IORESOURCE_MEM_WRITEABLE);
-#ifdef CONFIG_MMU
-	mmu_init();
-
-	arm_create_section(0x80000000, 0x80000000, 256, PMD_SECT_DEF_CACHED);
-	/* warning: This shadows the second half of our ram */
-	arm_create_section(0x90000000, 0x80000000, 256, PMD_SECT_DEF_UNCACHED);
-
-	mmu_enable();
-#endif
 	return 0;
 }
 mem_initcall(pcm049_mem_init);
diff --git a/arch/arm/boards/phycard-i.MX27/pca100.c b/arch/arm/boards/phycard-i.MX27/pca100.c
index 3c2a0e458f..f285466641 100644
--- a/arch/arm/boards/phycard-i.MX27/pca100.c
+++ b/arch/arm/boards/phycard-i.MX27/pca100.c
@@ -73,16 +73,6 @@ static int pca100_mem_init(void)
 {
 	arm_add_mem_device("ram0", 0xa0000000, 128 * 1024 * 1024);
 
-#ifdef CONFIG_MMU
-	mmu_init();
-
-	arm_create_section(0xa0000000, 0xa0000000, 128, PMD_SECT_DEF_CACHED);
-	arm_create_section(0xb0000000, 0xa0000000, 128, PMD_SECT_DEF_UNCACHED);
-
-	setup_dma_coherent(0x10000000);
-
-	mmu_enable();
-#endif
 	return 0;
 }
 mem_initcall(pca100_mem_init);
diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
index bb067e36b4..1f62d61b69 100644
--- a/arch/arm/cpu/mmu.c
+++ b/arch/arm/cpu/mmu.c
@@ -1,10 +1,13 @@
 #include <common.h>
 #include <init.h>
 #include <asm/mmu.h>
+#include <errno.h>
+#include <sizes.h>
+#include <asm/memory.h>
 
 static unsigned long *ttb;
 
-void arm_create_section(unsigned long virt, unsigned long phys, int size_m,
+static void create_section(unsigned long virt, unsigned long phys, int size_m,
 		unsigned int flags)
 {
 	int i;
@@ -24,6 +27,33 @@ void arm_create_section(unsigned long virt, unsigned long phys, int size_m,
 }
 
 /*
+ * Do it the simple way for now and invalidate the entire
+ * tlb
+ */
+static inline void tlb_invalidate(void)
+{
+	asm volatile (
+		"mov	r0, #0\n"
+		"mcr	p15, 0, r0, c7, c10, 4;	@ drain write buffer\n"
+		"mcr	p15, 0, r0, c8, c6, 0;  @ invalidate D TLBs\n"
+		"mcr	p15, 0, r0, c8, c5, 0;  @ invalidate I TLBs\n"
+		:
+		:
+		: "r0"
+	);
+}
+
+#ifdef CONFIG_CPU_V7
+#define PTE_FLAGS_CACHED (PTE_EXT_TEX(1) | PTE_BUFFERABLE | PTE_CACHEABLE)
+#define PTE_FLAGS_UNCACHED (0)
+#else
+#define PTE_FLAGS_CACHED (PTE_SMALL_AP_UNO_SRW | PTE_BUFFERABLE | PTE_CACHEABLE)
+#define PTE_FLAGS_UNCACHED PTE_SMALL_AP_UNO_SRW
+#endif
+
+#define PTE_MASK ((1 << 12) - 1)
+
+/*
  * Create a second level translation table for the given virtual address.
  * We initially create a flat uncached mapping on it.
  * Not yet exported, but may be later if someone finds use for it.
@@ -37,12 +67,92 @@ static u32 *arm_create_pte(unsigned long virt)
 
 	ttb[virt] = (unsigned long)table | PMD_TYPE_TABLE;
 
-	for (i = 0; i < 256; i++)
-		table[i] = virt | PTE_TYPE_SMALL | PTE_SMALL_AP_UNO_SRW;
+	for (i = 0; i < 256; i++) {
+		table[i] = virt | PTE_TYPE_SMALL | PTE_FLAGS_UNCACHED;
+		virt += PAGE_SIZE;
+	}
 
 	return table;
 }
 
+static void remap_range(void *_start, size_t size, uint32_t flags)
+{
+	u32 pteentry;
+	struct arm_memory *mem;
+	unsigned long start = (unsigned long)_start;
+	u32 *p;
+	int numentries, i;
+
+	for_each_sdram_bank(mem) {
+		if (start >= mem->start && start < mem->start + mem->size)
+			goto found;
+	}
+
+	BUG();
+	return;
+
+found:
+	pteentry = (start - mem->start) >> PAGE_SHIFT;
+
+	numentries = size >> PAGE_SHIFT;
+
+	p = mem->ptes + pteentry;
+
+	for (i = 0; i < numentries; i++) {
+		p[i] &= ~PTE_MASK;
+		p[i] |= flags | PTE_TYPE_SMALL;
+	}
+
+	dma_flush_range((unsigned long)p,
+			(unsigned long)p + numentries * sizeof(u32));
+
+	tlb_invalidate();
+}
+
+/*
+ * remap the memory bank described by mem cachable and
+ * bufferable
+ */
+static int arm_mmu_remap_sdram(struct arm_memory *mem)
+{
+	unsigned long phys = (unsigned long)mem->start;
+	unsigned long ttb_start = phys >> 20;
+	unsigned long ttb_end = (phys + mem->size) >> 20;
+	unsigned long num_ptes = mem->size >> 10;
+	int i, pte;
+
+	debug("remapping SDRAM from 0x%08lx (size 0x%08lx)\n",
+			phys, mem->size);
+
+	/*
+	 * We replace each 1MiB section in this range with second level page
+	 * tables, therefore we must have 1Mib aligment here.
+	 */
+	if ((phys & (SZ_1M - 1)) || (mem->size & (SZ_1M - 1)))
+		return -EINVAL;
+
+	mem->ptes = memalign(0x400, num_ptes * sizeof(u32));
+
+	debug("ptes: 0x%p ttb_start: 0x%08lx ttb_end: 0x%08lx\n",
+			mem->ptes, ttb_start, ttb_end);
+
+	for (i = 0; i < num_ptes; i++) {
+		mem->ptes[i] = (phys + i * 4096) | PTE_TYPE_SMALL |
+			PTE_FLAGS_CACHED;
+	}
+
+	pte = 0;
+
+	for (i = ttb_start; i < ttb_end; i++) {
+		ttb[i] = (unsigned long)(&mem->ptes[pte]) | PMD_TYPE_TABLE |
+			(0 << 4);
+		pte += 256;
+	}
+
+	tlb_invalidate();
+
+	return 0;
+}
 /*
  * We have 8 exception vectors and the table consists of absolute
  * jumps, so we need 8 * 4 bytes for the instructions and another
@@ -66,19 +176,21 @@ static void vectors_init(void)
 	memset(vectors, 0, PAGE_SIZE);
 	memcpy(vectors, &exception_vectors, ARM_VECTORS_SIZE);
 
-	exc[0] = (u32)vectors | PTE_TYPE_SMALL | PTE_SMALL_AP_UNO_SRW;
+	exc[0] = (u32)vectors | PTE_TYPE_SMALL | PTE_FLAGS_CACHED;
 }
 
 /*
- * Prepare MMU for usage and create a flat mapping. Board
- * code is responsible to remap the SDRAM cached
+ * Prepare MMU for usage enable it.
  */
-void mmu_init(void)
+static int mmu_init(void)
 {
+	struct arm_memory *mem;
 	int i;
 
 	ttb = memalign(0x10000, 0x4000);
 
+	debug("ttb: 0x%p\n", ttb);
+
 	/* Set the ttb register */
 	asm volatile ("mcr  p15,0,%0,c2,c0,0" : : "r"(ttb) /*:*/);
 
@@ -86,24 +198,38 @@ void mmu_init(void)
 	i = 0x3;
 	asm volatile ("mcr  p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
 
-	/* create a flat mapping */
-	arm_create_section(0, 0, 4096, PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT);
+	/* create a flat mapping using 1MiB sections */
+	create_section(0, 0, 4096, PMD_SECT_AP_WRITE | PMD_SECT_AP_READ |
+			PMD_TYPE_SECT);
 
 	vectors_init();
-}
 
-/*
- * enable the MMU. Should be called after mmu_init()
- */
-void mmu_enable(void)
-{
+	/*
+	 * First remap sdram cached using sections.
+	 * This is to speed up the generation of 2nd level page tables
+	 * below
+	 */
+	for_each_sdram_bank(mem)
+		create_section(mem->start, mem->start, mem->size >> 20,
+				PMD_SECT_DEF_CACHED);
+
 	asm volatile (
 		"bl __mmu_cache_on;"
 		:
 		:
 		: "r0", "r1", "r2", "r3", "r6", "r10", "r12", "cc", "memory"
         );
+
+	/*
+	 * Now that we have the MMU and caches on remap sdram again using
+	 * page tables
+	 */
+	for_each_sdram_bank(mem)
+		arm_mmu_remap_sdram(mem);
+
+	return 0;
 }
+mmu_initcall(mmu_init);
 
 struct outer_cache_fns outer_cache;
 
@@ -125,39 +251,41 @@ void mmu_disable(void)
 	);
 }
 
-/*
- * For boards which need coherent memory for DMA. The idea
- * is simple: Setup a uncached section containing your SDRAM
- * and call setup_dma_coherent() with the offset between the
- * cached and the uncached section. dma_alloc_coherent() then
- * works using normal malloc but returns the corresponding
- * pointer in the uncached area.
- */
-static unsigned long dma_coherent_offset;
-
-void setup_dma_coherent(unsigned long offset)
-{
-	dma_coherent_offset = offset;
-}
+#define PAGE_ALIGN(s) ((s) + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1);
 
 void *dma_alloc_coherent(size_t size)
 {
-	return xmemalign(4096, size) + dma_coherent_offset;
+	void *ret;
+
+	size = PAGE_ALIGN(size);
+	ret = xmemalign(4096, size);
+
+#ifdef CONFIG_MMU
+	dma_inv_range((unsigned long)ret, (unsigned long)ret + size);
+
+	remap_range(ret, size, PTE_FLAGS_UNCACHED);
+#endif
+
+	return ret;
 }
 
 unsigned long virt_to_phys(void *virt)
 {
-	return (unsigned long)virt - dma_coherent_offset;
+	return (unsigned long)virt;
 }
 
 void *phys_to_virt(unsigned long phys)
 {
-	return (void *)(phys + dma_coherent_offset);
+	return (void *)phys;
 }
 
 void dma_free_coherent(void *mem, size_t size)
 {
-	free(mem - dma_coherent_offset);
+#ifdef CONFIG_MMU
+	remap_range(mem, size, PTE_FLAGS_CACHED);
+#endif
+
+	free(mem);
 }
 
 void dma_clean_range(unsigned long start, unsigned long end)
diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h
index 9ebc2cd4c1..9ca5e2ab3a 100644
--- a/arch/arm/include/asm/mmu.h
+++ b/arch/arm/include/asm/mmu.h
@@ -3,17 +3,25 @@
 
 #include <asm/pgtable.h>
 #include <malloc.h>
+#include <errno.h>
 
 #define PMD_SECT_DEF_UNCACHED (PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT)
 #define PMD_SECT_DEF_CACHED (PMD_SECT_WB | PMD_SECT_DEF_UNCACHED)
 
-void mmu_init(void);
-void mmu_enable(void);
+struct arm_memory;
+
+static inline void mmu_enable(void)
+{
+}
 void mmu_disable(void);
-void arm_create_section(unsigned long virt, unsigned long phys, int size_m,
-		unsigned int flags);
+static inline void arm_create_section(unsigned long virt, unsigned long phys, int size_m,
+		unsigned int flags)
+{
+}
 
-void setup_dma_coherent(unsigned long offset);
+static inline void setup_dma_coherent(unsigned long offset)
+{
+}
 
 #ifdef CONFIG_MMU
 void *dma_alloc_coherent(size_t size);
@@ -26,11 +34,6 @@ unsigned long virt_to_phys(void *virt);
 void *phys_to_virt(unsigned long phys);
 
 #else
-static inline int mmu_init(void)
-{
-	return -EINVAL;
-}
-
 static inline void *dma_alloc_coherent(size_t size)
 {
 	return xmemalign(4096, size);
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index e661142306..8dc6a24fb5 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -182,7 +182,6 @@ config MACH_SCB9328
 	select HAS_DM9000
 	select HAS_CFI
 	select MACH_HAS_LOWLEVEL_INIT
-	select HAVE_MMU
 	help
 	  Say Y here if you are using the Synertronixx scb9328 board
 
@@ -222,7 +221,6 @@ choice
 config MACH_EUKREA_CPUIMX25
 	bool "Eukrea CPUIMX25"
 	select MACH_HAS_LOWLEVEL_INIT
-	select HAVE_MMU
 	help
 	  Say Y here if you are using the Eukrea Electromatique's CPUIMX25
 	  equipped with a Freescale i.MX25 Processor
@@ -240,7 +238,6 @@ config MACH_FREESCALE_MX25_3STACK
 config MACH_TX25
 	bool "Ka-Ro TX25"
 	select MACH_HAS_LOWLEVEL_INIT
-	select HAVE_MMU
 	help
 	  Say Y here if you are using the Ka-Ro tx25 board
 
@@ -259,7 +256,6 @@ choice
 config MACH_EUKREA_CPUIMX27
 	bool "EUKREA CPUIMX27"
 	select HAS_CFI
-	select HAVE_MMU
 	select MACH_HAS_LOWLEVEL_INIT
 	help
 	  Say Y here if you are using Eukrea's CPUIMX27 equipped
@@ -276,7 +272,6 @@ config MACH_IMX27ADS
 config MACH_PCA100
 	bool "phyCard-i.MX27"
 	select MACH_HAS_LOWLEVEL_INIT
-	select HAVE_MMU
 	help
 	  Say Y here if you are using Phytec's phyCard-i.MX27 (pca100) equipped
 	  with a Freescale i.MX27 Processor
@@ -288,7 +283,6 @@ config MACH_PCM038
 	select SPI
 	select DRIVER_SPI_IMX
 	select DRIVER_SPI_MC13783
-	select HAVE_MMU
 	help
 	  Say Y here if you are using Phytec's phyCORE-i.MX27 (pcm038) equipped
 	  with a Freescale i.MX27 Processor
@@ -296,7 +290,6 @@ config MACH_PCM038
 config MACH_NESO
 	bool "Garz+Fricke Neso"
 	select MACH_HAS_LOWLEVEL_INIT
-	select HAVE_MMU
 	help
 	  Say Y here if you are using the Garz+Fricke Neso board equipped
 	  with a Freescale i.MX27 Processor
@@ -316,7 +309,6 @@ choice
 config MACH_PCM037
 	bool "phyCORE-i.MX31"
 	select MACH_HAS_LOWLEVEL_INIT
-	select HAVE_MMU
 	select USB_ISP1504 if USB
 	select ARCH_HAS_L2X0
 	help
@@ -337,7 +329,6 @@ choice
 
 config MACH_EUKREA_CPUIMX35
 	bool "EUKREA CPUIMX35"
-	select HAVE_MMU
 	select MACH_HAS_LOWLEVEL_INIT
 	select ARCH_HAS_L2X0
 	help
@@ -357,21 +348,19 @@ config MACH_FREESCALE_MX35_3STACK
 	  with a Freescale i.MX35 Processor
 
 config MACH_PCM043
-        bool "phyCORE-i.MX35"
-        select HAS_CFI
-	select HAVE_MMU
+	bool "phyCORE-i.MX35"
+	select HAS_CFI
 	select MACH_HAS_LOWLEVEL_INIT
 	select ARCH_HAS_L2X0
-        help
-          Say Y here if you are using Phytec's phyCORE-i.MX35 (pcm043) equipped
-          with a Freescale i.MX35 Processor
+	help
+	  Say Y here if you are using Phytec's phyCORE-i.MX35 (pcm043) equipped
+	  with a Freescale i.MX35 Processor
 
 config MACH_GUF_CUPID
-        bool "Garz+Fricke Cupid"
-	select HAVE_MMU
+	bool "Garz+Fricke Cupid"
 	select MACH_HAS_LOWLEVEL_INIT
 	select ARCH_HAS_L2X0
-        help
+	help
 	  Say Y here if you are using the Garz+Fricke Neso board equipped
 	  with a Freescale i.MX35 Processor
 
@@ -389,12 +378,10 @@ choice
 
 config MACH_FREESCALE_MX51_PDK
 	bool "Freescale i.MX51 PDK"
-	select HAVE_MMU
 	select MACH_HAS_LOWLEVEL_INIT
 
 config MACH_EUKREA_CPUIMX51SD
 	bool "EUKREA CPUIMX51"
-	select HAVE_MMU
 	select MACH_HAS_LOWLEVEL_INIT
 	help
 	  Say Y here if you are using Eukrea's CPUIMX51 equipped
@@ -414,7 +401,6 @@ choice
 
 config MACH_FREESCALE_MX53_LOCO
 	bool "Freescale i.MX53 LOCO"
-	select HAVE_MMU
 	select MACH_HAS_LOWLEVEL_INIT
 
 endchoice
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index f9cefaf907..caef7e0225 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -39,7 +39,6 @@ config MACH_MX23EVK
 
 config MACH_CHUMBY
 	bool "Chumby Falconwing"
-	select HAVE_MMU
 	help
 	  Say Y here if you are using the "chumby one" aka falconwing from
 	  Chumby Industries
@@ -55,7 +54,6 @@ choice
 
 config MACH_TX28
 	bool "KARO tx28"
-	select HAVE_MMU
 	help
 	  Say Y here if you are using the KARO TX28 CPU module.
 
diff --git a/arch/arm/mach-omap/Kconfig b/arch/arm/mach-omap/Kconfig
index f256310cef..1174df072f 100644
--- a/arch/arm/mach-omap/Kconfig
+++ b/arch/arm/mach-omap/Kconfig
@@ -140,7 +140,6 @@ config MACH_OMAP3EVM
 
 config MACH_PANDA
 	bool "Texas Instrument's Panda Board"
-	select HAVE_MMU
 	select HAVE_NOSHELL
 	select MACH_HAS_LOWLEVEL_INIT
 	help
@@ -148,7 +147,6 @@ config MACH_PANDA
 
 config MACH_PCM049
 	bool "Phytec phyCORE pcm049"
-	select HAVE_MMU
 	select HAVE_NOSHELL
 	depends on ARCH_OMAP4
 	select MACH_HAS_LOWLEVEL_INIT
diff --git a/common/Kconfig b/common/Kconfig
index 382b407b98..422d1856b1 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -70,12 +70,8 @@ config ENVIRONMENT_VARIABLES
 
 menu "memory layout                 "
 
-config HAVE_MMU
-	bool
-
 config MMU
 	bool "Enable MMU"
-	depends on HAVE_MMU
 	help
 	  Saying yes here enables the MMU. This is useful on some architectures
 	  to enable the data cache which depends on the MMU. See Documentation/mmu.txt
diff --git a/include/common.h b/include/common.h
index f3353c8643..0ce4a70b56 100644
--- a/include/common.h
+++ b/include/common.h
@@ -221,6 +221,7 @@ int run_shell(void);
 #define ULLONG_MAX	(~0ULL)
 
 #define PAGE_SIZE	4096
+#define PAGE_SHIFT	12
 
 int memory_display(char *addr, ulong offs, ulong nbytes, int size);