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| author | Juergen Beisert <jbe@pengutronix.de> | 2010-11-25 17:52:42 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2011-08-25 11:59:24 +0200 |
| commit | d61e266d248386d00ffb21e4530a30974b3767e5 (patch) | |
| tree | 2a890a8a96eceb321b8b2fa078ba9fffe2348577 | |
| parent | 3f4eb716c42099d771543fbc5af34734e4fad53c (diff) | |
| download | barebox-d61e266d248386d00ffb21e4530a30974b3767e5.tar.gz barebox-d61e266d248386d00ffb21e4530a30974b3767e5.tar.xz | |
phyCORE-i.MX27: Keep frequency multiplier enabled to be able to do a warmstart
commit 7d25a0552dd3a4b65412ae1cbf8f9ca8a88b5d27
Author: Juergen Beisert <jbe@pengutronix.de>
Date: Thu Nov 25 17:49:11 2010 +0100
Keep frequency multiplier enabled to be able to do a warmstart
The wachtdog's reset does only reset the ARM core, not the whole silicon.
But the PLLs seems to do some strange things: It seems they switch back to
the low frequency reference when the watchdog barks. But in the case the
frequency multiplier is off (not used due to 26 MHz reference usage) the
machine stops, because the PLLs are stopping due to the lack of a reference
frequency. As the power on reset will set the FPM_EN bit again, a power cycle
brings the machine back to life.
By keeping the frequency multiplier enabled, also a warmstart triggered by the
watchdog can restart the machine now.
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| -rw-r--r-- | arch/arm/boards/pcm038/pll.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/boards/pcm038/pll.h b/arch/arm/boards/pcm038/pll.h index 13a7989cb5..15b94cfe6a 100644 --- a/arch/arm/boards/pcm038/pll.h +++ b/arch/arm/boards/pcm038/pll.h @@ -36,6 +36,7 @@ CSCR_MCU_SEL | /* 26 MHz reference */ \ CSCR_ARM_DIV(0) | /* CPU runs at MPLL/3 clock */ \ CSCR_AHB_DIV(1) | /* AHB runs at MPLL/6 clock */ \ + CSCR_FPM_EN | \ CSCR_SPEN | \ CSCR_MPEN) @@ -51,6 +52,7 @@ CSCR_ARM_SRC_MPLL | /* use main MPLL clock */ \ CSCR_ARM_DIV(0) | /* CPU run at full MPLL clock */ \ CSCR_AHB_DIV(1) | /* AHB runs at MPLL/6 clock */ \ + CSCR_FPM_EN | /* do not disable it! */ \ CSCR_SPEN | \ CSCR_MPEN) |