Merge branch 'next'

195 files changed, 5411 insertions, 4255 deletions

diff --git a/Documentation/boards.dox b/Documentation/boards.dox
index 8087f015cd..4070d31473 100644
--- a/Documentation/boards.dox
+++ b/Documentation/boards.dox
@@ -18,6 +18,7 @@ ARM type:
 @li @subpage the3stack
 @li @subpage mx23_evk
 @li @subpage board_babage
+@li @subpage board_loco
 @li @subpage chumbyone
 @li @subpage scb9328
 @li @subpage netx
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index c367786fae..f1c045e04f 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -102,6 +102,7 @@ board-$(CONFIG_MACH_MX23EVK)			:= freescale-mx23-evk
 board-$(CONFIG_MACH_CHUMBY)			:= chumby_falconwing
 board-$(CONFIG_MACH_TX28)			:= karo-tx28
 board-$(CONFIG_MACH_FREESCALE_MX51_PDK)		:= freescale-mx51-pdk
+board-$(CONFIG_MACH_FREESCALE_MX53_LOCO)	:= freescale-mx53-loco
 board-$(CONFIG_MACH_GUF_CUPID)			:= guf-cupid
 board-$(CONFIG_MACH_MINI2440)			:= mini2440
 board-$(CONFIG_MACH_VERSATILEPB)		:= versatile
diff --git a/arch/arm/boards/a9m2410/a9m2410.c b/arch/arm/boards/a9m2410/a9m2410.c
index 8cbaec59e3..44ac44bcbc 100644
--- a/arch/arm/boards/a9m2410/a9m2410.c
+++ b/arch/arm/boards/a9m2410/a9m2410.c
@@ -35,44 +35,14 @@
 #include <mach/s3c24x0-iomap.h>
 #include <mach/s3c24x0-nand.h>
 
-static struct memory_platform_data ram_pdata = {
-	.name		= "ram0",
-	.flags		= DEVFS_RDWR,
-};
-
-static struct device_d sdram_dev = {
-	.id		= -1,
-	.name     	= "ram",
-	.map_base	= CS6_BASE,
-	.platform_data  = &ram_pdata,
-};
-
 // {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
 static struct s3c24x0_nand_platform_data nand_info = {
 	.nand_timing = CALC_NFCONF_TIMING(A9M2410_TACLS, A9M2410_TWRPH0, A9M2410_TWRPH1)
 };
 
-static struct device_d nand_dev = {
-	.id	  = -1,
-	.name     = "s3c24x0_nand",
-	.map_base = S3C24X0_NAND_BASE,
-	.platform_data	= &nand_info,
-};
-
-/*
- * SMSC 91C111 network controller on the baseboard
- * connected to CS line 1 and interrupt line
- * GPIO3, data width is 32 bit
- */
-static struct device_d network_dev = {
-	.id       = -1,
-        .name     = "smc91c111",
-        .map_base = CS1_BASE + 0x300,
-        .size     = 16,
-};
-
-static int a9m2410_devices_init(void)
+static int a9m2410_mem_init(void)
 {
+	resource_size_t size = 0;
 	uint32_t reg;
 
 	/*
@@ -83,25 +53,25 @@ static int a9m2410_devices_init(void)
 
 	switch (reg &= 0x7) {
 	case 0:
-		sdram_dev.size = 32 * 1024 * 1024;
+		size = 32 * 1024 * 1024;
 		break;
 	case 1:
-		sdram_dev.size = 64 * 1024 * 1024;
+		size = 64 * 1024 * 1024;
 		break;
 	case 2:
-		sdram_dev.size = 128 * 1024 * 1024;
+		size = 128 * 1024 * 1024;
 		break;
 	case 4:
-		sdram_dev.size = 2 * 1024 * 1024;
+		size = 2 * 1024 * 1024;
 		break;
 	case 5:
-		sdram_dev.size = 4 * 1024 * 1024;
+		size = 4 * 1024 * 1024;
 		break;
 	case 6:
-		sdram_dev.size = 8 * 1024 * 1024;
+		size = 8 * 1024 * 1024;
 		break;
 	case 7:
-		sdram_dev.size = 16 * 1024 * 1024;
+		size = 16 * 1024 * 1024;
 		break;
 	}
 
@@ -130,6 +100,16 @@ static int a9m2410_devices_init(void)
 	 */
 	writel(0x40140, MISCCR);
 
+	arm_add_mem_device("ram0", CS6_BASE, size);
+
+	return 0;
+}
+mem_initcall(a9m2410_mem_init);
+
+static int a9m2410_devices_init(void)
+{
+	uint32_t reg;
+
 	/* ----------- configure the access to the outer space ---------- */
 	reg = readl(BWSCON);
 
@@ -151,9 +131,15 @@ static int a9m2410_devices_init(void)
 	writel(reg, MISCCR);
 
 	/* ----------- the devices the boot loader should work with -------- */
-	register_device(&nand_dev);
-	register_device(&sdram_dev);
-	register_device(&network_dev);
+	add_generic_device("s3c24x0_nand", -1, NULL, S3C24X0_NAND_BASE, 0,
+			   IORESOURCE_MEM, &nand_info);
+	/*
+	 * SMSC 91C111 network controller on the baseboard
+	 * connected to CS line 1 and interrupt line
+	 * GPIO3, data width is 32 bit
+	 */
+	add_generic_device("smc91c111", -1, NULL, CS1_BASE + 0x300, 16,
+			   IORESOURCE_MEM, NULL);
 
 #ifdef CONFIG_NAND
 	/* ----------- add some vital partitions -------- */
@@ -164,8 +150,7 @@ static int a9m2410_devices_init(void)
 	dev_add_bb_dev("env_raw", "env0");
 #endif
 
-	armlinux_add_dram(&sdram_dev);
-	armlinux_set_bootparams((void *)sdram_dev.map_base + 0x100);
+	armlinux_set_bootparams((void*)CS6_BASE + 0x100);
 	armlinux_set_architecture(MACH_TYPE_A9M2410);
 
 	return 0;
@@ -180,16 +165,10 @@ void __bare_init nand_boot(void)
 }
 #endif
 
-static struct device_d a9m2410_serial_device = {
-	.id       = -1,
-	.name     = "s3c24x0_serial",
-	.map_base = UART1_BASE,
-	.size     = UART1_SIZE,
-};
-
 static int a9m2410_console_init(void)
 {
-	register_device(&a9m2410_serial_device);
+	add_generic_device("s3c24x0_serial", -1, NULL, UART1_BASE, UART1_SIZE,
+			   IORESOURCE_MEM, NULL);
 	return 0;
 }
 
diff --git a/arch/arm/boards/a9m2440/a9m2440.c b/arch/arm/boards/a9m2440/a9m2440.c
index 39b52761c5..89c9cdf57e 100644
--- a/arch/arm/boards/a9m2440/a9m2440.c
+++ b/arch/arm/boards/a9m2440/a9m2440.c
@@ -38,41 +38,10 @@
 
 #include "baseboards.h"
 
-static struct memory_platform_data ram_pdata = {
-	.name		= "ram0",
-	.flags		= DEVFS_RDWR,
-};
-
-static struct device_d sdram_dev = {
-	.id		= -1,
-	.name		= "mem",
-	.map_base	= CS6_BASE,
-	.platform_data	= &ram_pdata,
-};
-
 static struct s3c24x0_nand_platform_data nand_info = {
 	.nand_timing = CALC_NFCONF_TIMING(A9M2440_TACLS, A9M2440_TWRPH0, A9M2440_TWRPH1)
 };
 
-static struct device_d nand_dev = {
-	.id	  = -1,
-	.name     = "s3c24x0_nand",
-	.map_base = S3C24X0_NAND_BASE,
-	.platform_data	= &nand_info,
-};
-
-/*
- * cs8900 network controller onboard
- * Connected to CS line 5 + A24 and interrupt line EINT9,
- * data width is 16 bit
- */
-static struct device_d network_dev = {
-	.id	  = -1,
-	.name     = "cs8900",
-	.map_base = CS5_BASE + (1 << 24) + 0x300,
-	.size     = 16,
-};
-
 static int a9m2440_check_for_ram(uint32_t addr)
 {
 	uint32_t tmp1, tmp2;
@@ -103,10 +72,8 @@ static void a9m2440_disable_second_sdram_bank(void)
 	writel(readl(MISCCR) | (1 << 18), MISCCR); /* disable clock */
 }
 
-static int a9m2440_devices_init(void)
+static int a9m2440_mem_init(void)
 {
-	uint32_t reg;
-
 	/*
 	 * The special SDRAM setup code for this machine will always enable
 	 * both SDRAM banks. But the second SDRAM device may not exists!
@@ -136,7 +103,15 @@ static int a9m2440_devices_init(void)
 		break;
 	}
 
-	sdram_dev.size = s3c24x0_get_memory_size();
+	arm_add_mem_device("ram0", CS6_BASE, s3c24x0_get_memory_size());
+
+	return 0;
+}
+mem_initcall(a9m2440_mem_init);
+
+static int a9m2440_devices_init(void)
+{
+	uint32_t reg;
 
 	/* ----------- configure the access to the outer space ---------- */
 	reg = readl(BWSCON);
@@ -158,9 +133,15 @@ static int a9m2440_devices_init(void)
 	writel(reg, MISCCR);
 
 	/* ----------- the devices the boot loader should work with -------- */
-	register_device(&nand_dev);
-	register_device(&sdram_dev);
-	register_device(&network_dev);
+	add_generic_device("s3c24x0_nand", -1, NULL, S3C24X0_NAND_BASE, 0,
+			   IORESOURCE_MEM, &nand_info);
+	/*
+	 * cs8900 network controller onboard
+	 * Connected to CS line 5 + A24 and interrupt line EINT9,
+	 * data width is 16 bit
+	 */
+	add_generic_device("cs8900", -1, NULL, CS5_BASE + (1 << 24) + 0x300, 16,
+			   IORESOURCE_MEM, NULL);
 
 #ifdef CONFIG_NAND
 	/* ----------- add some vital partitions -------- */
@@ -170,8 +151,7 @@ static int a9m2440_devices_init(void)
 	devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
 	dev_add_bb_dev("env_raw", "env0");
 #endif
-	armlinux_add_dram(&sdram_dev);
-	armlinux_set_bootparams((void *)sdram_dev.map_base + 0x100);
+	armlinux_set_bootparams((void*)CS6_BASE + 0x100);
 	armlinux_set_architecture(MACH_TYPE_A9M2440);
 
 	return 0;
@@ -186,16 +166,10 @@ void __bare_init nand_boot(void)
 }
 #endif
 
-static struct device_d a9m2440_serial_device = {
-	.id	  = -1,
-	.name     = "s3c24x0_serial",
-	.map_base = UART1_BASE,
-	.size     = UART1_SIZE,
-};
-
 static int a9m2440_console_init(void)
 {
-	register_device(&a9m2440_serial_device);
+	add_generic_device("s3c24x0_serial", -1, NULL, UART1_BASE, UART1_SIZE,
+			   IORESOURCE_MEM, NULL);
 	return 0;
 }
 
diff --git a/arch/arm/boards/at91rm9200ek/init.c b/arch/arm/boards/at91rm9200ek/init.c
index a449326d5c..cff7ede4d3 100644
--- a/arch/arm/boards/at91rm9200ek/init.c
+++ b/arch/arm/boards/at91rm9200ek/init.c
@@ -34,17 +34,19 @@
 #include <mach/gpio.h>
 #include <mach/io.h>
 
-static struct device_d cfi_dev = {
-	.id		= 0,
-	.name		= "cfi_flash",
-	.map_base	= AT91_CHIPSELECT_0,
-};
-
 static struct at91_ether_platform_data ether_pdata = {
 	.flags = AT91SAM_ETHER_RMII,
 	.phy_addr = 0,
 };
 
+static int at91rm9200ek_mem_init(void)
+{
+	at91_add_device_sdram(64 * 1024 * 1024);
+
+	return 0;
+}
+mem_initcall(at91rm9200ek_mem_init);
+
 static int at91rm9200ek_devices_init(void)
 {
 	/*
@@ -53,9 +55,9 @@ static int at91rm9200ek_devices_init(void)
 	 */
 	at91_set_gpio_output(AT91_PIN_PA23, 1);
 
-	at91_add_device_sdram(64 * 1024 * 1024);
 	at91_add_device_eth(&ether_pdata);
-	register_device(&cfi_dev);
+
+	add_cfi_flash_device(0, AT91_CHIPSELECT_0, 0, 0);
 
 #if defined(CONFIG_DRIVER_CFI) || defined(CONFIG_DRIVER_CFI_OLD)
 	devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self");
diff --git a/arch/arm/boards/at91sam9260ek/init.c b/arch/arm/boards/at91sam9260ek/init.c
index 966dd2fd30..861e8980a5 100644
--- a/arch/arm/boards/at91sam9260ek/init.c
+++ b/arch/arm/boards/at91sam9260ek/init.c
@@ -141,13 +141,20 @@ static void at91sam9260ek_phy_reset(void)
 				     AT91_RSTC_URSTEN);
 }
 
+static int at91sam9260ek_mem_init(void)
+{
+	at91_add_device_sdram(64 * 1024 * 1024);
+
+	return 0;
+}
+mem_initcall(at91sam9260ek_mem_init);
+
 static int at91sam9260ek_devices_init(void)
 {
 	ek_add_device_nand();
 	at91sam9260ek_phy_reset();
 	at91_add_device_eth(&macb_pdata);
 
-	at91_add_device_sdram(64 * 1024 * 1024);
 	armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100));
 	ek_set_board_type();
 
diff --git a/arch/arm/boards/at91sam9261ek/init.c b/arch/arm/boards/at91sam9261ek/init.c
index b1388e183a..69111a0099 100644
--- a/arch/arm/boards/at91sam9261ek/init.c
+++ b/arch/arm/boards/at91sam9261ek/init.c
@@ -89,20 +89,9 @@ static void ek_add_device_nand(void)
  */
 #if defined(CONFIG_DRIVER_NET_DM9000)
 static struct dm9000_platform_data dm9000_data = {
-	.iobase		= AT91_CHIPSELECT_2,
-	.iodata		= AT91_CHIPSELECT_2 + 4,
-	.buswidth	= DM9000_WIDTH_16,
 	.srom		= 0,
 };
 
-static struct device_d dm9000_dev = {
-	.id		= 0,
-	.name		= "dm9000",
-	.map_base	= AT91_CHIPSELECT_2,
-	.size		= 8,
-	.platform_data	= &dm9000_data,
-};
-
 /*
  * SMC timings for the DM9000.
  * Note: These timings were calculated for MASTER_CLOCK = 100000000 according to the DM9000 timings.
@@ -136,16 +125,24 @@ static void __init ek_add_device_dm9000(void)
 	/* Configure Interrupt pin as input, no pull-up */
 	at91_set_gpio_input(AT91_PIN_PC11, 0);
 
-	register_device(&dm9000_dev);
+	add_dm9000_device(0, AT91_CHIPSELECT_2, AT91_CHIPSELECT_2 + 4,
+			  IORESOURCE_MEM_16BIT, &dm9000_data);
 }
 #else
 static void __init ek_add_device_dm9000(void) {}
 #endif /* CONFIG_DRIVER_NET_DM9000 */
 
+static int at91sam9261ek_mem_init(void)
+{
+	at91_add_device_sdram(64 * 1024 * 1024);
+
+	return 0;
+}
+mem_initcall(at91sam9261ek_mem_init);
+
 static int at91sam9261ek_devices_init(void)
 {
 
-	at91_add_device_sdram(64 * 1024 * 1024);
 	ek_add_device_nand();
 	ek_add_device_dm9000();
 
diff --git a/arch/arm/boards/at91sam9263ek/init.c b/arch/arm/boards/at91sam9263ek/init.c
index 9a763b3cad..46f3a7ede2 100644
--- a/arch/arm/boards/at91sam9263ek/init.c
+++ b/arch/arm/boards/at91sam9263ek/init.c
@@ -87,13 +87,6 @@ static void ek_add_device_nand(void)
 	at91_add_device_nand(&nand_pdata);
 }
 
-static struct device_d cfi_dev = {
-	.id		= -1,
-	.name		= "cfi_flash",
-	.map_base	= AT91_CHIPSELECT_0,
-	.size		= 8 * 1024 * 1024,
-};
-
 static struct at91_ether_platform_data macb_pdata = {
 	.flags = AT91SAM_ETHER_RMII,
 	.phy_addr = 0,
@@ -114,6 +107,14 @@ static void ek_add_device_mci(void)
 static void ek_add_device_mci(void) {}
 #endif
 
+static int at91sam9263ek_mem_init(void)
+{
+	at91_add_device_sdram(64 * 1024 * 1024);
+
+	return 0;
+}
+mem_initcall(at91sam9263ek_mem_init);
+
 static int at91sam9263ek_devices_init(void)
 {
 	/*
@@ -124,10 +125,9 @@ static int at91sam9263ek_devices_init(void)
 	at91_set_gpio_output(AT91_PIN_PB27, 1);
 	at91_set_gpio_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */
 
-	at91_add_device_sdram(64 * 1024 * 1024);
 	ek_add_device_nand();
 	at91_add_device_eth(&macb_pdata);
-	register_device(&cfi_dev);
+	add_cfi_flash_device(0, AT91_CHIPSELECT_0, 8 * 1024 * 1024, 0);
 	ek_add_device_mci();
 
 #if defined(CONFIG_DRIVER_CFI) || defined(CONFIG_DRIVER_CFI_OLD)
diff --git a/arch/arm/boards/at91sam9m10g45ek/init.c b/arch/arm/boards/at91sam9m10g45ek/init.c
index 8cdcb8d626..ba7c2fff48 100644
--- a/arch/arm/boards/at91sam9m10g45ek/init.c
+++ b/arch/arm/boards/at91sam9m10g45ek/init.c
@@ -126,10 +126,16 @@ static void ek_add_device_mci(void)
 static void ek_add_device_mci(void) {}
 #endif
 
+static int at91sam9m10g45ek_mem_init(void)
+{
+	at91_add_device_sdram(128 * 1024 * 1024);
+
+	return 0;
+}
+mem_initcall(at91sam9m10g45ek_mem_init);
 
 static int at91sam9m10g45ek_devices_init(void)
 {
-	at91_add_device_sdram(128 * 1024 * 1024);
 	ek_add_device_nand();
 	at91_add_device_eth(&macb_pdata);
 	ek_add_device_mci();
diff --git a/arch/arm/boards/chumby_falconwing/falconwing.c b/arch/arm/boards/chumby_falconwing/falconwing.c
index 15ca11b7a4..1c66eb231a 100644
--- a/arch/arm/boards/chumby_falconwing/falconwing.c
+++ b/arch/arm/boards/chumby_falconwing/falconwing.c
@@ -34,30 +34,11 @@
 #include <mach/fb.h>
 #include <mach/usb.h>
 
-static struct memory_platform_data ram_pdata = {
-	.name = "ram0",
-	.flags = DEVFS_RDWR,
-};
-
-static struct device_d sdram_dev = {
-	.id       = -1,
-	.name     = "mem",
-	.map_base = IMX_MEMORY_BASE,
-	.size     = 64 * 1024 * 1024,
-	.platform_data = &ram_pdata,
-};
-
 static struct mxs_mci_platform_data mci_pdata = {
 	.caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz,
 	.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,	/* fixed to 3.3 V */
 };
 
-static struct device_d mci_dev = {
-	.name     = "mxs_mci",
-	.map_base = IMX_SSP1_BASE,
-	.platform_data = &mci_pdata,
-};
-
 #define GPIO_LCD_RESET		50
 #define GPIO_LCD_BACKLIGHT	60
 
@@ -111,13 +92,6 @@ static struct imx_fb_platformdata fb_mode = {
 	.fixed_screen_size = MAX_FB_SIZE,
 };
 
-static struct device_d ldcif_dev = {
-	.name = "stmfb",
-	.map_base = IMX_FB_BASE,
-	.size = 4096,
-	.platform_data = &fb_mode,
-};
-
 static const uint32_t pad_setup[] = {
 	/* may be not required as already done by the bootlet code */
 #if 0
@@ -287,22 +261,13 @@ static const uint32_t pad_setup[] = {
 	GPMI_RDY3_GPIO | GPIO_IN | PULLUP(1),
 };
 
-#ifdef CONFIG_MMU
-static int falconwing_mmu_init(void)
+static int falconwing_mem_init(void)
 {
-	mmu_init();
-
-	arm_create_section(0x40000000, 0x40000000, 64, PMD_SECT_DEF_CACHED);
-	arm_create_section(0x50000000, 0x40000000, 64, PMD_SECT_DEF_UNCACHED);
-
-	setup_dma_coherent(0x10000000);
-
-	mmu_enable();
+	arm_add_mem_device("ram0", IMX_MEMORY_BASE, 64 * 1024 * 1024);
 
 	return 0;
 }
-postcore_initcall(falconwing_mmu_init);
-#endif
+mem_initcall(falconwing_mem_init);
 
 /**
  * Try to register an environment storage on the attached MCI card
@@ -340,20 +305,6 @@ static int register_persistant_environment(void)
 	return devfs_add_partition("disk0.1", 0, cdev->size, DEVFS_PARTITION_FIXED, "env0");
 }
 
-static struct ehci_platform_data chumby_usb_pdata = {
-	.flags = EHCI_HAS_TT,
-	.hccr_offset = 0x100,
-	.hcor_offset = 0x140,
-};
-
-static struct device_d usb_dev = {
-	.name		= "ehci",
-	.id		= -1,
-	.map_base	= IMX_USB_BASE,
-	.size		= 0x200,
-	.platform_data	= &chumby_usb_pdata,
-};
-
 #define GPIO_USB_HUB_RESET	29
 #define GPIO_USB_HUB_POWER	26
 
@@ -366,7 +317,8 @@ static void falconwing_init_usb(void)
 	gpio_direction_output(GPIO_USB_HUB_RESET, 1);
 
 	imx_usb_phy_enable();
-	register_device(&usb_dev);
+
+	add_generic_usb_ehci_device(-1, IMX_USB_BASE, NULL);
 }
 
 static int falconwing_devices_init(void)
@@ -377,17 +329,17 @@ static int falconwing_devices_init(void)
 	for (i = 0; i < ARRAY_SIZE(pad_setup); i++)
 		imx_gpio_mode(pad_setup[i]);
 
-	register_device(&sdram_dev);
 	imx_set_ioclk(480000000); /* enable IOCLK to run at the PLL frequency */
 	/* run the SSP unit clock at 100,000 kHz */
 	imx_set_sspclk(0, 100000000, 1);
-	register_device(&mci_dev);
-	register_device(&ldcif_dev);
+	add_generic_device("mxs_mci", 0, NULL, IMX_SSP1_BASE, 0,
+			   IORESOURCE_MEM, &mci_pdata);
+	add_generic_device("stmfb", 0, NULL, IMX_FB_BASE, 4096,
+			   IORESOURCE_MEM, &fb_mode);
 
 	falconwing_init_usb();
 
-	armlinux_add_dram(&sdram_dev);
-	armlinux_set_bootparams((void*)(sdram_dev.map_base + 0x100));
+	armlinux_set_bootparams((void *)IMX_MEMORY_BASE + 0x100);
 	armlinux_set_architecture(MACH_TYPE_CHUMBY);
 
 	rc = register_persistant_environment();
@@ -399,15 +351,12 @@ static int falconwing_devices_init(void)
 
 device_initcall(falconwing_devices_init);
 
-static struct device_d falconwing_serial_device = {
-	.name     = "stm_serial",
-	.map_base = IMX_DBGUART_BASE,
-	.size     = 8192,
-};
-
 static int falconwing_console_init(void)
 {
-	return register_device(&falconwing_serial_device);
+	add_generic_device("stm_serial", 0, NULL, IMX_DBGUART_BASE, 8192,
+			   IORESOURCE_MEM, NULL);
+
+	return 0;
 }
 
 console_initcall(falconwing_console_init);
diff --git a/arch/arm/boards/edb93xx/edb93xx.c b/arch/arm/boards/edb93xx/edb93xx.c
index 0f127b5c5e..3e4e0b04a0 100644
--- a/arch/arm/boards/edb93xx/edb93xx.c
+++ b/arch/arm/boards/edb93xx/edb93xx.c
@@ -34,83 +34,30 @@
 
 #define DEVCFG_U1EN (1 << 18)
 
-/*
- * Up to 32MiB NOR type flash, connected to
- * CS line 6, data width is 16 bit
- */
-static struct device_d cfi_dev = {
-	.id	  = -1,
-	.name     = "cfi_flash",
-	.map_base = 0x60000000,
-	.size     = EDB93XX_CFI_FLASH_SIZE,
-};
-
-static struct memory_platform_data ram_dev_pdata0 = {
-	.name = "ram0",
-	.flags = DEVFS_RDWR,
-};
-
-static struct device_d sdram0_dev = {
-	.id	  = -1,
-	.name     = "mem",
-	.map_base = CONFIG_EP93XX_SDRAM_BANK0_BASE,
-	.size     = CONFIG_EP93XX_SDRAM_BANK0_SIZE,
-	.platform_data = &ram_dev_pdata0,
-};
-
+static int ep93xx_mem_init(void)
+{
+	arm_add_mem_device("ram0", CONFIG_EP93XX_SDRAM_BANK0_BASE,
+				   CONFIG_EP93XX_SDRAM_BANK0_SIZE);
 #if (CONFIG_EP93XX_SDRAM_NUM_BANKS >= 2)
-static struct memory_platform_data ram_dev_pdata1 = {
-	.name = "ram1",
-	.flags = DEVFS_RDWR,
-};
-
-static struct device_d sdram1_dev = {
-	.id	  = -1,
-	.name     = "mem",
-	.map_base = CONFIG_EP93XX_SDRAM_BANK1_BASE,
-	.size     = CONFIG_EP93XX_SDRAM_BANK1_SIZE,
-	.platform_data = &ram_dev_pdata1,
-};
+	arm_add_mem_device("ram1", CONFIG_EP93XX_SDRAM_BANK1_BASE,
+				   CONFIG_EP93XX_SDRAM_BANK1_SIZE);
 #endif
-
 #if (CONFIG_EP93XX_SDRAM_NUM_BANKS >= 3)
-static struct memory_platform_data ram_dev_pdata2 = {
-	.name = "ram2",
-	.flags = DEVFS_RDWR,
-};
-
-static struct device_d sdram2_dev = {
-	.id	  = -1,
-	.name     = "mem",
-	.map_base = CONFIG_EP93XX_SDRAM_BANK2_BASE,
-	.size     = CONFIG_EP93XX_SDRAM_BANK2_SIZE,
-	.platform_data = &ram_dev_pdata2,
-};
+	arm_add_mem_device("ram2", CONFIG_EP93XX_SDRAM_BANK2_BASE,
+				   CONFIG_EP93XX_SDRAM_BANK2_SIZE);
 #endif
-
 #if (CONFIG_EP93XX_SDRAM_NUM_BANKS == 4)
-static struct memory_platform_data ram_dev_pdata3 = {
-	.name = "ram3",
-	.flags = DEVFS_RDWR,
-};
-
-static struct device_d sdram3_dev = {
-	.id	  = -1,
-	.name     = "mem",
-	.map_base = CONFIG_EP93XX_SDRAM_BANK3_BASE,
-	.size     = CONFIG_EP93XX_SDRAM_BANK3_SIZE,
-	.platform_data = &ram_dev_pdata3,
-};
+	arm_add_mem_device("ram3", CONFIG_EP93XX_SDRAM_BANK3_BASE,
+				   CONFIG_EP93XX_SDRAM_BANK2_SIZE);
 #endif
 
-static struct device_d eth_dev = {
-	.id	  = -1,
-	.name     = "ep93xx_eth",
-};
+	return 0;
+}
+mem_initcall(ep93xx_mem_init);
 
 static int ep93xx_devices_init(void)
 {
-	register_device(&cfi_dev);
+	add_cfi_flash_device(-1, 0x60000000, EDB93XX_CFI_FLASH_SIZE, 0);
 
 	/*
 	 * Create partitions that should be
@@ -121,29 +68,11 @@ static int ep93xx_devices_init(void)
 
 	protect_file("/dev/env0", 1);
 
-	register_device(&sdram0_dev);
-#if (CONFIG_EP93XX_SDRAM_NUM_BANKS >= 2)
-	register_device(&sdram1_dev);
-#endif
-#if (CONFIG_EP93XX_SDRAM_NUM_BANKS >= 3)
-	register_device(&sdram2_dev);
-#endif
-#if (CONFIG_EP93XX_SDRAM_NUM_BANKS == 4)
-	register_device(&sdram3_dev);
-#endif
-
-	armlinux_add_dram(&sdram0_dev);
-#if (CONFIG_EP93XX_SDRAM_NUM_BANKS >= 2)
-	armlinux_add_dram(&sdram1_dev);
-#endif
-#if (CONFIG_EP93XX_SDRAM_NUM_BANKS >= 3)
-	armlinux_add_dram(&sdram2_dev);
-#endif
-#if (CONFIG_EP93XX_SDRAM_NUM_BANKS == 4)
-	armlinux_add_dram(&sdram3_dev);
-#endif
-
-	register_device(&eth_dev);
+	/*
+	 * Up to 32MiB NOR type flash, connected to
+	 * CS line 6, data width is 16 bit
+	 */
+	add_generic_device("ep93xx_eth", -1, NULL, 0, 0, IORESOURCE_MEM, NULL);
 
 	armlinux_set_bootparams((void *)CONFIG_EP93XX_SDRAM_BANK0_BASE + 0x100);
 
@@ -154,13 +83,6 @@ static int ep93xx_devices_init(void)
 
 device_initcall(ep93xx_devices_init);
 
-static struct device_d edb93xx_serial_device = {
-	.id	  = -1,
-	.name     = "pl010_serial",
-	.map_base = UART1_BASE,
-	.size     = 4096,
-};
-
 static int edb93xx_console_init(void)
 {
 	struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
@@ -179,7 +101,8 @@ static int edb93xx_console_init(void)
 	writel(0xAA, &syscon->sysswlock);
 	writel(value, &syscon->devicecfg);
 
-	register_device(&edb93xx_serial_device);
+	add_generic_device("pl010_serial", -1, NULL, UART1_BASE, 4096,
+			   IORESOURCE_MEM, NULL);
 
 	return 0;
 }
diff --git a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
index f2b2523a4b..1c54202dfa 100644
--- a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
+++ b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
@@ -37,6 +37,7 @@
 #include <generated/mach-types.h>
 #include <mach/imx-nand.h>
 #include <mach/imxfb.h>
+#include <mach/iim.h>
 #include <fec.h>
 #include <nand.h>
 #include <mach/imx-flash-header.h>
@@ -90,19 +91,6 @@ static struct fec_platform_data fec_info = {
 	.phy_addr	= 1,
 };
 
-static struct memory_platform_data sdram_pdata = {
-	.name	= "ram0",
-	.flags	= DEVFS_RDWR,
-};
-
-static struct device_d sdram0_dev = {
-	.id	  = -1,
-	.name     = "mem",
-	.map_base = IMX_SDRAM_CS0,
-	.size     = 64 * 1024 * 1024,
-	.platform_data = &sdram_pdata,
-};
-
 struct imx_nand_platform_data nand_info = {
 	.width	= 1,
 	.hw_ecc	= 1,
@@ -161,12 +149,6 @@ static void imx25_usb_init(void)
 	writel(tmp | 0x3, IMX_OTG_BASE + 0x5a8);
 }
 
-static struct device_d usbh2_dev = {
-	.id	  = -1,
-	.name     = "ehci",
-	.map_base = IMX_OTG_BASE + 0x400,
-	.size     = 0x200,
-};
 #endif
 
 static struct fsl_usb2_platform_data usb_pdata = {
@@ -174,30 +156,13 @@ static struct fsl_usb2_platform_data usb_pdata = {
 	.phy_mode	= FSL_USB2_PHY_UTMI,
 };
 
-static struct device_d usbotg_dev = {
-	.name     = "fsl-udc",
-	.map_base = IMX_OTG_BASE,
-	.size     = 0x200,
-	.platform_data = &usb_pdata,
-};
-
-#ifdef CONFIG_MMU
-static void eukrea_cpuimx25_mmu_init(void)
+static int eukrea_cpuimx25_mem_init(void)
 {
-	mmu_init();
-
-	arm_create_section(0x80000000, 0x80000000, 128, PMD_SECT_DEF_CACHED);
-	arm_create_section(0x90000000, 0x80000000, 128, PMD_SECT_DEF_UNCACHED);
+	arm_add_mem_device("ram0", IMX_SDRAM_CS0, 64 * 1024 * 1024);
 
-	setup_dma_coherent(0x10000000);
-
-	mmu_enable();
-}
-#else
-static void eukrea_cpuimx25_mmu_init(void)
-{
+	return 0;
 }
-#endif
+mem_initcall(eukrea_cpuimx25_mem_init);
 
 static struct pad_desc eukrea_cpuimx25_pads[] = {
 	MX25_PAD_FEC_MDC__FEC_MDC,
@@ -255,13 +220,12 @@ static struct pad_desc eukrea_cpuimx25_pads[] = {
 
 static int eukrea_cpuimx25_devices_init(void)
 {
-	eukrea_cpuimx25_mmu_init();
-
 	mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx25_pads,
 		ARRAY_SIZE(eukrea_cpuimx25_pads));
 
 	led_gpio_register(&led0);
 
+	imx25_iim_register_fec_ethaddr();
 	imx25_add_fec(&fec_info);
 
 	nand_info.width = 1;
@@ -275,8 +239,6 @@ static int eukrea_cpuimx25_devices_init(void)
 		PARTITION_FIXED, "env_raw");
 	dev_add_bb_dev("env_raw", "env0");
 
-	register_device(&sdram0_dev);
-
 	/* enable LCD */
 	gpio_direction_output(26, 1);
 	gpio_set_value(26, 1);
@@ -291,11 +253,11 @@ static int eukrea_cpuimx25_devices_init(void)
 
 #ifdef CONFIG_USB
 	imx25_usb_init();
-	register_device(&usbh2_dev);
+	add_generic_usb_ehci_device(-1, IMX_OTG_BASE + 0x400, NULL);
 #endif
-	register_device(&usbotg_dev);
+	add_generic_device("fsl-udc", -1, NULL, IMX_OTG_BASE, 0x200,
+			   IORESOURCE_MEM, &usb_pdata);
 
-	armlinux_add_dram(&sdram0_dev);
 	armlinux_set_bootparams((void *)0x80000100);
 	armlinux_set_architecture(MACH_TYPE_EUKREA_CPUIMX25);
 
diff --git a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
index a7e99513df..a5aadac0d9 100644
--- a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
+++ b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
@@ -48,40 +48,12 @@
 #include <mach/iomux-mx27.h>
 #include <mach/devices-imx27.h>
 
-static struct device_d cfi_dev = {
-	.id	  = -1,
-	.name     = "cfi_flash",
-	.map_base = 0xC0000000,
-	.size     = 32 * 1024 * 1024,
-};
-#ifdef CONFIG_EUKREA_CPUIMX27_NOR_64MB
-static struct device_d cfi_dev1 = {
-	.id	  = -1,
-	.name     = "cfi_flash",
-	.map_base = 0xC2000000,
-	.size     = 32 * 1024 * 1024,
-};
-#endif
-
-static struct memory_platform_data ram_pdata = {
-	.name = "ram0",
-	.flags = DEVFS_RDWR,
-};
-
 #if defined CONFIG_EUKREA_CPUIMX27_SDRAM_256MB
 #define SDRAM0	256
 #elif defined CONFIG_EUKREA_CPUIMX27_SDRAM_128MB
 #define SDRAM0	128
 #endif
 
-static struct device_d sdram_dev = {
-	.id	  = -1,
-	.name     = "mem",
-	.map_base = 0xa0000000,
-	.size     = SDRAM0 * 1024 * 1024,
-	.platform_data = &ram_pdata,
-};
-
 static struct fec_platform_data fec_info = {
 	.xcv_type = MII100,
 	.phy_addr = 1,
@@ -94,28 +66,9 @@ struct imx_nand_platform_data nand_info = {
 };
 
 #ifdef CONFIG_DRIVER_SERIAL_NS16550
-unsigned int quad_uart_read(unsigned long base, unsigned char reg_idx)
-{
-	unsigned int reg_addr = (unsigned int)base;
-	reg_addr += reg_idx << 1;
-	return 0xff & readw(reg_addr);
-}
-EXPORT_SYMBOL(quad_uart_read);
-
-void quad_uart_write(unsigned int val, unsigned long base,
-		     unsigned char reg_idx)
-{
-	unsigned int reg_addr = (unsigned int)base;
-	reg_addr += reg_idx << 1;
-	writew(0xff & val, reg_addr);
-}
-EXPORT_SYMBOL(quad_uart_write);
-
 static struct NS16550_plat quad_uart_serial_plat = {
 	.clock = 14745600,
-	.f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR,
-	.reg_read = quad_uart_read,
-	.reg_write = quad_uart_write,
+	.shift = 1,
 };
 
 #ifdef CONFIG_EUKREA_CPUIMX27_QUART1
@@ -127,14 +80,6 @@ static struct NS16550_plat quad_uart_serial_plat = {
 #elif defined CONFIG_EUKREA_CPUIMX27_QUART4
 #define QUART_OFFSET 0x1000000
 #endif
-
-static struct device_d quad_uart_serial_device = {
-	.id = -1,
-	.name = "serial_ns16550",
-	.map_base = IMX_CS3_BASE + QUART_OFFSET,
-	.size = 0xF,
-	.platform_data = (void *)&quad_uart_serial_plat,
-};
 #endif
 
 static struct i2c_board_info i2c_devices[] = {
@@ -143,23 +88,13 @@ static struct i2c_board_info i2c_devices[] = {
 	},
 };
 
-#ifdef CONFIG_MMU
-static void eukrea_cpuimx27_mmu_init(void)
+static int eukrea_cpuimx27_mem_init(void)
 {
-	mmu_init();
-
-	arm_create_section(0xa0000000, 0xa0000000, 128, PMD_SECT_DEF_CACHED);
-	arm_create_section(0xb0000000, 0xa0000000, 128, PMD_SECT_DEF_UNCACHED);
-
-	setup_dma_coherent(0x10000000);
+	arm_add_mem_device("ram0", 0xa0000000, SDRAM0 * 1024 * 1024);
 
-	mmu_enable();
-}
-#else
-static void eukrea_cpuimx27_mmu_init(void)
-{
+	return 0;
 }
-#endif
+mem_initcall(eukrea_cpuimx27_mem_init);
 
 #ifdef CONFIG_DRIVER_VIDEO_IMX
 static struct imx_fb_videomode imxfb_mode = {
@@ -185,14 +120,6 @@ static struct imx_fb_platform_data eukrea_cpuimx27_fb_data = {
 	.lscr1	= 0x00120300,
 	.dmacr	= 0x00020010,
 };
-
-static struct device_d imxfb_dev = {
-	.id		= -1,
-	.name		= "imxfb",
-	.map_base	= 0x10021000,
-	.size		= 0x1000,
-	.platform_data	= &eukrea_cpuimx27_fb_data,
-};
 #endif
 
 static int eukrea_cpuimx27_devices_init(void)
@@ -255,8 +182,6 @@ static int eukrea_cpuimx27_devices_init(void)
 #endif
 	};
 
-	eukrea_cpuimx27_mmu_init();
-
 	/* configure 16 bit nor flash on cs0 */
 	CS0U = 0x00008F03;
 	CS0L = 0xA0330D01;
@@ -266,12 +191,11 @@ static int eukrea_cpuimx27_devices_init(void)
 	for (i = 0; i < ARRAY_SIZE(mode); i++)
 		imx_gpio_mode(mode[i]);
 
-	register_device(&cfi_dev);
+	add_cfi_flash_device(-1, 0xC0000000, 32 * 1024 * 1024, 0);
 #ifdef CONFIG_EUKREA_CPUIMX27_NOR_64MB
-	register_device(&cfi_dev1);
+	add_cfi_flash_device(-1, 0xC2000000, 32 * 1024 * 1024, 0);
 #endif
 	imx27_add_nand(&nand_info);
-	register_device(&sdram_dev);
 
 	PCCR0 |= PCCR0_I2C1_EN;
 	i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
@@ -285,14 +209,13 @@ static int eukrea_cpuimx27_devices_init(void)
 	printf("Using environment in %s Flash\n", envdev);
 
 #ifdef CONFIG_DRIVER_VIDEO_IMX
-	register_device(&imxfb_dev);
+	imx_add_fb((void *)0x10021000, &eukrea_cpuimx27_fb_data);
 	gpio_direction_output(GPIO_PORTE | 5, 0);
 	gpio_set_value(GPIO_PORTE | 5, 1);
 	gpio_direction_output(GPIO_PORTA | 25, 0);
 	gpio_set_value(GPIO_PORTA | 25, 1);
 #endif
 
-	armlinux_add_dram(&sdram_dev);
 	armlinux_set_bootparams((void *)0xa0000100);
 	armlinux_set_architecture(MACH_TYPE_CPUIMX27);
 
@@ -301,19 +224,10 @@ static int eukrea_cpuimx27_devices_init(void)
 
 device_initcall(eukrea_cpuimx27_devices_init);
 
-#ifdef CONFIG_DRIVER_SERIAL_IMX
-static struct device_d eukrea_cpuimx27_serial_device = {
-	.id	  = -1,
-	.name     = "imx_serial",
-	.map_base = IMX_UART1_BASE,
-	.size     = 4096,
-};
-#endif
-
 static int eukrea_cpuimx27_console_init(void)
 {
 #ifdef CONFIG_DRIVER_SERIAL_IMX
-	register_device(&eukrea_cpuimx27_serial_device);
+	imx_add_uart((void *)IMX_UART1_BASE, -1);
 #endif
 	/* configure 8 bit UART on cs3 */
 	FMCR &= ~0x2;
@@ -321,7 +235,8 @@ static int eukrea_cpuimx27_console_init(void)
 	CS3L = 0x0D1D0D01;
 	CS3A = 0x00D20000;
 #ifdef CONFIG_DRIVER_SERIAL_NS16550
-	register_device(&quad_uart_serial_device);
+	add_ns16550_device(-1, IMX_CS3_BASE + QUART_OFFSET, 0xf,
+			 IORESOURCE_MEM_16BIT, &quad_uart_serial_plat);
 #endif
 	return 0;
 }
diff --git a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
index f0eb088617..426445f59d 100644
--- a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
+++ b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
@@ -61,19 +61,6 @@ static struct fec_platform_data fec_info = {
 	.phy_addr	= 0x1F,
 };
 
-static struct memory_platform_data sdram_pdata = {
-	.name	= "ram0",
-	.flags	= DEVFS_RDWR,
-};
-
-static struct device_d sdram_dev = {
-	.id		= -1,
-	.name		= "mem",
-	.map_base	= IMX_SDRAM_CS0,
-	.size		= 128 * 1024 * 1024,
-	.platform_data	= &sdram_pdata,
-};
-
 struct imx_nand_platform_data nand_info = {
 	.width		= 1,
 	.hw_ecc		= 1,
@@ -130,46 +117,30 @@ static void imx35_usb_init(void)
 	tmp = readl(IMX_OTG_BASE + 0x5a8);
 	writel(tmp | 0x3, IMX_OTG_BASE + 0x5a8);
 }
-
-static struct device_d usbh2_dev = {
-	.id	  = -1,
-	.name     = "ehci",
-	.map_base = IMX_OTG_BASE + 0x400,
-	.size     = 0x200,
-};
 #endif
 
+#ifdef CONFIG_USB_GADGET
 static struct fsl_usb2_platform_data usb_pdata = {
 	.operating_mode	= FSL_USB2_DR_DEVICE,
 	.phy_mode	= FSL_USB2_PHY_UTMI,
 };
+#endif
 
-static struct device_d usbotg_dev = {
-	.name     = "fsl-udc",
-	.map_base = IMX_OTG_BASE,
-	.size     = 0x200,
-	.platform_data = &usb_pdata,
-};
-
-#ifdef CONFIG_MMU
-static int eukrea_cpuimx35_mmu_init(void)
+static int eukrea_cpuimx35_mem_init(void)
 {
-	mmu_init();
+	arm_add_mem_device("ram0", IMX_SDRAM_CS0, 128 * 1024 * 1024);
 
-	arm_create_section(0x80000000, 0x80000000, 128, PMD_SECT_DEF_CACHED);
-	arm_create_section(0x90000000, 0x80000000, 128, PMD_SECT_DEF_UNCACHED);
-
-	setup_dma_coherent(0x10000000);
-
-	mmu_enable();
+	return 0;
+}
+mem_initcall(eukrea_cpuimx35_mem_init);
 
-#ifdef CONFIG_CACHE_L2X0
+static int eukrea_cpuimx35_mmu_init(void)
+{
 	l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000);
-#endif
+
 	return 0;
 }
-postcore_initcall(eukrea_cpuimx35_mmu_init);
-#endif
+postmmu_initcall(eukrea_cpuimx35_mmu_init);
 
 static int eukrea_cpuimx35_devices_init(void)
 {
@@ -181,8 +152,6 @@ static int eukrea_cpuimx35_devices_init(void)
 	dev_add_bb_dev("env_raw", "env0");
 
 	imx35_add_fec(&fec_info);
-
-	register_device(&sdram_dev);
 	imx35_add_fb(&ipu_fb_data);
 
 	imx35_add_i2c0(NULL);
@@ -190,15 +159,15 @@ static int eukrea_cpuimx35_devices_init(void)
 
 #ifdef CONFIG_USB
 	imx35_usb_init();
-	register_device(&usbh2_dev);
+	add_generic_usb_ehci_device(-1, IMX_OTG_BASE + 0x400, NULL);
 #endif
 #ifdef CONFIG_USB_GADGET
 	/* Workaround ENGcm09152 */
 	tmp = readl(IMX_OTG_BASE + 0x608);
 	writel(tmp | (1 << 23), IMX_OTG_BASE + 0x608);
-	register_device(&usbotg_dev);
+	add_generic_device("fsl-udc", -1, NULL, IMX_OTG_BASE, 0x200,
+			   IORESOURCE_MEM, &usb_pdata);
 #endif
-	armlinux_add_dram(&sdram_dev);
 	armlinux_set_bootparams((void *)0x80000100);
 	armlinux_set_architecture(MACH_TYPE_EUKREA_CPUIMX35);
 
diff --git a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c
index 0847bb1da1..727db29241 100644
--- a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c
+++ b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c
@@ -42,19 +42,6 @@
 #include <mach/iomux-mx51.h>
 #include <mach/devices-imx51.h>
 
-static struct memory_platform_data ram_pdata = {
-	.name = "ram0",
-	.flags = DEVFS_RDWR,
-};
-
-static struct device_d sdram_dev = {
-	.id       = -1,
-	.name     = "mem",
-	.map_base = 0x90000000,
-	.size     = 256 * 1024 * 1024,
-	.platform_data = &ram_pdata,
-};
-
 static struct fec_platform_data fec_info = {
 	.xcv_type = MII100,
 };
@@ -106,35 +93,16 @@ static struct pad_desc eukrea_cpuimx51_pads[] = {
 #define GPIO_LAN8700_RESET	(1 * 32 + 31)
 #define GPIO_LCD_BL		(2 * 32 + 4)
 
-#ifdef CONFIG_MMU
-static void eukrea_cpuimx51_mmu_init(void)
+static int eukrea_cpuimx51_mem_init(void)
 {
-	mmu_init();
+	arm_add_mem_device("ram0", 0x90000000, 256 * 1024 * 1024);
 
-	arm_create_section(0x90000000, 0x90000000, 256, PMD_SECT_DEF_CACHED);
-	arm_create_section(0xa0000000, 0x90000000, 256, PMD_SECT_DEF_UNCACHED);
-
-	setup_dma_coherent(0x10000000);
-
-#if TEXT_BASE & (0x100000 - 1)
-#warning cannot create vector section. Adjust TEXT_BASE to a 1M boundary
-#else
-	arm_create_section(0x0,        TEXT_BASE,   1, PMD_SECT_DEF_UNCACHED);
-#endif
-
-	mmu_enable();
-}
-#else
-static void eukrea_cpuimx51_mmu_init(void)
-{
+	return 0;
 }
-#endif
+mem_initcall(eukrea_cpuimx51_mem_init);
 
 static int eukrea_cpuimx51_devices_init(void)
 {
-	eukrea_cpuimx51_mmu_init();
-
-	register_device(&sdram_dev);
 	imx51_add_fec(&fec_info);
 #ifdef CONFIG_MCI_IMX_ESDHC
 	imx51_add_mmc0(NULL);
@@ -150,7 +118,6 @@ static int eukrea_cpuimx51_devices_init(void)
 	gpio_set_value(GPIO_LAN8700_RESET, 1);
 	gpio_direction_output(GPIO_LCD_BL, 0);
 
-	armlinux_add_dram(&sdram_dev);
 	armlinux_set_bootparams((void *)0x90000100);
 	armlinux_set_architecture(MACH_TYPE_EUKREA_CPUIMX51SD);
 
diff --git a/arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S b/arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S
index 793104c7c2..0b3726f6d5 100644
--- a/arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S
+++ b/arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S
@@ -19,29 +19,29 @@
 
 #include <config.h>
 #include <mach/imx-regs.h>
-#include <mach/clock-imx51.h>
+#include <mach/clock-imx51_53.h>
 
 #define ROM_SI_REV_OFFSET                   0x48
 
 .macro setup_pll pll, freq
 	ldr r2, =\pll
 	ldr r1, =0x00001232
-	str r1, [r2, #MX51_PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
+	str r1, [r2, #MX5_PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
 	mov r1, #0x2
-	str r1, [r2, #MX51_PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
+	str r1, [r2, #MX5_PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
 
-	str r3, [r2, #MX51_PLL_DP_OP]
-	str r3, [r2, #MX51_PLL_DP_HFS_OP]
+	str r3, [r2, #MX5_PLL_DP_OP]
+	str r3, [r2, #MX5_PLL_DP_HFS_OP]
 
-	str r4, [r2, #MX51_PLL_DP_MFD]
-	str r4, [r2, #MX51_PLL_DP_HFS_MFD]
+	str r4, [r2, #MX5_PLL_DP_MFD]
+	str r4, [r2, #MX5_PLL_DP_HFS_MFD]
 
-	str r5, [r2, #MX51_PLL_DP_MFN]
-	str r5, [r2, #MX51_PLL_DP_HFS_MFN]
+	str r5, [r2, #MX5_PLL_DP_MFN]
+	str r5, [r2, #MX5_PLL_DP_HFS_MFN]
 
 	ldr r1, =0x00001232
-	str r1, [r2, #MX51_PLL_DP_CTL]
-1:	ldr r1, [r2, #MX51_PLL_DP_CTL]
+	str r1, [r2, #MX5_PLL_DP_CTL]
+1:	ldr r1, [r2, #MX5_PLL_DP_CTL]
 	ands r1, r1, #0x1
 	beq 1b
 .endm
@@ -80,67 +80,67 @@ board_init_lowlevel:
 
 	/* Gate of clocks to the peripherals first */
 	ldr r1, =0x3FFFFFFF
-	str r1, [r0, #MX51_CCM_CCGR0]
+	str r1, [r0, #MX5_CCM_CCGR0]
 	ldr r1, =0x0
-	str r1, [r0, #MX51_CCM_CCGR1]
-	str r1, [r0, #MX51_CCM_CCGR2]
-	str r1, [r0, #MX51_CCM_CCGR3]
+	str r1, [r0, #MX5_CCM_CCGR1]
+	str r1, [r0, #MX5_CCM_CCGR2]
+	str r1, [r0, #MX5_CCM_CCGR3]
 
 	ldr r1, =0x00030000
-	str r1, [r0, #MX51_CCM_CCGR4]
+	str r1, [r0, #MX5_CCM_CCGR4]
 	ldr r1, =0x00FFF030
-	str r1, [r0, #MX51_CCM_CCGR5]
+	str r1, [r0, #MX5_CCM_CCGR5]
 	ldr r1, =0x00000300
-	str r1, [r0, #MX51_CCM_CCGR6]
+	str r1, [r0, #MX5_CCM_CCGR6]
 
 	/* Disable IPU and HSC dividers */
 	mov r1, #0x60000
-	str r1, [r0, #MX51_CCM_CCDR]
+	str r1, [r0, #MX5_CCM_CCDR]
 
 #ifdef IMX51_TO_2
 	/* Make sure to switch the DDR away from PLL 1 */
 	ldr r1, =0x19239145
-	str r1, [r0, #MX51_CCM_CBCDR]
+	str r1, [r0, #MX5_CCM_CBCDR]
 	/* make sure divider effective */
-1:	ldr r1, [r0, #MX51_CCM_CDHIPR]
+1:	ldr r1, [r0, #MX5_CCM_CDHIPR]
 	cmp r1, #0x0
 	bne 1b
 #endif
 
 	/* Switch ARM to step clock */
 	mov r1, #0x4
-	str r1, [r0, #MX51_CCM_CCSR]
+	str r1, [r0, #MX5_CCM_CCSR]
 
-	mov r3, #MX51_PLL_DP_OP_800
-	mov r4, #MX51_PLL_DP_MFD_800
-	mov r5, #MX51_PLL_DP_MFN_800
+	mov r3, #MX5_PLL_DP_OP_800
+	mov r4, #MX5_PLL_DP_MFD_800
+	mov r5, #MX5_PLL_DP_MFN_800
 	setup_pll MX51_PLL1_BASE_ADDR
 
-	mov r3, #MX51_PLL_DP_OP_665
-	mov r4, #MX51_PLL_DP_MFD_665
-	mov r5, #MX51_PLL_DP_MFN_665
+	mov r3, #MX5_PLL_DP_OP_665
+	mov r4, #MX5_PLL_DP_MFD_665
+	mov r5, #MX5_PLL_DP_MFN_665
 	setup_pll MX51_PLL3_BASE_ADDR
 
 	/* Switch peripheral to PLL 3 */
 	ldr r1, =0x000010C0
-	str r1, [r0, #MX51_CCM_CBCMR]
+	str r1, [r0, #MX5_CCM_CBCMR]
 	ldr r1, =0x13239145
-	str r1, [r0, #MX51_CCM_CBCDR]
+	str r1, [r0, #MX5_CCM_CBCDR]
 
-	mov r3, #MX51_PLL_DP_OP_665
-	mov r4, #MX51_PLL_DP_MFD_665
-	mov r5, #MX51_PLL_DP_MFN_665
+	mov r3, #MX5_PLL_DP_OP_665
+	mov r4, #MX5_PLL_DP_MFD_665
+	mov r5, #MX5_PLL_DP_MFN_665
 	setup_pll MX51_PLL2_BASE_ADDR
 
 	/* Switch peripheral to PLL2 */
 	ldr r1, =0x19239145
-	str r1, [r0, #MX51_CCM_CBCDR]
+	str r1, [r0, #MX5_CCM_CBCDR]
 	ldr r1, =0x000020C0
-	str r1, [r0, #MX51_CCM_CBCMR]
+	str r1, [r0, #MX5_CCM_CBCMR]
 
-	mov r3, #MX51_PLL_DP_OP_216
-	mov r4, #MX51_PLL_DP_MFD_216
-	mov r5, #MX51_PLL_DP_MFN_216
+	mov r3, #MX5_PLL_DP_OP_216
+	mov r4, #MX5_PLL_DP_MFD_216
+	mov r5, #MX5_PLL_DP_MFN_216
 	setup_pll MX51_PLL3_BASE_ADDR
 
 	/* Set the platform clock dividers */
@@ -154,52 +154,52 @@ board_init_lowlevel:
 	cmp r3, #0x10
 	movls r1, #0x1
 	movhi r1, #0
-	str r1, [r0, #MX51_CCM_CACRR]
+	str r1, [r0, #MX5_CCM_CACRR]
 
 	/* Switch ARM back to PLL 1 */
 	mov r1, #0
-	str r1, [r0,  #MX51_CCM_CCSR]
+	str r1, [r0,  #MX5_CCM_CCSR]
 
         /* setup the rest */
         /* Use lp_apm (24MHz) source for perclk */
 #ifdef IMX51_TO_2
         ldr r1, =0x000020C2
-        str r1, [r0, #MX51_CCM_CBCMR]
+        str r1, [r0, #MX5_CCM_CBCMR]
         // ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz
         ldr r1, =0x59239100
-        str r1, [r0, #MX51_CCM_CBCDR]
+        str r1, [r0, #MX5_CCM_CBCDR]
 #else
         ldr r1, =0x0000E3C2
-        str r1, [r0, #MX51_CCM_CBCMR]
+        str r1, [r0, #MX5_CCM_CBCMR]
         // emi=ahb, all perclk dividers are 1 since using 24MHz
         // DDR divider=6 to have 665/6=110MHz
         ldr r1, =0x013B9100
-        str r1, [r0, #MX51_CCM_CBCDR]
+        str r1, [r0, #MX5_CCM_CBCDR]
 #endif
 
         /* Restore the default values in the Gate registers */
         ldr r1, =0xFFFFFFFF
-        str r1, [r0, #MX51_CCM_CCGR0]
-        str r1, [r0, #MX51_CCM_CCGR1]
-        str r1, [r0, #MX51_CCM_CCGR2]
-        str r1, [r0, #MX51_CCM_CCGR3]
-        str r1, [r0, #MX51_CCM_CCGR4]
-        str r1, [r0, #MX51_CCM_CCGR5]
-        str r1, [r0, #MX51_CCM_CCGR6]
+        str r1, [r0, #MX5_CCM_CCGR0]
+        str r1, [r0, #MX5_CCM_CCGR1]
+        str r1, [r0, #MX5_CCM_CCGR2]
+        str r1, [r0, #MX5_CCM_CCGR3]
+        str r1, [r0, #MX5_CCM_CCGR4]
+        str r1, [r0, #MX5_CCM_CCGR5]
+        str r1, [r0, #MX5_CCM_CCGR6]
 
         /* Use PLL 2 for UART's, get 66.5MHz from it */
         ldr r1, =0xA5A2A020
-        str r1, [r0, #MX51_CCM_CSCMR1]
+        str r1, [r0, #MX5_CCM_CSCMR1]
         ldr r1, =0x00C30321
-        str r1, [r0, #MX51_CCM_CSCDR1]
+        str r1, [r0, #MX5_CCM_CSCDR1]
 
         /* make sure divider effective */
-    1:  ldr r1, [r0, #MX51_CCM_CDHIPR]
+    1:  ldr r1, [r0, #MX5_CCM_CDHIPR]
         cmp r1, #0x0
         bne 1b
 
 	mov r1, #0x0
-	str r1, [r0, #MX51_CCM_CCDR]
+	str r1, [r0, #MX5_CCM_CCDR]
 
 	writel(0x1, 0x73fa8074)
 	ldr	r0, =0x73f88000
diff --git a/arch/arm/boards/freescale-mx23-evk/mx23-evk.c b/arch/arm/boards/freescale-mx23-evk/mx23-evk.c
index 1ce72be8d7..47f676919a 100644
--- a/arch/arm/boards/freescale-mx23-evk/mx23-evk.c
+++ b/arch/arm/boards/freescale-mx23-evk/mx23-evk.c
@@ -25,24 +25,17 @@
 #include <generated/mach-types.h>
 #include <mach/imx-regs.h>
 
-static struct memory_platform_data ram_pdata = {
-	.name = "ram0",
-	.flags = DEVFS_RDWR,
-};
-
-static struct device_d sdram_dev = {
-	.name     = "mem",
-	.map_base = IMX_MEMORY_BASE,
-	.size     = 32 * 1024 * 1024,
-	.platform_data = &ram_pdata,
-};
+static int mx23_evk_mem_init(void)
+{
+	arm_add_mem_device("ram0", IMX_MEMORY_BASE, 32 * 1024 * 1024);
+
+	return 0;
+}
+mem_initcall(mx23_evk_mem_init);
 
 static int mx23_evk_devices_init(void)
 {
-	register_device(&sdram_dev);
-
-	armlinux_add_dram(&sdram_dev);
-	armlinux_set_bootparams((void*)(sdram_dev.map_base + 0x100));
+	armlinux_set_bootparams((void*)IMX_MEMORY_BASE + 0x100);
 	armlinux_set_architecture(MACH_TYPE_MX23EVK);
 
 	return 0;
@@ -50,15 +43,12 @@ static int mx23_evk_devices_init(void)
 
 device_initcall(mx23_evk_devices_init);
 
-static struct device_d mx23_evk_serial_device = {
-	.name     = "stm_serial",
-	.map_base = IMX_DBGUART_BASE,
-	.size     = 8192,
-};
-
 static int mx23_evk_console_init(void)
 {
-	return register_device(&mx23_evk_serial_device);
+	add_generic_device("stm_serial", 0, NULL, IMX_DBGUART_BASE, 8192,
+			   IORESOURCE_MEM, NULL);
+	
+	return 0;
 }
 
 console_initcall(mx23_evk_console_init);
diff --git a/arch/arm/boards/freescale-mx25-3-stack/3stack.c b/arch/arm/boards/freescale-mx25-3-stack/3stack.c
index e3607f532a..979115d927 100644
--- a/arch/arm/boards/freescale-mx25-3-stack/3stack.c
+++ b/arch/arm/boards/freescale-mx25-3-stack/3stack.c
@@ -37,6 +37,7 @@
 #include <mach/imx-flash-header.h>
 #include <mach/iomux-mx25.h>
 #include <mach/generic.h>
+#include <mach/iim.h>
 #include <linux/err.h>
 #include <i2c/i2c.h>
 #include <mfd/mc34704.h>
@@ -113,38 +114,6 @@ static struct fec_platform_data fec_info = {
 	.phy_addr	= 1,
 };
 
-static struct memory_platform_data sdram_pdata = {
-	.name	= "ram0",
-	.flags	= DEVFS_RDWR,
-};
-
-static struct device_d sdram0_dev = {
-	.id	  = -1,
-	.name     = "mem",
-	.map_base = IMX_SDRAM_CS0,
-#if defined CONFIG_FREESCALE_MX25_3STACK_SDRAM_64MB_DDR2
-	.size     = 64 * 1024 * 1024,
-#elif defined CONFIG_FREESCALE_MX25_3STACK_SDRAM_128MB_MDDR
-	.size     = 128 * 1024 * 1024,
-#else
-#error "Unsupported SDRAM type"
-#endif
-	.platform_data = &sdram_pdata,
-};
-
-static struct memory_platform_data sram_pdata = {
-	.name	= "sram0",
-	.flags	= DEVFS_RDWR,
-};
-
-static struct device_d sram0_dev = {
-	.id	  = -1,
-	.name     = "mem",
-	.map_base = 0x78000000,
-	.size     = 128 * 1024,
-	.platform_data = &sram_pdata,
-};
-
 struct imx_nand_platform_data nand_info = {
 	.width	= 1,
 	.hw_ecc	= 1,
@@ -169,13 +138,6 @@ static void imx25_usb_init(void)
 	tmp = readl(IMX_OTG_BASE + 0x5a8);
 	writel(tmp | 0x3, IMX_OTG_BASE + 0x5a8);
 }
-
-static struct device_d usbh2_dev = {
-	.id	  = -1,
-	.name     = "ehci",
-	.map_base = IMX_OTG_BASE + 0x400,
-	.size     = 0x200,
-};
 #endif
 
 static struct i2c_board_info i2c_devices[] = {
@@ -230,6 +192,22 @@ static int imx25_3ds_fec_init(void)
 }
 late_initcall(imx25_3ds_fec_init);
 
+static int imx25_mem_init(void)
+{
+#if defined CONFIG_FREESCALE_MX25_3STACK_SDRAM_64MB_DDR2
+#define SDRAM_SIZE	64 * 1024 * 1024
+#elif defined CONFIG_FREESCALE_MX25_3STACK_SDRAM_128MB_MDDR
+#define SDRAM_SIZE	128 * 1024 * 1024
+#else
+#error "Unsupported SDRAM type"
+#endif
+	arm_add_mem_device("ram0", IMX_SDRAM_CS0, SDRAM_SIZE);
+	add_mem_device("sram0", 0x78000000, 128 * 1024, IORESOURCE_MEM_WRITEABLE);
+
+	return 0;
+}
+mem_initcall(imx25_mem_init);
+
 static int imx25_devices_init(void)
 {
 #ifdef CONFIG_USB
@@ -237,9 +215,10 @@ static int imx25_devices_init(void)
 	 * the CPLD has to be initialized.
 	 */
 	imx25_usb_init();
-	register_device(&usbh2_dev);
+	add_generic_usb_ehci_device(-1, IMX_OTG_BASE + 0x400, NULL);
 #endif
 
+	imx25_iim_register_fec_ethaddr();
 	imx25_add_fec(&fec_info);
 
 	if (readl(IMX_CCM_BASE + CCM_RCSR) & (1 << 14))
@@ -253,13 +232,9 @@ static int imx25_devices_init(void)
 	devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
 	dev_add_bb_dev("env_raw", "env0");
 
-	register_device(&sdram0_dev);
-	register_device(&sram0_dev);
-
 	i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
 	imx25_add_i2c0(NULL);
 
-	armlinux_add_dram(&sdram0_dev);
 	armlinux_set_bootparams((void *)0x80000100);
 	armlinux_set_architecture(MACH_TYPE_MX25_3DS);
 	armlinux_set_serial(imx_uid());
diff --git a/arch/arm/boards/freescale-mx35-3-stack/3stack.c b/arch/arm/boards/freescale-mx35-3-stack/3stack.c
index 03960a4cbf..ab702650ab 100644
--- a/arch/arm/boards/freescale-mx35-3-stack/3stack.c
+++ b/arch/arm/boards/freescale-mx35-3-stack/3stack.c
@@ -59,43 +59,16 @@
 #define MX35PDK_BOARD_REV_1		0
 #define MX35PDK_BOARD_REV_2		1
 
-static struct device_d cfi_dev = {
-	.id		= -1,
-	.name		= "cfi_flash",
-	.map_base	= IMX_CS0_BASE,
-	.size		= 64 * 1024 * 1024,
-};
-
 static struct fec_platform_data fec_info = {
 	.xcv_type	= MII100,
 	.phy_addr	= 0x1F,
 };
 
-static struct memory_platform_data sdram_pdata = {
-	.name	= "ram0",
-	.flags	= DEVFS_RDWR,
-};
-
-static struct device_d sdram_dev = {
-	.id		= -1,
-	.name		= "mem",
-	.map_base	= IMX_SDRAM_CS0,
-	.size		= 128 * 1024 * 1024,
-	.platform_data	= &sdram_pdata,
-};
-
 struct imx_nand_platform_data nand_info = {
 	.hw_ecc		= 1,
 	.flash_bbt	= 1,
 };
 
-static struct device_d smc911x_dev = {
-	.id		= -1,
-	.name		= "smc911x",
-	.map_base	= IMX_CS5_BASE,
-	.size		= IMX_CS5_RANGE,
-};
-
 static struct i2c_board_info i2c_devices[] = {
 	{
 		I2C_BOARD_INFO("mc13892-i2c", 0x08),
@@ -104,12 +77,6 @@ static struct i2c_board_info i2c_devices[] = {
 	},
 };
 
-static struct device_d i2c_dev = {
-	.id		= -1,
-	.name		= "i2c-imx",
-	.map_base	= IMX_I2C1_BASE,
-};
-
 /*
  * Generic display, shipped with the PDK
  */
@@ -161,6 +128,13 @@ static void set_board_rev(int rev)
 	imx35_3ds_system_rev =  (imx35_3ds_system_rev & ~(0xF << 8)) | (rev & 0xF) << 8;
 }
 
+static int f3s_mem_init(void)
+{
+	arm_add_mem_device("ram0", IMX_SDRAM_CS0, 124 * 1024 * 1024);
+
+	return 0;
+}
+mem_initcall(f3s_mem_init);
 
 static int f3s_devices_init(void)
 {
@@ -182,7 +156,7 @@ static int f3s_devices_init(void)
 	 * This platform supports NOR and NAND
 	 */
 	imx35_add_nand(&nand_info);
-	register_device(&cfi_dev);
+	add_cfi_flash_device(-1, IMX_CS0_BASE, 64 * 1024 * 1024, 0);
 
 	switch ((reg >> 25) & 0x3) {
 	case 0x01:		/* NAND is the source */
@@ -202,17 +176,16 @@ static int f3s_devices_init(void)
 	set_silicon_rev(imx_silicon_revision());
 
 	i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
-	register_device(&i2c_dev);
+	imx35_add_i2c0(NULL);
 
 	imx35_add_fec(&fec_info);
-	register_device(&smc911x_dev);
+	add_generic_device("smc911x", -1, NULL,	IMX_CS5_BASE, IMX_CS5_RANGE,
+			IORESOURCE_MEM, NULL);
 
 	imx35_add_mmc0(NULL);
 
-	register_device(&sdram_dev);
 	imx35_add_fb(&ipu_fb_data);
 
-	armlinux_add_dram(&sdram_dev);
 	armlinux_set_bootparams((void *)0x80000100);
 	armlinux_set_architecture(MACH_TYPE_MX35_3DS);
 
diff --git a/arch/arm/boards/freescale-mx51-pdk/board.c b/arch/arm/boards/freescale-mx51-pdk/board.c
index ee2fbee0e4..d6472df69f 100644
--- a/arch/arm/boards/freescale-mx51-pdk/board.c
+++ b/arch/arm/boards/freescale-mx51-pdk/board.c
@@ -19,7 +19,6 @@
  */
 
 #include <common.h>
-#include <net.h>
 #include <init.h>
 #include <environment.h>
 #include <mach/imx-regs.h>
@@ -40,19 +39,7 @@
 #include <mach/generic.h>
 #include <mach/iomux-mx51.h>
 #include <mach/devices-imx51.h>
-
-static struct memory_platform_data ram_pdata = {
-	.name = "ram0",
-	.flags = DEVFS_RDWR,
-};
-
-static struct device_d sdram_dev = {
-	.id       = -1,
-	.name     = "mem",
-	.map_base = 0x90000000,
-	.size     = 512 * 1024 * 1024,
-	.platform_data = &ram_pdata,
-};
+#include <mach/iim.h>
 
 static struct fec_platform_data fec_info = {
 	.xcv_type = MII100,
@@ -86,23 +73,13 @@ static struct pad_desc f3s_pads[] = {
 	IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, 0x85), /* FIXME: needed? */
 };
 
-#ifdef CONFIG_MMU
-static void babbage_mmu_init(void)
+static int babbage_mem_init(void)
 {
-	mmu_init();
-
-	arm_create_section(0x90000000, 0x90000000, 512, PMD_SECT_DEF_CACHED);
-	arm_create_section(0xb0000000, 0x90000000, 512, PMD_SECT_DEF_UNCACHED);
+	arm_add_mem_device("ram0", 0x90000000, 512 * 1024 * 1024);
 
-	setup_dma_coherent(0x20000000);
-
-	mmu_enable();
-}
-#else
-static void babbage_mmu_init(void)
-{
+	return 0;
 }
-#endif
+mem_initcall(babbage_mem_init);
 
 #define BABBAGE_ECSPI1_CS0	(3 * 32 + 24)
 static int spi_0_cs[] = {BABBAGE_ECSPI1_CS0};
@@ -240,9 +217,7 @@ static void babbage_power_init(void)
 
 static int f3s_devices_init(void)
 {
-	babbage_mmu_init();
-
-	register_device(&sdram_dev);
+	imx51_iim_register_fec_ethaddr();
 	imx51_add_fec(&fec_info);
 	imx51_add_mmc0(NULL);
 
@@ -252,7 +227,6 @@ static int f3s_devices_init(void)
 
 	babbage_power_init();
 
-	armlinux_add_dram(&sdram_dev);
 	armlinux_set_bootparams((void *)0x90000100);
 	armlinux_set_architecture(MACH_TYPE_MX51_BABBAGE);
 
diff --git a/arch/arm/boards/freescale-mx51-pdk/lowlevel_init.S b/arch/arm/boards/freescale-mx51-pdk/lowlevel_init.S
index 793104c7c2..0b3726f6d5 100644
--- a/arch/arm/boards/freescale-mx51-pdk/lowlevel_init.S
+++ b/arch/arm/boards/freescale-mx51-pdk/lowlevel_init.S
@@ -19,29 +19,29 @@
 
 #include <config.h>
 #include <mach/imx-regs.h>
-#include <mach/clock-imx51.h>
+#include <mach/clock-imx51_53.h>
 
 #define ROM_SI_REV_OFFSET                   0x48
 
 .macro setup_pll pll, freq
 	ldr r2, =\pll
 	ldr r1, =0x00001232
-	str r1, [r2, #MX51_PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
+	str r1, [r2, #MX5_PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
 	mov r1, #0x2
-	str r1, [r2, #MX51_PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
+	str r1, [r2, #MX5_PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
 
-	str r3, [r2, #MX51_PLL_DP_OP]
-	str r3, [r2, #MX51_PLL_DP_HFS_OP]
+	str r3, [r2, #MX5_PLL_DP_OP]
+	str r3, [r2, #MX5_PLL_DP_HFS_OP]
 
-	str r4, [r2, #MX51_PLL_DP_MFD]
-	str r4, [r2, #MX51_PLL_DP_HFS_MFD]
+	str r4, [r2, #MX5_PLL_DP_MFD]
+	str r4, [r2, #MX5_PLL_DP_HFS_MFD]
 
-	str r5, [r2, #MX51_PLL_DP_MFN]
-	str r5, [r2, #MX51_PLL_DP_HFS_MFN]
+	str r5, [r2, #MX5_PLL_DP_MFN]
+	str r5, [r2, #MX5_PLL_DP_HFS_MFN]
 
 	ldr r1, =0x00001232
-	str r1, [r2, #MX51_PLL_DP_CTL]
-1:	ldr r1, [r2, #MX51_PLL_DP_CTL]
+	str r1, [r2, #MX5_PLL_DP_CTL]
+1:	ldr r1, [r2, #MX5_PLL_DP_CTL]
 	ands r1, r1, #0x1
 	beq 1b
 .endm
@@ -80,67 +80,67 @@ board_init_lowlevel:
 
 	/* Gate of clocks to the peripherals first */
 	ldr r1, =0x3FFFFFFF
-	str r1, [r0, #MX51_CCM_CCGR0]
+	str r1, [r0, #MX5_CCM_CCGR0]
 	ldr r1, =0x0
-	str r1, [r0, #MX51_CCM_CCGR1]
-	str r1, [r0, #MX51_CCM_CCGR2]
-	str r1, [r0, #MX51_CCM_CCGR3]
+	str r1, [r0, #MX5_CCM_CCGR1]
+	str r1, [r0, #MX5_CCM_CCGR2]
+	str r1, [r0, #MX5_CCM_CCGR3]
 
 	ldr r1, =0x00030000
-	str r1, [r0, #MX51_CCM_CCGR4]
+	str r1, [r0, #MX5_CCM_CCGR4]
 	ldr r1, =0x00FFF030
-	str r1, [r0, #MX51_CCM_CCGR5]
+	str r1, [r0, #MX5_CCM_CCGR5]
 	ldr r1, =0x00000300
-	str r1, [r0, #MX51_CCM_CCGR6]
+	str r1, [r0, #MX5_CCM_CCGR6]
 
 	/* Disable IPU and HSC dividers */
 	mov r1, #0x60000
-	str r1, [r0, #MX51_CCM_CCDR]
+	str r1, [r0, #MX5_CCM_CCDR]
 
 #ifdef IMX51_TO_2
 	/* Make sure to switch the DDR away from PLL 1 */
 	ldr r1, =0x19239145
-	str r1, [r0, #MX51_CCM_CBCDR]
+	str r1, [r0, #MX5_CCM_CBCDR]
 	/* make sure divider effective */
-1:	ldr r1, [r0, #MX51_CCM_CDHIPR]
+1:	ldr r1, [r0, #MX5_CCM_CDHIPR]
 	cmp r1, #0x0
 	bne 1b
 #endif
 
 	/* Switch ARM to step clock */
 	mov r1, #0x4
-	str r1, [r0, #MX51_CCM_CCSR]
+	str r1, [r0, #MX5_CCM_CCSR]
 
-	mov r3, #MX51_PLL_DP_OP_800
-	mov r4, #MX51_PLL_DP_MFD_800
-	mov r5, #MX51_PLL_DP_MFN_800
+	mov r3, #MX5_PLL_DP_OP_800
+	mov r4, #MX5_PLL_DP_MFD_800
+	mov r5, #MX5_PLL_DP_MFN_800
 	setup_pll MX51_PLL1_BASE_ADDR
 
-	mov r3, #MX51_PLL_DP_OP_665
-	mov r4, #MX51_PLL_DP_MFD_665
-	mov r5, #MX51_PLL_DP_MFN_665
+	mov r3, #MX5_PLL_DP_OP_665
+	mov r4, #MX5_PLL_DP_MFD_665
+	mov r5, #MX5_PLL_DP_MFN_665
 	setup_pll MX51_PLL3_BASE_ADDR
 
 	/* Switch peripheral to PLL 3 */
 	ldr r1, =0x000010C0
-	str r1, [r0, #MX51_CCM_CBCMR]
+	str r1, [r0, #MX5_CCM_CBCMR]
 	ldr r1, =0x13239145
-	str r1, [r0, #MX51_CCM_CBCDR]
+	str r1, [r0, #MX5_CCM_CBCDR]
 
-	mov r3, #MX51_PLL_DP_OP_665
-	mov r4, #MX51_PLL_DP_MFD_665
-	mov r5, #MX51_PLL_DP_MFN_665
+	mov r3, #MX5_PLL_DP_OP_665
+	mov r4, #MX5_PLL_DP_MFD_665
+	mov r5, #MX5_PLL_DP_MFN_665
 	setup_pll MX51_PLL2_BASE_ADDR
 
 	/* Switch peripheral to PLL2 */
 	ldr r1, =0x19239145
-	str r1, [r0, #MX51_CCM_CBCDR]
+	str r1, [r0, #MX5_CCM_CBCDR]
 	ldr r1, =0x000020C0
-	str r1, [r0, #MX51_CCM_CBCMR]
+	str r1, [r0, #MX5_CCM_CBCMR]
 
-	mov r3, #MX51_PLL_DP_OP_216
-	mov r4, #MX51_PLL_DP_MFD_216
-	mov r5, #MX51_PLL_DP_MFN_216
+	mov r3, #MX5_PLL_DP_OP_216
+	mov r4, #MX5_PLL_DP_MFD_216
+	mov r5, #MX5_PLL_DP_MFN_216
 	setup_pll MX51_PLL3_BASE_ADDR
 
 	/* Set the platform clock dividers */
@@ -154,52 +154,52 @@ board_init_lowlevel:
 	cmp r3, #0x10
 	movls r1, #0x1
 	movhi r1, #0
-	str r1, [r0, #MX51_CCM_CACRR]
+	str r1, [r0, #MX5_CCM_CACRR]
 
 	/* Switch ARM back to PLL 1 */
 	mov r1, #0
-	str r1, [r0,  #MX51_CCM_CCSR]
+	str r1, [r0,  #MX5_CCM_CCSR]
 
         /* setup the rest */
         /* Use lp_apm (24MHz) source for perclk */
 #ifdef IMX51_TO_2
         ldr r1, =0x000020C2
-        str r1, [r0, #MX51_CCM_CBCMR]
+        str r1, [r0, #MX5_CCM_CBCMR]
         // ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz
         ldr r1, =0x59239100
-        str r1, [r0, #MX51_CCM_CBCDR]
+        str r1, [r0, #MX5_CCM_CBCDR]
 #else
         ldr r1, =0x0000E3C2
-        str r1, [r0, #MX51_CCM_CBCMR]
+        str r1, [r0, #MX5_CCM_CBCMR]
         // emi=ahb, all perclk dividers are 1 since using 24MHz
         // DDR divider=6 to have 665/6=110MHz
         ldr r1, =0x013B9100
-        str r1, [r0, #MX51_CCM_CBCDR]
+        str r1, [r0, #MX5_CCM_CBCDR]
 #endif
 
         /* Restore the default values in the Gate registers */
         ldr r1, =0xFFFFFFFF
-        str r1, [r0, #MX51_CCM_CCGR0]
-        str r1, [r0, #MX51_CCM_CCGR1]
-        str r1, [r0, #MX51_CCM_CCGR2]
-        str r1, [r0, #MX51_CCM_CCGR3]
-        str r1, [r0, #MX51_CCM_CCGR4]
-        str r1, [r0, #MX51_CCM_CCGR5]
-        str r1, [r0, #MX51_CCM_CCGR6]
+        str r1, [r0, #MX5_CCM_CCGR0]
+        str r1, [r0, #MX5_CCM_CCGR1]
+        str r1, [r0, #MX5_CCM_CCGR2]
+        str r1, [r0, #MX5_CCM_CCGR3]
+        str r1, [r0, #MX5_CCM_CCGR4]
+        str r1, [r0, #MX5_CCM_CCGR5]
+        str r1, [r0, #MX5_CCM_CCGR6]
 
         /* Use PLL 2 for UART's, get 66.5MHz from it */
         ldr r1, =0xA5A2A020
-        str r1, [r0, #MX51_CCM_CSCMR1]
+        str r1, [r0, #MX5_CCM_CSCMR1]
         ldr r1, =0x00C30321
-        str r1, [r0, #MX51_CCM_CSCDR1]
+        str r1, [r0, #MX5_CCM_CSCDR1]
 
         /* make sure divider effective */
-    1:  ldr r1, [r0, #MX51_CCM_CDHIPR]
+    1:  ldr r1, [r0, #MX5_CCM_CDHIPR]
         cmp r1, #0x0
         bne 1b
 
 	mov r1, #0x0
-	str r1, [r0, #MX51_CCM_CCDR]
+	str r1, [r0, #MX5_CCM_CCDR]
 
 	writel(0x1, 0x73fa8074)
 	ldr	r0, =0x73f88000
diff --git a/arch/arm/boards/freescale-mx53-loco/Makefile b/arch/arm/boards/freescale-mx53-loco/Makefile
new file mode 100644
index 0000000000..8e0c87c96f
--- /dev/null
+++ b/arch/arm/boards/freescale-mx53-loco/Makefile
@@ -0,0 +1,3 @@
+obj-y += lowlevel_init.o
+obj-y += board.o
+obj-y += flash_header.o
diff --git a/arch/arm/boards/freescale-mx53-loco/board.c b/arch/arm/boards/freescale-mx53-loco/board.c
new file mode 100644
index 0000000000..b5240f4f3a
--- /dev/null
+++ b/arch/arm/boards/freescale-mx53-loco/board.c
@@ -0,0 +1,129 @@
+/*
+ * Copyright (C) 2007 Sascha Hauer, Pengutronix
+ * Copyright (C) 2011 Marc Kleine-Budde <mkl@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <environment.h>
+#include <fcntl.h>
+#include <fec.h>
+#include <fs.h>
+#include <init.h>
+#include <nand.h>
+#include <net.h>
+#include <partition.h>
+#include <sizes.h>
+
+#include <generated/mach-types.h>
+
+#include <mach/imx-regs.h>
+#include <mach/iomux-mx53.h>
+#include <mach/devices-imx53.h>
+#include <mach/generic.h>
+#include <mach/gpio.h>
+#include <mach/imx-nand.h>
+#include <mach/iim.h>
+
+#include <asm/armlinux.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+
+static struct fec_platform_data fec_info = {
+	.xcv_type = RMII,
+};
+
+static struct pad_desc loco_pads[] = {
+	/* UART1 */
+	MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
+	MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
+
+	/* FEC */
+	MX53_PAD_FEC_MDC__FEC_MDC,
+	MX53_PAD_FEC_MDIO__FEC_MDIO,
+	MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
+	MX53_PAD_FEC_RX_ER__FEC_RX_ER,
+	MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
+	MX53_PAD_FEC_RXD1__FEC_RDATA_1,
+	MX53_PAD_FEC_RXD0__FEC_RDATA_0,
+	MX53_PAD_FEC_TX_EN__FEC_TX_EN,
+	MX53_PAD_FEC_TXD1__FEC_TDATA_1,
+	MX53_PAD_FEC_TXD0__FEC_TDATA_0,
+	/* FEC_nRST */
+	MX53_PAD_PATA_DA_0__GPIO7_6,
+
+	/* SD1 */
+	MX53_PAD_SD1_CMD__ESDHC1_CMD,
+	MX53_PAD_SD1_CLK__ESDHC1_CLK,
+	MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
+	MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
+	MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
+	MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
+	/* SD1_CD */
+	MX53_PAD_EIM_DA13__GPIO3_13,
+};
+
+static int loco_mem_init(void)
+{
+	arm_add_mem_device("ram0", 0x70000000, SZ_512M);
+	arm_add_mem_device("ram1", 0xb0000000, SZ_512M);
+
+	return 0;
+}
+mem_initcall(loco_mem_init);
+
+#define LOCO_FEC_PHY_RST		IMX_GPIO_NR(7, 6)
+
+static void loco_fec_reset(void)
+{
+	gpio_direction_output(LOCO_FEC_PHY_RST, 0);
+	mdelay(1);
+	gpio_set_value(LOCO_FEC_PHY_RST, 1);
+}
+
+static int loco_devices_init(void)
+{
+	imx51_iim_register_fec_ethaddr();
+	imx53_add_fec(&fec_info);
+	imx53_add_mmc0(NULL);
+
+	loco_fec_reset();
+
+	armlinux_set_bootparams((void *)0x70000100);
+	armlinux_set_architecture(MACH_TYPE_MX53_LOCO);
+
+	loco_fec_reset();
+
+	return 0;
+}
+
+device_initcall(loco_devices_init);
+
+static int loco_part_init(void)
+{
+	devfs_add_partition("disk0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
+	devfs_add_partition("disk0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
+
+	return 0;
+}
+late_initcall(loco_part_init);
+
+static int loco_console_init(void)
+{
+	mxc_iomux_v3_setup_multiple_pads(loco_pads, ARRAY_SIZE(loco_pads));
+
+	imx53_add_uart0();
+	return 0;
+}
+
+console_initcall(loco_console_init);
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/boards/freescale-mx53-loco/config.h
index 51d9405d65..b7effe5d28 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/boards/freescale-mx53-loco/config.h
@@ -1,9 +1,6 @@
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
+/**
+ * @file
+ * @brief Global defintions for the ARM i.MX51 based babbage board
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -12,7 +9,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -21,10 +18,7 @@
  * MA 02111-1307 USA
  */
 
-#ifndef	__ASM_GBL_DATA_H
-#define __ASM_GBL_DATA_H
-typedef	struct	global_data gd_t;
-
-#define DECLARE_GLOBAL_DATA_PTR
+#ifndef __CONFIG_H
+#define __CONFIG_H
 
-#endif /* __ASM_GBL_DATA_H */
+#endif	/* __CONFIG_H */
diff --git a/arch/arm/boards/freescale-mx53-loco/env/config b/arch/arm/boards/freescale-mx53-loco/env/config
new file mode 100644
index 0000000000..3659a629a9
--- /dev/null
+++ b/arch/arm/boards/freescale-mx53-loco/env/config
@@ -0,0 +1,51 @@
+#!/bin/sh
+
+machine=loco
+eth0.serverip=
+user=
+
+# use 'dhcp' to do dhcp in barebox and in kernel
+# use 'none' if you want to skip kernel ip autoconfiguration
+ip=dhcp
+
+# or set your networking parameters here
+#eth0.ipaddr=a.b.c.d
+#eth0.netmask=a.b.c.d
+#eth0.gateway=a.b.c.d
+#eth0.serverip=a.b.c.d
+
+# can be either 'nfs', 'tftp', 'nor' or 'nand'
+kernel_loc=tftp
+# can be either 'net', 'nor', 'nand' or 'initrd'
+rootfs_loc=net
+
+# can be either 'jffs2' or 'ubifs'
+rootfs_type=ubifs
+rootfsimage=root-$machine.$rootfs_type
+
+# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo
+kernelimage_type=zimage
+kernelimage=zImage-$machine
+#kernelimage_type=uimage
+#kernelimage=uImage-$machine
+#kernelimage_type=raw
+#kernelimage=Image-$machine
+#kernelimage_type=raw_lzo
+#kernelimage=Image-$machine.lzo
+
+if [ -n $user ]; then
+	kernelimage="$user"-"$kernelimage"
+	nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine"
+	rootfsimage="$user"-"$rootfsimage"
+else
+	nfsroot="$eth0.serverip:/path/to/nfs/root"
+fi
+
+autoboot_timeout=3
+
+bootargs="console=ttymxc0,115200"
+
+disk_parts="256k(barebox)ro,128k(bareboxenv),4M(kernel),-(root)"
+
+# set a fancy prompt (if support is compiled in)
+PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "
diff --git a/arch/arm/boards/freescale-mx53-loco/flash_header.c b/arch/arm/boards/freescale-mx53-loco/flash_header.c
new file mode 100644
index 0000000000..d6ff898711
--- /dev/null
+++ b/arch/arm/boards/freescale-mx53-loco/flash_header.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2011 Marc Kleine-Budde <mkl@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <common.h>
+#include <asm/byteorder.h>
+#include <mach/imx-flash-header.h>
+
+void __naked __flash_header_start go(void)
+{
+	__asm__ __volatile__("b exception_vectors\n");
+}
+
+struct imx_dcd_v2_entry __dcd_entry_section dcd_entry[] = {
+	{ .addr = cpu_to_be32(0x53fa8554), .val = cpu_to_be32(0x00300000), },
+	{ .addr = cpu_to_be32(0x53fa8558), .val = cpu_to_be32(0x00300040), },
+	{ .addr = cpu_to_be32(0x53fa8560), .val = cpu_to_be32(0x00300000), },
+	{ .addr = cpu_to_be32(0x53fa8564), .val = cpu_to_be32(0x00300040), },
+	{ .addr = cpu_to_be32(0x53fa8568), .val = cpu_to_be32(0x00300040), },
+	{ .addr = cpu_to_be32(0x53fa8570), .val = cpu_to_be32(0x00300000), },
+	{ .addr = cpu_to_be32(0x53fa8574), .val = cpu_to_be32(0x00300000), },
+	{ .addr = cpu_to_be32(0x53fa8578), .val = cpu_to_be32(0x00300000), },
+	{ .addr = cpu_to_be32(0x53fa857c), .val = cpu_to_be32(0x00300040), },
+	{ .addr = cpu_to_be32(0x53fa8580), .val = cpu_to_be32(0x00300040), },
+	{ .addr = cpu_to_be32(0x53fa8584), .val = cpu_to_be32(0x00300000), },
+	{ .addr = cpu_to_be32(0x53fa8588), .val = cpu_to_be32(0x00300000), },
+	{ .addr = cpu_to_be32(0x53fa8590), .val = cpu_to_be32(0x00300040), },
+	{ .addr = cpu_to_be32(0x53fa8594), .val = cpu_to_be32(0x00300000), },
+	{ .addr = cpu_to_be32(0x53fa86f0), .val = cpu_to_be32(0x00300000), },
+	{ .addr = cpu_to_be32(0x53fa86f4), .val = cpu_to_be32(0x00000000), },
+	{ .addr = cpu_to_be32(0x53fa86fc), .val = cpu_to_be32(0x00000000), },
+	{ .addr = cpu_to_be32(0x53fa8714), .val = cpu_to_be32(0x00000000), },
+	{ .addr = cpu_to_be32(0x53fa8718), .val = cpu_to_be32(0x00300000), },
+	{ .addr = cpu_to_be32(0x53fa871c), .val = cpu_to_be32(0x00300000), },
+	{ .addr = cpu_to_be32(0x53fa8720), .val = cpu_to_be32(0x00300000), },
+	{ .addr = cpu_to_be32(0x53fa8724), .val = cpu_to_be32(0x04000000), },
+	{ .addr = cpu_to_be32(0x53fa8728), .val = cpu_to_be32(0x00300000), },
+	{ .addr = cpu_to_be32(0x53fa872c), .val = cpu_to_be32(0x00300000), },
+	{ .addr = cpu_to_be32(0x63fd9088), .val = cpu_to_be32(0x35343535), },
+	{ .addr = cpu_to_be32(0x63fd9090), .val = cpu_to_be32(0x4d444c44), },
+	{ .addr = cpu_to_be32(0x63fd907c), .val = cpu_to_be32(0x01370138), },
+	{ .addr = cpu_to_be32(0x63fd9080), .val = cpu_to_be32(0x013b013c), },
+	{ .addr = cpu_to_be32(0x63fd9018), .val = cpu_to_be32(0x00011740), },
+	{ .addr = cpu_to_be32(0x63fd9000), .val = cpu_to_be32(0xc3190000), },
+	{ .addr = cpu_to_be32(0x63fd900c), .val = cpu_to_be32(0x9f5152e3), },
+	{ .addr = cpu_to_be32(0x63fd9010), .val = cpu_to_be32(0xb68e8a63), },
+	{ .addr = cpu_to_be32(0x63fd9014), .val = cpu_to_be32(0x01ff00db), },
+	{ .addr = cpu_to_be32(0x63fd902c), .val = cpu_to_be32(0x000026d2), },
+	{ .addr = cpu_to_be32(0x63fd9030), .val = cpu_to_be32(0x009f0e21), },
+	{ .addr = cpu_to_be32(0x63fd9008), .val = cpu_to_be32(0x12273030), },
+	{ .addr = cpu_to_be32(0x63fd9004), .val = cpu_to_be32(0x0002002d), },
+	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008032), },
+	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008033), },
+	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00028031), },
+	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x092080b0), },
+	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008040), },
+	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0000803a), },
+	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0000803b), },
+	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00028039), },
+	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x09208138), },
+	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008048), },
+	{ .addr = cpu_to_be32(0x63fd9020), .val = cpu_to_be32(0x00001800), },
+	{ .addr = cpu_to_be32(0x63fd9040), .val = cpu_to_be32(0x04b80003), },
+	{ .addr = cpu_to_be32(0x63fd9058), .val = cpu_to_be32(0x00022227), },
+	{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00000000), },
+};
+
+#define APP_DEST	CONFIG_TEXT_BASE
+
+struct imx_flash_header_v2 __flash_header_section flash_header = {
+	.header.tag		= IVT_HEADER_TAG,
+	.header.length		= cpu_to_be16(32),
+	.header.version		= IVT_VERSION,
+
+	.entry			= APP_DEST + 0x1000,
+	.dcd_ptr		= APP_DEST + 0x400 + offsetof(struct imx_flash_header_v2, dcd),
+	.boot_data_ptr		= APP_DEST + 0x400 + offsetof(struct imx_flash_header_v2, boot_data),
+	.self			= APP_DEST + 0x400,
+
+	.boot_data.start	= APP_DEST,
+	.boot_data.size		= 0x40000,
+
+	.dcd.header.tag		= DCD_HEADER_TAG,
+	.dcd.header.length	= cpu_to_be16(sizeof(struct imx_dcd) + sizeof(dcd_entry)),
+	.dcd.header.version	= DCD_VERSION,
+
+	.dcd.command.tag	= DCD_COMMAND_WRITE_TAG,
+	.dcd.command.length	= cpu_to_be16(sizeof(struct imx_dcd_command) + sizeof(dcd_entry)),
+	.dcd.command.param	= DCD_COMMAND_WRITE_PARAM,
+};
diff --git a/arch/arm/boards/freescale-mx53-loco/lowlevel_init.S b/arch/arm/boards/freescale-mx53-loco/lowlevel_init.S
new file mode 100644
index 0000000000..44102c9b59
--- /dev/null
+++ b/arch/arm/boards/freescale-mx53-loco/lowlevel_init.S
@@ -0,0 +1,172 @@
+/*
+ * Copyright (C) 2007 Guennadi Liakhovetski <lg@denx.de>
+ * Copyright (C) 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <config.h>
+#include <mach/imx-regs.h>
+#include <mach/clock-imx51_53.h>
+
+/*
+ * L2CC Cache setup/invalidation/disable
+ */
+.macro init_l2cc
+	/* explicitly disable L2 cache */
+	mrc 15, 0, r0, c1, c0, 1
+	bic r0, r0, #0x2
+	mcr 15, 0, r0, c1, c0, 1
+
+	/* reconfigure L2 cache aux control reg */
+	mov r0, #0xC0			/* tag RAM */
+	add r0, r0, #0x4		/* data RAM */
+	orr r0, r0, #(1 << 24)		/* disable write allocate delay */
+	orr r0, r0, #(1 << 23)		/* disable write allocate combine */
+	orr r0, r0, #(1 << 22)		/* disable write allocate */
+
+	cmp r3, #0x10			/* r3 contains the silicon rev */
+
+	/* disable write combine for TO 2 and lower revs */
+	orrls r0, r0, #(1 << 25)
+
+	mcr 15, 1, r0, c9, c0, 2
+.endm /* init_l2cc */
+
+/* AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.*/
+.macro init_aips
+	/*
+	 * Set all MPROTx to be non-bufferable, trusted for R/W,
+	 * not forced to user-mode.
+	 */
+	ldr r0, =MX53_AIPS1_BASE_ADDR
+	ldr r1, =0x77777777
+	str r1, [r0, #0x0]
+	str r1, [r0, #0x4]
+
+	ldr r0, =MX53_AIPS2_BASE_ADDR
+	str r1, [r0, #0x0]
+	str r1, [r0, #0x4]
+	/*
+	 * Clear the on and off peripheral modules Supervisor Protect bit
+	 * for SDMA to access them. Did not change the AIPS control registers
+	 * (offset 0x20) access type
+	 */
+.endm /* init_aips */
+
+.macro setup_pll pll, freq
+	ldr r0, =\pll
+	ldr r1, =0x00001232
+	str r1, [r0, #MX5_PLL_DP_CTL]		/* Set DPLL ON (set UPEN bit): BRMO=1 */
+	mov r1, #0x2
+	str r1, [r0, #MX5_PLL_DP_CONFIG]	/* Enable auto-restart AREN bit */
+
+	ldr r1, W_DP_OP_\freq
+	str r1, [r0, #MX5_PLL_DP_OP]
+	str r1, [r0, #MX5_PLL_DP_HFS_OP]
+
+	ldr r1, W_DP_MFD_\freq
+	str r1, [r0, #MX5_PLL_DP_MFD]
+	str r1, [r0, #MX5_PLL_DP_HFS_MFD]
+
+	ldr r1, W_DP_MFN_\freq
+	str r1, [r0, #MX5_PLL_DP_MFN]
+	str r1, [r0, #MX5_PLL_DP_HFS_MFN]
+
+	ldr r1, =0x00001232
+	str r1, [r0, #MX5_PLL_DP_CTL]
+1:	ldr r1, [r0, #MX5_PLL_DP_CTL]
+	ands r1, r1, #0x1
+	beq 1b
+.endm
+
+.macro init_clock
+	ldr r0, =MX53_CCM_BASE_ADDR
+
+
+	/* Switch ARM to step clock */
+	mov r1, #0x4
+	str r1, [r0, #MX5_CCM_CCSR]
+
+	setup_pll MX53_PLL1_BASE_ADDR, 1000
+	setup_pll MX53_PLL3_BASE_ADDR, 216
+
+	/* Set the platform clock dividers */
+	ldr r0, =MX53_ARM_BASE_ADDR
+	ldr r1, =0x00000725
+	str r1, [r0, #0x14]
+
+	ldr r0, =MX53_CCM_BASE_ADDR
+	mov r1, #0
+	str r1, [r0, #MX5_CCM_CACRR]
+
+	/* Switch ARM back to PLL 1 */
+	mov r1, #0
+	str r1, [r0, #MX5_CCM_CCSR]
+
+
+	/* Restore the default values in the Gate registers */
+	ldr r1, =0xFFFFFFFF
+	str r1, [r0, #MX5_CCM_CCGR0]
+	str r1, [r0, #MX5_CCM_CCGR1]
+	str r1, [r0, #MX5_CCM_CCGR2]
+	str r1, [r0, #MX5_CCM_CCGR3]
+	str r1, [r0, #MX5_CCM_CCGR4]
+	str r1, [r0, #MX5_CCM_CCGR5]
+	str r1, [r0, #MX5_CCM_CCGR6]
+#if 0
+	str r1, [r0, #MX5_CCM_CCGR7]
+#endif
+
+	ldr r1, [r0, #MX5_CCM_CSCDR1]
+	orr r1, r1, #0x3f
+	eor r1, r1, #0x3f
+	orr r1, r1, #0x21
+	str r1, [r0, #MX5_CCM_CSCDR1]
+	/* make sure divider effective */
+1:	ldr r1, [r0, #MX5_CCM_CDHIPR]
+	cmp r1, #0x0
+	bne 1b
+
+	mov r1, #0x0
+	str r1, [r0, #MX5_CCM_CCDR]
+
+	/* for cko - for ARM div by 8 */
+	mov r1, #0x000A0000
+	add r1, r1, #0x00000F0
+	str r1, [r0, #MX5_CCM_CCOSR]
+.endm
+
+.globl board_init_lowlevel
+board_init_lowlevel:
+	mov r10, lr
+
+	init_l2cc
+	init_aips
+	init_clock
+
+	mov pc, r10
+
+/* Board level setting value */
+W_DP_OP_1000:		.word MX5_PLL_DP_OP_1000
+W_DP_MFD_1000:		.word MX5_PLL_DP_MFD_1000
+W_DP_MFN_1000:		.word MX5_PLL_DP_MFN_1000
+W_DP_OP_800:		.word MX5_PLL_DP_OP_800
+W_DP_MFD_800:		.word MX5_PLL_DP_MFD_800
+W_DP_MFN_800:		.word MX5_PLL_DP_MFN_800
+W_DP_OP_665:		.word MX5_PLL_DP_OP_665
+W_DP_MFD_665:		.word MX5_PLL_DP_MFD_665
+W_DP_MFN_665:		.word MX5_PLL_DP_MFN_665
+W_DP_OP_216:		.word MX5_PLL_DP_OP_216
+W_DP_MFD_216:		.word MX5_PLL_DP_MFD_216
+W_DP_MFN_216:		.word MX5_PLL_DP_MFN_216
diff --git a/arch/arm/boards/freescale-mx53-loco/mx53-pdk.dox b/arch/arm/boards/freescale-mx53-loco/mx53-pdk.dox
new file mode 100644
index 0000000000..3a2c84fc3f
--- /dev/null
+++ b/arch/arm/boards/freescale-mx53-loco/mx53-pdk.dox
@@ -0,0 +1,4 @@
+/** @page board_loco Freescale i.MX53 PDK (Loco) Board
+
+
+*/
diff --git a/arch/arm/boards/guf-cupid/board.c b/arch/arm/boards/guf-cupid/board.c
index d04af78930..706707d0bb 100644
--- a/arch/arm/boards/guf-cupid/board.c
+++ b/arch/arm/boards/guf-cupid/board.c
@@ -43,44 +43,18 @@
 #include <mach/imx-ipu-fb.h>
 #include <mach/imx-pll.h>
 #include <mach/iomux-mx35.h>
+#include <mach/devices-imx35.h>
 
 static struct fec_platform_data fec_info = {
 	.xcv_type = MII100,
 };
 
-static struct device_d fec_dev = {
-	.id	  = -1,
-	.name     = "fec_imx",
-	.map_base = IMX_FEC_BASE,
-	.platform_data	= &fec_info,
-};
-
-static struct memory_platform_data ram_pdata = {
-	.name = "ram0",
-	.flags = DEVFS_RDWR,
-};
-
-static struct device_d sdram0_dev = {
-	.id	  = -1,
-	.name     = "mem",
-	.map_base = IMX_SDRAM_CS0,
-	.size     = 128 * 1024 * 1024,
-	.platform_data = &ram_pdata,
-};
-
 struct imx_nand_platform_data nand_info = {
 	.width	= 1,
 	.hw_ecc	= 1,
 	.flash_bbt = 1,
 };
 
-static struct device_d nand_dev = {
-	.id	  = -1,
-	.name     = "imx_nand",
-	.map_base = IMX_NFC_BASE,
-	.platform_data	= &nand_info,
-};
-
 static struct fb_videomode guf_cupid_fb_mode = {
 	/* 800x480 @ 70 Hz */
 	.name		= "CPT CLAA070LC0JCT",
@@ -122,38 +96,21 @@ static struct imx_ipu_fb_platform_data ipu_fb_data = {
 	.enable		= cupid_fb_enable,
 };
 
-static struct device_d imx_ipu_fb_dev = {
-	.id		= -1,
-	.name		= "imx-ipu-fb",
-	.map_base	= 0x53fc0000,
-	.size		= 0x1000,
-	.platform_data	= &ipu_fb_data,
-};
+static int cupid_mem_init(void)
+{
+	arm_add_mem_device("ram0", IMX_SDRAM_CS0, 128 * 1024 * 1024);
 
-static struct device_d esdhc_dev = {
-	.name		= "imx-esdhc",
-	.map_base	= IMX_SDHC1_BASE,
-};
+	return 0;
+}
+mem_initcall(cupid_mem_init);
 
-#ifdef CONFIG_MMU
 static int cupid_mmu_init(void)
 {
-	mmu_init();
-
-	arm_create_section(0x80000000, 0x80000000, 128, PMD_SECT_DEF_CACHED);
-	arm_create_section(0x90000000, 0x80000000, 128, PMD_SECT_DEF_UNCACHED);
-
-	setup_dma_coherent(0x10000000);
-
-	mmu_enable();
-
-#ifdef CONFIG_CACHE_L2X0
 	l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000);
-#endif
+
 	return 0;
 }
-postcore_initcall(cupid_mmu_init);
-#endif
+postmmu_initcall(cupid_mmu_init);
 
 static int cupid_devices_init(void)
 {
@@ -169,19 +126,17 @@ static int cupid_devices_init(void)
 	else
 		nand_info.width = 1;    /* 8 bit */
 
-	register_device(&fec_dev);
-	register_device(&nand_dev);
+	imx35_add_fec(&fec_info);
+	imx35_add_nand(&nand_info);
 
 	devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
 	dev_add_bb_dev("self_raw", "self0");
 	devfs_add_partition("nand0", 0x40000, 0x80000, PARTITION_FIXED, "env_raw");
 	dev_add_bb_dev("env_raw", "env0");
 
-	register_device(&sdram0_dev);
-	register_device(&imx_ipu_fb_dev);
-	register_device(&esdhc_dev);
+	imx35_add_fb(&ipu_fb_data);
+	imx35_add_mmc0(NULL);
 
-	armlinux_add_dram(&sdram0_dev);
 	armlinux_set_bootparams((void *)0x80000100);
 	armlinux_set_architecture(MACH_TYPE_GUF_CUPID);
 
@@ -190,13 +145,6 @@ static int cupid_devices_init(void)
 
 device_initcall(cupid_devices_init);
 
-static struct device_d cupid_serial_device = {
-	.id	  = -1,
-	.name     = "imx_serial",
-	.map_base = IMX_UART1_BASE,
-	.size     = 16 * 1024,
-};
-
 static struct pad_desc cupid_pads[] = {
 	/* UART1 */
 	MX35_PAD_CTS1__UART1_CTS,
@@ -289,7 +237,8 @@ static int cupid_console_init(void)
 {
 	mxc_iomux_v3_setup_multiple_pads(cupid_pads, ARRAY_SIZE(cupid_pads));
 
-	register_device(&cupid_serial_device);
+	imx35_add_uart0();
+
 	return 0;
 }
 
diff --git a/arch/arm/boards/guf-neso/board.c b/arch/arm/boards/guf-neso/board.c
index c4b2fa11d5..446b333f1f 100644
--- a/arch/arm/boards/guf-neso/board.c
+++ b/arch/arm/boards/guf-neso/board.c
@@ -54,19 +54,6 @@
 #define LCD_POWER_GPIO (GPIO_PORTF + 18)
 #define BACKLIGHT_POWER_GPIO (GPIO_PORTE + 5)
 
-static struct memory_platform_data ram_pdata = {
-	.name = "ram0",
-	.flags = DEVFS_RDWR,
-};
-
-static struct device_d sdram_dev = {
-	.id	  = -1,
-	.name     = "mem",
-	.map_base = 0xa0000000,
-	.size     = 128 * 1024 * 1024,
-	.platform_data = &ram_pdata,
-};
-
 static struct fec_platform_data fec_info = {
 	.xcv_type = MII100,
 	.phy_addr = 31,
@@ -127,14 +114,6 @@ static struct imx_fb_platform_data neso_fb_data = {
 };
 
 #ifdef CONFIG_USB
-
-static struct device_d usbh2_dev = {
-	.id	  = -1,
-	.name     = "ehci",
-	.map_base = IMX_OTG_BASE + 0x400,
-	.size     = 0x200,
-};
-
 static void neso_usbh_init(void)
 {
 	uint32_t temp;
@@ -157,23 +136,13 @@ static void neso_usbh_init(void)
 }
 #endif
 
-#ifdef CONFIG_MMU
-static void neso_mmu_init(void)
+static int neso_mem_init(void)
 {
-	mmu_init();
-
-	arm_create_section(0xa0000000, 0xa0000000, 128, PMD_SECT_DEF_CACHED);
-	arm_create_section(0xb0000000, 0xa0000000, 128, PMD_SECT_DEF_UNCACHED);
+	arm_add_mem_device("ram0", 0xa0000000, 128 * 1024 * 1024);
 
-	setup_dma_coherent(0x10000000);
-
-	mmu_enable();
-}
-#else
-static void neso_mmu_init(void)
-{
+	return 0;
 }
-#endif
+mem_initcall(neso_mem_init);
 
 static int neso_devices_init(void)
 {
@@ -301,20 +270,16 @@ static int neso_devices_init(void)
 	gpio_direction_output(OTG_PHY_CS_GPIO, 1);
 	gpio_direction_output(USBH2_PHY_CS_GPIO, 1);
 
-
-	neso_mmu_init();
-
 	/* initialize gpios */
 	for (i = 0; i < ARRAY_SIZE(mode); i++)
 		imx_gpio_mode(mode[i]);
 
 	imx27_add_nand(&nand_info);
-	register_device(&sdram_dev);
 	imx27_add_fb(&neso_fb_data);
 
 #ifdef CONFIG_USB
 	neso_usbh_init();
-	register_device(&usbh2_dev);
+	add_generic_usb_ehci_device(-1, IMX_OTG_BASE + 0x400, NULL);
 #endif
 
 	imx27_add_fec(&fec_info);
@@ -325,7 +290,6 @@ static int neso_devices_init(void)
 	devfs_add_partition("nand0", 0x40000, 0x80000, PARTITION_FIXED, "env_raw");
 	dev_add_bb_dev("env_raw", "env0");
 
-	armlinux_add_dram(&sdram_dev);
 	armlinux_set_bootparams((void *)0xa0000100);
 	armlinux_set_architecture(MACH_TYPE_NESO);
 
diff --git a/arch/arm/boards/imx21ads/imx21ads.c b/arch/arm/boards/imx21ads/imx21ads.c
index 394258154d..d58831e748 100644
--- a/arch/arm/boards/imx21ads/imx21ads.c
+++ b/arch/arm/boards/imx21ads/imx21ads.c
@@ -41,38 +41,11 @@
 #define MX21ADS_IO_REG    0xCC800000
 #define MX21ADS_IO_LCDON  (1 << 9)
 
-static struct device_d cfi_dev = {
-	.id	  = -1,
-	.name     = "cfi_flash",
-	.map_base = 0xC8000000,
-	.size     = 32 * 1024 * 1024,
-};
-
-static struct memory_platform_data ram_pdata = {
-	.name = "ram0",
-	.flags = DEVFS_RDWR,
-};
-
-static struct device_d sdram_dev = {
-	.id	  = -1,
-	.name     = "mem",
-	.map_base = 0xc0000000,
-	.size     = 64 * 1024 * 1024,
-	.platform_data = &ram_pdata,
-};
-
 struct imx_nand_platform_data nand_info = {
 	.width = 1,
 	.hw_ecc = 1,
 };
 
-static struct device_d cs8900_dev = {
-	.id	  = -1,
-	.name     = "cs8900",
-	.map_base = IMX_CS1_BASE,
-	// IRQ is connected to UART3_RTS
-};
-
 /* Sharp LQ035Q7DB02 QVGA display */
 static struct imx_fb_videomode imx_fb_modedata = {
         .mode = {
@@ -142,6 +115,14 @@ static int imx21ads_timing_init(void)
 
 core_initcall(imx21ads_timing_init);
 
+static int mx21ads_mem_init(void)
+{
+	arm_add_mem_device("ram0", 0xc0000000, 64 * 1024 * 1024);
+
+	return 0;
+}
+mem_initcall(mx21ads_mem_init);
+
 static int mx21ads_devices_init(void)
 {
 	int i;
@@ -183,13 +164,12 @@ static int mx21ads_devices_init(void)
 	for (i = 0; i < ARRAY_SIZE(mode); i++)
 		imx_gpio_mode(mode[i]);
 
-	register_device(&cfi_dev);
-	register_device(&sdram_dev);
+	add_cfi_flash_device(-1, 0xC8000000, 32 * 1024 * 1024, 0);
 	imx21_add_nand(&nand_info);
-	register_device(&cs8900_dev);
+	add_generic_device("cs8900", -1, NULL,	IMX_CS1_BASE, 0x1000,
+			IORESOURCE_MEM, NULL);
 	imx21_add_fb(&imx_fb_data);
 
-	armlinux_add_dram(&sdram_dev);
 	armlinux_set_bootparams((void *)0xc0000100);
 	armlinux_set_architecture(MACH_TYPE_MX21ADS);
 
diff --git a/arch/arm/boards/imx27ads/imx27ads.c b/arch/arm/boards/imx27ads/imx27ads.c
index 0d433c12e8..da4260fa58 100644
--- a/arch/arm/boards/imx27ads/imx27ads.c
+++ b/arch/arm/boards/imx27ads/imx27ads.c
@@ -34,26 +34,6 @@
 #include <mach/iomux-mx27.h>
 #include <mach/devices-imx27.h>
 
-static struct device_d cfi_dev = {
-	.id	  = -1,
-	.name     = "cfi_flash",
-	.map_base = 0xC0000000,
-	.size     = 32 * 1024 * 1024,
-};
-
-static struct memory_platform_data ram_pdata = {
-	.name = "ram0",
-	.flags = DEVFS_RDWR,
-};
-
-static struct device_d sdram_dev = {
-	.id	  = -1,
-	.name     = "mem",
-	.map_base = 0xa0000000,
-	.size     = 128 * 1024 * 1024,
-	.platform_data = &ram_pdata,
-};
-
 static struct fec_platform_data fec_info = {
 	.xcv_type = MII100,
 	.phy_addr = 1,
@@ -94,6 +74,14 @@ static int imx27ads_timing_init(void)
 
 core_initcall(imx27ads_timing_init);
 
+static int mx27ads_mem_init(void)
+{
+	arm_add_mem_device("ram0", 0xa0000000, 128 * 1024 * 1024);
+
+	return 0;
+}
+mem_initcall(mx27ads_mem_init);
+
 static int mx27ads_devices_init(void)
 {
 	int i;
@@ -126,15 +114,13 @@ static int mx27ads_devices_init(void)
 	for (i = 0; i < ARRAY_SIZE(mode); i++)
 		imx_gpio_mode(mode[i]);
 
-	register_device(&cfi_dev);
-	register_device(&sdram_dev);
-	imx27_add_fec(&fec_info);
+	add_cfi_flash_device(-1, 0xC0000000, 32 * 1024 * 1024, 0);
 
+	imx27_add_fec(&fec_info);
 	devfs_add_partition("nor0", 0x00000, 0x20000, PARTITION_FIXED, "self0");
 	devfs_add_partition("nor0", 0x20000, 0x20000, PARTITION_FIXED, "env0");
 	protect_file("/dev/env0", 1);
 
-	armlinux_add_dram(&sdram_dev);
 	armlinux_set_bootparams((void *)0xa0000100);
 	armlinux_set_architecture(MACH_TYPE_MX27ADS);
 
diff --git a/arch/arm/boards/karo-tx25/board.c b/arch/arm/boards/karo-tx25/board.c
index c59a9faac4..22bc27a291 100644
--- a/arch/arm/boards/karo-tx25/board.c
+++ b/arch/arm/boards/karo-tx25/board.c
@@ -36,6 +36,7 @@
 #include <nand.h>
 #include <mach/iomux-mx25.h>
 #include <mach/generic.h>
+#include <mach/iim.h>
 #include <linux/err.h>
 #include <mach/devices-imx25.h>
 #include <asm/mmu.h>
@@ -45,74 +46,22 @@ static struct fec_platform_data fec_info = {
 	.phy_addr	= 0x1f,
 };
 
-static struct memory_platform_data sdram0_pdata = {
-	.name	= "ram0",
-	.flags	= DEVFS_RDWR,
-};
-
-static struct device_d sdram0_dev = {
-	.id	  = -1,
-	.name     = "mem",
-	.map_base = IMX_SDRAM_CS0,
-	.size     = 32 * 1024 * 1024,
-	.platform_data = &sdram0_pdata,
-};
-
-static struct memory_platform_data sdram1_pdata = {
-	.name	= "ram1",
-	.flags	= DEVFS_RDWR,
-};
-
-static struct device_d sdram1_dev = {
-	.id	  = -1,
-	.name     = "mem",
-	.map_base = IMX_SDRAM_CS1,
-	.size     = 32 * 1024 * 1024,
-	.platform_data = &sdram1_pdata,
-};
-
-static struct memory_platform_data sram_pdata = {
-	.name	= "sram0",
-	.flags	= DEVFS_RDWR,
-};
-
-static struct device_d sram0_dev = {
-	.id	  = -1,
-	.name     = "mem",
-	.map_base = 0x78000000,
-	.size     = 128 * 1024,
-	.platform_data = &sram_pdata,
-};
-
 struct imx_nand_platform_data nand_info = {
 	.width	= 1,
 	.hw_ecc	= 1,
 	.flash_bbt = 1,
 };
 
-#ifdef CONFIG_MMU
-static int tx25_mmu_init(void)
+static int tx25_mem_init(void)
 {
-	mmu_init();
-
-	arm_create_section(0x80000000, 0x80000000, 32, PMD_SECT_DEF_CACHED);
-	arm_create_section(0x82000000, 0x80000000, 32, PMD_SECT_DEF_UNCACHED);
-	arm_create_section(0x90000000, 0x90000000, 32, PMD_SECT_DEF_CACHED);
-	arm_create_section(0x92000000, 0x90000000, 32, PMD_SECT_DEF_UNCACHED);
-
-	setup_dma_coherent(0x02000000);
-
-#if TEXT_BASE & (0x100000 - 1)
-#warning cannot create vector section. Adjust TEXT_BASE to a 1M boundary
-#else
-	arm_create_section(0x0,        TEXT_BASE,   1, PMD_SECT_DEF_UNCACHED);
-#endif
-	mmu_enable();
+	arm_add_mem_device("ram0", IMX_SDRAM_CS0, 32 * 1024 * 1024);
+	arm_add_mem_device("ram0", IMX_SDRAM_CS1, 32 * 1024 * 1024);
+	add_mem_device("ram0", 0x78000000, 128 * 1024,
+				   IORESOURCE_MEM_WRITEABLE);
 
 	return 0;
 }
-postcore_initcall(tx25_mmu_init);
-#endif
+mem_initcall(tx25_mem_init);
 
 static struct pad_desc karo_tx25_padsd_fec[] = {
 	MX25_PAD_D11__GPIO_4_9,		/* FEC PHY power on pin */
@@ -158,6 +107,7 @@ static int tx25_devices_init(void)
 {
 	gpio_fec_active();
 
+	imx25_iim_register_fec_ethaddr();
 	imx25_add_fec(&fec_info);
 
 	if (readl(IMX_CCM_BASE + CCM_RCSR) & (1 << 14))
@@ -171,12 +121,6 @@ static int tx25_devices_init(void)
 	devfs_add_partition("nand0", 0x40000, 0x80000, PARTITION_FIXED, "env_raw");
 	dev_add_bb_dev("env_raw", "env0");
 
-	register_device(&sdram0_dev);
-	register_device(&sdram1_dev);
-	register_device(&sram0_dev);
-
-	armlinux_add_dram(&sdram0_dev);
-	armlinux_add_dram(&sdram1_dev);
 	armlinux_set_bootparams((void *)0x80000100);
 	armlinux_set_architecture(MACH_TYPE_TX25);
 	armlinux_set_serial(imx_uid());
diff --git a/arch/arm/boards/karo-tx28/tx28-stk5.c b/arch/arm/boards/karo-tx28/tx28-stk5.c
index 81cb80c7e0..8427dc2391 100644
--- a/arch/arm/boards/karo-tx28/tx28-stk5.c
+++ b/arch/arm/boards/karo-tx28/tx28-stk5.c
@@ -35,24 +35,12 @@ static struct mxs_mci_platform_data mci_pdata = {
 	.f_max = 25000000,
 };
 
-static struct device_d mci_socket = {
-	.name = "mxs_mci",
-	.map_base = IMX_SSP0_BASE,
-	.platform_data = &mci_pdata,
-};
-
 /* PhyAD[0..2]=0, RMIISEL=1 */
 static struct fec_platform_data fec_info = {
 	.xcv_type = RMII,
 	.phy_addr = 0,
 };
 
-static struct device_d fec_dev = {
-	.name = "fec_imx",
-	.map_base = IMX_FEC0_BASE,
-	.platform_data = &fec_info,
-};
-
 /*
  * The TX28 EVK comes with a VGA connector. We can support many video modes
  *
@@ -215,13 +203,6 @@ static struct imx_fb_platformdata tx28_fb_pdata = {
 	.enable = tx28_fb_enable,
 };
 
-static struct device_d ldcif_dev = {
-	.name = "stmfb",
-	.map_base = IMX_FB_BASE,
-	.size = 4096,
-	.platform_data = &tx28_fb_pdata,
-};
-
 static const uint32_t tx28_starterkit_pad_setup[] = {
 	/*
 	 * Part II of phy's initialization
@@ -378,17 +359,20 @@ void base_board_init(void)
 	/* run the SSP unit clock at 100 MHz */
 	imx_set_sspclk(0, 100000000, 1);
 
-	register_device(&mci_socket);
+	add_generic_device("mxs_mci", 0, NULL, IMX_SSP0_BASE, 0,
+			   IORESOURCE_MEM, &mci_pdata);
 
 	if (tx28_fb_pdata.fixed_screen < (void *)&_end) {
 		printf("Warning: fixed_screen overlaps barebox\n");
 		tx28_fb_pdata.fixed_screen = NULL;
 	}
 
-	register_device(&ldcif_dev);
+	add_generic_device("stmfb", 0, NULL, IMX_FB_BASE, 4096,
+			   IORESOURCE_MEM, &tx28_fb_pdata);
 
 	imx_enable_enetclk();
-	register_device(&fec_dev);
+	add_generic_device("fec_imx", 0, NULL, IMX_FEC0_BASE, 0,
+			   IORESOURCE_MEM, &fec_info);
 
 	ret = register_persistent_environment();
 	if (ret != 0)
@@ -396,15 +380,12 @@ void base_board_init(void)
 				"storage (%d)\n", ret);
 }
 
-static struct device_d tx28kit_serial_device = {
-	.name     = "stm_serial",
-	.map_base = IMX_DBGUART_BASE,
-	.size     = 8192,
-};
-
 static int tx28kit_console_init(void)
 {
-	return register_device(&tx28kit_serial_device);
+	add_generic_device("stm_serial", 0, NULL, IMX_DBGUART_BASE, 8192,
+			   IORESOURCE_MEM, NULL);
+	
+	return 0;
 }
 
 console_initcall(tx28kit_console_init);
diff --git a/arch/arm/boards/karo-tx28/tx28.c b/arch/arm/boards/karo-tx28/tx28.c
index 1f47a8d30f..def388a8d9 100644
--- a/arch/arm/boards/karo-tx28/tx28.c
+++ b/arch/arm/boards/karo-tx28/tx28.c
@@ -23,19 +23,6 @@
 #include <mach/imx-regs.h>
 #include <asm/mmu.h>
 
-static struct memory_platform_data ram_pdata = {
-	.name = "ram0",
-	.flags = DEVFS_RDWR,
-};
-
-static struct device_d sdram_dev = {
-	.id = -1,
-	.name = "mem",
-	.map_base = IMX_MEMORY_BASE,
-	.size = 128 * 1024 * 1024,
-	.platform_data = &ram_pdata,
-};
-
 /* setup the CPU card internal signals */
 static const uint32_t tx28_pad_setup[] = {
 	/* NAND interface */
@@ -83,22 +70,13 @@ static const uint32_t tx28_pad_setup[] = {
 
 extern void base_board_init(void);
 
-#ifdef CONFIG_MMU
-static int tx28_mmu_init(void)
+static int tx28_mem_init(void)
 {
-	mmu_init();
-
-	arm_create_section(0x40000000, 0x40000000, 128, PMD_SECT_DEF_CACHED);
-	arm_create_section(0x50000000, 0x40000000, 128, PMD_SECT_DEF_UNCACHED);
-
-	setup_dma_coherent(0x10000000);
-
-	mmu_enable();
+	arm_add_mem_device("ram0", IMX_MEMORY_BASE, 128 * 1024 * 1024);
 
 	return 0;
 }
-postcore_initcall(tx28_mmu_init);
-#endif
+mem_initcall(tx28_mem_init);
 
 static int tx28_devices_init(void)
 {
@@ -108,10 +86,7 @@ static int tx28_devices_init(void)
 	for (i = 0; i < ARRAY_SIZE(tx28_pad_setup); i++)
 		imx_gpio_mode(tx28_pad_setup[i]);
 
-	register_device(&sdram_dev);
-
-	armlinux_add_dram(&sdram_dev);
-	armlinux_set_bootparams((void *)(sdram_dev.map_base + 0x100));
+	armlinux_set_bootparams((void *)IMX_MEMORY_BASE + 0x100);
 	armlinux_set_architecture(MACH_TYPE_TX28);
 
 	base_board_init();
diff --git a/arch/arm/boards/mini2440/mini2440.c b/arch/arm/boards/mini2440/mini2440.c
index dcc7c3f8a4..fd1f2f27c3 100644
--- a/arch/arm/boards/mini2440/mini2440.c
+++ b/arch/arm/boards/mini2440/mini2440.c
@@ -44,29 +44,11 @@
 #include <mach/mci.h>
 #include <mach/fb.h>
 
-static struct memory_platform_data ram_pdata = {
-	.name		= "ram0",
-	.flags		= DEVFS_RDWR,
-};
-
-static struct device_d sdram_dev = {
-	.id		= -1,
-	.name		= "mem",
-	.map_base	= CS6_BASE,
-	.platform_data	= &ram_pdata,
-};
-
 static struct s3c24x0_nand_platform_data nand_info = {
 	.nand_timing = CALC_NFCONF_TIMING(A9M2440_TACLS, A9M2440_TWRPH0, A9M2440_TWRPH1),
 	.flash_bbt = 1,	/* same as the kernel */
 };
 
-static struct device_d nand_dev = {
-	.name     = "s3c24x0_nand",
-	.map_base = S3C24X0_NAND_BASE,
-	.platform_data	= &nand_info,
-};
-
 /*
  * dm9000 network controller onboard
  * Connected to CS line 4 and interrupt line EINT7,
@@ -75,19 +57,9 @@ static struct device_d nand_dev = {
  * Area 2: Offset 0x304...0x307
  */
 static struct dm9000_platform_data dm9000_data = {
-	.iobase   = CS4_BASE + 0x300,
-	.iodata   = CS4_BASE + 0x304,
-	.buswidth = DM9000_WIDTH_16,
 	.srom     = 1,
 };
 
-static struct device_d dm9000_dev = {
-	.name     = "dm9000",
-	.map_base = CS4_BASE + 0x300,
-	.size     = 8,
-	.platform_data = &dm9000_data,
-};
-
 static struct s3c_mci_platform_data mci_data = {
 	.caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz,
 	.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
@@ -95,12 +67,6 @@ static struct s3c_mci_platform_data mci_data = {
 	.detect_invert = 0,
 };
 
-static struct device_d mci_dev = {
-	.name     = "s3c_mci",
-	.map_base = S3C2410_SDI_BASE,
-	.platform_data	= &mci_data,
-};
-
 static struct fb_videomode s3c24x0_fb_modes[] = {
 #ifdef CONFIG_MINI2440_VIDEO_N35
 	{
@@ -166,12 +132,6 @@ static struct s3c_fb_platform_data s3c24x0_fb_data = {
 	.passive_display	= 0,
 };
 
-static struct device_d s3cfb_dev = {
-	.name    = "s3c_fb",
-	.map_base = S3C2410_LCD_BASE,
-	.platform_data	= &s3c24x0_fb_data,
-};
-
 static const unsigned pin_usage[] = {
 	/* address bus, used by NOR, SDRAM */
 	GPA1_ADDR16,
@@ -303,13 +263,19 @@ static const unsigned pin_usage[] = {
 	GPH7_RXD2,
 };
 
+static int mini2440_mem_init(void)
+{
+	arm_add_mem_device("ram0", CS6_BASE, s3c24x0_get_memory_size());
+
+	return 0;
+}
+mem_initcall(mini2440_mem_init);
+
 static int mini2440_devices_init(void)
 {
 	uint32_t reg;
 	int i;
 
-	sdram_dev.size = s3c24x0_get_memory_size();
-
 	/* ----------- configure the access to the outer space ---------- */
 	for (i = 0; i < ARRAY_SIZE(pin_usage); i++)
 		s3c_gpio_mode(pin_usage[i]);
@@ -328,9 +294,11 @@ static int mini2440_devices_init(void)
 	reg |= 0x10000;
 	writel(reg, MISCCR);
 
-	register_device(&nand_dev);
-	register_device(&sdram_dev);
-	register_device(&dm9000_dev);
+	add_generic_device("s3c24x0_nand", -1, NULL, S3C24X0_NAND_BASE, 0,
+			   IORESOURCE_MEM, &nand_info);
+
+	add_dm9000_device(0, CS4_BASE + 0x300, CS4_BASE + 0x304,
+			  IORESOURCE_MEM_16BIT, &dm9000_data);
 #ifdef CONFIG_NAND
 	/* ----------- add some vital partitions -------- */
 	devfs_del_partition("self_raw");
@@ -341,10 +309,11 @@ static int mini2440_devices_init(void)
 	devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
 	dev_add_bb_dev("env_raw", "env0");
 #endif
-	register_device(&mci_dev);
-	register_device(&s3cfb_dev);
-	armlinux_add_dram(&sdram_dev);
-	armlinux_set_bootparams((void *)sdram_dev.map_base + 0x100);
+	add_generic_device("s3c_mci", 0, NULL, S3C2410_SDI_BASE, 0,
+			   IORESOURCE_MEM, &mci_data);
+	add_generic_device("s3c_fb", 0, NULL, S3C2410_LCD_BASE, 0,
+			   IORESOURCE_MEM, &s3c24x0_fb_data);
+	armlinux_set_bootparams((void*)CS6_BASE + 0x100);
 	armlinux_set_architecture(MACH_TYPE_MINI2440);
 
 	return 0;
@@ -359,12 +328,6 @@ void __bare_init nand_boot(void)
 }
 #endif
 
-static struct device_d mini2440_serial_device = {
-	.name     = "s3c24x0_serial",
-	.map_base = UART1_BASE,
-	.size     = UART1_SIZE,
-};
-
 static int mini2440_console_init(void)
 {
 	/*
@@ -376,7 +339,8 @@ static int mini2440_console_init(void)
 	s3c_gpio_mode(GPH2_TXD0);
 	s3c_gpio_mode(GPH3_RXD0);
 
-	register_device(&mini2440_serial_device);
+	add_generic_device("s3c24x0_serial", -1, NULL, UART1_BASE, UART1_SIZE,
+			   IORESOURCE_MEM, NULL);
 	return 0;
 }
 
diff --git a/arch/arm/boards/mmccpu/init.c b/arch/arm/boards/mmccpu/init.c
index 7cba01c4f0..36bc193bfc 100644
--- a/arch/arm/boards/mmccpu/init.c
+++ b/arch/arm/boards/mmccpu/init.c
@@ -37,18 +37,19 @@
 #include <mach/gpio.h>
 #include <mach/io.h>
 
-static struct device_d cfi_dev = {
-	.id		= -1,
-	.name		= "cfi_flash",
-	.map_base	= AT91_CHIPSELECT_0,
-	.size		= 0,	/* zero means autodetect size */
-};
-
 static struct at91_ether_platform_data macb_pdata = {
 	.flags		= AT91SAM_ETHER_MII | AT91SAM_ETHER_FORCE_LINK,
 	.phy_addr	= 4,
 };
 
+static int mmccpu_mem_init(void)
+{
+	at91_add_device_sdram(128 * 1024 * 1024);
+
+	return 0;
+}
+mem_initcall(mmccpu_mem_init);
+
 static int mmccpu_devices_init(void)
 {
 	/*
@@ -59,9 +60,8 @@ static int mmccpu_devices_init(void)
 	at91_set_gpio_output(AT91_PIN_PB27, 1);
 	at91_set_gpio_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */
 
-	at91_add_device_sdram(128 * 1024 * 1024);
 	at91_add_device_eth(&macb_pdata);
-	register_device(&cfi_dev);
+	add_cfi_flash_device(0, AT91_CHIPSELECT_0, 0, 0);
 
 	devfs_add_partition("nor0", 0x00000, 256 * 1024, PARTITION_FIXED, "self0");
 	devfs_add_partition("nor0", 0x40000, 128 * 1024, PARTITION_FIXED, "env0");
diff --git a/arch/arm/boards/netx/netx.c b/arch/arm/boards/netx/netx.c
index c735d26bc4..92d2911e68 100644
--- a/arch/arm/boards/netx/netx.c
+++ b/arch/arm/boards/netx/netx.c
@@ -30,51 +30,27 @@
 #include <generated/mach-types.h>
 #include <mach/netx-eth.h>
 
-static struct device_d cfi_dev = {
-	.id	  = -1,
-	.name     = "cfi_flash",
-	.map_base = 0xC0000000,
-	.size     = 32 * 1024 * 1024,
-};
-
-static struct memory_platform_data ram_pdata = {
-	.name = "ram0",
-	.flags = DEVFS_RDWR,
-};
-
-static struct device_d sdram_dev = {
-	.id	  = -1,
-	.name     = "mem",
-	.map_base = 0x80000000,
-	.size     = 64 * 1024 * 1024,
-	.platform_data = &ram_pdata,
-};
-
 struct netx_eth_platform_data eth0_data = {
 	.xcno = 0,
 };
 
-static struct device_d netx_eth_dev0 = {
-	.id		= -1,
-	.name		= "netx-eth",
-	.platform_data	= &eth0_data,
-};
-
 struct netx_eth_platform_data eth1_data = {
 	.xcno = 1,
 };
 
-static struct device_d netx_eth_dev1 = {
-	.id		= -1,
-	.name		= "netx-eth",
-	.platform_data	= &eth1_data,
-};
+static int netx_mem_init(void)
+{
+	arm_add_mem_device("ram0", 0x80000000, 64 * 1024 * 1024);
+
+	return 0;
+}
+mem_initcall(netx_mem_init);
 
 static int netx_devices_init(void) {
-	register_device(&cfi_dev);
-	register_device(&sdram_dev);
-	register_device(&netx_eth_dev0);
-	register_device(&netx_eth_dev1);
+	add_cfi_flash_device(-1, 0xC0000000, 32 * 1024 * 1024, 0);
+
+	add_generic_device("netx-eth", -1, NULL, 0, 0, IORESOURCE_MEM, &eth0_data);
+	add_generic_device("netx-eth", -1, NULL, 0, 0, IORESOURCE_MEM, &eth1_data);
 
 	devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
 
@@ -83,7 +59,6 @@ static int netx_devices_init(void) {
 
 	protect_file("/dev/env0", 1);
 
-	armlinux_add_dram(&sdram_dev);
 	armlinux_set_bootparams((void *)0x80000100);
 	armlinux_set_architecture(MACH_TYPE_NXDB500);
 
@@ -92,13 +67,6 @@ static int netx_devices_init(void) {
 
 device_initcall(netx_devices_init);
 
-static struct device_d netx_serial_device = {
-	.id	  = -1,
-	.name     = "netx_serial",
-	.map_base = NETX_PA_UART0,
-	.size     = 0x40,
-};
-
 static int netx_console_init(void)
 {
 	/* configure gpio for serial */
@@ -107,7 +75,8 @@ static int netx_console_init(void)
 	*(volatile unsigned long *)(0x00100808) = 2;
 	*(volatile unsigned long *)(0x0010080c) = 2;
 
-	register_device(&netx_serial_device);
+	add_generic_device("netx_serial", -1, NULL, NETX_PA_UART0, 0x40,
+			   IORESOURCE_MEM, NULL);
 	return 0;
 }
 
diff --git a/arch/arm/boards/nhk8815/setup.c b/arch/arm/boards/nhk8815/setup.c
index 9cb0fd0494..dcf716620d 100644
--- a/arch/arm/boards/nhk8815/setup.c
+++ b/arch/arm/boards/nhk8815/setup.c
@@ -33,13 +33,6 @@
 #include <mach/nand.h>
 #include <mach/fsmc.h>
 
-static struct device_d nhk8815_network_dev = {
-	.id = -1,
-	.name = "smc91c111",
-	.map_base = 0x34000300,
-	.size = 16,
-};
-
 static int nhk8815_nand_init(void)
 {
 	/* FSMC setup for nand chip select (8-bit nand in 8815NHK) */
@@ -54,24 +47,45 @@ static int nhk8815_nand_init(void)
 }
 
 static struct nomadik_nand_platform_data nhk8815_nand_data = {
-	.addr_va	= NAND_IO_ADDR,
-	.cmd_va		= NAND_IO_CMD,
-	.data_va	= NAND_IO_DATA,
 	.options	= NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING \
 			| NAND_NO_READRDY | NAND_NO_AUTOINCR,
 	.init		= nhk8815_nand_init,
 };
 
+static struct resource nhk8815_nand_resources[] = {
+	{
+		.start	= NAND_IO_ADDR,
+		.size	= 0xfff,
+		.flags	= IORESOURCE_MEM,
+	}, {
+		.start	= NAND_IO_CMD,
+		.size	= 0xfff,
+		.flags	= IORESOURCE_MEM,
+	}, {
+		.start	= NAND_IO_DATA,
+		.size	= 0xfff,
+		.flags	= IORESOURCE_MEM,
+	}
+};
+
 static struct device_d nhk8815_nand_device = {
 	.id		= -1,
 	.name		= "nomadik_nand",
+	.num_resources	= ARRAY_SIZE(nhk8815_nand_resources),
+	.resource	= nhk8815_nand_resources,
 	.platform_data	= &nhk8815_nand_data,
 };
 
-static int nhk8815_devices_init(void)
+static int nhk8815_mem_init(void)
 {
 	st8815_add_device_sdram(64 * 1024 *1024);
 
+	return 0;
+}
+mem_initcall(nhk8815_mem_init);
+
+static int nhk8815_devices_init(void)
+{
 	writel(0xC37800F0, NOMADIK_GPIO1_BASE + 0x20);
 	writel(0x00000000, NOMADIK_GPIO1_BASE + 0x24);
 	writel(0x00000000, NOMADIK_GPIO1_BASE + 0x28);
@@ -81,7 +95,8 @@ static int nhk8815_devices_init(void)
 	writel(0x0000305b, FSMC_BCR(1));
 	writel(0x00033f33, FSMC_BTR(1));
 
-	register_device(&nhk8815_network_dev);
+	add_generic_device("smc91c111", -1, NULL, 0x34000300, 16,
+			   IORESOURCE_MEM, NULL);
 
 	register_device(&nhk8815_nand_device);
 
diff --git a/arch/arm/boards/omap/board-beagle.c b/arch/arm/boards/omap/board-beagle.c
index ced3df742d..49af40cf75 100644
--- a/arch/arm/boards/omap/board-beagle.c
+++ b/arch/arm/boards/omap/board-beagle.c
@@ -237,17 +237,6 @@ void board_init(void)
 
 static struct NS16550_plat serial_plat = {
 	.clock = 48000000,      /* 48MHz (APLL96/2) */
-	.f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR,
-	.reg_read = omap_uart_read,
-	.reg_write = omap_uart_write,
-};
-
-static struct device_d beagle_serial_device = {
-	.id = -1,
-	.name = "serial_ns16550",
-	.map_base = OMAP_UART3_BASE,
-	.size = 1024,
-	.platform_data = (void *)&serial_plat,
 };
 
 /**
@@ -259,24 +248,14 @@ static struct device_d beagle_serial_device = {
 static int beagle_console_init(void)
 {
 	/* Register the serial port */
-	return register_device(&beagle_serial_device);
+	add_ns16550_device(-1, OMAP_UART3_BASE, 1024, IORESOURCE_MEM_8BIT,
+			   &serial_plat);
+
+	return 0;
 }
 console_initcall(beagle_console_init);
 #endif /* CONFIG_DRIVER_SERIAL_NS16550 */
 
-static struct memory_platform_data sram_pdata = {
-	.name = "ram0",
-	.flags = DEVFS_RDWR,
-};
-
-static struct device_d sdram_dev = {
-	.id = -1,
-	.name = "mem",
-	.map_base = 0x80000000,
-	.size = 128 * 1024 * 1024,
-	.platform_data = &sram_pdata,
-};
-
 #ifdef CONFIG_USB_EHCI_OMAP
 static struct omap_hcd omap_ehci_pdata = {
 	.port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
@@ -290,52 +269,33 @@ static struct omap_hcd omap_ehci_pdata = {
 
 static struct ehci_platform_data ehci_pdata = {
 	.flags = 0,
-	.hccr_offset = 0x100,
-	.hcor_offset = 0x110,
-};
-
-static struct device_d usbh_dev = {
-	.id	  = -1,
-	.name     = "ehci",
-	.map_base = 0x48064700,
-	.size     = 4 * 1024,
-	.platform_data = &ehci_pdata,
 };
 #endif /* CONFIG_USB_EHCI_OMAP */
 
-static struct device_d i2c_dev = {
-	.id		= -1,
-	.name		= "i2c-omap",
-	.map_base	= OMAP_I2C1_BASE,
-};
-
 static struct i2c_board_info i2c_devices[] = {
 	{
 		I2C_BOARD_INFO("twl4030", 0x48),
 	},
 };
 
-static struct device_d hsmmc_dev = {
-	.id = -1,
-	.name = "omap-hsmmc",
-	.map_base = 0x4809C000,
-	.size = SZ_4K,
-};
-
-static int beagle_devices_init(void)
+static int beagle_mem_init(void)
 {
-	int ret;
+	arm_add_mem_device("ram0", 0x80000000, 128 * 1024 * 1024);
 
-	ret = register_device(&sdram_dev);
-	if (ret)
-		goto failed;
+	return 0;
+}
+mem_initcall(beagle_mem_init);
 
+static int beagle_devices_init(void)
+{
 	i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
-	register_device(&i2c_dev);
+	add_generic_device("i2c-omap", -1, NULL, 0x4809C000, SZ_4K,
+			   IORESOURCE_MEM, NULL);
 
 #ifdef CONFIG_USB_EHCI_OMAP
 	if (ehci_omap_init(&omap_ehci_pdata) >= 0)
-		register_device(&usbh_dev);
+		add_usb_ehci_device(-1, 0x48064700 + 0x100,
+				    0x48064700 + 0x110, &ehci_pdata);
 #endif /* CONFIG_USB_EHCI_OMAP */
 #ifdef CONFIG_GPMC
 	/* WP is made high and WAIT1 active Low */
@@ -343,13 +303,13 @@ static int beagle_devices_init(void)
 #endif
 	gpmc_generic_nand_devices_init(0, 16, OMAP_ECC_HAMMING_CODE_HW_ROMCODE);
 
-	register_device(&hsmmc_dev);
+	add_generic_device("omap-hsmmc", -1, NULL, OMAP_I2C1_BASE, 0,
+			   IORESOURCE_MEM, NULL);
 
-	armlinux_add_dram(&sdram_dev);
 	armlinux_set_bootparams((void *)0x80000100);
 	armlinux_set_architecture(MACH_TYPE_OMAP3_BEAGLE);
-failed:
-	return ret;
+
+	return 0;
 }
 device_initcall(beagle_devices_init);
 
diff --git a/arch/arm/boards/omap/board-omap3evm.c b/arch/arm/boards/omap/board-omap3evm.c
index c37f1519ff..a2532d5c02 100644
--- a/arch/arm/boards/omap/board-omap3evm.c
+++ b/arch/arm/boards/omap/board-omap3evm.c
@@ -58,6 +58,7 @@
 #include <mach/control.h>
 #include <mach/omap3-mux.h>
 #include <mach/gpmc.h>
+#include <errno.h>
 #include "board.h"
 
 
@@ -212,21 +213,6 @@ void board_init(void)
 
 static struct NS16550_plat serial_plat = {
 	.clock		= 48000000,      /* 48MHz (APLL96/2) */
-	.f_caps		= CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR,
-	.reg_read	= omap_uart_read,
-	.reg_write	= omap_uart_write,
-};
-
-static struct device_d omap3evm_serial_device = {
-	.id		= -1,
-	.name		= "serial_ns16550",
-#if defined(CONFIG_OMAP3EVM_UART1)
-	.map_base	= OMAP_UART1_BASE,
-#elif defined(CONFIG_OMAP3EVM_UART3)
-	.map_base	= OMAP_UART3_BASE,
-#endif
-	.size		= 1024,
-	.platform_data	= (void *)&serial_plat,
 };
 
 /**
@@ -236,42 +222,35 @@ static struct device_d omap3evm_serial_device = {
  */
 static int omap3evm_init_console(void)
 {
-	return register_device(&omap3evm_serial_device);
+	add_ns16550_device(-1,
+#if defined(CONFIG_OMAP3EVM_UART1)
+			OMAP_UART1_BASE,
+#elif defined(CONFIG_OMAP3EVM_UART3)
+			OMAP_UART3_BASE,
+#endif
+			1024, IORESOURCE_MEM_8BIT, &serial_plat);
+
+	return 0;
 }
 console_initcall(omap3evm_init_console);
 #endif /* CONFIG_DRIVER_SERIAL_NS16550 */
 
-static struct memory_platform_data sram_pdata = {
-	.name	= "ram0",
-	.flags	= DEVFS_RDWR,
-};
+static int omap3evm_mem_init(void)
+{
+	arm_add_mem_device("ram0", 0x80000000, 128 * 1024 * 1024);
 
-static struct device_d sdram_dev = {
-	.id		= -1,
-	.name		= "mem",
-	.map_base	= 0x80000000,
-	.size		= 128 * 1024 * 1024,
-	.platform_data	= &sram_pdata,
-};
+	return 0;
+}
+mem_initcall(omap3evm_mem_init);
 
 static int omap3evm_init_devices(void)
 {
-	int ret;
-
-	ret = register_device(&sdram_dev);
-	if (ret)
-		goto failed;
-
 #ifdef CONFIG_GPMC
 	/*
 	 * WP is made high and WAIT1 active Low
 	 */
 	gpmc_generic_init(0x10);
 #endif
-
-	armlinux_add_dram(&sdram_dev);
-
-failed:
-	return ret;
+	return 0;
 }
 device_initcall(omap3evm_init_devices);
diff --git a/arch/arm/boards/omap/board-sdp343x.c b/arch/arm/boards/omap/board-sdp343x.c
index f7615b4673..82fc16df63 100644
--- a/arch/arm/boards/omap/board-sdp343x.c
+++ b/arch/arm/boards/omap/board-sdp343x.c
@@ -61,6 +61,7 @@
 #include <mach/control.h>
 #include <mach/omap3-mux.h>
 #include <mach/gpmc.h>
+#include <errno.h>
 #include "board.h"
 
 /******************** Board Boot Time *******************/
@@ -604,17 +605,6 @@ static void mux_config(void)
 
 static struct NS16550_plat serial_plat = {
 	.clock = 48000000,	/* 48MHz (APLL96/2) */
-	.f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR,
-	.reg_read = omap_uart_read,
-	.reg_write = omap_uart_write,
-};
-
-static struct device_d sdp3430_serial_device = {
-	.id = -1,
-	.name = "serial_ns16550",
-	.map_base = OMAP_UART3_BASE,
-	.size = 1024,
-	.platform_data = (void *)&serial_plat,
 };
 
 /**
@@ -625,50 +615,31 @@ static struct device_d sdp3430_serial_device = {
 static int sdp3430_console_init(void)
 {
 	/* Register the serial port */
-	return register_device(&sdp3430_serial_device);
+	add_ns16550_device(-1, OMAP_UART3_BASE, 1024, IORESOURCE_MEM_8BIT,
+			   &serial_plat);
+
+	return 0;
 }
 
 console_initcall(sdp3430_console_init);
 #endif				/* CONFIG_DRIVER_SERIAL_NS16550 */
 
-/*------------------------- FLASH Devices -----------------------------------*/
-static int sdp3430_flash_init(void)
+static int sdp3430_mem_init(void)
 {
-#ifdef CONFIG_GPMC
-	/* WP is made high and WAIT1 active Low */
-	gpmc_generic_init(0x10);
-#endif
+	arm_add_mem_device("ram0", 0x80000000, 128 * 1024 * 1024);
+
 	return 0;
 }
-
-static struct memory_platform_data ram_pdata = {
-	.name = "ram0",
-	.flags = DEVFS_RDWR,
-};
-
-struct device_d sdram_dev = {
-	.id = -1,
-	.name = "mem",
-	.map_base = 0x80000000,
-	.size = 128 * 1024 * 1024,
-	.platform_data = &ram_pdata,
-};
-
-/*-----------------------Generic Devices Initialization ---------------------*/
+mem_initcall(sdp3430_mem_init);
 
 static int sdp3430_devices_init(void)
 {
-	int ret;
-	ret = register_device(&sdram_dev);
-	if (ret)
-		goto failed;
-	ret = sdp3430_flash_init();
-	if (ret)
-		goto failed;
+#ifdef CONFIG_GPMC
+	/* WP is made high and WAIT1 active Low */
+	gpmc_generic_init(0x10);
+#endif
 
-	armlinux_add_dram(&sdram_dev);
-failed:
-	return ret;
+	return 0;
 }
 
 device_initcall(sdp3430_devices_init);
diff --git a/arch/arm/boards/panda/board.c b/arch/arm/boards/panda/board.c
index ff05f9e24b..1303c47233 100644
--- a/arch/arm/boards/panda/board.c
+++ b/arch/arm/boards/panda/board.c
@@ -32,66 +32,29 @@ static int board_revision;
 
 static struct NS16550_plat serial_plat = {
 	.clock = 48000000,      /* 48MHz (APLL96/2) */
-	.f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR,
-	.reg_read = omap_uart_read,
-	.reg_write = omap_uart_write,
-};
-
-static struct device_d panda_serial_device = {
-	.id = -1,
-	.name = "serial_ns16550",
-	.map_base = OMAP44XX_UART3_BASE,
-	.size = 1024,
-	.platform_data = (void *)&serial_plat,
 };
 
 static int panda_console_init(void)
 {
 	/* Register the serial port */
-	return register_device(&panda_serial_device);
+	add_ns16550_device(-1, OMAP44XX_UART3_BASE, 1024, IORESOURCE_MEM_8BIT,
+			   &serial_plat);
+
+	return 0;
 }
 console_initcall(panda_console_init);
 
-static struct memory_platform_data sram_pdata = {
-	.name = "ram0",
-	.flags = DEVFS_RDWR,
-};
-
-static struct device_d sdram_dev = {
-	.id = -1,
-	.name = "mem",
-	.map_base = 0x80000000,
-	.size = SZ_1G,
-	.platform_data = &sram_pdata,
-};
-
-#ifdef CONFIG_MMU
-static int panda_mmu_init(void)
+static int panda_mem_init(void)
 {
-	mmu_init();
-
-	arm_create_section(0x80000000, 0x80000000, 256, PMD_SECT_DEF_CACHED);
-	arm_create_section(0x90000000, 0x80000000, 256, PMD_SECT_DEF_UNCACHED);
-
-	mmu_enable();
+	arm_add_mem_device("ram0", 0x80000000, SZ_1G);
 
 	return 0;
 }
-device_initcall(panda_mmu_init);
-#endif
+mem_initcall(panda_mem_init);
 
+#ifdef CONFIG_USB_EHCI
 static struct ehci_platform_data ehci_pdata = {
 	.flags = 0,
-	.hccr_offset = 0x0,
-	.hcor_offset = 0x10,
-};
-
-static struct device_d usbh_dev = {
-	.id	  = -1,
-	.name     = "ehci",
-	.map_base = 0x4a064c00,
-	.size     = 4 * 1024,
-	.platform_data = &ehci_pdata,
 };
 
 static void panda_ehci_init(void)
@@ -124,8 +87,13 @@ static void panda_ehci_init(void)
 	/* enable power to hub */
 	gpio_set_value(GPIO_HUB_POWER, 1);
 
-	register_device(&usbh_dev);
+	add_usb_ehci_device(-1, 0x4a064c00,
+			    0x4a064c00 + 0x10, &ehci_pdata);
 }
+#else
+static void panda_ehci_init(void)
+{}
+#endif
 
 static void __init panda_boardrev_init(void)
 {
@@ -136,13 +104,6 @@ static void __init panda_boardrev_init(void)
 	pr_info("PandaBoard Revision: %03d\n", board_revision);
 }
 
-static struct device_d hsmmc_dev = {
-	.id = -1,
-	.name = "omap-hsmmc",
-	.map_base = 0x4809C100,
-	.size = SZ_4K,
-};
-
 static int panda_devices_init(void)
 {
 	panda_boardrev_init();
@@ -171,11 +132,10 @@ static int panda_devices_init(void)
 		sr32(OMAP44XX_SCRM_ALTCLKSRC, 2, 2, 0x3);
 	}
 
-	register_device(&sdram_dev);
-	register_device(&hsmmc_dev);
+	add_generic_device("omap-hsmmc", -1, NULL, 0x4809C100, SZ_4K,
+			   IORESOURCE_MEM, NULL);
 	panda_ehci_init();
 
-	armlinux_add_dram(&sdram_dev);
 	armlinux_set_bootparams((void *)0x80000100);
 	armlinux_set_architecture(MACH_TYPE_OMAP4_PANDA);
 
diff --git a/arch/arm/boards/pcm037/pcm037.c b/arch/arm/boards/pcm037/pcm037.c
index cb4ffe69f4..85f004fe48 100644
--- a/arch/arm/boards/pcm037/pcm037.c
+++ b/arch/arm/boards/pcm037/pcm037.c
@@ -39,87 +39,18 @@
 #include <mach/imx-nand.h>
 #include <mach/devices-imx31.h>
 
-/*
- * Up to 32MiB NOR type flash, connected to
- * CS line 0, data width is 16 bit
- */
-static struct device_d cfi_dev = {
-	.id	  = -1,
-	.name     = "cfi_flash",
-	.map_base = IMX_CS0_BASE,
-	.size     = 32 * 1024 * 1024,	/* area size */
-};
-
-/*
- * up to 2MiB static RAM type memory, connected
- * to CS4, data width is 16 bit
- */
-static struct memory_platform_data sram_dev_pdata0 = {
-	.name = "sram0",
-	.flags = DEVFS_RDWR,
-};
-
-static struct device_d sram_dev = {
-	.id	  = -1,
-	.name     = "mem",
-	.map_base = IMX_CS4_BASE,
-	.size     = IMX_CS4_RANGE,	/* area size */
-	.platform_data = &sram_dev_pdata0,
-};
-
-/*
- * SMSC 9217 network controller
- * connected to CS line 1 and interrupt line
- * GPIO3, data width is 16 bit
- */
-static struct device_d network_dev = {
-	.id	  = -1,
-	.name     = "smc911x",
-	.map_base = IMX_CS1_BASE,
-	.size     = IMX_CS1_RANGE,	/* area size */
-};
-
 #if defined CONFIG_PCM037_SDRAM_BANK0_128MB
 #define SDRAM0	128
 #elif defined CONFIG_PCM037_SDRAM_BANK0_256MB
 #define SDRAM0	256
 #endif
 
-static struct memory_platform_data ram_dev_pdata0 = {
-	.name = "ram0",
-	.flags = DEVFS_RDWR,
-};
-
-static struct device_d sdram0_dev = {
-	.id	  = -1,
-	.name     = "mem",
-	.map_base = IMX_SDRAM_CS0,
-	.size     = SDRAM0 * 1024 * 1024,	/* fix size */
-	.platform_data = &ram_dev_pdata0,
-};
-
-#ifndef CONFIG_PCM037_SDRAM_BANK1_NONE
-
 #if defined CONFIG_PCM037_SDRAM_BANK1_128MB
 #define SDRAM1	128
 #elif defined CONFIG_PCM037_SDRAM_BANK1_256MB
 #define SDRAM1	256
 #endif
 
-static struct memory_platform_data ram_dev_pdata1 = {
-	.name = "ram1",
-	.flags = DEVFS_RDWR,
-};
-
-static struct device_d sdram1_dev = {
-	.id	  = -1,
-	.name     = "mem",
-	.map_base = IMX_SDRAM_CS1,
-	.size     = SDRAM1 * 1024 * 1024,	/* fix size */
-	.platform_data = &ram_dev_pdata1,
-};
-#endif
-
 struct imx_nand_platform_data nand_info = {
 	.width = 1,
 	.hw_ecc = 1,
@@ -127,20 +58,6 @@ struct imx_nand_platform_data nand_info = {
 };
 
 #ifdef CONFIG_USB
-static struct device_d usbotg_dev = {
-	.id	  = -1,
-	.name     = "ehci",
-	.map_base = IMX_OTG_BASE,
-	.size     = 0x200,
-};
-
-static struct device_d usbh2_dev = {
-	.id	  = -1,
-	.name     = "ehci",
-	.map_base = IMX_OTG_BASE + 0x400,
-	.size     = 0x200,
-};
-
 static void pcm037_usb_init(void)
 {
 	u32 tmp;
@@ -229,32 +146,27 @@ static void pcm037_usb_init(void)
 }
 #endif
 
-#ifdef CONFIG_MMU
-static void pcm037_mmu_init(void)
+static int pcm037_mem_init(void)
 {
-	mmu_init();
-
-	arm_create_section(0x80000000, 0x80000000, 128, PMD_SECT_DEF_CACHED);
-	arm_create_section(0x90000000, 0x80000000, 128, PMD_SECT_DEF_UNCACHED);
-
-	setup_dma_coherent(0x10000000);
-
-	mmu_enable();
-
-#ifdef CONFIG_CACHE_L2X0
-	l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000);
+	arm_add_mem_device("ram0", IMX_SDRAM_CS0, SDRAM0 * 1024 * 1024);
+#ifndef CONFIG_PCM037_SDRAM_BANK1_NONE
+	arm_add_mem_device("ram1", IMX_SDRAM_CS1, SDRAM1 * 1024 * 1024);
 #endif
+
+	return 0;
 }
-#else
-static void pcm037_mmu_init(void)
+mem_initcall(pcm037_mem_init);
+
+static int pcm037_mmu_init(void)
 {
+	l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000);
+
+	return 0;
 }
-#endif
+postmmu_initcall(pcm037_mmu_init);
 
 static int imx31_devices_init(void)
 {
-	pcm037_mmu_init();
-
 	__REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */
 	__REG(CSCR_L(0)) = 0x10000d03;
 	__REG(CSCR_A(0)) = 0x00720900;
@@ -271,7 +183,11 @@ static int imx31_devices_init(void)
 	__REG(CSCR_L(5)) = 0x444A0301;
 	__REG(CSCR_A(5)) = 0x44443302;
 
-	register_device(&cfi_dev);
+	/*
+	 * Up to 32MiB NOR type flash, connected to
+	 * CS line 0, data width is 16 bit
+	 */
+	add_cfi_flash_device(-1, IMX_CS0_BASE, 32 * 1024 * 1024, 0);
 
 	/*
 	 * Create partitions that should be
@@ -282,24 +198,28 @@ static int imx31_devices_init(void)
 
 	protect_file("/dev/env0", 1);
 
-	register_device(&sram_dev);
+	/*
+	 * up to 2MiB static RAM type memory, connected
+	 * to CS4, data width is 16 bit
+	 */
+	add_mem_device("sram0", IMX_CS4_BASE, IMX_CS4_RANGE, /* area size */
+				   IORESOURCE_MEM_WRITEABLE);
 	imx31_add_nand(&nand_info);
-	register_device(&network_dev);
 
-	register_device(&sdram0_dev);
-#ifndef CONFIG_PCM037_SDRAM_BANK1_NONE
-	register_device(&sdram1_dev);
-#endif
+	/*
+	 * SMSC 9217 network controller
+	 * connected to CS line 1 and interrupt line
+	 * GPIO3, data width is 16 bit
+	 */
+	add_generic_device("smc911x", -1, NULL,	IMX_CS1_BASE, IMX_CS1_RANGE,
+			IORESOURCE_MEM, NULL);
+
 #ifdef CONFIG_USB
 	pcm037_usb_init();
-	register_device(&usbotg_dev);
-	register_device(&usbh2_dev);
+	add_generic_usb_ehci_device(-1, IMX_OTG_BASE, NULL);
+	add_generic_usb_ehci_device(-1, IMX_OTG_BASE + 0x400, NULL);
 #endif
 
-	armlinux_add_dram(&sdram0_dev);
-#ifndef CONFIG_PCM037_SDRAM_BANK1_NONE
-	armlinux_add_dram(&sdram1_dev);
-#endif
 	armlinux_set_bootparams((void *)0x80000100);
 	armlinux_set_architecture(MACH_TYPE_PCM037);
 
diff --git a/arch/arm/boards/pcm038/pcm038.c b/arch/arm/boards/pcm038/pcm038.c
index 3ca6650443..4db50fe8c0 100644
--- a/arch/arm/boards/pcm038/pcm038.c
+++ b/arch/arm/boards/pcm038/pcm038.c
@@ -47,39 +47,6 @@
 
 #include "pll.h"
 
-static struct device_d cfi_dev = {
-	.id	  = -1,
-	.name     = "cfi_flash",
-	.map_base = 0xC0000000,
-	.size     = 32 * 1024 * 1024,
-};
-
-static struct memory_platform_data ram_pdata = {
-	.name = "ram0",
-	.flags = DEVFS_RDWR,
-};
-
-static struct device_d sdram_dev = {
-	.id	  = -1,
-	.name     = "mem",
-	.map_base = 0xa0000000,
-	.size     = 128 * 1024 * 1024,
-	.platform_data = &ram_pdata,
-};
-
-static struct memory_platform_data sram_pdata = {
-	.name = "sram0",
-	.flags = DEVFS_RDWR,
-};
-
-static struct device_d sram_dev = {
-	.id	  = -1,
-	.name     = "mem",
-	.map_base = 0xc8000000,
-	.size     = 512 * 1024, /* Can be up to 2MiB */
-	.platform_data = &sram_pdata,
-};
-
 static struct fec_platform_data fec_info = {
 	.xcv_type = MII100,
 	.phy_addr = 1,
@@ -142,13 +109,6 @@ static struct imx_fb_platform_data pcm038_fb_data = {
 };
 
 #ifdef CONFIG_USB
-static struct device_d usbh2_dev = {
-	.id	  = -1,
-	.name     = "ehci",
-	.map_base = IMX_OTG_BASE + 0x400,
-	.size     = 0x200,
-};
-
 static void pcm038_usbh_init(void)
 {
 	uint32_t temp;
@@ -169,23 +129,15 @@ static void pcm038_usbh_init(void)
 }
 #endif
 
-#ifdef CONFIG_MMU
-static void pcm038_mmu_init(void)
+static int pcm038_mem_init(void)
 {
-	mmu_init();
-
-	arm_create_section(0xa0000000, 0xa0000000, 128, PMD_SECT_DEF_CACHED);
-	arm_create_section(0xb0000000, 0xa0000000, 128, PMD_SECT_DEF_UNCACHED);
+	arm_add_mem_device("ram0", 0xa0000000, 128 * 1024 * 1024);
 
-	setup_dma_coherent(0x10000000);
-
-	mmu_enable();
-}
-#else
-static void pcm038_mmu_init(void)
-{
+	add_mem_device("ram0", 0xc8000000, 512 * 1024, /* Can be up to 2MiB */
+				   IORESOURCE_MEM_WRITEABLE);
+	return 0;
 }
-#endif
+mem_initcall(pcm038_mem_init);
 
 static int pcm038_devices_init(void)
 {
@@ -263,8 +215,6 @@ static int pcm038_devices_init(void)
 		PD26_AF_USBH2_DATA5,
 	};
 
-	pcm038_mmu_init();
-
 	/* configure 16 bit nor flash on cs0 */
 	CS0U = 0x0000CC03;
 	CS0L = 0xa0330D01;
@@ -289,18 +239,17 @@ static int pcm038_devices_init(void)
 
 	gpio_direction_output(GPIO_PORTD | 28, 0);
 	gpio_set_value(GPIO_PORTD | 28, 0);
+
 	spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info));
 	imx27_add_spi0(&pcm038_spi_0_data);
 
-	register_device(&cfi_dev);
+	add_cfi_flash_device(-1, 0xC0000000, 32 * 1024 * 1024, 0);
 	imx27_add_nand(&nand_info);
-	register_device(&sdram_dev);
-	register_device(&sram_dev);
 	imx27_add_fb(&pcm038_fb_data);
 
 #ifdef CONFIG_USB
 	pcm038_usbh_init();
-	register_device(&usbh2_dev);
+	add_generic_usb_ehci_device(-1, IMX_OTG_BASE + 0x400, NULL);
 #endif
 
 	/* Register the fec device after the PLL re-initialisation
@@ -330,7 +279,6 @@ static int pcm038_devices_init(void)
 
 	printf("Using environment in %s Flash\n", envdev);
 
-	armlinux_add_dram(&sdram_dev);
 	armlinux_set_bootparams((void *)0xa0000100);
 	armlinux_set_architecture(MACH_TYPE_PCM038);
 
diff --git a/arch/arm/boards/pcm043/pcm043.c b/arch/arm/boards/pcm043/pcm043.c
index 7db3c836c3..966899a5ba 100644
--- a/arch/arm/boards/pcm043/pcm043.c
+++ b/arch/arm/boards/pcm043/pcm043.c
@@ -46,34 +46,10 @@
 #include <mach/iomux-mx35.h>
 #include <mach/devices-imx35.h>
 
-/*
- * Up to 32MiB NOR type flash, connected to
- * CS line 0, data width is 16 bit
- */
-static struct device_d cfi_dev = {
-	.id	  = -1,
-	.name     = "cfi_flash",
-	.map_base = IMX_CS0_BASE,
-	.size     = 32 * 1024 * 1024,	/* area size */
-};
-
 static struct fec_platform_data fec_info = {
 	.xcv_type = MII100,
 };
 
-static struct memory_platform_data ram_pdata = {
-	.name = "ram0",
-	.flags = DEVFS_RDWR,
-};
-
-static struct device_d sdram0_dev = {
-	.id	  = -1,
-	.name     = "mem",
-	.map_base = IMX_SDRAM_CS0,
-	.size     = 128 * 1024 * 1024,
-	.platform_data = &ram_pdata,
-};
-
 struct imx_nand_platform_data nand_info = {
 	.width	= 1,
 	.hw_ecc	= 1,
@@ -123,25 +99,21 @@ static struct imx_ipu_fb_platform_data ipu_fb_data = {
 	.bpp		= 16,
 };
 
-#ifdef CONFIG_MMU
-static int pcm043_mmu_init(void)
+static int pcm043_mem_init(void)
 {
-	mmu_init();
-
-	arm_create_section(0x80000000, 0x80000000, 128, PMD_SECT_DEF_CACHED);
-	arm_create_section(0x90000000, 0x80000000, 128, PMD_SECT_DEF_UNCACHED);
-
-	setup_dma_coherent(0x10000000);
+	arm_add_mem_device("ram0", IMX_SDRAM_CS0, 128 * 1024 * 1024);
 
-	mmu_enable();
+	return 0;
+}
+mem_initcall(pcm043_mem_init);
 
-#ifdef CONFIG_CACHE_L2X0
+static int pcm043_mmu_init(void)
+{
 	l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000);
-#endif
+
 	return 0;
 }
-postcore_initcall(pcm043_mmu_init);
-#endif
+postmmu_initcall(pcm043_mmu_init);
 
 struct gpio_led led0 = {
 	.gpio = 1 * 32 + 6,
@@ -170,7 +142,11 @@ static int imx35_devices_init(void)
 	 * This platform supports NOR and NAND
 	 */
 	imx35_add_nand(&nand_info);
-	register_device(&cfi_dev);
+	/*
+	 * Up to 32MiB NOR type flash, connected to
+	 * CS line 0, data width is 16 bit
+	 */
+	add_cfi_flash_device(-1, IMX_CS0_BASE, 32 * 1024 * 1024, 0);
 
 	if ((reg & 0xc00) == 0x800) {   /* reset mode: external boot */
 		switch ( (reg >> 25) & 0x3) {
@@ -189,10 +165,9 @@ static int imx35_devices_init(void)
 		}
 	}
 
-	register_device(&sdram0_dev);
+
 	imx35_add_fb(&ipu_fb_data);
 
-	armlinux_add_dram(&sdram0_dev);
 	armlinux_set_bootparams((void *)0x80000100);
 	armlinux_set_architecture(MACH_TYPE_PCM043);
 
@@ -236,6 +211,7 @@ static int imx35_console_init(void)
 	mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));
 
 	imx35_add_uart0();
+
 	return 0;
 }
 
diff --git a/arch/arm/boards/pcm049/board.c b/arch/arm/boards/pcm049/board.c
index 2303a9c21c..502e121b45 100644
--- a/arch/arm/boards/pcm049/board.c
+++ b/arch/arm/boards/pcm049/board.c
@@ -43,81 +43,26 @@
 
 static struct NS16550_plat serial_plat = {
 	.clock = 48000000,      /* 48MHz (APLL96/2) */
-	.f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR,
-	.reg_read = omap_uart_read,
-	.reg_write = omap_uart_write,
-};
-
-static struct device_d pcm049_serial_device = {
-	.id = -1,
-	.name = "serial_ns16550",
-	.map_base = OMAP44XX_UART3_BASE,
-	.size = 1024,
-	.platform_data = (void *)&serial_plat,
 };
 
 static int pcm049_console_init(void)
 {
 	/* Register the serial port */
-	return register_device(&pcm049_serial_device);
+	add_ns16550_device(-1, OMAP44XX_UART3_BASE, 1024, IORESOURCE_MEM_8BIT, &serial_plat);
+
+	return 0;
 }
 console_initcall(pcm049_console_init);
 
-static struct memory_platform_data sram_pdata = {
-	.name = "sram0",
-	.flags = DEVFS_RDWR,
-};
-
-static struct device_d sram_dev = {
-	.id = -1,
-	.name = "mem",
-	.map_base = 0x40300000,
-	.size = 48 * 1024,
-	.platform_data = &sram_pdata,
-};
-
-static struct memory_platform_data sdram_pdata = {
-	.name = "ram0",
-	.flags = DEVFS_RDWR,
-};
-
-static struct device_d sdram_dev = {
-	.id = -1,
-	.name = "mem",
-	.map_base = 0x80000000,
-	.size = SZ_512M,
-	.platform_data = &sdram_pdata,
-};
-
-#ifdef CONFIG_MMU
-static int pcm049_mmu_init(void)
+static int pcm049_mem_init(void)
 {
-	mmu_init();
-
-	arm_create_section(0x80000000, 0x80000000, 256, PMD_SECT_DEF_CACHED);
-	/* warning: This shadows the second half of our ram */
-	arm_create_section(0x90000000, 0x80000000, 256, PMD_SECT_DEF_UNCACHED);
-
-	mmu_enable();
+	arm_add_mem_device("ram0", 0x80000000, SZ_512M);
 
+	add_mem_device("sram0", 0x40300000, 48 * 1024,
+				   IORESOURCE_MEM_WRITEABLE);
 	return 0;
 }
-device_initcall(pcm049_mmu_init);
-#endif
-
-static struct device_d hsmmc_dev = {
-	.id = -1,
-	.name = "omap-hsmmc",
-	.map_base = 0x4809C100,
-	.size = SZ_4K,
-};
-
-static struct device_d smc911x_dev = {
-	.id		= -1,
-	.name		= "smc911x",
-	.map_base	= 0x2C000000,
-	.size		= 0x4000,
-};
+mem_initcall(pcm049_mem_init);
 
 static struct gpmc_config net_cfg = {
 	.cfg = {
@@ -136,14 +81,14 @@ static void pcm049_network_init(void)
 {
 	gpmc_cs_config(5, &net_cfg);
 
-	register_device(&smc911x_dev);
+	add_generic_device("smc911x", -1, NULL, 0x2C000000, 0x4000,
+			   IORESOURCE_MEM, NULL);
 }
 
 static int pcm049_devices_init(void)
 {
-	register_device(&sdram_dev);
-	register_device(&sram_dev);
-	register_device(&hsmmc_dev);
+	add_generic_device("omap-hsmmc", -1, NULL, 0x4809C100, SZ_4K,
+			   IORESOURCE_MEM, NULL);
 
 	gpmc_generic_init(0x10);
 
@@ -160,7 +105,6 @@ static int pcm049_devices_init(void)
 	dev_add_bb_dev("env_raw", "env0");
 #endif
 
-	armlinux_add_dram(&sdram_dev);
 	armlinux_set_bootparams((void *)0x80000100);
 	armlinux_set_architecture(MACH_TYPE_PCM049);
 
diff --git a/arch/arm/boards/phycard-i.MX27/pca100.c b/arch/arm/boards/phycard-i.MX27/pca100.c
index 89c0a14ac7..f285466641 100644
--- a/arch/arm/boards/phycard-i.MX27/pca100.c
+++ b/arch/arm/boards/phycard-i.MX27/pca100.c
@@ -41,19 +41,6 @@
 #include <mach/iomux-mx27.h>
 #include <mach/devices-imx27.h>
 
-static struct memory_platform_data ram_pdata = {
-	.name = "ram0",
-	.flags = DEVFS_RDWR,
-};
-
-static struct device_d sdram_dev = {
-	.id	  = -1,
-	.name     = "mem",
-	.map_base = 0xa0000000,
-	.size     = 128 * 1024 * 1024,
-	.platform_data = &ram_pdata,
-};
-
 static struct fec_platform_data fec_info = {
 	.xcv_type = MII100,
 	.phy_addr = 1,
@@ -66,20 +53,6 @@ struct imx_nand_platform_data nand_info = {
 };
 
 #ifdef CONFIG_USB
-static struct device_d usbotg_dev = {
-	.id	  = -1,
-	.name     = "ehci",
-	.map_base = IMX_OTG_BASE,
-	.size     = 0x200,
-};
-
-static struct device_d usbh2_dev = {
-	.id	  = -1,
-	.name     = "ehci",
-	.map_base = IMX_OTG_BASE + 0x400,
-	.size     = 0x200,
-};
-
 static void pca100_usb_register(void)
 {
 	mdelay(10);
@@ -90,29 +63,19 @@ static void pca100_usb_register(void)
 	mdelay(10);
 
 	isp1504_set_vbus_power((void *)(IMX_OTG_BASE + 0x170), 1);
-	register_device(&usbotg_dev);
+	add_generic_usb_ehci_device(-1, IMX_OTG_BASE, NULL);
 	isp1504_set_vbus_power((void *)(IMX_OTG_BASE + 0x570), 1);
-	register_device(&usbh2_dev);
+	add_generic_usb_ehci_device(-1, IMX_OTG_BASE + 0x400, NULL);
 }
 #endif
 
-#ifdef CONFIG_MMU
-static void pca100_mmu_init(void)
+static int pca100_mem_init(void)
 {
-	mmu_init();
+	arm_add_mem_device("ram0", 0xa0000000, 128 * 1024 * 1024);
 
-	arm_create_section(0xa0000000, 0xa0000000, 128, PMD_SECT_DEF_CACHED);
-	arm_create_section(0xb0000000, 0xa0000000, 128, PMD_SECT_DEF_UNCACHED);
-
-	setup_dma_coherent(0x10000000);
-
-	mmu_enable();
-}
-#else
-static void pca100_mmu_init(void)
-{
+	return 0;
 }
-#endif
+mem_initcall(pca100_mem_init);
 
 static void pca100_usb_init(void)
 {
@@ -224,7 +187,6 @@ static int pca100_devices_init(void)
 		imx_gpio_mode(mode[i]);
 
 	imx27_add_nand(&nand_info);
-	register_device(&sdram_dev);
 	imx27_add_fec(&fec_info);
 	imx27_add_mmc0(NULL);
 
@@ -241,7 +203,6 @@ static int pca100_devices_init(void)
 	devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
 	dev_add_bb_dev("env_raw", "env0");
 
-	armlinux_add_dram(&sdram_dev);
 	armlinux_set_bootparams((void *)0xa0000100);
 	armlinux_set_architecture(2149);
 
@@ -250,17 +211,9 @@ static int pca100_devices_init(void)
 
 device_initcall(pca100_devices_init);
 
-static struct device_d pca100_serial_device = {
-	.id	  = -1,
-	.name     = "imx_serial",
-	.map_base = IMX_UART1_BASE,
-	.size     = 4096,
-};
-
 static int pca100_console_init(void)
 {
-	pca100_mmu_init();
-	register_device(&pca100_serial_device);
+	imx27_add_uart0();
 	return 0;
 }
 
diff --git a/arch/arm/boards/pm9261/init.c b/arch/arm/boards/pm9261/init.c
index 6fb14f7bce..efc5dcc1fb 100644
--- a/arch/arm/boards/pm9261/init.c
+++ b/arch/arm/boards/pm9261/init.c
@@ -89,20 +89,9 @@ static void pm_add_device_nand(void)
  */
 #if defined(CONFIG_DRIVER_NET_DM9000)
 static struct dm9000_platform_data dm9000_data = {
-	.iobase		= AT91_CHIPSELECT_2,
-	.iodata		= AT91_CHIPSELECT_2 + 4,
-	.buswidth	= DM9000_WIDTH_16,
 	.srom		= 1,
 };
 
-static struct device_d dm9000_dev = {
-	.id		= 0,
-	.name		= "dm9000",
-	.map_base	= AT91_CHIPSELECT_2,
-	.size		= 8,
-	.platform_data	= &dm9000_data,
-};
-
 /*
  * SMC timings for the DM9000.
  * Note: These timings were calculated for MASTER_CLOCK = 100000000 according to the DM9000 timings.
@@ -130,25 +119,26 @@ static void __init pm_add_device_dm9000(void)
 	/* Configure chip-select 2 (DM9000) */
 	sam9_smc_configure(2, &dm9000_smc_config);
 
-	register_device(&dm9000_dev);
+	add_dm9000_device(0, AT91_CHIPSELECT_2, AT91_CHIPSELECT_2 + 4,
+			  IORESOURCE_MEM_16BIT, &dm9000_data);
 }
 #else
 static void __init ek_add_device_dm9000(void) {}
 #endif /* CONFIG_DRIVER_NET_DM9000 */
 
-static struct device_d cfi_dev = {
-	.id		= 0,
-	.name		= "cfi_flash",
-	.map_base	= AT91_CHIPSELECT_0,
-	.size		= 4 * 1024 * 1024,
-};
+static int pm9261_mem_init(void)
+{
+	at91_add_device_sdram(64 * 1024 * 1024);
+
+	return 0;
+}
+mem_initcall(pm9261_mem_init);
 
 static int pm9261_devices_init(void)
 {
-	at91_add_device_sdram(64 * 1024 * 1024);
 	pm_add_device_nand();
-	register_device(&cfi_dev);
 	pm_add_device_dm9000();
+	add_cfi_flash_device(0, AT91_CHIPSELECT_0, 4 * 1024 * 1024, 0);
 
 	devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self");
 	devfs_add_partition("nor0", 0x40000, 0x10000, PARTITION_FIXED, "env0");
diff --git a/arch/arm/boards/pm9263/init.c b/arch/arm/boards/pm9263/init.c
index abe8def13c..aeca4e7d79 100644
--- a/arch/arm/boards/pm9263/init.c
+++ b/arch/arm/boards/pm9263/init.c
@@ -86,18 +86,19 @@ static void pm_add_device_nand(void)
 	at91_add_device_nand(&nand_pdata);
 }
 
-static struct device_d cfi_dev = {
-	.id	  = -1,
-	.name     = "cfi_flash",
-	.map_base = AT91_CHIPSELECT_0,
-	.size     = 4 * 1024 * 1024,
-};
-
 static struct at91_ether_platform_data macb_pdata = {
 	.flags = AT91SAM_ETHER_RMII,
 	.phy_addr = 0,
 };
 
+static int pm9263_mem_init(void)
+{
+	at91_add_device_sdram(64 * 1024 * 1024);
+
+	return 0;
+}
+mem_initcall(pm9263_mem_init);
+
 static int pm9263_devices_init(void)
 {
 	/*
@@ -108,10 +109,9 @@ static int pm9263_devices_init(void)
 	at91_set_gpio_output(AT91_PIN_PB27, 1);
 	at91_set_gpio_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */
 
-	at91_add_device_sdram(64 * 1024 * 1024);
 	pm_add_device_nand();
 	at91_add_device_eth(&macb_pdata);
-	register_device(&cfi_dev);
+	add_cfi_flash_device(0, AT91_CHIPSELECT_0, 4 * 1024 * 1024, 0);
 
 	devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
 	devfs_add_partition("nor0", 0x40000, 0x10000, PARTITION_FIXED, "env0");
diff --git a/arch/arm/boards/pm9g45/init.c b/arch/arm/boards/pm9g45/init.c
index 8031ce5b64..35c9ce9f83 100644
--- a/arch/arm/boards/pm9g45/init.c
+++ b/arch/arm/boards/pm9g45/init.c
@@ -82,9 +82,16 @@ static struct at91_ether_platform_data macb_pdata = {
 	.phy_addr = 0,
 };
 
-static int pm9g45_devices_init(void)
+static int pm9g45_mem_init(void)
 {
 	at91_add_device_sdram(128 * 1024 * 1024);
+
+	return 0;
+}
+mem_initcall(pm9g45_mem_init);
+
+static int pm9g45_devices_init(void)
+{
 	pm_add_device_nand();
 	at91_add_device_eth(&macb_pdata);
 
diff --git a/arch/arm/boards/scb9328/env/config b/arch/arm/boards/scb9328/env/config
new file mode 100644
index 0000000000..d0f3f25ee8
--- /dev/null
+++ b/arch/arm/boards/scb9328/env/config
@@ -0,0 +1,56 @@
+#!/bin/sh
+
+machine=scb9328
+eth0.serverip=
+user=
+
+# use 'dhcp' to do dhcp in barebox and in kernel
+# use 'none' if you want to skip kernel ip autoconfiguration
+ip=dhcp
+
+# or set your networking parameters here
+#eth0.ipaddr=a.b.c.d
+#eth0.netmask=a.b.c.d
+#eth0.gateway=a.b.c.d
+#eth0.serverip=a.b.c.d
+
+# can be either 'net', 'nor' or 'nand'
+kernel_loc=net
+# can be either 'net', 'nor', 'nand' or 'initrd'
+rootfs_loc=net
+
+# can be either 'jffs2' or 'ubifs'
+rootfs_type=ubifs
+rootfsimage=root-$machine.$rootfs_type
+
+# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo
+kernelimage_type=zimage
+kernelimage=zImage-$machine
+#kernelimage_type=uimage
+#kernelimage=uImage-$machine
+#kernelimage_type=raw
+#kernelimage=Image-$machine
+#kernelimage_type=raw_lzo
+#kernelimage=Image-$machine.lzo
+
+if [ -n $user ]; then
+	kernelimage="$user"-"$kernelimage"
+	nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine"
+	rootfsimage="$user"-"$rootfsimage"
+else
+	nfsroot="$eth0.serverip:/path/to/nfs/root"
+fi
+
+autoboot_timeout=3
+
+bootargs="console=ttymxc0,115200"
+
+nor_parts="256k(barebox)ro,128k(bareboxenv),2M(kernel),-(root)"
+rootfs_mtdblock_nor=3
+
+nand_parts="256k(barebox)ro,128k(bareboxenv),2M(kernel),-(root)"
+rootfs_mtdblock_nand=7
+
+# set a fancy prompt (if support is compiled in)
+PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "
+
diff --git a/arch/arm/boards/scb9328/scb9328.c b/arch/arm/boards/scb9328/scb9328.c
index a98d9fe26e..e90417f01e 100644
--- a/arch/arm/boards/scb9328/scb9328.c
+++ b/arch/arm/boards/scb9328/scb9328.c
@@ -32,43 +32,12 @@
 #include <fcntl.h>
 #include <dm9000.h>
 #include <led.h>
-
-static struct device_d cfi_dev = {
-	.id	  = -1,
-	.name     = "cfi_flash",
-
-	.map_base = 0x10000000,
-	.size     = 16 * 1024 * 1024,
-};
-
-static struct memory_platform_data sdram_pdata = {
-	.name = "ram0",
-	.flags = DEVFS_RDWR,
-};
-
-static struct device_d sdram_dev = {
-	.id	  = -1,
-	.name     = "mem",
-	.map_base = 0x08000000,
-	.size     = 16 * 1024 * 1024,
-	.platform_data = &sdram_pdata,
-};
+#include <mach/devices-imx1.h>
 
 static struct dm9000_platform_data dm9000_data = {
-	.iobase   = 0x16000000,
-	.iodata   = 0x16000004,
-	.buswidth = DM9000_WIDTH_16,
 	.srom     = 1,
 };
 
-static struct device_d dm9000_dev = {
-	.id	  = -1,
-	.name     = "dm9000",
-	.map_base = 0x16000000,
-	.size     = 8,
-	.platform_data = &dm9000_data,
-};
-
 struct gpio_led leds[] = {
 	{
 		.gpio = 32 + 21,
@@ -81,6 +50,14 @@ struct gpio_led leds[] = {
 	},
 };
 
+static int scb9328_mem_init(void)
+{
+	arm_add_mem_device("ram0", 0x08000000, 16 * 1024 * 1024);
+
+	return 0;
+}
+mem_initcall(scb9328_mem_init);
+
 static int scb9328_devices_init(void)
 {
 	int i;
@@ -111,15 +88,14 @@ static int scb9328_devices_init(void)
 	CS5U = 0x00008400;
 	CS5L = 0x00000D03;
 
-	register_device(&cfi_dev);
-	register_device(&sdram_dev);
-	register_device(&dm9000_dev);
+	add_cfi_flash_device(-1, 0x10000000, 16 * 1024 * 1024, 0);
+	add_dm9000_device(-1, 0x16000000, 0x16000004,
+			  IORESOURCE_MEM_16BIT, &dm9000_data);
 
 	devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
 	devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
 	protect_file("/dev/env0", 1);
 
-	armlinux_add_dram(&sdram_dev);
 	armlinux_set_bootparams((void *)0x08000100);
 	armlinux_set_architecture(MACH_TYPE_SCB9328);
 
@@ -128,20 +104,14 @@ static int scb9328_devices_init(void)
 
 device_initcall(scb9328_devices_init);
 
-static struct device_d scb9328_serial_device = {
-	.id	  = -1,
-	.name     = "imx_serial",
-	.map_base = IMX_UART1_BASE,
-	.size     = 4096,
-};
-
 static int scb9328_console_init(void)
 {
 	/* init gpios for serial port */
 	imx_gpio_mode(PC11_PF_UART1_TXD);
 	imx_gpio_mode(PC12_PF_UART1_RXD);
 
-	register_device(&scb9328_serial_device);
+	imx1_add_uart0();
+
 	return 0;
 }
 
diff --git a/arch/arm/boards/versatile/versatilepb.c b/arch/arm/boards/versatile/versatilepb.c
index 5568f216e4..4e09de3c34 100644
--- a/arch/arm/boards/versatile/versatilepb.c
+++ b/arch/arm/boards/versatile/versatilepb.c
@@ -33,13 +33,6 @@
 #include <partition.h>
 #include <sizes.h>
 
-static struct device_d cfi_dev = {
-	.id		= -1,
-	.name		= "cfi_flash",
-	.map_base	= VERSATILE_FLASH_BASE,
-	.size		= VERSATILE_FLASH_SIZE,
-};
-
 static int vpb_console_init(void)
 {
 	versatile_register_uart(0);
@@ -47,22 +40,22 @@ static int vpb_console_init(void)
 }
 console_initcall(vpb_console_init);
 
-static struct device_d smc911x_dev = {
-	.id		= -1,
-	.name		= "smc91c111",
-	.map_base	= VERSATILE_ETH_BASE,
-	.size		= 64 * 1024,
-};
-
-static int vpb_devices_init(void)
+static int vpb_mem_init(void)
 {
 	versatile_add_sdram(64 * 1024 *1024);
 
-	register_device(&cfi_dev);
+	return 0;
+}
+mem_initcall(vpb_mem_init);
+
+static int vpb_devices_init(void)
+{
+	add_cfi_flash_device(-1, VERSATILE_FLASH_BASE, VERSATILE_FLASH_SIZE, 0);
 	devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self");
 	devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
 
-	register_device(&smc911x_dev);
+	add_generic_device("smc91c111", -1, NULL, VERSATILE_ETH_BASE, 64 * 1024,
+			   IORESOURCE_MEM, NULL);
 
 	armlinux_set_architecture(MACH_TYPE_VERSATILE_PB);
 	armlinux_set_bootparams((void *)(0x00000100));
diff --git a/arch/arm/configs/cupid_defconfig b/arch/arm/configs/cupid_defconfig
index e24afe1d5a..b842469b72 100644
--- a/arch/arm/configs/cupid_defconfig
+++ b/arch/arm/configs/cupid_defconfig
@@ -5,9 +5,11 @@ CONFIG_MACH_GUF_CUPID=y
 CONFIG_IMX_CLKO=y
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_ARM_UNWIND=y
 CONFIG_MMU=y
 CONFIG_TEXT_BASE=0x87F00000
 CONFIG_MALLOC_SIZE=0x1000000
+CONFIG_KALLSYMS=y
 CONFIG_LONGHELP=y
 CONFIG_GLOB=y
 CONFIG_HUSH_FANCY_PROMPT=y
@@ -46,9 +48,9 @@ CONFIG_DRIVER_NET_FEC_IMX=y
 # CONFIG_SPI is not set
 CONFIG_MTD=y
 CONFIG_NAND=y
+# CONFIG_NAND_ECC_SOFT is not set
+# CONFIG_NAND_ECC_HW_SYNDROME is not set
 CONFIG_NAND_IMX=y
-CONFIG_NAND_IMX_BOOT=y
-CONFIG_NAND_IMX_BOOT_2K=y
 CONFIG_UBI=y
 CONFIG_VIDEO=y
 CONFIG_DRIVER_VIDEO_IMX_IPU=y
diff --git a/arch/arm/configs/freescale_mx51_babbage_defconfig b/arch/arm/configs/freescale_mx51_babbage_defconfig
index d99d91a31e..472ed62090 100644
--- a/arch/arm/configs/freescale_mx51_babbage_defconfig
+++ b/arch/arm/configs/freescale_mx51_babbage_defconfig
@@ -1,17 +1,21 @@
 CONFIG_ARCH_IMX=y
-CONFIG_ARCH_IMX_INTERNAL_BOOT=y
 CONFIG_ARCH_IMX51=y
+CONFIG_IMX_IIM=y
+CONFIG_IMX_IIM_FUSE_BLOW=y
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_ARM_UNWIND=y
 CONFIG_MMU=y
 CONFIG_TEXT_BASE=0x97f00000
 CONFIG_MALLOC_SIZE=0x2000000
+CONFIG_KALLSYMS=y
 CONFIG_LONGHELP=y
 CONFIG_GLOB=y
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
 CONFIG_AUTO_COMPLETE=y
 CONFIG_PARTITION=y
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
 CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv arch/arm/boards/freescale-mx51-pdk/env/"
 CONFIG_CMD_EDIT=y
 CONFIG_CMD_SLEEP=y
@@ -22,7 +26,6 @@ CONFIG_CMD_PRINTENV=y
 CONFIG_CMD_READLINE=y
 CONFIG_CMD_ECHO_E=y
 CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_CRC=y
 CONFIG_CMD_FLASH=y
 CONFIG_CMD_RESET=y
 CONFIG_CMD_GO=y
@@ -31,8 +34,10 @@ CONFIG_CMD_PARTITION=y
 CONFIG_CMD_GPIO=y
 CONFIG_NET=y
 CONFIG_NET_DHCP=y
+CONFIG_NET_NFS=y
 CONFIG_NET_PING=y
 CONFIG_NET_TFTP=y
+CONFIG_NET_TFTP_PUSH=y
 CONFIG_DRIVER_NET_FEC_IMX=y
 CONFIG_DRIVER_SPI_IMX=y
 CONFIG_DRIVER_CFI=y
diff --git a/arch/arm/configs/freescale_mx53_loco_defconfig b/arch/arm/configs/freescale_mx53_loco_defconfig
new file mode 100644
index 0000000000..8e4a7ce328
--- /dev/null
+++ b/arch/arm/configs/freescale_mx53_loco_defconfig
@@ -0,0 +1,51 @@
+CONFIG_ARCH_IMX=y
+CONFIG_ARCH_IMX53=y
+CONFIG_IMX_IIM=y
+CONFIG_IMX_IIM_FUSE_BLOW=y
+CONFIG_AEABI=y
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_ARM_UNWIND=y
+CONFIG_MMU=y
+CONFIG_TEXT_BASE=0x7ff00000
+CONFIG_MALLOC_SIZE=0x2000000
+CONFIG_KALLSYMS=y
+CONFIG_LONGHELP=y
+CONFIG_GLOB=y
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_PARTITION=y
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
+CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv arch/arm/boards/freescale-mx53-loco/env/"
+CONFIG_DEBUG_INFO=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_LOADENV=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_UNLZO=y
+CONFIG_NET=y
+CONFIG_NET_DHCP=y
+CONFIG_NET_NFS=y
+CONFIG_NET_PING=y
+CONFIG_NET_TFTP=y
+CONFIG_NET_TFTP_PUSH=y
+CONFIG_NET_NETCONSOLE=y
+CONFIG_DRIVER_NET_FEC_IMX=y
+# CONFIG_SPI is not set
+CONFIG_MCI=y
+CONFIG_MCI_STARTUP=y
+CONFIG_MCI_IMX_ESDHC=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FAT_WRITE=y
+CONFIG_FS_FAT_LFN=y
diff --git a/arch/arm/configs/neso_defconfig b/arch/arm/configs/neso_defconfig
index 24125f914b..1b533df1fa 100644
--- a/arch/arm/configs/neso_defconfig
+++ b/arch/arm/configs/neso_defconfig
@@ -1,11 +1,14 @@
 CONFIG_ARCH_IMX=y
+CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND=y
 CONFIG_ARCH_IMX27=y
 CONFIG_MACH_NESO=y
 CONFIG_IMX_CLKO=y
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_ARM_UNWIND=y
 CONFIG_MMU=y
 CONFIG_MALLOC_SIZE=0x1000000
+CONFIG_KALLSYMS=y
 CONFIG_LONGHELP=y
 CONFIG_GLOB=y
 CONFIG_HUSH_FANCY_PROMPT=y
@@ -23,7 +26,6 @@ CONFIG_CMD_PRINTENV=y
 CONFIG_CMD_READLINE=y
 CONFIG_CMD_ECHO_E=y
 CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_CRC=y
 CONFIG_CMD_MTEST=y
 CONFIG_CMD_FLASH=y
 CONFIG_CMD_RESET=y
@@ -45,11 +47,11 @@ CONFIG_DRIVER_NET_FEC_IMX=y
 CONFIG_NET_USB=y
 CONFIG_NET_USB_ASIX=y
 CONFIG_DRIVER_SPI_IMX=y
-CONFIG_DRIVER_SPI_MC13783=y
 CONFIG_MTD=y
 CONFIG_NAND=y
+# CONFIG_NAND_ECC_SOFT is not set
+# CONFIG_NAND_ECC_HW_SYNDROME is not set
 CONFIG_NAND_IMX=y
-CONFIG_NAND_IMX_BOOT=y
 CONFIG_UBI=y
 CONFIG_USB=y
 CONFIG_USB_EHCI=y
@@ -57,3 +59,4 @@ CONFIG_USB_ISP1504=y
 CONFIG_VIDEO=y
 CONFIG_DRIVER_VIDEO_IMX=y
 CONFIG_IMXFB_DRIVER_VIDEO_IMX_OVERLAY=y
+CONFIG_DRIVER_SPI_MC13783=y
diff --git a/arch/arm/configs/pca100_defconfig b/arch/arm/configs/pca100_defconfig
index 3450b8edb8..88e7b9f5e8 100644
--- a/arch/arm/configs/pca100_defconfig
+++ b/arch/arm/configs/pca100_defconfig
@@ -1,11 +1,14 @@
 CONFIG_ARCH_IMX=y
+CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND=y
 CONFIG_ARCH_IMX27=y
 CONFIG_MACH_PCA100=y
 CONFIG_IMX_CLKO=y
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_ARM_UNWIND=y
 CONFIG_MMU=y
 CONFIG_MALLOC_SIZE=0x500000
+CONFIG_KALLSYMS=y
 CONFIG_LONGHELP=y
 CONFIG_GLOB=y
 CONFIG_HUSH_FANCY_PROMPT=y
@@ -43,8 +46,9 @@ CONFIG_NET_USB_ASIX=y
 # CONFIG_SPI is not set
 CONFIG_MTD=y
 CONFIG_NAND=y
+# CONFIG_NAND_ECC_SOFT is not set
+# CONFIG_NAND_ECC_HW_SYNDROME is not set
 CONFIG_NAND_IMX=y
-CONFIG_NAND_IMX_BOOT=y
 CONFIG_UBI=y
 CONFIG_USB=y
 CONFIG_USB_EHCI=y
diff --git a/arch/arm/configs/pcm037_defconfig b/arch/arm/configs/pcm037_defconfig
index b8ba53ce55..d9525a215c 100644
--- a/arch/arm/configs/pcm037_defconfig
+++ b/arch/arm/configs/pcm037_defconfig
@@ -1,9 +1,13 @@
 CONFIG_ARCH_IMX=y
 CONFIG_CACHE_L2X0=y
 CONFIG_ARCH_IMX31=y
+CONFIG_IMX_IIM=y
+CONFIG_IMX_IIM_FUSE_BLOW=y
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_ARM_UNWIND=y
 CONFIG_MMU=y
+CONFIG_KALLSYMS=y
 CONFIG_LONGHELP=y
 CONFIG_GLOB=y
 CONFIG_HUSH_FANCY_PROMPT=y
@@ -30,6 +34,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_UNLZO=y
 CONFIG_NET=y
 CONFIG_NET_DHCP=y
+CONFIG_NET_NFS=y
 CONFIG_NET_PING=y
 CONFIG_NET_TFTP=y
 CONFIG_NET_TFTP_PUSH=y
diff --git a/arch/arm/configs/pcm038_defconfig b/arch/arm/configs/pcm038_defconfig
index 2038f1431f..2f4823a83f 100644
--- a/arch/arm/configs/pcm038_defconfig
+++ b/arch/arm/configs/pcm038_defconfig
@@ -1,12 +1,15 @@
 CONFIG_ARCH_IMX=y
+CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND=y
 CONFIG_ARCH_IMX27=y
 CONFIG_MACH_PCM038=y
 CONFIG_IMX_CLKO=y
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_ARM_UNWIND=y
 CONFIG_MMU=y
 CONFIG_TEXT_BASE=0xa7f00000
 CONFIG_MALLOC_SIZE=0x1000000
+CONFIG_KALLSYMS=y
 CONFIG_LONGHELP=y
 CONFIG_GLOB=y
 CONFIG_HUSH_FANCY_PROMPT=y
@@ -24,7 +27,6 @@ CONFIG_CMD_PRINTENV=y
 CONFIG_CMD_READLINE=y
 CONFIG_CMD_ECHO_E=y
 CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_CRC=y
 CONFIG_CMD_MTEST=y
 CONFIG_CMD_FLASH=y
 CONFIG_CMD_RESET=y
@@ -46,8 +48,9 @@ CONFIG_DRIVER_CFI=y
 CONFIG_CFI_BUFFER_WRITE=y
 CONFIG_MTD=y
 CONFIG_NAND=y
+# CONFIG_NAND_ECC_SOFT is not set
+# CONFIG_NAND_ECC_HW_SYNDROME is not set
 CONFIG_NAND_IMX=y
-CONFIG_NAND_IMX_BOOT=y
 CONFIG_UBI=y
 CONFIG_USB=y
 CONFIG_USB_EHCI=y
diff --git a/arch/arm/configs/pcm043_defconfig b/arch/arm/configs/pcm043_defconfig
index 64b7987c89..3bf21c8660 100644
--- a/arch/arm/configs/pcm043_defconfig
+++ b/arch/arm/configs/pcm043_defconfig
@@ -4,6 +4,7 @@ CONFIG_ARCH_IMX35=y
 CONFIG_MACH_PCM043=y
 CONFIG_IMX_CLKO=y
 CONFIG_IMX_IIM=y
+CONFIG_IMX_IIM_FUSE_BLOW=y
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 CONFIG_ARM_UNWIND=y
diff --git a/arch/arm/configs/scb9328_defconfig b/arch/arm/configs/scb9328_defconfig
index ee0e2fc37b..73ef2382eb 100644
--- a/arch/arm/configs/scb9328_defconfig
+++ b/arch/arm/configs/scb9328_defconfig
@@ -2,6 +2,9 @@ CONFIG_ARCH_IMX=y
 CONFIG_MACH_SCB9328=y
 CONFIG_AEABI=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_ARM_UNWIND=y
+CONFIG_MMU=y
+CONFIG_KALLSYMS=y
 CONFIG_LONGHELP=y
 CONFIG_GLOB=y
 CONFIG_HUSH_FANCY_PROMPT=y
@@ -10,7 +13,6 @@ CONFIG_AUTO_COMPLETE=y
 CONFIG_PARTITION=y
 CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
 CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/scb9328/env/"
-CONFIG_POLLER=y
 CONFIG_CMD_EDIT=y
 CONFIG_CMD_SLEEP=y
 CONFIG_CMD_SAVEENV=y
diff --git a/arch/arm/cpu/Kconfig b/arch/arm/cpu/Kconfig
index 8ee7d6ce27..5337c46420 100644
--- a/arch/arm/cpu/Kconfig
+++ b/arch/arm/cpu/Kconfig
@@ -87,5 +87,5 @@ config ARCH_HAS_L2X0
 
 config CACHE_L2X0
 	bool "Enable L2x0 PrimeCell"
-	depends on ARCH_HAS_L2X0
+	depends on MMU && ARCH_HAS_L2X0
 
diff --git a/arch/arm/cpu/cpu.c b/arch/arm/cpu/cpu.c
index cf30789064..3df0c0f647 100644
--- a/arch/arm/cpu/cpu.c
+++ b/arch/arm/cpu/cpu.c
@@ -30,6 +30,7 @@
 #include <cache.h>
 #include <asm/mmu.h>
 #include <asm/system.h>
+#include <asm/memory.h>
 
 /**
  * Enable processor's instruction cache
@@ -89,6 +90,19 @@ void arch_shutdown(void)
 #endif
 }
 
+LIST_HEAD(memory_list);
+
+void armlinux_add_dram(struct device_d *dev)
+{
+	struct arm_memory *mem = xzalloc(sizeof(*mem));
+
+	mem->dev = dev;
+	mem->start = dev->resource[0].start;
+	mem->size = dev->resource[0].size;
+
+	list_add_tail(&mem->list, &memory_list);
+}
+
 /**
  * @page arm_boot_preparation Linux Preparation on ARM
  *
diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
index 8465d1a5a6..1f62d61b69 100644
--- a/arch/arm/cpu/mmu.c
+++ b/arch/arm/cpu/mmu.c
@@ -1,10 +1,13 @@
 #include <common.h>
 #include <init.h>
 #include <asm/mmu.h>
+#include <errno.h>
+#include <sizes.h>
+#include <asm/memory.h>
 
 static unsigned long *ttb;
 
-void arm_create_section(unsigned long virt, unsigned long phys, int size_m,
+static void create_section(unsigned long virt, unsigned long phys, int size_m,
 		unsigned int flags)
 {
 	int i;
@@ -24,6 +27,33 @@ void arm_create_section(unsigned long virt, unsigned long phys, int size_m,
 }
 
 /*
+ * Do it the simple way for now and invalidate the entire
+ * tlb
+ */
+static inline void tlb_invalidate(void)
+{
+	asm volatile (
+		"mov	r0, #0\n"
+		"mcr	p15, 0, r0, c7, c10, 4;	@ drain write buffer\n"
+		"mcr	p15, 0, r0, c8, c6, 0;  @ invalidate D TLBs\n"
+		"mcr	p15, 0, r0, c8, c5, 0;  @ invalidate I TLBs\n"
+		:
+		:
+		: "r0"
+	);
+}
+
+#ifdef CONFIG_CPU_V7
+#define PTE_FLAGS_CACHED (PTE_EXT_TEX(1) | PTE_BUFFERABLE | PTE_CACHEABLE)
+#define PTE_FLAGS_UNCACHED (0)
+#else
+#define PTE_FLAGS_CACHED (PTE_SMALL_AP_UNO_SRW | PTE_BUFFERABLE | PTE_CACHEABLE)
+#define PTE_FLAGS_UNCACHED PTE_SMALL_AP_UNO_SRW
+#endif
+
+#define PTE_MASK ((1 << 12) - 1)
+
+/*
  * Create a second level translation table for the given virtual address.
  * We initially create a flat uncached mapping on it.
  * Not yet exported, but may be later if someone finds use for it.
@@ -37,12 +67,92 @@ static u32 *arm_create_pte(unsigned long virt)
 
 	ttb[virt] = (unsigned long)table | PMD_TYPE_TABLE;
 
-	for (i = 0; i < 256; i++)
-		table[i] = virt | PTE_TYPE_SMALL | PTE_SMALL_AP_UNO_SRW;
+	for (i = 0; i < 256; i++) {
+		table[i] = virt | PTE_TYPE_SMALL | PTE_FLAGS_UNCACHED;
+		virt += PAGE_SIZE;
+	}
 
 	return table;
 }
 
+static void remap_range(void *_start, size_t size, uint32_t flags)
+{
+	u32 pteentry;
+	struct arm_memory *mem;
+	unsigned long start = (unsigned long)_start;
+	u32 *p;
+	int numentries, i;
+
+	for_each_sdram_bank(mem) {
+		if (start >= mem->start && start < mem->start + mem->size)
+			goto found;
+	}
+
+	BUG();
+	return;
+
+found:
+	pteentry = (start - mem->start) >> PAGE_SHIFT;
+
+	numentries = size >> PAGE_SHIFT;
+
+	p = mem->ptes + pteentry;
+
+	for (i = 0; i < numentries; i++) {
+		p[i] &= ~PTE_MASK;
+		p[i] |= flags | PTE_TYPE_SMALL;
+	}
+
+	dma_flush_range((unsigned long)p,
+			(unsigned long)p + numentries * sizeof(u32));
+
+	tlb_invalidate();
+}
+
+/*
+ * remap the memory bank described by mem cachable and
+ * bufferable
+ */
+static int arm_mmu_remap_sdram(struct arm_memory *mem)
+{
+	unsigned long phys = (unsigned long)mem->start;
+	unsigned long ttb_start = phys >> 20;
+	unsigned long ttb_end = (phys + mem->size) >> 20;
+	unsigned long num_ptes = mem->size >> 10;
+	int i, pte;
+
+	debug("remapping SDRAM from 0x%08lx (size 0x%08lx)\n",
+			phys, mem->size);
+
+	/*
+	 * We replace each 1MiB section in this range with second level page
+	 * tables, therefore we must have 1Mib aligment here.
+	 */
+	if ((phys & (SZ_1M - 1)) || (mem->size & (SZ_1M - 1)))
+		return -EINVAL;
+
+	mem->ptes = memalign(0x400, num_ptes * sizeof(u32));
+
+	debug("ptes: 0x%p ttb_start: 0x%08lx ttb_end: 0x%08lx\n",
+			mem->ptes, ttb_start, ttb_end);
+
+	for (i = 0; i < num_ptes; i++) {
+		mem->ptes[i] = (phys + i * 4096) | PTE_TYPE_SMALL |
+			PTE_FLAGS_CACHED;
+	}
+
+	pte = 0;
+
+	for (i = ttb_start; i < ttb_end; i++) {
+		ttb[i] = (unsigned long)(&mem->ptes[pte]) | PMD_TYPE_TABLE |
+			(0 << 4);
+		pte += 256;
+	}
+
+	tlb_invalidate();
+
+	return 0;
+}
 /*
  * We have 8 exception vectors and the table consists of absolute
  * jumps, so we need 8 * 4 bytes for the instructions and another
@@ -66,19 +176,21 @@ static void vectors_init(void)
 	memset(vectors, 0, PAGE_SIZE);
 	memcpy(vectors, &exception_vectors, ARM_VECTORS_SIZE);
 
-	exc[0] = (u32)vectors | PTE_TYPE_SMALL | PTE_SMALL_AP_UNO_SRW;
+	exc[0] = (u32)vectors | PTE_TYPE_SMALL | PTE_FLAGS_CACHED;
 }
 
 /*
- * Prepare MMU for usage and create a flat mapping. Board
- * code is responsible to remap the SDRAM cached
+ * Prepare MMU for usage enable it.
  */
-void mmu_init(void)
+static int mmu_init(void)
 {
+	struct arm_memory *mem;
 	int i;
 
 	ttb = memalign(0x10000, 0x4000);
 
+	debug("ttb: 0x%p\n", ttb);
+
 	/* Set the ttb register */
 	asm volatile ("mcr  p15,0,%0,c2,c0,0" : : "r"(ttb) /*:*/);
 
@@ -86,24 +198,38 @@ void mmu_init(void)
 	i = 0x3;
 	asm volatile ("mcr  p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
 
-	/* create a flat mapping */
-	arm_create_section(0, 0, 4096, PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT);
+	/* create a flat mapping using 1MiB sections */
+	create_section(0, 0, 4096, PMD_SECT_AP_WRITE | PMD_SECT_AP_READ |
+			PMD_TYPE_SECT);
 
 	vectors_init();
-}
 
-/*
- * enable the MMU. Should be called after mmu_init()
- */
-void mmu_enable(void)
-{
+	/*
+	 * First remap sdram cached using sections.
+	 * This is to speed up the generation of 2nd level page tables
+	 * below
+	 */
+	for_each_sdram_bank(mem)
+		create_section(mem->start, mem->start, mem->size >> 20,
+				PMD_SECT_DEF_CACHED);
+
 	asm volatile (
 		"bl __mmu_cache_on;"
 		:
 		:
 		: "r0", "r1", "r2", "r3", "r6", "r10", "r12", "cc", "memory"
         );
+
+	/*
+	 * Now that we have the MMU and caches on remap sdram again using
+	 * page tables
+	 */
+	for_each_sdram_bank(mem)
+		arm_mmu_remap_sdram(mem);
+
+	return 0;
 }
+mmu_initcall(mmu_init);
 
 struct outer_cache_fns outer_cache;
 
@@ -125,39 +251,41 @@ void mmu_disable(void)
 	);
 }
 
-/*
- * For boards which need coherent memory for DMA. The idea
- * is simple: Setup a uncached section containing your SDRAM
- * and call setup_dma_coherent() with the offset between the
- * cached and the uncached section. dma_alloc_coherent() then
- * works using normal malloc but returns the corresponding
- * pointer in the uncached area.
- */
-static unsigned long dma_coherent_offset;
-
-void setup_dma_coherent(unsigned long offset)
-{
-	dma_coherent_offset = offset;
-}
+#define PAGE_ALIGN(s) ((s) + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1);
 
 void *dma_alloc_coherent(size_t size)
 {
-	return xmemalign(4096, size) + dma_coherent_offset;
+	void *ret;
+
+	size = PAGE_ALIGN(size);
+	ret = xmemalign(4096, size);
+
+#ifdef CONFIG_MMU
+	dma_inv_range((unsigned long)ret, (unsigned long)ret + size);
+
+	remap_range(ret, size, PTE_FLAGS_UNCACHED);
+#endif
+
+	return ret;
 }
 
 unsigned long virt_to_phys(void *virt)
 {
-	return (unsigned long)virt - dma_coherent_offset;
+	return (unsigned long)virt;
 }
 
 void *phys_to_virt(unsigned long phys)
 {
-	return (void *)(phys + dma_coherent_offset);
+	return (void *)phys;
 }
 
-void dma_free_coherent(void *mem)
+void dma_free_coherent(void *mem, size_t size)
 {
-	free(mem - dma_coherent_offset);
+#ifdef CONFIG_MMU
+	remap_range(mem, size, PTE_FLAGS_CACHED);
+#endif
+
+	free(mem);
 }
 
 void dma_clean_range(unsigned long start, unsigned long end)
diff --git a/arch/arm/include/asm/armlinux.h b/arch/arm/include/asm/armlinux.h
index 3cab209d60..bb25f9a87d 100644
--- a/arch/arm/include/asm/armlinux.h
+++ b/arch/arm/include/asm/armlinux.h
@@ -1,11 +1,12 @@
 #ifndef __ARCH_ARMLINUX_H
 #define __ARCH_ARMLINUX_H
 
+#include <asm/memory.h>
+
 #if defined CONFIG_CMD_BOOTM || defined CONFIG_CMD_BOOTZ || \
 	defined CONFIG_CMD_BOOTU
 void armlinux_set_bootparams(void *params);
 void armlinux_set_architecture(int architecture);
-void armlinux_add_dram(struct device_d *dev);
 void armlinux_set_revision(unsigned int);
 void armlinux_set_serial(u64);
 #else
@@ -17,10 +18,6 @@ static inline void armlinux_set_architecture(int architecture)
 {
 }
 
-static inline void armlinux_add_dram(struct device_d *dev)
-{
-}
-
 static inline void armlinux_set_revision(unsigned int rev)
 {
 }
@@ -34,4 +31,7 @@ struct image_data;
 
 void start_linux(void *adr, int swap, struct image_data *data);
 
+struct device_d *arm_add_mem_device(const char* name, resource_size_t start,
+				    resource_size_t size);
+
 #endif /* __ARCH_ARMLINUX_H */
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index f746bc241f..93c2fe6007 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -1,16 +1,18 @@
-/*
- *  linux/include/asm-arm/memory.h
- *
- *  Copyright (C) 2000-2002 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  Note: this file should not be included by non-asm/.h files
- */
 #ifndef __ASM_ARM_MEMORY_H
 #define __ASM_ARM_MEMORY_H
 
+struct arm_memory {
+	struct list_head list;
+	struct device_d *dev;
+	u32 *ptes;
+	unsigned long start;
+	unsigned long size;
+};
+
+extern struct list_head memory_list;
+
+void armlinux_add_dram(struct device_d *dev);
+
+#define for_each_sdram_bank(mem)	list_for_each_entry(mem, &memory_list, list)
 
 #endif	/* __ASM_ARM_MEMORY_H */
diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h
index 7789cc9b23..9ca5e2ab3a 100644
--- a/arch/arm/include/asm/mmu.h
+++ b/arch/arm/include/asm/mmu.h
@@ -3,21 +3,29 @@
 
 #include <asm/pgtable.h>
 #include <malloc.h>
+#include <errno.h>
 
 #define PMD_SECT_DEF_UNCACHED (PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT)
 #define PMD_SECT_DEF_CACHED (PMD_SECT_WB | PMD_SECT_DEF_UNCACHED)
 
-void mmu_init(void);
-void mmu_enable(void);
+struct arm_memory;
+
+static inline void mmu_enable(void)
+{
+}
 void mmu_disable(void);
-void arm_create_section(unsigned long virt, unsigned long phys, int size_m,
-		unsigned int flags);
+static inline void arm_create_section(unsigned long virt, unsigned long phys, int size_m,
+		unsigned int flags)
+{
+}
 
-void setup_dma_coherent(unsigned long offset);
+static inline void setup_dma_coherent(unsigned long offset)
+{
+}
 
 #ifdef CONFIG_MMU
 void *dma_alloc_coherent(size_t size);
-void dma_free_coherent(void *mem);
+void dma_free_coherent(void *mem, size_t size);
 
 void dma_clean_range(unsigned long, unsigned long);
 void dma_flush_range(unsigned long, unsigned long);
@@ -28,10 +36,10 @@ void *phys_to_virt(unsigned long phys);
 #else
 static inline void *dma_alloc_coherent(size_t size)
 {
-	return xmalloc(size);
+	return xmemalign(4096, size);
 }
 
-static inline void dma_free_coherent(void *mem)
+static inline void dma_free_coherent(void *mem, size_t size)
 {
 	free(mem);
 }
@@ -60,7 +68,13 @@ static inline void dma_inv_range(unsigned long s, unsigned long e)
 
 #endif
 
+#ifdef CONFIG_CACHE_L2X0
 void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask);
+#else
+static inline void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
+{
+}
+#endif
 
 struct outer_cache_fns {
 	void (*inv_range)(unsigned long, unsigned long);
diff --git a/arch/arm/lib/armlinux.c b/arch/arm/lib/armlinux.c
index ce1cc6bce3..5bdbb92bff 100644
--- a/arch/arm/lib/armlinux.c
+++ b/arch/arm/lib/armlinux.c
@@ -37,11 +37,11 @@
 #include <errno.h>
 
 #include <asm/byteorder.h>
-#include <asm/global_data.h>
 #include <asm/setup.h>
 #include <asm/barebox-arm.h>
 #include <asm/armlinux.h>
 #include <asm/system.h>
+#include <asm/memory.h>
 
 static struct tag *params;
 static int armlinux_architecture = 0;
@@ -64,23 +64,16 @@ static void setup_start_tag(void)
 	params = tag_next(params);
 }
 
-struct arm_memory {
-	struct list_head list;
-	struct device_d *dev;
-};
-
-static LIST_HEAD(memory_list);
-
 static void setup_memory_tags(void)
 {
 	struct arm_memory *mem;
 
-	list_for_each_entry(mem, &memory_list, list) {
+	for_each_sdram_bank(mem) {
 		params->hdr.tag = ATAG_MEM;
 		params->hdr.size = tag_size(tag_mem32);
 
-		params->u.mem.start = mem->dev->map_base;
-		params->u.mem.size = mem->dev->size;
+		params->u.mem.start = mem->dev->resource[0].start;
+		params->u.mem.size = mem->dev->resource[0].size;
 
 		params = tag_next(params);
 	}
@@ -196,15 +189,6 @@ void armlinux_set_architecture(int architecture)
 	armlinux_architecture = architecture;
 }
 
-void armlinux_add_dram(struct device_d *dev)
-{
-	struct arm_memory *mem = xzalloc(sizeof(*mem));
-
-	mem->dev = dev;
-
-	list_add_tail(&mem->list, &memory_list);
-}
-
 void armlinux_set_revision(unsigned int rev)
 {
 	system_rev = rev;
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index b09fe70e3e..7156eeab81 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -14,7 +14,6 @@
 #include <errno.h>
 
 #include <asm/byteorder.h>
-#include <asm/global_data.h>
 #include <asm/setup.h>
 #include <asm/barebox-arm.h>
 #include <asm/armlinux.h>
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index f45008aa43..84605e4651 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -20,23 +20,9 @@
 
 #include "generic.h"
 
-static struct memory_platform_data ram_pdata = {
-	.name = "ram0",
-	.flags = DEVFS_RDWR,
-};
-
-static struct device_d sdram_dev = {
-	.id = -1,
-	.name = "mem",
-	.map_base = AT91_CHIPSELECT_1,
-	.platform_data = &ram_pdata,
-};
-
 void at91_add_device_sdram(u32 size)
 {
-	sdram_dev.size = size;
-	register_device(&sdram_dev);
-	armlinux_add_dram(&sdram_dev);
+	arm_add_mem_device("ram0", AT91_CHIPSELECT_1, size);
 }
 
 /* --------------------------------------------------------------------
@@ -44,13 +30,6 @@ void at91_add_device_sdram(u32 size)
  * -------------------------------------------------------------------- */
 
 #if defined(CONFIG_DRIVER_NET_AT91_ETHER)
-static struct device_d at91rm9200_eth_device = {
-	.id		= 0,
-	.name		= "at91_ether",
-	.map_base	= AT91_VA_BASE_EMAC,
-	.size		= 0x1000,
-};
-
 void __init at91_add_device_eth(struct at91_ether_platform_data *data)
 {
 	if (!data)
@@ -79,8 +58,8 @@ void __init at91_add_device_eth(struct at91_ether_platform_data *data)
 		at91_set_B_periph(AT91_PIN_PB12, 0);	/* ETX2 */
 	}
 
-	at91rm9200_eth_device.platform_data = data;
-	register_device(&at91rm9200_eth_device);
+	add_generic_device("at91_ether", 0, NULL, AT91_VA_BASE_EMAC, 0x1000,
+			   IORESOURCE_MEM, data);
 }
 #else
 void __init at91_add_device_eth(struct at91_ether_platform_data *data) {}
@@ -91,13 +70,6 @@ void __init at91_add_device_eth(struct at91_ether_platform_data *data) {}
  * -------------------------------------------------------------------- */
 
 #if defined(CONFIG_NAND_ATMEL)
-static struct device_d at91rm9200_nand_device = {
-	.id		= -1,
-	.name		= "atmel_nand",
-	.map_base	= AT91_CHIPSELECT_3,
-	.size		= 0x10,
-};
-
 void __init at91_add_device_nand(struct atmel_nand_data *data)
 {
 	unsigned int csa;
@@ -132,8 +104,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
 	at91_set_A_periph(AT91_PIN_PC1, 0);		/* SMOE */
 	at91_set_A_periph(AT91_PIN_PC3, 0);		/* SMWE */
 
-	at91rm9200_nand_device.platform_data = data;
-	platform_device_register(&at91rm9200_nand_device);
+	add_generic_device("atmel_nand", 0, NULL, AT91_CHIPSELECT_3, 0x10,
+			   IORESOURCE_MEM, data);
 }
 #else
 void __init at91_add_device_nand(struct atmel_nand_data *data) {}
@@ -143,26 +115,12 @@ void __init at91_add_device_nand(struct atmel_nand_data *data) {}
  *  UART
  * -------------------------------------------------------------------- */
 
-static struct device_d dbgu_serial_device = {
-	.id		= 0,
-	.name		= "atmel_serial",
-	.map_base	= (AT91_BASE_SYS + AT91_DBGU),
-	.size		= 4096,
-};
-
 static inline void configure_dbgu_pins(void)
 {
 	at91_set_A_periph(AT91_PIN_PA30, 0);		/* DRXD */
 	at91_set_A_periph(AT91_PIN_PA31, 1);		/* DTXD */
 }
 
-static struct device_d uart0_serial_device = {
-	.id		= 1,
-	.name		= "atmel_serial",
-	.map_base	= AT91RM9200_BASE_US0,
-	.size		= 4096,
-};
-
 static inline void configure_usart0_pins(unsigned pins)
 {
 	at91_set_A_periph(AT91_PIN_PA17, 1);		/* TXD0 */
@@ -180,13 +138,6 @@ static inline void configure_usart0_pins(unsigned pins)
 	}
 }
 
-static struct device_d uart1_serial_device = {
-	.id		= 2,
-	.name		= "atmel_serial",
-	.map_base	= AT91RM9200_BASE_US1,
-	.size		= 4096,
-};
-
 static inline void configure_usart1_pins(unsigned pins)
 {
 	at91_set_A_periph(AT91_PIN_PB20, 1);		/* TXD1 */
@@ -206,13 +157,6 @@ static inline void configure_usart1_pins(unsigned pins)
 		at91_set_A_periph(AT91_PIN_PB26, 0);	/* RTS1 */
 }
 
-static struct device_d uart2_serial_device = {
-	.id		= 3,
-	.name		= "atmel_serial",
-	.map_base	= AT91RM9200_BASE_US2,
-	.size		= 4096,
-};
-
 static inline void configure_usart2_pins(unsigned pins)
 {
 	at91_set_A_periph(AT91_PIN_PA22, 0);		/* RXD2 */
@@ -224,13 +168,6 @@ static inline void configure_usart2_pins(unsigned pins)
 		at91_set_B_periph(AT91_PIN_PA31, 0);	/* RTS2 */
 }
 
-static struct device_d uart3_serial_device = {
-	.id		= 4,
-	.name		= "atmel_serial",
-	.map_base	= AT91RM9200_BASE_US3,
-	.size		= 4096,
-};
-
 static inline void configure_usart3_pins(unsigned pins)
 {
 	at91_set_B_periph(AT91_PIN_PA5, 1);		/* TXD3 */
@@ -244,33 +181,46 @@ static inline void configure_usart3_pins(unsigned pins)
 
 void __init at91_register_uart(unsigned id, unsigned pins)
 {
+	resource_size_t start;
+	struct device_d *dev;
+	char* clk_name;
+
 	switch (id) {
 		case 0:		/* DBGU */
 			configure_dbgu_pins();
-			at91_clock_associate("mck", &dbgu_serial_device, "usart");
-			register_device(&dbgu_serial_device);
+			start = AT91_BASE_SYS + AT91_DBGU;
+			clk_name = "mck";
+			id = 0;
 			break;
 		case AT91RM9200_ID_US0:
 			configure_usart0_pins(pins);
-			at91_clock_associate("usart0_clk", &uart0_serial_device, "usart");
+			clk_name = "usart0_clk";
+			start = AT91RM9200_BASE_US0;
+			id = 1;
 			break;
 		case AT91RM9200_ID_US1:
 			configure_usart1_pins(pins);
-			at91_clock_associate("usart1_clk", &uart1_serial_device, "usart");
-			register_device(&uart1_serial_device);
+			clk_name = "usart1_clk";
+			start = AT91RM9200_BASE_US1;
+			id = 2;
 			break;
 		case AT91RM9200_ID_US2:
 			configure_usart2_pins(pins);
-			at91_clock_associate("usart2_clk", &uart2_serial_device, "usart");
-			register_device(&uart2_serial_device);
+			clk_name = "usart2_clk";
+			start = AT91RM9200_BASE_US2;
+			id = 3;
 			break;
 		case AT91RM9200_ID_US3:
 			configure_usart3_pins(pins);
-			at91_clock_associate("usart3_clk", &uart3_serial_device, "usart");
-			register_device(&uart3_serial_device);
+			clk_name = "usart3_clk";
+			start = AT91RM9200_BASE_US3;
+			id = 4;
 			break;
 		default:
 			return;
 	}
 
+	dev = add_generic_device("atmel_serial", id, NULL, start, 4096,
+			   IORESOURCE_MEM, NULL);
+	at91_clock_associate(clk_name, dev, "usart");
 }
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index d44e280907..5c1bbbe464 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -21,33 +21,12 @@
 
 #include "generic.h"
 
-static struct memory_platform_data sram_pdata = {
-	.name = "sram0",
-	.flags = DEVFS_RDWR,
-};
-
-static struct device_d sdram_dev = {
-	.id	  = -1,
-	.name     = "mem",
-	.map_base = AT91_CHIPSELECT_1,
-	.platform_data = &sram_pdata,
-};
-
 void at91_add_device_sdram(u32 size)
 {
-	sdram_dev.size = size;
-	register_device(&sdram_dev);
-	armlinux_add_dram(&sdram_dev);
+	arm_add_mem_device("ram0", AT91_CHIPSELECT_1, size);
 }
 
 #if defined(CONFIG_DRIVER_NET_MACB)
-static struct device_d macb_dev = {
-	.id	  = -1,
-	.name     = "macb",
-	.map_base = AT91SAM9260_BASE_EMAC,
-	.size     = 0x1000,
-};
-
 void at91_add_device_eth(struct at91_ether_platform_data *data)
 {
 	if (!data)
@@ -76,21 +55,14 @@ void at91_add_device_eth(struct at91_ether_platform_data *data)
 		at91_set_B_periph(AT91_PIN_PA22, 0);	/* ETXER */
 	}
 
-	macb_dev.platform_data = data;
-	register_device(&macb_dev);
+	add_generic_device("macb", 0, NULL, AT91SAM9260_BASE_EMAC, 0x1000,
+			   IORESOURCE_MEM, data);
 }
 #else
 void at91_add_device_eth(struct at91_ether_platform_data *data) {}
 #endif
 
 #if defined(CONFIG_NAND_ATMEL)
-static struct device_d nand_dev = {
-	.id	  = -1,
-	.name     = "atmel_nand",
-	.map_base = AT91_CHIPSELECT_3,
-	.size     = 0x10,
-};
-
 void at91_add_device_nand(struct atmel_nand_data *data)
 {
 	unsigned long csa;
@@ -113,33 +85,19 @@ void at91_add_device_nand(struct atmel_nand_data *data)
 	if (data->det_pin)
 		at91_set_gpio_input(data->det_pin, 1);
 
-	nand_dev.platform_data = data;
-	register_device(&nand_dev);
+	add_generic_device("atmel_nand", 0, NULL, AT91_CHIPSELECT_3, 0x10,
+			   IORESOURCE_MEM, data);
 }
 #else
 void at91_add_device_nand(struct atmel_nand_data *data) {}
 #endif
 
-static struct device_d dbgu_serial_device = {
-	.id	  = 0,
-	.name     = "atmel_serial",
-	.map_base = AT91_BASE_SYS + AT91_DBGU,
-	.size     = 4096,
-};
-
 static inline void configure_dbgu_pins(void)
 {
 	at91_set_A_periph(AT91_PIN_PB14, 0);		/* DRXD */
 	at91_set_A_periph(AT91_PIN_PB15, 1);		/* DTXD */
 }
 
-static struct device_d uart0_serial_device = {
-	.id	  = 1,
-	.name     = "atmel_serial",
-	.map_base = AT91SAM9260_BASE_US0,
-	.size     = 4096,
-};
-
 static inline void configure_usart0_pins(unsigned pins)
 {
 	at91_set_A_periph(AT91_PIN_PB4, 1);		/* TXD0 */
@@ -159,13 +117,6 @@ static inline void configure_usart0_pins(unsigned pins)
 		at91_set_A_periph(AT91_PIN_PB25, 0);	/* RI0 */
 }
 
-static struct device_d uart1_serial_device = {
-	.id	  = 2,
-	.name     = "atmel_serial",
-	.map_base = AT91SAM9260_BASE_US1,
-	.size     = 4096,
-};
-
 static inline void configure_usart1_pins(unsigned pins)
 {
 	at91_set_A_periph(AT91_PIN_PB6, 1);		/* TXD1 */
@@ -177,13 +128,6 @@ static inline void configure_usart1_pins(unsigned pins)
 		at91_set_A_periph(AT91_PIN_PB29, 0);	/* CTS1 */
 }
 
-static struct device_d uart2_serial_device = {
-	.id	  = 3,
-	.name     = "atmel_serial",
-	.map_base = AT91SAM9260_BASE_US2,
-	.size     = 4096,
-};
-
 static inline void configure_usart2_pins(unsigned pins)
 {
 	at91_set_A_periph(AT91_PIN_PB8, 1);		/* TXD2 */
@@ -195,13 +139,6 @@ static inline void configure_usart2_pins(unsigned pins)
 		at91_set_A_periph(AT91_PIN_PA5, 0);	/* CTS2 */
 }
 
-static struct device_d uart3_serial_device = {
-	.id	  = 4,
-	.name     = "atmel_serial",
-	.map_base = AT91SAM9260_BASE_US3,
-	.size     = 4096,
-};
-
 static inline void configure_usart3_pins(unsigned pins)
 {
 	at91_set_A_periph(AT91_PIN_PB10, 1);		/* TXD3 */
@@ -213,26 +150,12 @@ static inline void configure_usart3_pins(unsigned pins)
 		at91_set_B_periph(AT91_PIN_PC10, 0);	/* CTS3 */
 }
 
-static struct device_d uart4_serial_device = {
-	.id	  = 5,
-	.name     = "atmel_serial",
-	.map_base = AT91SAM9260_BASE_US4,
-	.size     = 4096,
-};
-
 static inline void configure_usart4_pins(void)
 {
 	at91_set_B_periph(AT91_PIN_PA31, 1);		/* TXD4 */
 	at91_set_B_periph(AT91_PIN_PA30, 0);		/* RXD4 */
 }
 
-static struct device_d uart5_serial_device = {
-	.id	  = 6,
-	.name     = "atmel_serial",
-	.map_base = AT91SAM9260_BASE_US5,
-	.size     = 4096,
-};
-
 static inline void configure_usart5_pins(void)
 {
 	at91_set_A_periph(AT91_PIN_PB12, 1);		/* TXD5 */
@@ -241,58 +164,68 @@ static inline void configure_usart5_pins(void)
 
 void at91_register_uart(unsigned id, unsigned pins)
 {
+	resource_size_t start;
+	struct device_d *dev;
+	char* clk_name;
+
 	switch (id) {
 		case 0:		/* DBGU */
 			configure_dbgu_pins();
-			at91_clock_associate("mck", &dbgu_serial_device, "usart");
-			register_device(&dbgu_serial_device);
+			start = AT91_BASE_SYS + AT91_DBGU;
+			clk_name = "mck";
+			id = 0;
 			break;
 		case AT91SAM9260_ID_US0:
 			configure_usart0_pins(pins);
-			at91_clock_associate("usart0_clk", &uart0_serial_device, "usart");
-			register_device(&uart0_serial_device);
+			clk_name = "usart0_clk";
+			start = AT91SAM9260_BASE_US0;
+			id = 1;
 			break;
 		case AT91SAM9260_ID_US1:
 			configure_usart1_pins(pins);
-			at91_clock_associate("usart1_clk", &uart1_serial_device, "usart");
-			register_device(&uart1_serial_device);
+			clk_name = "usart1_clk";
+			start = AT91SAM9260_BASE_US1;
+			id = 2;
 			break;
 		case AT91SAM9260_ID_US2:
 			configure_usart2_pins(pins);
-			at91_clock_associate("usart2_clk", &uart2_serial_device, "usart");
-			register_device(&uart2_serial_device);
+			clk_name = "usart2_clk";
+			start = AT91SAM9260_BASE_US2;
+			id = 3;
 			break;
 		case AT91SAM9260_ID_US3:
 			configure_usart3_pins(pins);
-			at91_clock_associate("usart3_clk", &uart3_serial_device, "usart");
-			register_device(&uart3_serial_device);
+			clk_name = "usart3_clk";
+			start = AT91SAM9260_BASE_US3;
+			id = 4;
 			break;
 		case AT91SAM9260_ID_US4:
 			configure_usart4_pins();
-			at91_clock_associate("usart4_clk", &uart4_serial_device, "usart");
-			register_device(&uart4_serial_device);
+			clk_name = "usart4_clk";
+			start = AT91SAM9260_BASE_US4;
+			id = 5;
 			break;
 		case AT91SAM9260_ID_US5:
 			configure_usart5_pins();
-			at91_clock_associate("usart5_clk", &uart5_serial_device, "usart");
-			register_device(&uart5_serial_device);
+			clk_name = "usart5_clk";
+			start = AT91SAM9260_BASE_US5;
+			id = 6;
 			break;
 		default:
 			return;
 	}
+
+	dev = add_generic_device("atmel_serial", id, NULL, start, 4096,
+			   IORESOURCE_MEM, NULL);
+	at91_clock_associate(clk_name, dev, "usart");
 }
 
 #if defined(CONFIG_MCI_ATMEL)
-static struct device_d mci_device = {
-	.id		= -1,
-	.name		= "atmel_mci",
-	.map_base	= AT91SAM9260_BASE_MCI,
-	.size		= SZ_16K,
-};
-
 /* Consider only one slot : slot 0 */
 void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
 {
+	struct device_d *dev;
+
 	if (!data)
 		return;
 
@@ -323,9 +256,9 @@ void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
 		at91_set_A_periph(AT91_PIN_PA11, 1);
 	}
 
-	mci_device.platform_data = data;
-	at91_clock_associate("mci_clk", &mci_device, "mci_clk");
-	register_device(&mci_device);
+	dev = add_generic_device("atmel_mci", 0, NULL, AT91SAM9260_BASE_MCI, SZ_16K,
+			   IORESOURCE_MEM, data);
+	at91_clock_associate("mci_clk", dev, "mci_clk");
 }
 #else
 void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data) {}
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index d8b70a37e6..4985cf1542 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -21,33 +21,12 @@
 
 #include "generic.h"
 
-static struct memory_platform_data ram_pdata = {
-	.name = "ram0",
-	.flags = DEVFS_RDWR,
-};
-
-static struct device_d sdram_dev = {
-	.id		= -1,
-	.name		= "mem",
-	.map_base	= AT91_CHIPSELECT_1,
-	.platform_data	= &ram_pdata,
-};
-
 void at91_add_device_sdram(u32 size)
 {
-	sdram_dev.size = size;
-	register_device(&sdram_dev);
-	armlinux_add_dram(&sdram_dev);
+	arm_add_mem_device("ram0", AT91_CHIPSELECT_1, size);
 }
 
 #if defined(CONFIG_NAND_ATMEL)
-static struct device_d nand_dev = {
-	.id		= 0,
-	.name		= "atmel_nand",
-	.map_base	= AT91_CHIPSELECT_3,
-	.size		= 0x10,
-};
-
 void at91_add_device_nand(struct atmel_nand_data *data)
 {
 	unsigned long csa;
@@ -73,33 +52,19 @@ void at91_add_device_nand(struct atmel_nand_data *data)
 	at91_set_A_periph(AT91_PIN_PC0, 0);		/* NANDOE */
 	at91_set_A_periph(AT91_PIN_PC1, 0);		/* NANDWE */
 
-	nand_dev.platform_data = data;
-	register_device(&nand_dev);
+	add_generic_device("atmel_nand", 0, NULL, AT91_CHIPSELECT_3, 0x10,
+			   IORESOURCE_MEM, data);
 }
 #else
 void at91_add_device_nand(struct atmel_nand_data *data) {}
 #endif
 
-static struct device_d dbgu_serial_device = {
-	.id		= 0,
-	.name		= "atmel_serial",
-	.map_base	= (AT91_BASE_SYS + AT91_DBGU),
-	.size		= 4096,
-};
-
 static inline void configure_dbgu_pins(void)
 {
 	at91_set_A_periph(AT91_PIN_PA9, 0);		/* DRXD */
 	at91_set_A_periph(AT91_PIN_PA10, 1);		/* DTXD */
 }
 
-static struct device_d uart0_serial_device = {
-	.id		= 1,
-	.name		= "atmel_serial",
-	.map_base	= AT91SAM9261_BASE_US0,
-	.size		= 4096,
-};
-
 static inline void configure_usart0_pins(unsigned pins)
 {
 	at91_set_A_periph(AT91_PIN_PC8, 1);		/* TXD0 */
@@ -111,13 +76,6 @@ static inline void configure_usart0_pins(unsigned pins)
 		at91_set_A_periph(AT91_PIN_PC11, 0);	/* CTS0 */
 }
 
-static struct device_d uart1_serial_device = {
-	.id		= 2,
-	.name		= "atmel_serial",
-	.map_base	= AT91SAM9261_BASE_US1,
-	.size		= 4096,
-};
-
 static inline void configure_usart1_pins(unsigned pins)
 {
 	at91_set_A_periph(AT91_PIN_PC12, 1);		/* TXD1 */
@@ -129,13 +87,6 @@ static inline void configure_usart1_pins(unsigned pins)
 		at91_set_B_periph(AT91_PIN_PA13, 0);	/* CTS1 */
 }
 
-static struct device_d uart2_serial_device = {
-	.id		= 3,
-	.name		= "atmel_serial",
-	.map_base	= AT91SAM9261_BASE_US2,
-	.size		= 4096,
-};
-
 static inline void configure_usart2_pins(unsigned pins)
 {
 	at91_set_A_periph(AT91_PIN_PC15, 0);		/* RXD2 */
@@ -149,43 +100,50 @@ static inline void configure_usart2_pins(unsigned pins)
 
 void at91_register_uart(unsigned id, unsigned pins)
 {
+	resource_size_t start;
+	struct device_d *dev;
+	char* clk_name;
+
 	switch (id) {
 		case 0:		/* DBGU */
 			configure_dbgu_pins();
-			at91_clock_associate("mck", &dbgu_serial_device, "usart");
-			register_device(&dbgu_serial_device);
+			start = AT91_BASE_SYS + AT91_DBGU;
+			clk_name = "mck";
+			id = 0;
 			break;
 		case AT91SAM9261_ID_US0:
 			configure_usart0_pins(pins);
-			at91_clock_associate("usart0_clk", &uart0_serial_device, "usart");
-			register_device(&uart0_serial_device);
+			clk_name = "usart0_clk";
+			start = AT91SAM9261_BASE_US0;
+			id = 1;
 			break;
 		case AT91SAM9261_ID_US1:
 			configure_usart1_pins(pins);
-			at91_clock_associate("usart1_clk", &uart1_serial_device, "usart");
-			register_device(&uart1_serial_device);
+			clk_name = "usart1_clk";
+			start = AT91SAM9261_BASE_US1;
+			id = 2;
 			break;
 		case AT91SAM9261_ID_US2:
 			configure_usart2_pins(pins);
-			at91_clock_associate("usart2_clk", &uart2_serial_device, "usart");
-			register_device(&uart2_serial_device);
+			clk_name = "usart3_clk";
+			start = AT91SAM9261_BASE_US2;
+			id = 3;
 			break;
 		default:
 			return;
 	}
+
+	dev = add_generic_device("atmel_serial", id, NULL, start, 4096,
+			   IORESOURCE_MEM, NULL);
+	at91_clock_associate(clk_name, dev, "usart");
 }
 
 #if defined(CONFIG_MCI_ATMEL)
-static struct device_d mci_device = {
-	.id		= -1,
-	.name		= "atmel_mci",
-	.map_base	= AT91SAM9261_BASE_MCI,
-	.size		= SZ_16K,
-};
-
 /* Consider only one slot : slot 0 */
 void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
 {
+	struct device_d *dev;
+
 	if (!data)
 		return;
 
@@ -216,9 +174,9 @@ void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
 		at91_set_B_periph(AT91_PIN_PA6, 1);
 	}
 
-	mci_device.platform_data = data;
-	at91_clock_associate("mci_clk", &mci_device, "mci_clk");
-	register_device(&mci_device);
+	dev = add_generic_device("atmel_mci", 0, NULL, AT91SAM9261_BASE_MCI, SZ_16K,
+			   IORESOURCE_MEM, data);
+	at91_clock_associate("mci_clk", dev, "mci_clk");
 }
 #else
 void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data) {}
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index 04fb79e359..540220eebf 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -21,33 +21,12 @@
 
 #include "generic.h"
 
-static struct memory_platform_data ram_pdata = {
-	.name = "ram0",
-	.flags = DEVFS_RDWR,
-};
-
-static struct device_d sdram_dev = {
-	.id	  = -1,
-	.name     = "mem",
-	.map_base = AT91_CHIPSELECT_1,
-	.platform_data = &ram_pdata,
-};
-
 void at91_add_device_sdram(u32 size)
 {
-	sdram_dev.size = size;
-	register_device(&sdram_dev);
-	armlinux_add_dram(&sdram_dev);
+	arm_add_mem_device("ram0", AT91_CHIPSELECT_1, size);
 }
 
 #if defined(CONFIG_DRIVER_NET_MACB)
-static struct device_d macb_dev = {
-	.id	  = -1,
-	.name     = "macb",
-	.map_base = AT91SAM9263_BASE_EMAC,
-	.size     = 0x1000,
-};
-
 void at91_add_device_eth(struct at91_ether_platform_data *data)
 {
 	if (!data)
@@ -75,21 +54,14 @@ void at91_add_device_eth(struct at91_ether_platform_data *data)
 		at91_set_B_periph(AT91_PIN_PC24, 0);	/* ETXER */
 	}
 
-	macb_dev.platform_data = data;
-	register_device(&macb_dev);
+	add_generic_device("macb", 0, NULL, AT91SAM9263_BASE_EMAC, 0x1000,
+			   IORESOURCE_MEM, data);
 }
 #else
 void at91_add_device_eth(struct at91_ether_platform_data *data) {}
 #endif
 
 #if defined(CONFIG_NAND_ATMEL)
-static struct device_d nand_dev = {
-	.id	  = -1,
-	.name     = "atmel_nand",
-	.map_base = AT91_CHIPSELECT_3,
-	.size     = 0x10,
-};
-
 void at91_add_device_nand(struct atmel_nand_data *data)
 {
 	unsigned long csa;
@@ -112,33 +84,19 @@ void at91_add_device_nand(struct atmel_nand_data *data)
 	if (data->det_pin)
 		at91_set_gpio_input(data->det_pin, 1);
 
-	nand_dev.platform_data = data;
-	register_device(&nand_dev);
+	add_generic_device("atmel_nand", -1, NULL, AT91_CHIPSELECT_3, 0x10,
+			   IORESOURCE_MEM, data);
 }
 #else
 void at91_add_device_nand(struct atmel_nand_data *data) {}
 #endif
 
-static struct device_d dbgu_serial_device = {
-	.id	  = 0,
-	.name     = "atmel_serial",
-	.map_base = (AT91_BASE_SYS + AT91_DBGU),
-	.size     = 4096,
-};
-
 static inline void configure_dbgu_pins(void)
 {
 	at91_set_A_periph(AT91_PIN_PC30, 0);		/* DRXD */
 	at91_set_A_periph(AT91_PIN_PC31, 1);		/* DTXD */
 }
 
-static struct device_d uart0_serial_device = {
-	.id	  = 1,
-	.name     = "atmel_serial",
-	.map_base = AT91SAM9263_BASE_US0,
-	.size     = 4096,
-};
-
 static inline void configure_usart0_pins(unsigned pins)
 {
 	at91_set_A_periph(AT91_PIN_PA26, 1);		/* TXD0 */
@@ -150,13 +108,6 @@ static inline void configure_usart0_pins(unsigned pins)
 		at91_set_A_periph(AT91_PIN_PA29, 0);	/* CTS0 */
 }
 
-static struct device_d uart1_serial_device = {
-	.id	  = 2,
-	.name     = "atmel_serial",
-	.map_base = AT91SAM9263_BASE_US1,
-	.size     = 4096,
-};
-
 static inline void configure_usart1_pins(unsigned pins)
 {
 	at91_set_A_periph(AT91_PIN_PD0, 1);		/* TXD1 */
@@ -168,13 +119,6 @@ static inline void configure_usart1_pins(unsigned pins)
 		at91_set_B_periph(AT91_PIN_PD8, 0);	/* CTS1 */
 }
 
-static struct device_d uart2_serial_device = {
-	.id	  = 3,
-	.name     = "atmel_serial",
-	.map_base = AT91SAM9263_BASE_US2,
-	.size     = 4096,
-};
-
 static inline void configure_usart2_pins(unsigned pins)
 {
 	at91_set_A_periph(AT91_PIN_PD2, 1);		/* TXD2 */
@@ -188,51 +132,53 @@ static inline void configure_usart2_pins(unsigned pins)
 
 void at91_register_uart(unsigned id, unsigned pins)
 {
+	resource_size_t start;
+	struct device_d *dev;
+	char* clk_name;
+
 	switch (id) {
 		case 0:		/* DBGU */
 			configure_dbgu_pins();
-			at91_clock_associate("mck", &dbgu_serial_device, "usart");
-			register_device(&dbgu_serial_device);
+			start = AT91_BASE_SYS + AT91_DBGU;
+			clk_name = "mck";
+			id = 0;
 			break;
 		case AT91SAM9263_ID_US0:
 			configure_usart0_pins(pins);
-			at91_clock_associate("usart0_clk", &uart0_serial_device, "usart");
-			register_device(&uart0_serial_device);
+			clk_name = "usart0_clk";
+			start = AT91SAM9263_BASE_US0;
+			id = 1;
 			break;
 		case AT91SAM9263_ID_US1:
 			configure_usart1_pins(pins);
-			at91_clock_associate("usart1_clk", &uart1_serial_device, "usart");
-			register_device(&uart1_serial_device);
+			clk_name = "usart1_clk";
+			start = AT91SAM9263_BASE_US1;
+			id = 2;
 			break;
 		case AT91SAM9263_ID_US2:
 			configure_usart2_pins(pins);
-			at91_clock_associate("usart2_clk", &uart2_serial_device, "usart");
-			register_device(&uart2_serial_device);
+			clk_name = "usart2_clk";
+			start = AT91SAM9263_BASE_US2;
+			id = 3;
 			break;
 		default:
 			return;
 	}
 
+	dev = add_generic_device("atmel_serial", id, NULL, start, 4096,
+			   IORESOURCE_MEM, NULL);
+	at91_clock_associate(clk_name, dev, "usart");
+
 }
 
 #if defined(CONFIG_MCI_ATMEL)
-static struct device_d mci0_device = {
-	.id		= 0,
-	.name		= "atmel_mci",
-	.map_base	= AT91SAM9263_BASE_MCI0,
-	.size		= SZ_16K,
-};
-
-static struct device_d mci1_device = {
-	.id		= 1,
-	.name		= "atmel_mci",
-	.map_base	= AT91SAM9263_BASE_MCI1,
-	.size		= SZ_16K,
-};
-
 /* Consider only one slot : slot 0 */
 void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
 {
+	resource_size_t start;
+	struct device_d *dev;
+	char* clk_name;
+
 	if (!data)
 		return;
 
@@ -250,6 +196,8 @@ void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
 		at91_set_gpio_input(data->wp_pin, 1);
 
 	if (mmc_id == 0) {		/* MCI0 */
+		start = AT91SAM9263_BASE_MCI0;
+		clk_name = "mci0_clk";
 		/* CLK */
 		at91_set_A_periph(AT91_PIN_PA12, 0);
 
@@ -263,12 +211,9 @@ void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
 			at91_set_A_periph(AT91_PIN_PA4, 1);
 			at91_set_A_periph(AT91_PIN_PA5, 1);
 		}
-
-		mci0_device.platform_data = data;
-		at91_clock_associate("mci0_clk", &mci0_device, "mci_clk");
-		register_device(&mci0_device);
-
 	} else {			/* MCI1 */
+		start = AT91SAM9263_BASE_MCI1;
+		clk_name = "mci1_clk";
 		/* CLK */
 		at91_set_A_periph(AT91_PIN_PA6, 0);
 
@@ -282,11 +227,11 @@ void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
 			at91_set_A_periph(AT91_PIN_PA10, 1);
 			at91_set_A_periph(AT91_PIN_PA11, 1);
 		}
-
-		mci1_device.platform_data = data;
-		at91_clock_associate("mci1_clk", &mci1_device, "mci_clk");
-		register_device(&mci1_device);
 	}
+
+	dev = add_generic_device("atmel_mci", mmc_id, NULL, start, 4096,
+			   IORESOURCE_MEM, data);
+	at91_clock_associate(clk_name, dev, "mci_clk");
 }
 #else
 void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data) {}
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index a474bd74e2..2cd5a952b5 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -21,33 +21,12 @@
 
 #include "generic.h"
 
-static struct memory_platform_data ram_pdata = {
-	.name = "ram0",
-	.flags = DEVFS_RDWR,
-};
-
-static struct device_d sdram_dev = {
-	.id		= -1,
-	.name		= "mem",
-	.map_base	= AT91_CHIPSELECT_6,
-	.platform_data	= &ram_pdata,
-};
-
 void at91_add_device_sdram(u32 size)
 {
-	sdram_dev.size = size;
-	register_device(&sdram_dev);
-	armlinux_add_dram(&sdram_dev);
+	arm_add_mem_device("ram0", AT91_CHIPSELECT_6, size);
 }
 
 #if defined(CONFIG_DRIVER_NET_MACB)
-static struct device_d macb_dev = {
-	.id		= 0,
-	.name		= "macb",
-	.map_base	= AT91SAM9G45_BASE_EMAC,
-	.size		= 0x1000,
-};
-
 void at91_add_device_eth(struct at91_ether_platform_data *data)
 {
 	if (!data)
@@ -76,21 +55,14 @@ void at91_add_device_eth(struct at91_ether_platform_data *data)
 		at91_set_B_periph(AT91_PIN_PA27, 0);	/* ETXER */
 	}
 
-	macb_dev.platform_data = data;
-	register_device(&macb_dev);
+	add_generic_device("macb", 0, NULL, AT91SAM9G45_BASE_EMAC, 0x1000,
+			   IORESOURCE_MEM, data);
 }
 #else
 void at91_add_device_eth(struct at91_ether_platform_data *data) {}
 #endif
 
 #if defined(CONFIG_NAND_ATMEL)
-static struct device_d nand_dev = {
-	.id		= -1,
-	.name		= "atmel_nand",
-	.map_base	= AT91_CHIPSELECT_3,
-	.size		= 0x10,
-};
-
 void at91_add_device_nand(struct atmel_nand_data *data)
 {
 	unsigned long csa;
@@ -116,33 +88,19 @@ void at91_add_device_nand(struct atmel_nand_data *data)
 	if (data->det_pin)
 		at91_set_gpio_input(data->det_pin, 1);
 
-	nand_dev.platform_data = data;
-	register_device(&nand_dev);
+	add_generic_device("atmel_nand", -1, NULL, AT91_CHIPSELECT_3, 0x10,
+			   IORESOURCE_MEM, data);
 }
 #else
 void at91_add_device_nand(struct atmel_nand_data *data) {}
 #endif
 
-static struct device_d dbgu_serial_device = {
-	.id	  = -1,
-	.name     = "atmel_serial",
-	.map_base = (AT91_BASE_SYS + AT91_DBGU),
-	.size     = 4096,
-};
-
 static inline void configure_dbgu_pins(void)
 {
 	at91_set_A_periph(AT91_PIN_PB12, 0);		/* DRXD */
 	at91_set_A_periph(AT91_PIN_PB13, 1);		/* DTXD */
 }
 
-static struct device_d uart0_serial_device = {
-	.id	  = -1,
-	.name     = "atmel_serial",
-	.map_base = AT91SAM9G45_BASE_US0,
-	.size     = 4096,
-};
-
 static inline void configure_usart0_pins(unsigned pins)
 {
 	at91_set_A_periph(AT91_PIN_PB19, 1);		/* TXD0 */
@@ -154,13 +112,6 @@ static inline void configure_usart0_pins(unsigned pins)
 		at91_set_B_periph(AT91_PIN_PB15, 0);	/* CTS0 */
 }
 
-static struct device_d uart1_serial_device = {
-	.id	  = -1,
-	.name     = "atmel_serial",
-	.map_base = AT91SAM9G45_BASE_US1,
-	.size     = 4096,
-};
-
 static inline void configure_usart1_pins(unsigned pins)
 {
 	at91_set_A_periph(AT91_PIN_PB4, 1);		/* TXD1 */
@@ -172,13 +123,6 @@ static inline void configure_usart1_pins(unsigned pins)
 		at91_set_A_periph(AT91_PIN_PD17, 0);	/* CTS1 */
 }
 
-static struct device_d uart2_serial_device = {
-	.id	  = -1,
-	.name     = "atmel_serial",
-	.map_base = AT91SAM9G45_BASE_US2,
-	.size     = 4096,
-};
-
 static inline void configure_usart2_pins(unsigned pins)
 {
 	at91_set_A_periph(AT91_PIN_PB6, 1);		/* TXD2 */
@@ -190,13 +134,6 @@ static inline void configure_usart2_pins(unsigned pins)
 		at91_set_B_periph(AT91_PIN_PC11, 0);	/* CTS2 */
 }
 
-static struct device_d uart3_serial_device = {
-	.id	  = -1,
-	.name     = "atmel_serial",
-	.map_base = AT91SAM9G45_ID_US3,
-	.size     = 4096,
-};
-
 static inline void configure_usart3_pins(unsigned pins)
 {
 	at91_set_A_periph(AT91_PIN_PB8, 1);		/* TXD3 */
@@ -210,56 +147,59 @@ static inline void configure_usart3_pins(unsigned pins)
 
 void at91_register_uart(unsigned id, unsigned pins)
 {
+	resource_size_t start;
+	struct device_d *dev;
+	char* clk_name;
+
 	switch (id) {
 		case 0:		/* DBGU */
 			configure_dbgu_pins();
-			at91_clock_associate("mck", &dbgu_serial_device, "usart");
-			register_device(&dbgu_serial_device);
+			start = AT91_BASE_SYS + AT91_DBGU;
+			clk_name = "mck";
+			id = 0;
 			break;
 		case AT91SAM9G45_ID_US0:
 			configure_usart0_pins(pins);
-			at91_clock_associate("usart0_clk", &uart0_serial_device, "usart");
-			register_device(&uart0_serial_device);
+			clk_name = "usart0_clk";
+			start = AT91SAM9G45_BASE_US0;
+			id = 1;
 			break;
 		case AT91SAM9G45_ID_US1:
 			configure_usart1_pins(pins);
-			at91_clock_associate("usart1_clk", &uart1_serial_device, "usart");
-			register_device(&uart1_serial_device);
+			clk_name = "usart1_clk";
+			start = AT91SAM9G45_BASE_US1;
+			id = 2;
 			break;
 		case AT91SAM9G45_ID_US2:
 			configure_usart2_pins(pins);
-			at91_clock_associate("usart2_clk", &uart2_serial_device, "usart");
-			register_device(&uart2_serial_device);
+			clk_name = "usart2_clk";
+			start = AT91SAM9G45_BASE_US2;
+			id = 3;
 			break;
 		case AT91SAM9G45_ID_US3:
 			configure_usart3_pins(pins);
-			at91_clock_associate("usart3_clk", &uart2_serial_device, "usart");
-			register_device(&uart3_serial_device);
+			clk_name = "usart3_clk";
+			start = AT91SAM9G45_BASE_US3;
+			id = 4;
 			break;
 		default:
 			return;
 	}
 
+	dev = add_generic_device("atmel_serial", id, NULL, start, 4096,
+			   IORESOURCE_MEM, NULL);
+	at91_clock_associate(clk_name, dev, "usart");
+
 }
 
 #if defined(CONFIG_MCI_ATMEL)
-static struct device_d mci0_device = {
-	.id		= 0,
-	.name		= "atmel_mci",
-	.map_base	= AT91SAM9G45_BASE_MCI0,
-	.size		= SZ_16K,
-};
-
-static struct device_d mci1_device = {
-	.id		= 1,
-	.name		= "atmel_mci",
-	.map_base	= AT91SAM9G45_BASE_MCI1,
-	.size		= SZ_16K,
-};
-
 /* Consider only one slot : slot 0 */
 void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
 {
+	resource_size_t start;
+	struct device_d *dev;
+	char* clk_name;
+
 	if (!data)
 		return;
 
@@ -277,6 +217,8 @@ void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
 		at91_set_gpio_input(data->wp_pin, 1);
 
 	if (mmc_id == 0) {		/* MCI0 */
+		start = AT91SAM9G45_BASE_MCI0;
+		clk_name = "mci0_clk";
 		/* CLK */
 		at91_set_A_periph(AT91_PIN_PA0, 0);
 
@@ -296,12 +238,9 @@ void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
 				at91_set_A_periph(AT91_PIN_PA9, 1);
 			}
 		}
-
-		mci0_device.platform_data = data;
-		at91_clock_associate("mci0_clk", &mci0_device, "mci_clk");
-		register_device(&mci0_device);
-
 	} else {			/* MCI1 */
+		start = AT91SAM9G45_BASE_MCI1;
+		clk_name = "mci1_clk";
 		/* CLK */
 		at91_set_A_periph(AT91_PIN_PA31, 0);
 
@@ -321,11 +260,11 @@ void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
 				at91_set_A_periph(AT91_PIN_PA30, 1);
 			}
 		}
-
-		mci1_device.platform_data = data;
-		at91_clock_associate("mci1_clk", &mci1_device, "mci_clk");
-		register_device(&mci1_device);
 	}
+
+	dev = add_generic_device("atmel_mci", mmc_id, NULL, start, 4096,
+			   IORESOURCE_MEM, data);
+	at91_clock_associate(clk_name, dev, "mci_clk");
 }
 #else
 void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data) {}
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index f497d35f63..8dc6a24fb5 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -19,6 +19,7 @@ config ARCH_TEXT_BASE
 	default 0x08f80000 if MACH_SCB9328
 	default 0xa7e00000 if MACH_NESO
 	default 0x97f00000 if MACH_MX51_PDK
+	default 0x7ff00000 if MACH_MX53_LOCO
 	default 0x87f00000 if MACH_GUF_CUPID
 	default 0x93d00000 if MACH_TX25
 
@@ -38,6 +39,7 @@ config BOARDINFO
 	default "Synertronixx scb9328" if MACH_SCB9328
 	default "Garz+Fricke Neso" if MACH_NESO
 	default "Freescale i.MX51 PDK" if MACH_FREESCALE_MX51_PDK
+	default "Freescale i.MX53 LOCO" if MACH_FREESCALE_MX53_LOCO
 	default "Garz+Fricke Cupid" if MACH_GUF_CUPID
 	default "Ka-Ro tx25" if MACH_TX25
 
@@ -50,8 +52,8 @@ choice
 	  used to setup SDRAM. The internal ROM code then initializes SDRAM
 	  using the register/value table, loads the whole barebox image to
 	  SDRAM and starts it. The internal boot mode is available on newer
-	  i.MX processors (i.MX25, i.MX35 and i.MX51). and supports booting
-	  from NOR, NAND, MMC/SD and serial ROMs.
+	  i.MX processors (i.MX25, i.MX35, i.MX51 and i.MX53). and supports
+	  booting from NOR, NAND, MMC/SD and serial ROMs.
 	  The external boot mode only supports booting from NAND and NOR. With
 	  NOR flash the image is just started in NOR flash. With NAND flash
 	  the NAND controller loads the first 2kbyte from NAND into the NAND
@@ -62,7 +64,7 @@ choice
 
 config ARCH_IMX_INTERNAL_BOOT
 	bool "support internal boot mode"
-	depends on ARCH_IMX25 || ARCH_IMX35 || ARCH_IMX51
+	depends on ARCH_IMX25 || ARCH_IMX35 || ARCH_IMX51 || ARCH_IMX53
 
 config ARCH_IMX_EXTERNAL_BOOT
 	bool "support external boot mode"
@@ -154,6 +156,11 @@ config ARCH_IMX51
 	select CPU_V7
 	select ARCH_HAS_FEC_IMX
 
+config ARCH_IMX53
+	bool "i.MX53"
+	select CPU_V7
+	select ARCH_HAS_FEC_IMX
+
 endchoice
 
 # ----------------------------------------------------------
@@ -175,7 +182,6 @@ config MACH_SCB9328
 	select HAS_DM9000
 	select HAS_CFI
 	select MACH_HAS_LOWLEVEL_INIT
-	select HAVE_MMU
 	help
 	  Say Y here if you are using the Synertronixx scb9328 board
 
@@ -215,7 +221,6 @@ choice
 config MACH_EUKREA_CPUIMX25
 	bool "Eukrea CPUIMX25"
 	select MACH_HAS_LOWLEVEL_INIT
-	select HAVE_MMU
 	help
 	  Say Y here if you are using the Eukrea Electromatique's CPUIMX25
 	  equipped with a Freescale i.MX25 Processor
@@ -233,7 +238,6 @@ config MACH_FREESCALE_MX25_3STACK
 config MACH_TX25
 	bool "Ka-Ro TX25"
 	select MACH_HAS_LOWLEVEL_INIT
-	select HAVE_MMU
 	help
 	  Say Y here if you are using the Ka-Ro tx25 board
 
@@ -252,7 +256,6 @@ choice
 config MACH_EUKREA_CPUIMX27
 	bool "EUKREA CPUIMX27"
 	select HAS_CFI
-	select HAVE_MMU
 	select MACH_HAS_LOWLEVEL_INIT
 	help
 	  Say Y here if you are using Eukrea's CPUIMX27 equipped
@@ -269,7 +272,6 @@ config MACH_IMX27ADS
 config MACH_PCA100
 	bool "phyCard-i.MX27"
 	select MACH_HAS_LOWLEVEL_INIT
-	select HAVE_MMU
 	help
 	  Say Y here if you are using Phytec's phyCard-i.MX27 (pca100) equipped
 	  with a Freescale i.MX27 Processor
@@ -281,7 +283,6 @@ config MACH_PCM038
 	select SPI
 	select DRIVER_SPI_IMX
 	select DRIVER_SPI_MC13783
-	select HAVE_MMU
 	help
 	  Say Y here if you are using Phytec's phyCORE-i.MX27 (pcm038) equipped
 	  with a Freescale i.MX27 Processor
@@ -289,7 +290,6 @@ config MACH_PCM038
 config MACH_NESO
 	bool "Garz+Fricke Neso"
 	select MACH_HAS_LOWLEVEL_INIT
-	select HAVE_MMU
 	help
 	  Say Y here if you are using the Garz+Fricke Neso board equipped
 	  with a Freescale i.MX27 Processor
@@ -309,7 +309,6 @@ choice
 config MACH_PCM037
 	bool "phyCORE-i.MX31"
 	select MACH_HAS_LOWLEVEL_INIT
-	select HAVE_MMU
 	select USB_ISP1504 if USB
 	select ARCH_HAS_L2X0
 	help
@@ -330,7 +329,6 @@ choice
 
 config MACH_EUKREA_CPUIMX35
 	bool "EUKREA CPUIMX35"
-	select HAVE_MMU
 	select MACH_HAS_LOWLEVEL_INIT
 	select ARCH_HAS_L2X0
 	help
@@ -350,21 +348,19 @@ config MACH_FREESCALE_MX35_3STACK
 	  with a Freescale i.MX35 Processor
 
 config MACH_PCM043
-        bool "phyCORE-i.MX35"
-        select HAS_CFI
-	select HAVE_MMU
+	bool "phyCORE-i.MX35"
+	select HAS_CFI
 	select MACH_HAS_LOWLEVEL_INIT
 	select ARCH_HAS_L2X0
-        help
-          Say Y here if you are using Phytec's phyCORE-i.MX35 (pcm043) equipped
-          with a Freescale i.MX35 Processor
+	help
+	  Say Y here if you are using Phytec's phyCORE-i.MX35 (pcm043) equipped
+	  with a Freescale i.MX35 Processor
 
 config MACH_GUF_CUPID
-        bool "Garz+Fricke Cupid"
-	select HAVE_MMU
+	bool "Garz+Fricke Cupid"
 	select MACH_HAS_LOWLEVEL_INIT
 	select ARCH_HAS_L2X0
-        help
+	help
 	  Say Y here if you are using the Garz+Fricke Neso board equipped
 	  with a Freescale i.MX35 Processor
 
@@ -382,12 +378,10 @@ choice
 
 config MACH_FREESCALE_MX51_PDK
 	bool "Freescale i.MX51 PDK"
-	select HAVE_MMU
 	select MACH_HAS_LOWLEVEL_INIT
 
 config MACH_EUKREA_CPUIMX51SD
 	bool "EUKREA CPUIMX51"
-	select HAVE_MMU
 	select MACH_HAS_LOWLEVEL_INIT
 	help
 	  Say Y here if you are using Eukrea's CPUIMX51 equipped
@@ -397,6 +391,24 @@ endchoice
 
 endif
 
+# ----------------------------------------------------------
+
+if ARCH_IMX53
+
+choice
+
+	prompt "i.MX53 Board Type"
+
+config MACH_FREESCALE_MX53_LOCO
+	bool "Freescale i.MX53 LOCO"
+	select MACH_HAS_LOWLEVEL_INIT
+
+endchoice
+
+endif
+
+# ----------------------------------------------------------
+
 menu "Board specific settings       "
 
 if MACH_PCM043
@@ -480,7 +492,7 @@ config IMX_CLKO
 
 config IMX_IIM
 	tristate "IIM fusebox device"
-	depends on ARCH_IMX25 || ARCH_IMX35
+	depends on !ARCH_IMX21 && !ARCH_IMX21
 	help
 	  Device driver for the IC Identification Module (IIM) fusebox. Use the 
 	  regular md/mw commands to program and read the fusebox.
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 5fcaac95e3..0b3b781e8b 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_IMX27) += speed-imx27.o imx27.o iomux-v1.o
 obj-$(CONFIG_ARCH_IMX31) += speed-imx31.o imx31.o iomux-v2.o
 obj-$(CONFIG_ARCH_IMX35) += speed-imx35.o imx35.o iomux-v3.o
 obj-$(CONFIG_ARCH_IMX51) += speed-imx51.o imx51.o iomux-v3.o
+obj-$(CONFIG_ARCH_IMX53) += speed-imx53.o imx53.o iomux-v3.o
 obj-$(CONFIG_IMX_CLKO)	+= clko.o
 obj-$(CONFIG_IMX_IIM)	+= iim.o
 obj-$(CONFIG_NAND_IMX) += nand.o
diff --git a/arch/arm/mach-imx/devices.c b/arch/arm/mach-imx/devices.c
index 0395b0e572..5b062f5f0f 100644
--- a/arch/arm/mach-imx/devices.c
+++ b/arch/arm/mach-imx/devices.c
@@ -2,20 +2,10 @@
 #include <driver.h>
 #include <mach/devices.h>
 
-static struct device_d *imx_add_device(char *name, int id, void *base, int size, void *pdata)
+static inline struct device_d *imx_add_device(char *name, int id, void *base, int size, void *pdata)
 {
-	struct device_d *dev;
-
-	dev = xzalloc(sizeof(*dev));
-	strcpy(dev->name,name);
-	dev->id = id;
-	dev->map_base = (unsigned long)base;
-	dev->size = size;
-	dev->platform_data = pdata;
-
-	register_device(dev);
-
-	return 0;
+	return add_generic_device(name, id, NULL, (resource_size_t)base, size,
+				  IORESOURCE_MEM, pdata);
 }
 
 struct device_d *imx_add_fec(void *base, struct fec_platform_data *pdata)
diff --git a/arch/arm/mach-imx/iim.c b/arch/arm/mach-imx/iim.c
index 0774ebba9c..ca89710329 100644
--- a/arch/arm/mach-imx/iim.c
+++ b/arch/arm/mach-imx/iim.c
@@ -22,6 +22,8 @@
 #include <xfuncs.h>
 #include <errno.h>
 #include <param.h>
+#include <fcntl.h>
+#include <malloc.h>
 
 #include <asm/io.h>
 
@@ -31,7 +33,15 @@
 
 static unsigned long mac_addr_base;
 
-static int do_fuse_sense(unsigned long reg_base, unsigned int bank,
+struct iim_priv {
+	struct cdev cdev;
+	void __iomem *base;
+	void __iomem *bankbase;
+	int bank;
+	int banksize;
+};
+
+static int do_fuse_sense(void __iomem *reg_base, unsigned int bank,
 		unsigned int row)
 {
 	u8 err, stat;
@@ -73,41 +83,38 @@ static int do_fuse_sense(unsigned long reg_base, unsigned int bank,
 	return readb(reg_base + IIM_SDAT);
 }
 
-static ssize_t imx_iim_read(struct cdev *cdev, void *buf, size_t count,
+static ssize_t imx_iim_cdev_read(struct cdev *cdev, void *buf, size_t count,
 		ulong offset, ulong flags)
 {
 	ulong size, i;
-	struct device_d *dev = cdev->dev;
+	struct iim_priv *priv = cdev->priv;
 	const char *sense_param;
 	unsigned long explicit_sense = 0;
 
-	if (dev == NULL)
-		return -EINVAL;
-
-	if ((sense_param = dev_get_param(dev, "explicit_sense_enable")))
+	if ((sense_param = dev_get_param(cdev->dev, "explicit_sense_enable")))
 		explicit_sense = simple_strtoul(sense_param, NULL, 0);
 
-	size = min((ulong)count, dev->size - offset);
+	size = min((ulong)count, priv->banksize - offset);
 	if (explicit_sense) {
 		for (i = 0; i < size; i++) {
 			int row_val;
 
-			row_val = do_fuse_sense(dev->parent->map_base,
-				dev->id, (offset+i)*4);
+			row_val = do_fuse_sense(priv->base,
+				priv->bank, (offset + i) * 4);
 			if (row_val < 0)
 				return row_val;
 			((u8 *)buf)[i] = (u8)row_val;
 		}
 	} else {
 		for (i = 0; i < size; i++)
-			((u8 *)buf)[i] = ((u8 *)dev->map_base)[(offset+i)*4];
+			((u8 *)buf)[i] = ((u8 *)priv->bankbase)[(offset+i)*4];
 	}
 
 	return size;
 }
 
 #ifdef CONFIG_IMX_IIM_FUSE_BLOW
-static int do_fuse_blow(unsigned long reg_base, unsigned int bank,
+static int do_fuse_blow(void __iomem *reg_base, unsigned int bank,
 		unsigned int row, u8 value)
 {
 	int bit, ret = 0;
@@ -168,28 +175,25 @@ out:
 }
 #endif /* CONFIG_IMX_IIM_FUSE_BLOW */
 
-static ssize_t imx_iim_write(struct cdev *cdev, const void *buf, size_t count,
+static ssize_t imx_iim_cdev_write(struct cdev *cdev, const void *buf, size_t count,
 		ulong offset, ulong flags)
 {
 	ulong size, i;
-	struct device_d *dev = cdev->dev;
+	struct iim_priv *priv = cdev->priv;
 	const char *write_param;
 	unsigned int blow_enable = 0;
 
-	if (dev == NULL)
-		return -EINVAL;
-
-	if ((write_param = dev_get_param(dev, "permanent_write_enable")))
+	if ((write_param = dev_get_param(cdev->dev, "permanent_write_enable")))
 		blow_enable = simple_strtoul(write_param, NULL, 0);
 
-	size = min((ulong)count, dev->size - offset);
+	size = min((ulong)count, priv->banksize - offset);
 #ifdef CONFIG_IMX_IIM_FUSE_BLOW
 	if (blow_enable) {
 		for (i = 0; i < size; i++) {
 			int ret;
 
-			ret = do_fuse_blow(dev->parent->map_base, dev->id,
-					(offset+i)*4, ((u8 *)buf)[i]);
+			ret = do_fuse_blow(priv->base, priv->bank,
+					(offset + i) * 4, ((u8 *)buf)[i]);
 			if (ret < 0)
 				return ret;
 		}
@@ -197,15 +201,15 @@ static ssize_t imx_iim_write(struct cdev *cdev, const void *buf, size_t count,
 #endif /* CONFIG_IMX_IIM_FUSE_BLOW */
 	{
 		for (i = 0; i < size; i++)
-			((u8 *)dev->map_base)[(offset+i)*4] = ((u8 *)buf)[i];
+			((u8 *)priv->bankbase)[(offset+i)*4] = ((u8 *)buf)[i];
 	}
 
 	return size;
 }
 
 static struct file_operations imx_iim_ops = {
-	.read	= imx_iim_read,
-	.write	= imx_iim_write,
+	.read	= imx_iim_cdev_read,
+	.write	= imx_iim_cdev_write,
 	.lseek	= dev_lseek_default,
 };
 
@@ -224,38 +228,44 @@ static int imx_iim_blow_enable_set(struct device_d *dev, struct param_d *param,
 	return dev_param_set_generic(dev, param, blow_enable ? "1" : "0");
 }
 
-static int imx_iim_probe(struct device_d *dev)
+static int imx_iim_add_bank(struct device_d *dev, void __iomem *base, int num)
 {
-	struct imx_iim_platform_data *pdata = dev->platform_data;
+	struct iim_priv *priv;
+	struct cdev *cdev;
 
-	if (pdata)
-		mac_addr_base = pdata->mac_addr_base;
+	priv = xzalloc(sizeof (*priv));
 
-	return 0;
+	priv->base	= base;
+	priv->bankbase	= priv->base + 0x800 + 0x400 * num;
+	priv->bank	= num;
+	priv->banksize	= 32;
+	cdev = &priv->cdev;
+	cdev->dev	= dev;
+	cdev->ops	= &imx_iim_ops;
+	cdev->priv	= priv;
+	cdev->size	= 32;
+	cdev->name	= asprintf(DRIVERNAME "_bank%d", num);
+	if (cdev->name == NULL)
+		return -ENOMEM;
+
+	return devfs_create(cdev);
 }
 
-static int imx_iim_bank_probe(struct device_d *dev)
+static int imx_iim_probe(struct device_d *dev)
 {
-	struct cdev *cdev;
-	struct device_d *parent;
+	struct imx_iim_platform_data *pdata = dev->platform_data;
 	int err;
+	int i;
+	void __iomem *base;
 
-	cdev = xzalloc(sizeof (struct cdev));
-	dev->priv = cdev;
+	base = dev_request_mem_region(dev, 0);
 
-	cdev->dev	= dev;
-	cdev->ops	= &imx_iim_ops;
-	cdev->size	= dev->size;
-	cdev->name	= asprintf(DRIVERNAME "_bank%d", dev->id);
-	if (cdev->name == NULL)
-		return -ENOMEM;
+	if (pdata)
+		mac_addr_base = pdata->mac_addr_base;
 
-	parent = get_device_by_name(DRIVERNAME "0");
-	if (parent == NULL)
-		return -ENODEV;
-	err = dev_add_child(parent, dev);
-	if (err < 0)
-		return err;
+	for (i = 0; i < 8; i++) {
+		imx_iim_add_bank(dev, base, i);
+	}
 
 #ifdef CONFIG_IMX_IIM_FUSE_BLOW
 	err = dev_add_param(dev, "permanent_write_enable",
@@ -271,11 +281,11 @@ static int imx_iim_bank_probe(struct device_d *dev)
 			imx_iim_blow_enable_set, NULL, 0);
 	if (err < 0)
 		return err;
-	err = dev_set_param(dev, "explicit_sense_enable", "0");
+	err = dev_set_param(dev, "explicit_sense_enable", "1");
 	if (err < 0)
 		return err;
 
-	return devfs_create(cdev);
+	return 0;
 }
 
 static struct driver_d imx_iim_driver = {
@@ -283,29 +293,28 @@ static struct driver_d imx_iim_driver = {
 	.probe	= imx_iim_probe,
 };
 
-static struct driver_d imx_iim_bank_driver = {
-	.name	= DRIVERNAME "_bank",
-	.probe	= imx_iim_bank_probe,
-};
-
 static int imx_iim_init(void)
 {
 	register_driver(&imx_iim_driver);
-	register_driver(&imx_iim_bank_driver);
 
 	return 0;
 }
 coredevice_initcall(imx_iim_init);
 
-int imx_iim_get_mac(unsigned char *mac)
+int imx_iim_read(unsigned int bank, int offset, void *buf, int count)
 {
-	int i;
+	struct cdev *cdev;
+	char *name = asprintf(DRIVERNAME "_bank%d", bank);
+	int ret;
 
-	if (mac_addr_base == 0)
-		return -EINVAL;
+	cdev = cdev_open(name, O_RDONLY);
+	if (!cdev)
+		return -ENODEV;
 
-	for (i = 0; i < 6; i++)
-		 mac[i] = readb(mac_addr_base + i*4);
+	ret = cdev_read(cdev, buf, count, offset, 0);
 
-	return 0;
+	cdev_close(cdev);
+	free(name);
+
+	return ret;
 }
diff --git a/arch/arm/mach-imx/imx25.c b/arch/arm/mach-imx/imx25.c
index 37eafafe6e..75ec8c7f45 100644
--- a/arch/arm/mach-imx/imx25.c
+++ b/arch/arm/mach-imx/imx25.c
@@ -20,6 +20,7 @@
 #include <mach/imx-regs.h>
 #include <mach/iim.h>
 #include <asm/io.h>
+#include <sizes.h>
 
 #include "gpio.h"
 
@@ -53,41 +54,11 @@ static struct imx_iim_platform_data imx25_iim_pdata = {
 	.mac_addr_base	= IIM_MAC_ADDR,
 };
 
-static struct device_d imx25_iim_dev = {
-	.id		= -1,
-	.name		= "imx_iim",
-	.map_base	= IMX_IIM_BASE,
-	.platform_data	= &imx25_iim_pdata,
-};
-
-static struct device_d imx25_iim_bank0_dev = {
-	.name		= "imx_iim_bank",
-	.id		= 0,
-	.map_base	= IIM_BANK0_BASE,
-	.size		= IIM_BANK_SIZE,
-};
-
-static struct device_d imx25_iim_bank1_dev = {
-	.name		= "imx_iim_bank",
-	.id		= 1,
-	.map_base	= IIM_BANK1_BASE,
-	.size		= IIM_BANK_SIZE,
-};
-
-static struct device_d imx25_iim_bank2_dev = {
-	.name		= "imx_iim_bank",
-	.id		= 2,
-	.map_base	= IIM_BANK2_BASE,
-	.size		= IIM_BANK_SIZE,
-};
-
-static int imx25_iim_init(void)
+static int imx25_init(void)
 {
-	register_device(&imx25_iim_dev);
-	register_device(&imx25_iim_bank0_dev);
-	register_device(&imx25_iim_bank1_dev);
-	register_device(&imx25_iim_bank2_dev);
+	add_generic_device("imx_iim", 0, NULL, IMX_IIM_BASE, SZ_4K,
+			IORESOURCE_MEM, &imx25_iim_pdata);
 
 	return 0;
 }
-coredevice_initcall(imx25_iim_init);
+coredevice_initcall(imx25_init);
diff --git a/arch/arm/mach-imx/imx27.c b/arch/arm/mach-imx/imx27.c
index 04bdd5f226..86039c4dea 100644
--- a/arch/arm/mach-imx/imx27.c
+++ b/arch/arm/mach-imx/imx27.c
@@ -17,6 +17,8 @@
 
 #include <common.h>
 #include <mach/imx-regs.h>
+#include <sizes.h>
+#include <init.h>
 
 #include "gpio.h"
 
@@ -36,3 +38,11 @@ void *imx_gpio_base[] = {
 
 int imx_gpio_count = ARRAY_SIZE(imx_gpio_base) * 32;
 
+static int imx27_init(void)
+{
+	add_generic_device("imx_iim", 0, NULL, IMX_IIM_BASE, SZ_4K,
+			IORESOURCE_MEM, NULL);
+
+	return 0;
+}
+coredevice_initcall(imx27_init);
diff --git a/arch/arm/mach-imx/imx31.c b/arch/arm/mach-imx/imx31.c
index f2fea4cdc4..bb713ca876 100644
--- a/arch/arm/mach-imx/imx31.c
+++ b/arch/arm/mach-imx/imx31.c
@@ -16,6 +16,9 @@
  */
 
 #include <common.h>
+#include <init.h>
+#include <sizes.h>
+#include <mach/imx-regs.h>
 
 #include "gpio.h"
 
@@ -27,3 +30,11 @@ void *imx_gpio_base[] = {
 
 int imx_gpio_count = ARRAY_SIZE(imx_gpio_base) * 32;
 
+static int imx31_init(void)
+{
+	add_generic_device("imx_iim", 0, NULL, IMX_IIM_BASE, SZ_4K,
+			IORESOURCE_MEM, NULL);
+
+	return 0;
+}
+coredevice_initcall(imx31_init);
diff --git a/arch/arm/mach-imx/imx35.c b/arch/arm/mach-imx/imx35.c
index 5a0cff4f09..c846260682 100644
--- a/arch/arm/mach-imx/imx35.c
+++ b/arch/arm/mach-imx/imx35.c
@@ -16,6 +16,7 @@
  */
 
 #include <common.h>
+#include <sizes.h>
 #include <init.h>
 #include <asm/io.h>
 #include <mach/imx-regs.h>
@@ -58,3 +59,12 @@ static int imx35_l2_fix(void)
 	return 0;
 }
 core_initcall(imx35_l2_fix);
+
+static int imx35_init(void)
+{
+	add_generic_device("imx_iim", 0, NULL, IMX_IIM_BASE, SZ_4K,
+			IORESOURCE_MEM, NULL);
+
+	return 0;
+}
+coredevice_initcall(imx35_init);
diff --git a/arch/arm/mach-imx/imx51.c b/arch/arm/mach-imx/imx51.c
index 075ed22f20..8b7c80792a 100644
--- a/arch/arm/mach-imx/imx51.c
+++ b/arch/arm/mach-imx/imx51.c
@@ -17,6 +17,7 @@
 
 #include <init.h>
 #include <common.h>
+#include <sizes.h>
 #include <asm/io.h>
 #include <mach/imx51-regs.h>
 
@@ -79,3 +80,12 @@ static int imx51_print_silicon_rev(void)
 	return 0;
 }
 device_initcall(imx51_print_silicon_rev);
+
+static int imx51_init(void)
+{
+	add_generic_device("imx_iim", 0, NULL, MX51_IIM_BASE_ADDR, SZ_4K,
+			IORESOURCE_MEM, NULL);
+
+	return 0;
+}
+coredevice_initcall(imx51_init);
diff --git a/arch/sandbox/include/asm/global_data.h b/arch/arm/mach-imx/imx53.c
index 51d9405d65..7a822c2c85 100644
--- a/arch/sandbox/include/asm/global_data.h
+++ b/arch/arm/mach-imx/imx53.c
@@ -1,10 +1,4 @@
 /*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
@@ -21,10 +15,31 @@
  * MA 02111-1307 USA
  */
 
-#ifndef	__ASM_GBL_DATA_H
-#define __ASM_GBL_DATA_H
-typedef	struct	global_data gd_t;
+#include <init.h>
+#include <common.h>
+#include <asm/io.h>
+#include <sizes.h>
+#include <mach/imx53-regs.h>
+
+#include "gpio.h"
+
+void *imx_gpio_base[] = {
+	(void *)MX53_GPIO1_BASE_ADDR,
+	(void *)MX53_GPIO2_BASE_ADDR,
+	(void *)MX53_GPIO3_BASE_ADDR,
+	(void *)MX53_GPIO4_BASE_ADDR,
+	(void *)MX53_GPIO5_BASE_ADDR,
+	(void *)MX53_GPIO6_BASE_ADDR,
+	(void *)MX53_GPIO7_BASE_ADDR,
+};
+
+int imx_gpio_count = ARRAY_SIZE(imx_gpio_base) * 32;
 
-#define DECLARE_GLOBAL_DATA_PTR
+static int imx53_init(void)
+{
+	add_generic_device("imx_iim", 0, NULL, MX53_IIM_BASE_ADDR, SZ_4K,
+			IORESOURCE_MEM, NULL);
 
-#endif /* __ASM_GBL_DATA_H */
+	return 0;
+}
+coredevice_initcall(imx53_init);
diff --git a/arch/arm/mach-imx/include/mach/clock-imx51.h b/arch/arm/mach-imx/include/mach/clock-imx51.h
deleted file mode 100644
index 0dee7c310c..0000000000
--- a/arch/arm/mach-imx/include/mach/clock-imx51.h
+++ /dev/null
@@ -1,696 +0,0 @@
-/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
-#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
-
-/* PLL Register Offsets */
-#define MX51_PLL_DP_CTL			0x00
-#define MX51_PLL_DP_CONFIG		0x04
-#define MX51_PLL_DP_OP			0x08
-#define MX51_PLL_DP_MFD			0x0C
-#define MX51_PLL_DP_MFN			0x10
-#define MX51_PLL_DP_MFNMINUS		0x14
-#define MX51_PLL_DP_MFNPLUS		0x18
-#define MX51_PLL_DP_HFS_OP		0x1C
-#define MX51_PLL_DP_HFS_MFD		0x20
-#define MX51_PLL_DP_HFS_MFN		0x24
-#define MX51_PLL_DP_MFN_TOGC		0x28
-#define MX51_PLL_DP_DESTAT		0x2c
-
-/* PLL Register Bit definitions */
-#define MX51_PLL_DP_CTL_MUL_CTRL		0x2000
-#define MX51_PLL_DP_CTL_DPDCK0_2_EN	0x1000
-#define MX51_PLL_DP_CTL_DPDCK0_2_OFFSET	12
-#define MX51_PLL_DP_CTL_ADE		0x800
-#define MX51_PLL_DP_CTL_REF_CLK_DIV	0x400
-#define MX51_PLL_DP_CTL_REF_CLK_SEL_MASK	(3 << 8)
-#define MX51_PLL_DP_CTL_REF_CLK_SEL_OFFSET	8
-#define MX51_PLL_DP_CTL_HFSM		0x80
-#define MX51_PLL_DP_CTL_PRE		0x40
-#define MX51_PLL_DP_CTL_UPEN		0x20
-#define MX51_PLL_DP_CTL_RST		0x10
-#define MX51_PLL_DP_CTL_RCP		0x8
-#define MX51_PLL_DP_CTL_PLM		0x4
-#define MX51_PLL_DP_CTL_BRM0		0x2
-#define MX51_PLL_DP_CTL_LRF		0x1
-
-#define MX51_PLL_DP_CONFIG_BIST		0x8
-#define MX51_PLL_DP_CONFIG_SJC_CE	0x4
-#define MX51_PLL_DP_CONFIG_AREN		0x2
-#define MX51_PLL_DP_CONFIG_LDREQ		0x1
-
-#define MX51_PLL_DP_OP_MFI_OFFSET	4
-#define MX51_PLL_DP_OP_MFI_MASK		(0xF << 4)
-#define MX51_PLL_DP_OP_PDF_OFFSET	0
-#define MX51_PLL_DP_OP_PDF_MASK		0xF
-
-#define MX51_PLL_DP_MFD_OFFSET		0
-#define MX51_PLL_DP_MFD_MASK		0x07FFFFFF
-
-#define MX51_PLL_DP_MFN_OFFSET		0x0
-#define MX51_PLL_DP_MFN_MASK		0x07FFFFFF
-
-#define MX51_PLL_DP_MFN_TOGC_TOG_DIS	(1 << 17)
-#define MX51_PLL_DP_MFN_TOGC_TOG_EN	(1 << 16)
-#define MX51_PLL_DP_MFN_TOGC_CNT_OFFSET	0x0
-#define MX51_PLL_DP_MFN_TOGC_CNT_MASK	0xFFFF
-
-#define MX51_PLL_DP_DESTAT_TOG_SEL	(1 << 31)
-#define MX51_PLL_DP_DESTAT_MFN		0x07FFFFFF
-
-/* Assuming 24MHz input clock with doubler ON */
-/*                            MFI         PDF */
-#define MX51_PLL_DP_OP_850	((8 << 4) + ((1 - 1)  << 0))
-#define MX51_PLL_DP_MFD_850	(48 - 1)
-#define MX51_PLL_DP_MFN_850	41
-
-#define MX51_PLL_DP_OP_800	((8 << 4) + ((1 - 1)  << 0))
-#define MX51_PLL_DP_MFD_800	(3 - 1)
-#define MX51_PLL_DP_MFN_800	1
-
-#define MX51_PLL_DP_OP_700	((7 << 4) + ((1 - 1)  << 0))
-#define MX51_PLL_DP_MFD_700	(24 - 1)
-#define MX51_PLL_DP_MFN_700	7
-
-#define MX51_PLL_DP_OP_665	((6 << 4) + ((1 - 1)  << 0))
-#define MX51_PLL_DP_MFD_665	(96 - 1)
-#define MX51_PLL_DP_MFN_665	89
-
-#define MX51_PLL_DP_OP_532	((5 << 4) + ((1 - 1)  << 0))
-#define MX51_PLL_DP_MFD_532	(24 - 1)
-#define MX51_PLL_DP_MFN_532	13
-
-#define MX51_PLL_DP_OP_400	((8 << 4) + ((2 - 1)  << 0))
-#define MX51_PLL_DP_MFD_400	(3 - 1)
-#define MX51_PLL_DP_MFN_400	1
-
-#define MX51_PLL_DP_OP_216	((6 << 4) + ((3 - 1)  << 0))
-#define MX51_PLL_DP_MFD_216	(4 - 1)
-#define MX51_PLL_DP_MFN_216	3
-
-/* Register addresses of CCM*/
-#define MX51_CCM_CCR		0x00
-#define MX51_CCM_CCDR		0x04
-#define MX51_CCM_CSR		0x08
-#define MX51_CCM_CCSR		0x0C
-#define MX51_CCM_CACRR		0x10
-#define MX51_CCM_CBCDR		0x14
-#define MX51_CCM_CBCMR		0x18
-#define MX51_CCM_CSCMR1		0x1C
-#define MX51_CCM_CSCMR2		0x20
-#define MX51_CCM_CSCDR1		0x24
-#define MX51_CCM_CS1CDR		0x28
-#define MX51_CCM_CS2CDR		0x2C
-#define MX51_CCM_CDCDR		0x30
-#define MX51_CCM_CHSCDR		0x34
-#define MX51_CCM_CSCDR2		0x38
-#define MX51_CCM_CSCDR3		0x3C
-#define MX51_CCM_CSCDR4		0x40
-#define MX51_CCM_CWDR		0x44
-#define MX51_CCM_CDHIPR		0x48
-#define MX51_CCM_CDCR		0x4C
-#define MX51_CCM_CTOR		0x50
-#define MX51_CCM_CLPCR		0x54
-#define MX51_CCM_CISR		0x58
-#define MX51_CCM_CIMR		0x5C
-#define MX51_CCM_CCOSR		0x60
-#define MX51_CCM_CGPR		0x64
-#define MX51_CCM_CCGR0		0x68
-#define MX51_CCM_CCGR1		0x6C
-#define MX51_CCM_CCGR2		0x70
-#define MX51_CCM_CCGR3		0x74
-#define MX51_CCM_CCGR4		0x78
-#define MX51_CCM_CCGR5		0x7C
-#define MX51_CCM_CCGR6		0x80
-#define MX51_CCM_CMEOR		0x84
-
-/* Define the bits in register CCR */
-#define MX51_CCM_CCR_COSC_EN		(1 << 12)
-#define MX51_CCM_CCR_FPM_MULT_MASK	(1 << 11)
-#define MX51_CCM_CCR_CAMP2_EN		(1 << 10)
-#define MX51_CCM_CCR_CAMP1_EN		(1 << 9)
-#define MX51_CCM_CCR_FPM_EN		(1 << 8)
-#define MX51_CCM_CCR_OSCNT_OFFSET	(0)
-#define MX51_CCM_CCR_OSCNT_MASK	(0xFF)
-
-/* Define the bits in register CCDR */
-#define MX51_CCM_CCDR_HSC_HS_MASK	(0x1 << 18)
-#define MX51_CCM_CCDR_IPU_HS_MASK	(0x1 << 17)
-#define MX51_CCM_CCDR_EMI_HS_MASK	(0x1 << 16)
-
-/* Define the bits in register CSR */
-#define MX51_CCM_CSR_COSR_READY	(1 << 5)
-#define MX51_CCM_CSR_LVS_VALUE		(1 << 4)
-#define MX51_CCM_CSR_CAMP2_READY	(1 << 3)
-#define MX51_CCM_CSR_CAMP1_READY	(1 << 2)
-#define MX51_CCM_CSR_FPM_READY	(1 << 1)
-#define MX51_CCM_CSR_REF_EN_B		(1 << 0)
-
-/* Define the bits in register CCSR */
-#define MX51_CCM_CCSR_LP_APM_SEL		(0x1 << 9)
-#define MX51_CCM_CCSR_STEP_SEL_OFFSET		(7)
-#define MX51_CCM_CCSR_STEP_SEL_MASK		(0x3 << 7)
-#define MX51_CCM_CCSR_PLL2_PODF_OFFSET	(5)
-#define MX51_CCM_CCSR_PLL2_PODF_MASK		(0x3 << 5)
-#define MX51_CCM_CCSR_PLL3_PODF_OFFSET	(3)
-#define MX51_CCM_CCSR_PLL3_PODF_MASK		(0x3 << 3)
-#define MX51_CCM_CCSR_PLL1_SW_CLK_SEL		(1 << 2)
-#define MX51_CCM_CCSR_PLL2_SW_CLK_SEL		(1 << 1)
-#define MX51_CCM_CCSR_PLL3_SW_CLK_SEL		(1 << 0)
-
-/* Define the bits in register CACRR */
-#define MX51_CCM_CACRR_ARM_PODF_OFFSET	(0)
-#define MX51_CCM_CACRR_ARM_PODF_MASK		(0x7)
-
-/* Define the bits in register CBCDR */
-#define MX51_CCM_CBCDR_EMI_CLK_SEL			(0x1 << 26)
-#define MX51_CCM_CBCDR_PERIPH_CLK_SEL			(0x1 << 25)
-#define MX51_CCM_CBCDR_DDR_HF_SEL_OFFSET		(30)
-#define MX51_CCM_CBCDR_DDR_HF_SEL			(0x1 << 30)
-#define MX51_CCM_CBCDR_DDR_PODF_OFFSET		(27)
-#define MX51_CCM_CBCDR_DDR_PODF_MASK			(0x7 << 27)
-#define MX51_CCM_CBCDR_EMI_PODF_OFFSET		(22)
-#define MX51_CCM_CBCDR_EMI_PODF_MASK			(0x7 << 22)
-#define MX51_CCM_CBCDR_AXI_B_PODF_OFFSET		(19)
-#define MX51_CCM_CBCDR_AXI_B_PODF_MASK		(0x7 << 19)
-#define MX51_CCM_CBCDR_AXI_A_PODF_OFFSET		(16)
-#define MX51_CCM_CBCDR_AXI_A_PODF_MASK		(0x7 << 16)
-#define MX51_CCM_CBCDR_NFC_PODF_OFFSET		(13)
-#define MX51_CCM_CBCDR_NFC_PODF_MASK			(0x7 << 13)
-#define MX51_CCM_CBCDR_AHB_PODF_OFFSET		(10)
-#define MX51_CCM_CBCDR_AHB_PODF_MASK			(0x7 << 10)
-#define MX51_CCM_CBCDR_IPG_PODF_OFFSET		(8)
-#define MX51_CCM_CBCDR_IPG_PODF_MASK			(0x3 << 8)
-#define MX51_CCM_CBCDR_PERCLK_PRED1_OFFSET		(6)
-#define MX51_CCM_CBCDR_PERCLK_PRED1_MASK		(0x3 << 6)
-#define MX51_CCM_CBCDR_PERCLK_PRED2_OFFSET		(3)
-#define MX51_CCM_CBCDR_PERCLK_PRED2_MASK		(0x7 << 3)
-#define MX51_CCM_CBCDR_PERCLK_PODF_OFFSET		(0)
-#define MX51_CCM_CBCDR_PERCLK_PODF_MASK		(0x7)
-
-/* Define the bits in register CBCMR */
-#define MX51_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET	(14)
-#define MX51_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK		(0x3 << 14)
-#define MX51_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET		(12)
-#define MX51_CCM_CBCMR_PERIPH_CLK_SEL_MASK		(0x3 << 12)
-#define MX51_CCM_CBCMR_DDR_CLK_SEL_OFFSET		(10)
-#define MX51_CCM_CBCMR_DDR_CLK_SEL_MASK		(0x3 << 10)
-#define MX51_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET	(8)
-#define MX51_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK		(0x3 << 8)
-#define MX51_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET	(6)
-#define MX51_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK		(0x3 << 6)
-#define MX51_CCM_CBCMR_GPU_CLK_SEL_OFFSET		(4)
-#define MX51_CCM_CBCMR_GPU_CLK_SEL_MASK		(0x3 << 4)
-#define MX51_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET        (14)
-#define MX51_CCM_CBCMR_GPU2D_CLK_SEL_MASK      (0x3 << 14)
-#define MX51_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL		(0x1 << 1)
-#define MX51_CCM_CBCMR_PERCLK_IPG_CLK_SEL		(0x1 << 0)
-
-/* Define the bits in register CSCMR1 */
-#define MX51_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET		(30)
-#define MX51_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK		(0x3 << 30)
-#define MX51_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET		(28)
-#define MX51_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK		(0x3 << 28)
-#define MX51_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET		(26)
-#define MX51_CCM_CSCMR1_USB_PHY_CLK_SEL			(0x1 << 26)
-#define MX51_CCM_CSCMR1_UART_CLK_SEL_OFFSET			(24)
-#define MX51_CCM_CSCMR1_UART_CLK_SEL_MASK			(0x3 << 24)
-#define MX51_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET		(22)
-#define MX51_CCM_CSCMR1_USBOH3_CLK_SEL_MASK			(0x3 << 22)
-#define MX51_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET	(20)
-#define MX51_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK		(0x3 << 20)
-#define MX51_CCM_CSCMR1_ESDHC3_CLK_SEL			(0x1 << 19)
-#define MX51_CCM_CSCMR1_ESDHC4_CLK_SEL			(0x1 << 18)
-#define MX51_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET	(16)
-#define MX51_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK		(0x3 << 16)
-#define MX51_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET			(14)
-#define MX51_CCM_CSCMR1_SSI1_CLK_SEL_MASK			(0x3 << 14)
-#define MX51_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET			(12)
-#define MX51_CCM_CSCMR1_SSI2_CLK_SEL_MASK			(0x3 << 12)
-#define MX51_CCM_CSCMR1_SSI3_CLK_SEL				(0x1 << 11)
-#define MX51_CCM_CSCMR1_VPU_RCLK_SEL				(0x1 << 10)
-#define MX51_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET		(8)
-#define MX51_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK		(0x3 << 8)
-#define MX51_CCM_CSCMR1_TVE_CLK_SEL				(0x1 << 7)
-#define MX51_CCM_CSCMR1_TVE_EXT_CLK_SEL			(0x1 << 6)
-#define MX51_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET			(4)
-#define MX51_CCM_CSCMR1_CSPI_CLK_SEL_MASK			(0x3 << 4)
-#define MX51_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET			(2)
-#define MX51_CCM_CSCMR1_SPDIF_CLK_SEL_MASK			(0x3 << 2)
-#define MX51_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL			(0x1 << 1)
-#define MX51_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL			(0x1)
-
-/* Define the bits in register CSCMR2 */
-#define MX51_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n)		(26+n*3)
-#define MX51_CCM_CSCMR2_DI_CLK_SEL_MASK(n)		(0x7 << (26+n*3))
-#define MX51_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET	(24)
-#define MX51_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK	(0x3 << 24)
-#define MX51_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET	(22)
-#define MX51_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK	(0x3 << 22)
-#define MX51_CCM_CSCMR2_ESC_CLK_SEL_OFFSET		(20)
-#define MX51_CCM_CSCMR2_ESC_CLK_SEL_MASK		(0x3 << 20)
-#define MX51_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET		(18)
-#define MX51_CCM_CSCMR2_HSC2_CLK_SEL_MASK		(0x3 << 18)
-#define MX51_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET		(16)
-#define MX51_CCM_CSCMR2_HSC1_CLK_SEL_MASK		(0x3 << 16)
-#define MX51_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET		(14)
-#define MX51_CCM_CSCMR2_HSI2C_CLK_SEL_MASK		(0x3 << 14)
-#define MX51_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET		(12)
-#define MX51_CCM_CSCMR2_FIRI_CLK_SEL_MASK		(0x3 << 12)
-#define MX51_CCM_CSCMR2_SIM_CLK_SEL_OFFSET		(10)
-#define MX51_CCM_CSCMR2_SIM_CLK_SEL_MASK		(0x3 << 10)
-#define MX51_CCM_CSCMR2_SLIMBUS_COM			(0x1 << 9)
-#define MX51_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET	(6)
-#define MX51_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK		(0x7 << 6)
-#define MX51_CCM_CSCMR2_SPDIF1_COM			(1 << 5)
-#define MX51_CCM_CSCMR2_SPDIF0_COM			(1 << 4)
-#define MX51_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET	(2)
-#define MX51_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK		(0x3 << 2)
-#define MX51_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET	(0)
-#define MX51_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK		(0x3)
-
-/* Define the bits in register CSCDR1 */
-#define MX51_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET	(22)
-#define MX51_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK		(0x7 << 22)
-#define MX51_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET	(19)
-#define MX51_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK		(0x7 << 19)
-#define MX51_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET	(16)
-#define MX51_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK		(0x7 << 16)
-#define MX51_CCM_CSCDR1_PGC_CLK_PODF_OFFSET			(14)
-#define MX51_CCM_CSCDR1_PGC_CLK_PODF_MASK			(0x3 << 14)
-#define MX51_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET	(11)
-#define MX51_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK		(0x7 << 11)
-#define MX51_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET		(8)
-#define MX51_CCM_CSCDR1_USBOH3_CLK_PRED_MASK		(0x7 << 8)
-#define MX51_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET		(6)
-#define MX51_CCM_CSCDR1_USBOH3_CLK_PODF_MASK		(0x3 << 6)
-#define MX51_CCM_CSCDR1_UART_CLK_PRED_OFFSET		(3)
-#define MX51_CCM_CSCDR1_UART_CLK_PRED_MASK			(0x7 << 3)
-#define MX51_CCM_CSCDR1_UART_CLK_PODF_OFFSET		(0)
-#define MX51_CCM_CSCDR1_UART_CLK_PODF_MASK			(0x7)
-
-/* Define the bits in register CS1CDR and CS2CDR */
-#define MX51_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET	(22)
-#define MX51_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK	(0x7 << 22)
-#define MX51_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET	(16)
-#define MX51_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK	(0x3F << 16)
-#define MX51_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET		(6)
-#define MX51_CCM_CS1CDR_SSI1_CLK_PRED_MASK		(0x7 << 6)
-#define MX51_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET		(0)
-#define MX51_CCM_CS1CDR_SSI1_CLK_PODF_MASK		(0x3F)
-
-#define MX51_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET	(22)
-#define MX51_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK	(0x7 << 22)
-#define MX51_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET	(16)
-#define MX51_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK	(0x3F << 16)
-#define MX51_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET		(6)
-#define MX51_CCM_CS2CDR_SSI2_CLK_PRED_MASK		(0x7 << 6)
-#define MX51_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET		(0)
-#define MX51_CCM_CS2CDR_SSI2_CLK_PODF_MASK		(0x3F)
-
-/* Define the bits in register CDCDR */
-#define MX51_CCM_CDCDR_TVE_CLK_PRED_OFFSET		(28)
-#define MX51_CCM_CDCDR_TVE_CLK_PRED_MASK		(0x7 << 28)
-#define MX51_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET	(25)
-#define MX51_CCM_CDCDR_SPDIF0_CLK_PRED_MASK		(0x7 << 25)
-#define MX51_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET	(19)
-#define MX51_CCM_CDCDR_SPDIF0_CLK_PODF_MASK		(0x3F << 19)
-#define MX51_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET	(16)
-#define MX51_CCM_CDCDR_SPDIF1_CLK_PRED_MASK		(0x7 << 16)
-#define MX51_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET	(9)
-#define MX51_CCM_CDCDR_SPDIF1_CLK_PODF_MASK		(0x3F << 9)
-#define MX51_CCM_CDCDR_DI_CLK_PRED_OFFSET		(6)
-#define MX51_CCM_CDCDR_DI_CLK_PRED_MASK		(0x7 << 6)
-#define MX51_CCM_CDCDR_USB_PHY_PRED_OFFSET		(3)
-#define MX51_CCM_CDCDR_USB_PHY_PRED_MASK		(0x7 << 3)
-#define MX51_CCM_CDCDR_USB_PHY_PODF_OFFSET		(0)
-#define MX51_CCM_CDCDR_USB_PHY_PODF_MASK		(0x7)
-
-/* Define the bits in register CHSCCDR */
-#define MX51_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET		(12)
-#define MX51_CCM_CHSCCDR_ESC_CLK_PRED_MASK		(0x7 << 12)
-#define MX51_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET	(6)
-#define MX51_CCM_CHSCCDR_ESC_CLK_PODF_MASK		(0x3F << 6)
-#define MX51_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET	(3)
-#define MX51_CCM_CHSCCDR_HSC2_CLK_PODF_MASK		(0x7 << 3)
-#define MX51_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET	(0)
-#define MX51_CCM_CHSCCDR_HSC1_CLK_PODF_MASK		(0x7)
-
-/* Define the bits in register CSCDR2 */
-#define MX51_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET		(25)
-#define MX51_CCM_CSCDR2_CSPI_CLK_PRED_MASK		(0x7 << 25)
-#define MX51_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET		(19)
-#define MX51_CCM_CSCDR2_CSPI_CLK_PODF_MASK		(0x3F << 19)
-#define MX51_CCM_CSCDR2_SIM_CLK_PRED_OFFSET		(16)
-#define MX51_CCM_CSCDR2_SIM_CLK_PRED_MASK		(0x7 << 16)
-#define MX51_CCM_CSCDR2_SIM_CLK_PODF_OFFSET		(9)
-#define MX51_CCM_CSCDR2_SIM_CLK_PODF_MASK		(0x3F << 9)
-#define MX51_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET	(6)
-#define MX51_CCM_CSCDR2_SLIMBUS_PRED_MASK		(0x7 << 6)
-#define MX51_CCM_CSCDR2_SLIMBUS_PODF_OFFSET		(0)
-#define MX51_CCM_CSCDR2_SLIMBUS_PODF_MASK		(0x3F)
-
-/* Define the bits in register CSCDR3 */
-#define MX51_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET	(16)
-#define MX51_CCM_CSCDR3_HSI2C_CLK_PRED_MASK		(0x7 << 16)
-#define MX51_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET	(9)
-#define MX51_CCM_CSCDR3_HSI2C_CLK_PODF_MASK		(0x3F << 9)
-#define MX51_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET		(6)
-#define MX51_CCM_CSCDR3_FIRI_CLK_PRED_MASK		(0x7 << 6)
-#define MX51_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET		(0)
-#define MX51_CCM_CSCDR3_FIRI_CLK_PODF_MASK		(0x3F)
-
-/* Define the bits in register CSCDR4 */
-#define MX51_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET	(16)
-#define MX51_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK	(0x7 << 16)
-#define MX51_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET	(9)
-#define MX51_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK	(0x3F << 9)
-#define MX51_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET	(6)
-#define MX51_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK	(0x7 << 6)
-#define MX51_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET	(0)
-#define MX51_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK	(0x3F)
-
-/* Define the bits in register CDHIPR */
-#define MX51_CCM_CDHIPR_ARM_PODF_BUSY			(1 << 16)
-#define MX51_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY		(1 << 8)
-#define MX51_CCM_CDHIPR_DDR_PODF_BUSY			(1 << 7)
-#define MX51_CCM_CDHIPR_EMI_CLK_SEL_BUSY			(1 << 6)
-#define MX51_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY		(1 << 5)
-#define MX51_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY	(1 << 4)
-#define MX51_CCM_CDHIPR_AHB_PODF_BUSY			(1 << 3)
-#define MX51_CCM_CDHIPR_EMI_PODF_BUSY			(1 << 2)
-#define MX51_CCM_CDHIPR_AXI_B_PODF_BUSY			(1 << 1)
-#define MX51_CCM_CDHIPR_AXI_A_PODF_BUSY			(1 << 0)
-
-/* Define the bits in register CDCR */
-#define MX51_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER			(0x1 << 2)
-#define MX51_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET		(0)
-#define MX51_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK		(0x3)
-
-/* Define the bits in register CLPCR */
-#define MX51_CCM_CLPCR_BYPASS_HSC_LPM_HS		(0x1 << 23)
-#define MX51_CCM_CLPCR_BYPASS_SCC_LPM_HS		(0x1 << 22)
-#define MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS		(0x1 << 21)
-#define MX51_CCM_CLPCR_BYPASS_SDMA_LPM_HS		(0x1 << 20)
-#define MX51_CCM_CLPCR_BYPASS_EMI_LPM_HS		(0x1 << 19)
-#define MX51_CCM_CLPCR_BYPASS_IPU_LPM_HS		(0x1 << 18)
-#define MX51_CCM_CLPCR_BYPASS_RTIC_LPM_HS		(0x1 << 17)
-#define MX51_CCM_CLPCR_BYPASS_RNGC_LPM_HS		(0x1 << 16)
-#define MX51_CCM_CLPCR_COSC_PWRDOWN			(0x1 << 11)
-#define MX51_CCM_CLPCR_STBY_COUNT_OFFSET		(9)
-#define MX51_CCM_CLPCR_STBY_COUNT_MASK		(0x3 << 9)
-#define MX51_CCM_CLPCR_VSTBY				(0x1 << 8)
-#define MX51_CCM_CLPCR_DIS_REF_OSC			(0x1 << 7)
-#define MX51_CCM_CLPCR_SBYOS				(0x1 << 6)
-#define MX51_CCM_CLPCR_ARM_CLK_DIS_ON_LPM		(0x1 << 5)
-#define MX51_CCM_CLPCR_LPSR_CLK_SEL_OFFSET		(3)
-#define MX51_CCM_CLPCR_LPSR_CLK_SEL_MASK		(0x3 << 3)
-#define MX51_CCM_CLPCR_LPM_OFFSET			(0)
-#define MX51_CCM_CLPCR_LPM_MASK			(0x3)
-
-/* Define the bits in register CISR */
-#define MX51_CCM_CISR_ARM_PODF_LOADED			(0x1 << 25)
-#define MX51_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED		(0x1 << 21)
-#define MX51_CCM_CISR_AHB_PODF_LOADED			(0x1 << 20)
-#define MX51_CCM_CISR_EMI_PODF_LOADED				(0x1 << 19)
-#define MX51_CCM_CISR_AXI_B_PODF_LOADED			(0x1 << 18)
-#define MX51_CCM_CISR_AXI_A_PODF_LOADED			(0x1 << 17)
-#define MX51_CCM_CISR_DIVIDER_LOADED				(0x1 << 16)
-#define MX51_CCM_CISR_COSC_READY				(0x1 << 6)
-#define MX51_CCM_CISR_CKIH2_READY				(0x1 << 5)
-#define MX51_CCM_CISR_CKIH_READY				(0x1 << 4)
-#define MX51_CCM_CISR_FPM_READY				(0x1 << 3)
-#define MX51_CCM_CISR_LRF_PLL3					(0x1 << 2)
-#define MX51_CCM_CISR_LRF_PLL2					(0x1 << 1)
-#define MX51_CCM_CISR_LRF_PLL1					(0x1)
-
-/* Define the bits in register CIMR */
-#define MX51_CCM_CIMR_MASK_ARM_PODF_LOADED		(0x1 << 25)
-#define MX51_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED	(0x1 << 21)
-#define MX51_CCM_CIMR_MASK_EMI_PODF_LOADED		(0x1 << 20)
-#define MX51_CCM_CIMR_MASK_AXI_C_PODF_LOADED		(0x1 << 19)
-#define MX51_CCM_CIMR_MASK_AXI_B_PODF_LOADED		(0x1 << 18)
-#define MX51_CCM_CIMR_MASK_AXI_A_PODF_LOADED		(0x1 << 17)
-#define MX51_CCM_CIMR_MASK_DIVIDER_LOADED		(0x1 << 16)
-#define MX51_CCM_CIMR_MASK_COSC_READY			(0x1 << 5)
-#define MX51_CCM_CIMR_MASK_CKIH_READY			(0x1 << 4)
-#define MX51_CCM_CIMR_MASK_FPM_READY			(0x1 << 3)
-#define MX51_CCM_CIMR_MASK_LRF_PLL3			(0x1 << 2)
-#define MX51_CCM_CIMR_MASK_LRF_PLL2			(0x1 << 1)
-#define MX51_CCM_CIMR_MASK_LRF_PLL1			(0x1)
-
-/* Define the bits in register CCOSR */
-#define MX51_CCM_CCOSR_CKO2_EN_OFFSET			(0x1 << 24)
-#define MX51_CCM_CCOSR_CKO2_DIV_OFFSET			(21)
-#define MX51_CCM_CCOSR_CKO2_DIV_MASK			(0x7 << 21)
-#define MX51_CCM_CCOSR_CKO2_SEL_OFFSET			(16)
-#define MX51_CCM_CCOSR_CKO2_SEL_MASK			(0x1F << 16)
-#define MX51_CCM_CCOSR_CKOL_EN				(0x1 << 7)
-#define MX51_CCM_CCOSR_CKOL_DIV_OFFSET			(4)
-#define MX51_CCM_CCOSR_CKOL_DIV_MASK			(0x7 << 4)
-#define MX51_CCM_CCOSR_CKOL_SEL_OFFSET			(0)
-#define MX51_CCM_CCOSR_CKOL_SEL_MASK			(0xF)
-
-/* Define the bits in registers CGPR */
-#define MX51_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE		(0x1 << 4)
-#define MX51_CCM_CGPR_FPM_SEL				(0x1 << 3)
-#define MX51_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET		(0)
-#define MX51_CCM_CGPR_VL_L2BIST_CLKDIV_MASK		(0x7)
-
-/* Define the bits in registers CCGRx */
-#define MX51_CCM_CCGR_CG_MASK				0x3
-#define MX51_CCM_CCGR_MOD_OFF				0x0
-#define MX51_CCM_CCGR_MOD_ON				0x3
-#define MX51_CCM_CCGR_MOD_IDLE				0x1
-
-#define MX51_CCM_CCGR0_CG15_OFFSET			30
-#define MX51_CCM_CCGR0_CG15_MASK			(0x3 << 30)
-#define MX51_CCM_CCGR0_CG14_OFFSET			28
-#define MX51_CCM_CCGR0_CG14_MASK			(0x3 << 28)
-#define MX51_CCM_CCGR0_CG13_OFFSET			26
-#define MX51_CCM_CCGR0_CG13_MASK			(0x3 << 26)
-#define MX51_CCM_CCGR0_CG12_OFFSET			24
-#define MX51_CCM_CCGR0_CG12_MASK			(0x3 << 24)
-#define MX51_CCM_CCGR0_CG11_OFFSET			22
-#define MX51_CCM_CCGR0_CG11_MASK			(0x3 << 22)
-#define MX51_CCM_CCGR0_CG10_OFFSET			20
-#define MX51_CCM_CCGR0_CG10_MASK			(0x3 << 20)
-#define MX51_CCM_CCGR0_CG9_OFFSET			18
-#define MX51_CCM_CCGR0_CG9_MASK			(0x3 << 18)
-#define MX51_CCM_CCGR0_CG8_OFFSET			16
-#define MX51_CCM_CCGR0_CG8_MASK			(0x3 << 16)
-#define MX51_CCM_CCGR0_CG7_OFFSET			14
-#define MX51_CCM_CCGR0_CG6_OFFSET			12
-#define MX51_CCM_CCGR0_CG5_OFFSET			10
-#define MX51_CCM_CCGR0_CG5_MASK			(0x3 << 10)
-#define MX51_CCM_CCGR0_CG4_OFFSET			8
-#define MX51_CCM_CCGR0_CG4_MASK			(0x3 << 8)
-#define MX51_CCM_CCGR0_CG3_OFFSET			6
-#define MX51_CCM_CCGR0_CG3_MASK			(0x3 << 6)
-#define MX51_CCM_CCGR0_CG2_OFFSET			4
-#define MX51_CCM_CCGR0_CG2_MASK			(0x3 << 4)
-#define MX51_CCM_CCGR0_CG1_OFFSET			2
-#define MX51_CCM_CCGR0_CG1_MASK			(0x3 << 2)
-#define MX51_CCM_CCGR0_CG0_OFFSET			0
-#define MX51_CCM_CCGR0_CG0_MASK			0x3
-
-#define MX51_CCM_CCGR1_CG15_OFFSET			30
-#define MX51_CCM_CCGR1_CG14_OFFSET			28
-#define MX51_CCM_CCGR1_CG13_OFFSET			26
-#define MX51_CCM_CCGR1_CG12_OFFSET			24
-#define MX51_CCM_CCGR1_CG11_OFFSET			22
-#define MX51_CCM_CCGR1_CG10_OFFSET			20
-#define MX51_CCM_CCGR1_CG9_OFFSET			18
-#define MX51_CCM_CCGR1_CG8_OFFSET			16
-#define MX51_CCM_CCGR1_CG7_OFFSET			14
-#define MX51_CCM_CCGR1_CG6_OFFSET			12
-#define MX51_CCM_CCGR1_CG5_OFFSET			10
-#define MX51_CCM_CCGR1_CG4_OFFSET			8
-#define MX51_CCM_CCGR1_CG3_OFFSET			6
-#define MX51_CCM_CCGR1_CG2_OFFSET			4
-#define MX51_CCM_CCGR1_CG1_OFFSET			2
-#define MX51_CCM_CCGR1_CG0_OFFSET			0
-
-#define MX51_CCM_CCGR2_CG15_OFFSET			30
-#define MX51_CCM_CCGR2_CG14_OFFSET			28
-#define MX51_CCM_CCGR2_CG13_OFFSET			26
-#define MX51_CCM_CCGR2_CG12_OFFSET			24
-#define MX51_CCM_CCGR2_CG11_OFFSET			22
-#define MX51_CCM_CCGR2_CG10_OFFSET			20
-#define MX51_CCM_CCGR2_CG9_OFFSET			18
-#define MX51_CCM_CCGR2_CG8_OFFSET			16
-#define MX51_CCM_CCGR2_CG7_OFFSET			14
-#define MX51_CCM_CCGR2_CG6_OFFSET			12
-#define MX51_CCM_CCGR2_CG5_OFFSET			10
-#define MX51_CCM_CCGR2_CG4_OFFSET			8
-#define MX51_CCM_CCGR2_CG3_OFFSET			6
-#define MX51_CCM_CCGR2_CG2_OFFSET			4
-#define MX51_CCM_CCGR2_CG1_OFFSET			2
-#define MX51_CCM_CCGR2_CG0_OFFSET			0
-
-#define MX51_CCM_CCGR3_CG15_OFFSET			30
-#define MX51_CCM_CCGR3_CG14_OFFSET			28
-#define MX51_CCM_CCGR3_CG13_OFFSET			26
-#define MX51_CCM_CCGR3_CG12_OFFSET			24
-#define MX51_CCM_CCGR3_CG11_OFFSET			22
-#define MX51_CCM_CCGR3_CG10_OFFSET			20
-#define MX51_CCM_CCGR3_CG9_OFFSET			18
-#define MX51_CCM_CCGR3_CG8_OFFSET			16
-#define MX51_CCM_CCGR3_CG7_OFFSET			14
-#define MX51_CCM_CCGR3_CG6_OFFSET			12
-#define MX51_CCM_CCGR3_CG5_OFFSET			10
-#define MX51_CCM_CCGR3_CG4_OFFSET			8
-#define MX51_CCM_CCGR3_CG3_OFFSET			6
-#define MX51_CCM_CCGR3_CG2_OFFSET			4
-#define MX51_CCM_CCGR3_CG1_OFFSET			2
-#define MX51_CCM_CCGR3_CG0_OFFSET			0
-
-#define MX51_CCM_CCGR4_CG15_OFFSET			30
-#define MX51_CCM_CCGR4_CG14_OFFSET			28
-#define MX51_CCM_CCGR4_CG13_OFFSET			26
-#define MX51_CCM_CCGR4_CG12_OFFSET			24
-#define MX51_CCM_CCGR4_CG11_OFFSET			22
-#define MX51_CCM_CCGR4_CG10_OFFSET			20
-#define MX51_CCM_CCGR4_CG9_OFFSET			18
-#define MX51_CCM_CCGR4_CG8_OFFSET			16
-#define MX51_CCM_CCGR4_CG7_OFFSET			14
-#define MX51_CCM_CCGR4_CG6_OFFSET			12
-#define MX51_CCM_CCGR4_CG5_OFFSET			10
-#define MX51_CCM_CCGR4_CG4_OFFSET			8
-#define MX51_CCM_CCGR4_CG3_OFFSET			6
-#define MX51_CCM_CCGR4_CG2_OFFSET			4
-#define MX51_CCM_CCGR4_CG1_OFFSET			2
-#define MX51_CCM_CCGR4_CG0_OFFSET			0
-
-#define MX51_CCM_CCGR5_CG15_OFFSET			30
-#define MX51_CCM_CCGR5_CG14_OFFSET			28
-#define MX51_CCM_CCGR5_CG14_MASK			(0x3 << 28)
-#define MX51_CCM_CCGR5_CG13_OFFSET			26
-#define MX51_CCM_CCGR5_CG13_MASK			(0x3 << 26)
-#define MX51_CCM_CCGR5_CG12_OFFSET			24
-#define MX51_CCM_CCGR5_CG12_MASK			(0x3 << 24)
-#define MX51_CCM_CCGR5_CG11_OFFSET			22
-#define MX51_CCM_CCGR5_CG11_MASK			(0x3 << 22)
-#define MX51_CCM_CCGR5_CG10_OFFSET			20
-#define MX51_CCM_CCGR5_CG10_MASK			(0x3 << 20)
-#define MX51_CCM_CCGR5_CG9_OFFSET			18
-#define MX51_CCM_CCGR5_CG9_MASK			(0x3 << 18)
-#define MX51_CCM_CCGR5_CG8_OFFSET			16
-#define MX51_CCM_CCGR5_CG8_MASK			(0x3 << 16)
-#define MX51_CCM_CCGR5_CG7_OFFSET			14
-#define MX51_CCM_CCGR5_CG7_MASK			(0x3 << 14)
-#define MX51_CCM_CCGR5_CG6_OFFSET			12
-#define MX51_CCM_CCGR5_CG5_OFFSET			10
-#define MX51_CCM_CCGR5_CG4_OFFSET			8
-#define MX51_CCM_CCGR5_CG3_OFFSET			6
-#define MX51_CCM_CCGR5_CG2_OFFSET			4
-#define MX51_CCM_CCGR5_CG2_MASK			(0x3 << 4)
-#define MX51_CCM_CCGR5_CG1_OFFSET			2
-#define MX51_CCM_CCGR5_CG0_OFFSET			0
-#define MX51_CCM_CCGR6_CG7_OFFSET            14
-#define MX51_CCM_CCGR6_CG7_MASK          (0x3 << 14)
-#define MX51_CCM_CCGR6_CG6_OFFSET			12
-#define MX51_CCM_CCGR6_CG6_MASK			(0x3 << 12)
-#define MX51_CCM_CCGR6_CG5_OFFSET			10
-#define MX51_CCM_CCGR6_CG5_MASK			(0x3 << 10)
-#define MX51_CCM_CCGR6_CG4_OFFSET			8
-#define MX51_CCM_CCGR6_CG4_MASK			(0x3 << 8)
-#define MX51_CCM_CCGR6_CG3_OFFSET			6
-#define MX51_CCM_CCGR6_CG2_OFFSET			4
-#define MX51_CCM_CCGR6_CG1_OFFSET			2
-#define MX51_CCM_CCGR6_CG0_OFFSET			0
-
-/* CORTEXA8 platform */
-#define MX51_CORTEXA8_PLAT_PVID		(MX51_CORTEXA8_BASE + 0x0)
-#define MX51_CORTEXA8_PLAT_GPC		(MX51_CORTEXA8_BASE + 0x4)
-#define MX51_CORTEXA8_PLAT_PIC		(MX51_CORTEXA8_BASE + 0x8)
-#define MX51_CORTEXA8_PLAT_LPC		(MX51_CORTEXA8_BASE + 0xC)
-#define MX51_CORTEXA8_PLAT_NEON_LPC	(MX51_CORTEXA8_BASE + 0x10)
-#define MX51_CORTEXA8_PLAT_ICGC		(MX51_CORTEXA8_BASE + 0x14)
-#define MX51_CORTEXA8_PLAT_AMC		(MX51_CORTEXA8_BASE + 0x18)
-#define MX51_CORTEXA8_PLAT_NMC		(MX51_CORTEXA8_BASE + 0x20)
-#define MX51_CORTEXA8_PLAT_NMS		(MX51_CORTEXA8_BASE + 0x24)
-
-/* DVFS CORE */
-#define MX51_DVFSTHRS		(MX51_DVFS_CORE_BASE + 0x00)
-#define MX51_DVFSCOUN		(MX51_DVFS_CORE_BASE + 0x04)
-#define MX51_DVFSSIG1		(MX51_DVFS_CORE_BASE + 0x08)
-#define MX51_DVFSSIG0		(MX51_DVFS_CORE_BASE + 0x0C)
-#define MX51_DVFSGPC0		(MX51_DVFS_CORE_BASE + 0x10)
-#define MX51_DVFSGPC1		(MX51_DVFS_CORE_BASE + 0x14)
-#define MX51_DVFSGPBT		(MX51_DVFS_CORE_BASE + 0x18)
-#define MX51_DVFSEMAC		(MX51_DVFS_CORE_BASE + 0x1C)
-#define MX51_DVFSCNTR		(MX51_DVFS_CORE_BASE + 0x20)
-#define MX51_DVFSLTR0_0		(MX51_DVFS_CORE_BASE + 0x24)
-#define MX51_DVFSLTR0_1		(MX51_DVFS_CORE_BASE + 0x28)
-#define MX51_DVFSLTR1_0		(MX51_DVFS_CORE_BASE + 0x2C)
-#define MX51_DVFSLTR1_1		(MX51_DVFS_CORE_BASE + 0x30)
-#define MX51_DVFSPT0 		(MX51_DVFS_CORE_BASE + 0x34)
-#define MX51_DVFSPT1 		(MX51_DVFS_CORE_BASE + 0x38)
-#define MX51_DVFSPT2 		(MX51_DVFS_CORE_BASE + 0x3C)
-#define MX51_DVFSPT3 		(MX51_DVFS_CORE_BASE + 0x40)
-
-/* GPC */
-#define MX51_GPC_CNTR		(MX51_GPC_BASE + 0x0)
-#define MX51_GPC_PGR		(MX51_GPC_BASE + 0x4)
-#define MX51_GPC_VCR		(MX51_GPC_BASE + 0x8)
-#define MX51_GPC_ALL_PU		(MX51_GPC_BASE + 0xC)
-#define MX51_GPC_NEON		(MX51_GPC_BASE + 0x10)
-#define MX51_GPC_PGR_ARMPG_OFFSET	8
-#define MX51_GPC_PGR_ARMPG_MASK		(3 << 8)
-
-/* PGC */
-#define MX51_PGC_IPU_PGCR	(MX51_PGC_IPU_BASE + 0x0)
-#define MX51_PGC_IPU_PGSR	(MX51_PGC_IPU_BASE + 0xC)
-#define MX51_PGC_VPU_PGCR	(MX51_PGC_VPU_BASE + 0x0)
-#define MX51_PGC_VPU_PGSR	(MX51_PGC_VPU_BASE + 0xC)
-#define MX51_PGC_GPU_PGCR	(MX51_PGC_GPU_BASE + 0x0)
-#define MX51_PGC_GPU_PGSR	(MX51_PGC_GPU_BASE + 0xC)
-
-#define MX51_PGCR_PCR		1
-#define MX51_SRPGCR_PCR		1
-#define MX51_EMPGCR_PCR		1
-#define MX51_PGSR_PSR		1
-
-
-#define MX51_CORTEXA8_PLAT_LPC_DSM	(1 << 0)
-#define MX51_CORTEXA8_PLAT_LPC_DBG_DSM	(1 << 1)
-
-/* SRPG */
-#define MX51_SRPG_NEON_SRPGCR	(MX51_SRPG_NEON_BASE + 0x0)
-#define MX51_SRPG_NEON_PUPSCR	(MX51_SRPG_NEON_BASE + 0x4)
-#define MX51_SRPG_NEON_PDNSCR	(MX51_SRPG_NEON_BASE + 0x8)
-
-#define MX51_SRPG_ARM_SRPGCR	(MX51_SRPG_ARM_BASE + 0x0)
-#define MX51_SRPG_ARM_PUPSCR	(MX51_SRPG_ARM_BASE + 0x4)
-#define MX51_SRPG_ARM_PDNSCR	(MX51_SRPG_ARM_BASE + 0x8)
-
-#define MX51_SRPG_EMPGC0_SRPGCR	(MX51_SRPG_EMPGC0_BASE + 0x0)
-#define MX51_SRPG_EMPGC0_PUPSCR	(MX51_SRPG_EMPGC0_BASE + 0x4)
-#define MX51_SRPG_EMPGC0_PDNSCR	(MX51_SRPG_EMPGC0_BASE + 0x8)
-
-#define MX51_SRPG_EMPGC1_SRPGCR	(MX51_SRPG_EMPGC1_BASE + 0x0)
-#define MX51_SRPG_EMPGC1_PUPSCR	(MX51_SRPG_EMPGC1_BASE + 0x4)
-#define MX51_SRPG_EMPGC1_PDNSCR	(MX51_SRPG_EMPGC1_BASE + 0x8)
-
-#define MX51_SRPG_MEGAMIX_SRPGCR		(MX51_SRPG_MEGAMIX_BASE + 0x0)
-#define MX51_SRPG_MEGAMIX_PUPSCR		(MX51_SRPG_MEGAMIX_BASE + 0x4)
-#define MX51_SRPG_MEGAMIX_PDNSCR		(MX51_SRPG_MEGAMIX_BASE + 0x8)
-
-#define MX51_SRPGC_EMI_SRPGCR	(MX51_SRPGC_EMI_BASE + 0x0)
-#define MX51_SRPGC_EMI_PUPSCR	(MX51_SRPGC_EMI_BASE + 0x4)
-#define MX51_SRPGC_EMI_PDNSCR	(MX51_SRPGC_EMI_BASE + 0x8)
-
-#endif				/* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
-
-
diff --git a/arch/arm/mach-imx/include/mach/clock-imx51_53.h b/arch/arm/mach-imx/include/mach/clock-imx51_53.h
new file mode 100644
index 0000000000..34ca1bb94f
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/clock-imx51_53.h
@@ -0,0 +1,623 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
+#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
+
+/* PLL Register Offsets */
+#define MX5_PLL_DP_CTL			0x00
+#define MX5_PLL_DP_CONFIG		0x04
+#define MX5_PLL_DP_OP			0x08
+#define MX5_PLL_DP_MFD			0x0C
+#define MX5_PLL_DP_MFN			0x10
+#define MX5_PLL_DP_MFNMINUS		0x14
+#define MX5_PLL_DP_MFNPLUS		0x18
+#define MX5_PLL_DP_HFS_OP		0x1C
+#define MX5_PLL_DP_HFS_MFD		0x20
+#define MX5_PLL_DP_HFS_MFN		0x24
+#define MX5_PLL_DP_MFN_TOGC		0x28
+#define MX5_PLL_DP_DESTAT		0x2c
+
+/* PLL Register Bit definitions */
+#define MX5_PLL_DP_CTL_MUL_CTRL		0x2000
+#define MX5_PLL_DP_CTL_DPDCK0_2_EN	0x1000
+#define MX5_PLL_DP_CTL_DPDCK0_2_OFFSET	12
+#define MX5_PLL_DP_CTL_ADE		0x800
+#define MX5_PLL_DP_CTL_REF_CLK_DIV	0x400
+#define MX5_PLL_DP_CTL_REF_CLK_SEL_MASK	(3 << 8)
+#define MX5_PLL_DP_CTL_REF_CLK_SEL_OFFSET	8
+#define MX5_PLL_DP_CTL_HFSM		0x80
+#define MX5_PLL_DP_CTL_PRE		0x40
+#define MX5_PLL_DP_CTL_UPEN		0x20
+#define MX5_PLL_DP_CTL_RST		0x10
+#define MX5_PLL_DP_CTL_RCP		0x8
+#define MX5_PLL_DP_CTL_PLM		0x4
+#define MX5_PLL_DP_CTL_BRM0		0x2
+#define MX5_PLL_DP_CTL_LRF		0x1
+
+#define MX5_PLL_DP_CONFIG_BIST		0x8
+#define MX5_PLL_DP_CONFIG_SJC_CE	0x4
+#define MX5_PLL_DP_CONFIG_AREN		0x2
+#define MX5_PLL_DP_CONFIG_LDREQ		0x1
+
+#define MX5_PLL_DP_OP_MFI_OFFSET	4
+#define MX5_PLL_DP_OP_MFI_MASK		(0xF << 4)
+#define MX5_PLL_DP_OP_PDF_OFFSET	0
+#define MX5_PLL_DP_OP_PDF_MASK		0xF
+
+#define MX5_PLL_DP_MFD_OFFSET		0
+#define MX5_PLL_DP_MFD_MASK		0x07FFFFFF
+
+#define MX5_PLL_DP_MFN_OFFSET		0x0
+#define MX5_PLL_DP_MFN_MASK		0x07FFFFFF
+
+#define MX5_PLL_DP_MFN_TOGC_TOG_DIS	(1 << 17)
+#define MX5_PLL_DP_MFN_TOGC_TOG_EN	(1 << 16)
+#define MX5_PLL_DP_MFN_TOGC_CNT_OFFSET	0x0
+#define MX5_PLL_DP_MFN_TOGC_CNT_MASK	0xFFFF
+
+#define MX5_PLL_DxP_DESTAT_TOG_SEL	(1 << 31)
+#define MX5_PLL_DP_DESTAT_MFN		0x07FFFFFF
+
+/* Register addresses of CCM */
+#define MX5_CCM_CCR		0x00
+#define MX5_CCM_CCDR		0x04
+#define MX5_CCM_CSR		0x08
+#define MX5_CCM_CCSR		0x0C
+#define MX5_CCM_CACRR		0x10
+#define MX5_CCM_CBCDR		0x14
+#define MX5_CCM_CBCMR		0x18
+#define MX5_CCM_CSCMR1		0x1C
+#define MX5_CCM_CSCMR2		0x20
+#define MX5_CCM_CSCDR1		0x24
+#define MX5_CCM_CS1CDR		0x28
+#define MX5_CCM_CS2CDR		0x2C
+#define MX5_CCM_CDCDR		0x30
+#define MX5_CCM_CHSCDR		0x34
+#define MX5_CCM_CSCDR2		0x38
+#define MX5_CCM_CSCDR3		0x3C
+#define MX5_CCM_CSCDR4		0x40
+#define MX5_CCM_CWDR		0x44
+#define MX5_CCM_CDHIPR		0x48
+#define MX5_CCM_CDCR		0x4C
+#define MX5_CCM_CTOR		0x50
+#define MX5_CCM_CLPCR		0x54
+#define MX5_CCM_CISR		0x58
+#define MX5_CCM_CIMR		0x5C
+#define MX5_CCM_CCOSR		0x60
+#define MX5_CCM_CGPR		0x64
+#define MX5_CCM_CCGR0		0x68
+#define MX5_CCM_CCGR1		0x6C
+#define MX5_CCM_CCGR2		0x70
+#define MX5_CCM_CCGR3		0x74
+#define MX5_CCM_CCGR4		0x78
+#define MX5_CCM_CCGR5		0x7C
+#define MX5_CCM_CCGR6		0x80
+#define MX5_CCM_CMEOR		0x84
+
+/* Define the bits in register CCR */
+#define MX5_CCM_CCR_COSC_EN		(1 << 12)
+#define MX5_CCM_CCR_FPM_MULT_MASK	(1 << 11)
+#define MX5_CCM_CCR_CAMP2_EN		(1 << 10)
+#define MX5_CCM_CCR_CAMP1_EN		(1 << 9)
+#define MX5_CCM_CCR_FPM_EN		(1 << 8)
+#define MX5_CCM_CCR_OSCNT_OFFSET	(0)
+#define MX5_CCM_CCR_OSCNT_MASK	(0xFF)
+
+/* Define the bits in register CCDR */
+#define MX5_CCM_CCDR_HSC_HS_MASK	(0x1 << 18)
+#define MX5_CCM_CCDR_IPU_HS_MASK	(0x1 << 17)
+#define MX5_CCM_CCDR_EMI_HS_MASK	(0x1 << 16)
+
+/* Define the bits in register CSR */
+#define MX5_CCM_CSR_COSR_READY	(1 << 5)
+#define MX5_CCM_CSR_LVS_VALUE	(1 << 4)
+#define MX5_CCM_CSR_CAMP2_READY	(1 << 3)
+#define MX5_CCM_CSR_CAMP1_READY	(1 << 2)
+#define MX5_CCM_CSR_FPM_READY	(1 << 1)
+#define MX5_CCM_CSR_REF_EN_B	(1 << 0)
+
+/* Define the bits in register CCSR */
+#define MX5_CCM_CCSR_LP_APM_SEL		(0x1 << 9)
+#define MX5_CCM_CCSR_STEP_SEL_OFFSET	(7)
+#define MX5_CCM_CCSR_STEP_SEL_MASK	(0x3 << 7)
+#define MX5_CCM_CCSR_STEP_SEL_LP_APM	   0
+#define MX5_CCM_CCSR_STEP_SEL_PLL1_BYPASS  1 /* Only when JTAG connected? */
+#define MX5_CCM_CCSR_STEP_SEL_PLL2_DIVIDED 2
+#define MX5_CCM_CCSR_STEP_SEL_PLL3_DIVIDED 3
+#define MX5_CCM_CCSR_PLL2_PODF_OFFSET	(5)
+#define MX5_CCM_CCSR_PLL2_PODF_MASK	(0x3 << 5)
+#define MX5_CCM_CCSR_PLL3_PODF_OFFSET	(3)
+#define MX5_CCM_CCSR_PLL3_PODF_MASK	(0x3 << 3)
+#define MX5_CCM_CCSR_PLL1_SW_CLK_SEL	(1 << 2) /* 0: pll1_main_clk,
+						    1: step_clk */
+#define MX5_CCM_CCSR_PLL2_SW_CLK_SEL	(1 << 1)
+#define MX5_CCM_CCSR_PLL3_SW_CLK_SEL	(1 << 0)
+
+/* Define the bits in register CACRR */
+#define MX5_CCM_CACRR_ARM_PODF_OFFSET	(0)
+#define MX5_CCM_CACRR_ARM_PODF_MASK	(0x7)
+
+/* Define the bits in register CBCDR */
+#define MX5_CCM_CBCDR_EMI_CLK_SEL		(0x1 << 26)
+#define MX5_CCM_CBCDR_PERIPH_CLK_SEL		(0x1 << 25)
+#define MX5_CCM_CBCDR_DDR_HF_SEL_OFFSET		(30)
+#define MX5_CCM_CBCDR_DDR_HF_SEL		(0x1 << 30)
+#define MX5_CCM_CBCDR_DDR_PODF_OFFSET		(27)
+#define MX5_CCM_CBCDR_DDR_PODF_MASK		(0x7 << 27)
+#define MX5_CCM_CBCDR_EMI_PODF_OFFSET		(22)
+#define MX5_CCM_CBCDR_EMI_PODF_MASK		(0x7 << 22)
+#define MX5_CCM_CBCDR_AXI_B_PODF_OFFSET		(19)
+#define MX5_CCM_CBCDR_AXI_B_PODF_MASK		(0x7 << 19)
+#define MX5_CCM_CBCDR_AXI_A_PODF_OFFSET		(16)
+#define MX5_CCM_CBCDR_AXI_A_PODF_MASK		(0x7 << 16)
+#define MX5_CCM_CBCDR_NFC_PODF_OFFSET		(13)
+#define MX5_CCM_CBCDR_NFC_PODF_MASK		(0x7 << 13)
+#define MX5_CCM_CBCDR_AHB_PODF_OFFSET		(10)
+#define MX5_CCM_CBCDR_AHB_PODF_MASK		(0x7 << 10)
+#define MX5_CCM_CBCDR_IPG_PODF_OFFSET		(8)
+#define MX5_CCM_CBCDR_IPG_PODF_MASK		(0x3 << 8)
+#define MX5_CCM_CBCDR_PERCLK_PRED1_OFFSET	(6)
+#define MX5_CCM_CBCDR_PERCLK_PRED1_MASK		(0x3 << 6)
+#define MX5_CCM_CBCDR_PERCLK_PRED2_OFFSET	(3)
+#define MX5_CCM_CBCDR_PERCLK_PRED2_MASK		(0x7 << 3)
+#define MX5_CCM_CBCDR_PERCLK_PODF_OFFSET	(0)
+#define MX5_CCM_CBCDR_PERCLK_PODF_MASK		(0x7)
+
+/* Define the bits in register CBCMR */
+#define MX5_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET	(14)
+#define MX5_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK	(0x3 << 14)
+#define MX5_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET	(12)
+#define MX5_CCM_CBCMR_PERIPH_CLK_SEL_MASK	(0x3 << 12)
+#define MX5_CCM_CBCMR_DDR_CLK_SEL_OFFSET	(10)
+#define MX5_CCM_CBCMR_DDR_CLK_SEL_MASK		(0x3 << 10)
+#define MX5_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET	(8)
+#define MX5_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK	(0x3 << 8)
+#define MX5_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET	(6)
+#define MX5_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK	(0x3 << 6)
+#define MX5_CCM_CBCMR_GPU_CLK_SEL_OFFSET	(4)
+#define MX5_CCM_CBCMR_GPU_CLK_SEL_MASK		(0x3 << 4)
+#define MX5_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET	(14)
+#define MX5_CCM_CBCMR_GPU2D_CLK_SEL_MASK	(0x3 << 14)
+#define MX5_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL	(0x1 << 1)
+#define MX5_CCM_CBCMR_PERCLK_IPG_CLK_SEL	(0x1 << 0)
+
+/* Define the bits in register CSCMR1 */
+#define MX5_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET		(30)
+#define MX5_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK		(0x3 << 30)
+#define MX5_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET		(28)
+#define MX5_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK		(0x3 << 28)
+#define MX5_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET		(26)
+#define MX5_CCM_CSCMR1_USB_PHY_CLK_SEL			(0x1 << 26)
+#define MX5_CCM_CSCMR1_UART_CLK_SEL_OFFSET		(24)
+#define MX5_CCM_CSCMR1_UART_CLK_SEL_MASK		(0x3 << 24)
+#define MX5_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET		(22)
+#define MX5_CCM_CSCMR1_USBOH3_CLK_SEL_MASK		(0x3 << 22)
+#define MX5_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET	(20)
+#define MX5_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK	(0x3 << 20)
+#define MX5_CCM_CSCMR1_ESDHC3_CLK_SEL			(0x1 << 19)
+#define MX5_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL	(0x1 << 19)
+#define MX5_CCM_CSCMR1_ESDHC4_CLK_SEL			(0x1 << 18)
+#define MX5_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET	(16)
+#define MX5_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK	(0x3 << 16)
+#define MX5_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_OFFSET	(16)
+#define MX5_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_MASK		(0x3 << 16)
+#define MX5_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET		(14)
+#define MX5_CCM_CSCMR1_SSI1_CLK_SEL_MASK		(0x3 << 14)
+#define MX5_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET		(12)
+#define MX5_CCM_CSCMR1_SSI2_CLK_SEL_MASK		(0x3 << 12)
+#define MX5_CCM_CSCMR1_SSI3_CLK_SEL			(0x1 << 11)
+#define MX5_CCM_CSCMR1_VPU_RCLK_SEL			(0x1 << 10)
+#define MX5_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET		(8)
+#define MX5_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK		(0x3 << 8)
+#define MX5_CCM_CSCMR1_TVE_CLK_SEL			(0x1 << 7)
+#define MX5_CCM_CSCMR1_TVE_EXT_CLK_SEL			(0x1 << 6)
+#define MX5_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET		(4)
+#define MX5_CCM_CSCMR1_CSPI_CLK_SEL_MASK		(0x3 << 4)
+#define MX5_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET		(2)
+#define MX5_CCM_CSCMR1_SPDIF_CLK_SEL_MASK		(0x3 << 2)
+#define MX5_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL		(0x1 << 1)
+#define MX5_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL		(0x1)
+
+/* Define the bits in register CSCMR2 */
+#define MX5_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n)		(26+n*3)
+#define MX5_CCM_CSCMR2_DI_CLK_SEL_MASK(n)		(0x7 << (26+n*3))
+#define MX5_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET		(24)
+#define MX5_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK		(0x3 << 24)
+#define MX5_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET		(22)
+#define MX5_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK		(0x3 << 22)
+#define MX5_CCM_CSCMR2_ESC_CLK_SEL_OFFSET		(20)
+#define MX5_CCM_CSCMR2_ESC_CLK_SEL_MASK			(0x3 << 20)
+#define MX5_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET		(18)
+#define MX5_CCM_CSCMR2_HSC2_CLK_SEL_MASK		(0x3 << 18)
+#define MX5_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET		(16)
+#define MX5_CCM_CSCMR2_HSC1_CLK_SEL_MASK		(0x3 << 16)
+#define MX5_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET		(14)
+#define MX5_CCM_CSCMR2_HSI2C_CLK_SEL_MASK		(0x3 << 14)
+#define MX5_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET		(12)
+#define MX5_CCM_CSCMR2_FIRI_CLK_SEL_MASK		(0x3 << 12)
+#define MX5_CCM_CSCMR2_SIM_CLK_SEL_OFFSET		(10)
+#define MX5_CCM_CSCMR2_SIM_CLK_SEL_MASK			(0x3 << 10)
+#define MX5_CCM_CSCMR2_SLIMBUS_COM			(0x1 << 9)
+#define MX5_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET		(6)
+#define MX5_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK		(0x7 << 6)
+#define MX5_CCM_CSCMR2_SPDIF1_COM			(1 << 5)
+#define MX5_CCM_CSCMR2_SPDIF0_COM			(1 << 4)
+#define MX5_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET		(2)
+#define MX5_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK		(0x3 << 2)
+#define MX5_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET		(0)
+#define MX5_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK		(0x3)
+
+/* Define the bits in register CSCDR1 */
+#define MX5_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET	(22)
+#define MX5_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK	(0x7 << 22)
+#define MX5_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET	(19)
+#define MX5_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK	(0x7 << 19)
+#define MX5_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_OFFSET	(22)
+#define MX5_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK	(0x7 << 22)
+#define MX5_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET	(19)
+#define MX5_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK	(0x7 << 19)
+#define MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET	(16)
+#define MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK	(0x7 << 16)
+#define MX5_CCM_CSCDR1_PGC_CLK_PODF_OFFSET		(14)
+#define MX5_CCM_CSCDR1_PGC_CLK_PODF_MASK		(0x3 << 14)
+#define MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET	(11)
+#define MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK	(0x7 << 11)
+#define MX5_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET		(8)
+#define MX5_CCM_CSCDR1_USBOH3_CLK_PRED_MASK		(0x7 << 8)
+#define MX5_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET		(6)
+#define MX5_CCM_CSCDR1_USBOH3_CLK_PODF_MASK		(0x3 << 6)
+#define MX5_CCM_CSCDR1_UART_CLK_PRED_OFFSET		(3)
+#define MX5_CCM_CSCDR1_UART_CLK_PRED_MASK		(0x7 << 3)
+#define MX5_CCM_CSCDR1_UART_CLK_PODF_OFFSET		(0)
+#define MX5_CCM_CSCDR1_UART_CLK_PODF_MASK		(0x7)
+
+/* Define the bits in register CS1CDR and CS2CDR */
+#define MX5_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET		(22)
+#define MX5_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK		(0x7 << 22)
+#define MX5_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET		(16)
+#define MX5_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK		(0x3F << 16)
+#define MX5_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET		(6)
+#define MX5_CCM_CS1CDR_SSI1_CLK_PRED_MASK		(0x7 << 6)
+#define MX5_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET		(0)
+#define MX5_CCM_CS1CDR_SSI1_CLK_PODF_MASK		(0x3F)
+
+#define MX5_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET		(22)
+#define MX5_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK		(0x7 << 22)
+#define MX5_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET		(16)
+#define MX5_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK		(0x3F << 16)
+#define MX5_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET		(6)
+#define MX5_CCM_CS2CDR_SSI2_CLK_PRED_MASK		(0x7 << 6)
+#define MX5_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET		(0)
+#define MX5_CCM_CS2CDR_SSI2_CLK_PODF_MASK		(0x3F)
+
+/* Define the bits in register CDCDR */
+#define MX5_CCM_CDCDR_TVE_CLK_PRED_OFFSET		(28)
+#define MX5_CCM_CDCDR_TVE_CLK_PRED_MASK			(0x7 << 28)
+#define MX5_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET		(25)
+#define MX5_CCM_CDCDR_SPDIF0_CLK_PRED_MASK		(0x7 << 25)
+#define MX5_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET		(19)
+#define MX5_CCM_CDCDR_SPDIF0_CLK_PODF_MASK		(0x3F << 19)
+#define MX5_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET		(16)
+#define MX5_CCM_CDCDR_SPDIF1_CLK_PRED_MASK		(0x7 << 16)
+#define MX5_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET		(9)
+#define MX5_CCM_CDCDR_SPDIF1_CLK_PODF_MASK		(0x3F << 9)
+#define MX5_CCM_CDCDR_DI_CLK_PRED_OFFSET		(6)
+#define MX5_CCM_CDCDR_DI_CLK_PRED_MASK			(0x7 << 6)
+#define MX5_CCM_CDCDR_USB_PHY_PRED_OFFSET		(3)
+#define MX5_CCM_CDCDR_USB_PHY_PRED_MASK			(0x7 << 3)
+#define MX5_CCM_CDCDR_USB_PHY_PODF_OFFSET		(0)
+#define MX5_CCM_CDCDR_USB_PHY_PODF_MASK			(0x7)
+
+/* Define the bits in register CHSCCDR */
+#define MX5_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET		(12)
+#define MX5_CCM_CHSCCDR_ESC_CLK_PRED_MASK		(0x7 << 12)
+#define MX5_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET		(6)
+#define MX5_CCM_CHSCCDR_ESC_CLK_PODF_MASK		(0x3F << 6)
+#define MX5_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET		(3)
+#define MX5_CCM_CHSCCDR_HSC2_CLK_PODF_MASK		(0x7 << 3)
+#define MX5_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET		(0)
+#define MX5_CCM_CHSCCDR_HSC1_CLK_PODF_MASK		(0x7)
+
+/* Define the bits in register CSCDR2 */
+#define MX5_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET		(25)
+#define MX5_CCM_CSCDR2_CSPI_CLK_PRED_MASK		(0x7 << 25)
+#define MX5_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET		(19)
+#define MX5_CCM_CSCDR2_CSPI_CLK_PODF_MASK		(0x3F << 19)
+#define MX5_CCM_CSCDR2_SIM_CLK_PRED_OFFSET		(16)
+#define MX5_CCM_CSCDR2_SIM_CLK_PRED_MASK		(0x7 << 16)
+#define MX5_CCM_CSCDR2_SIM_CLK_PODF_OFFSET		(9)
+#define MX5_CCM_CSCDR2_SIM_CLK_PODF_MASK		(0x3F << 9)
+#define MX5_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET		(6)
+#define MX5_CCM_CSCDR2_SLIMBUS_PRED_MASK		(0x7 << 6)
+#define MX5_CCM_CSCDR2_SLIMBUS_PODF_OFFSET		(0)
+#define MX5_CCM_CSCDR2_SLIMBUS_PODF_MASK		(0x3F)
+
+/* Define the bits in register CSCDR3 */
+#define MX5_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET		(16)
+#define MX5_CCM_CSCDR3_HSI2C_CLK_PRED_MASK		(0x7 << 16)
+#define MX5_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET		(9)
+#define MX5_CCM_CSCDR3_HSI2C_CLK_PODF_MASK		(0x3F << 9)
+#define MX5_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET		(6)
+#define MX5_CCM_CSCDR3_FIRI_CLK_PRED_MASK		(0x7 << 6)
+#define MX5_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET		(0)
+#define MX5_CCM_CSCDR3_FIRI_CLK_PODF_MASK		(0x3F)
+
+/* Define the bits in register CSCDR4 */
+#define MX5_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET	(16)
+#define MX5_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK		(0x7 << 16)
+#define MX5_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET	(9)
+#define MX5_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK		(0x3F << 9)
+#define MX5_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET	(6)
+#define MX5_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK		(0x7 << 6)
+#define MX5_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET	(0)
+#define MX5_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK		(0x3F)
+
+/* Define the bits in register CDHIPR */
+#define MX5_CCM_CDHIPR_ARM_PODF_BUSY			(1 << 16)
+#define MX5_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY		(1 << 8)
+#define MX5_CCM_CDHIPR_DDR_PODF_BUSY			(1 << 7)
+#define MX5_CCM_CDHIPR_EMI_CLK_SEL_BUSY			(1 << 6)
+#define MX5_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY		(1 << 5)
+#define MX5_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY	(1 << 4)
+#define MX5_CCM_CDHIPR_AHB_PODF_BUSY			(1 << 3)
+#define MX5_CCM_CDHIPR_EMI_PODF_BUSY			(1 << 2)
+#define MX5_CCM_CDHIPR_AXI_B_PODF_BUSY			(1 << 1)
+#define MX5_CCM_CDHIPR_AXI_A_PODF_BUSY			(1 << 0)
+
+/* Define the bits in register CDCR */
+#define MX5_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER		(0x1 << 2)
+#define MX5_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET	(0)
+#define MX5_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK		(0x3)
+
+/* Define the bits in register CLPCR */
+#define MX5_CCM_CLPCR_BYPASS_HSC_LPM_HS		(0x1 << 23)
+#define MX5_CCM_CLPCR_BYPASS_SCC_LPM_HS		(0x1 << 22)
+#define MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS		(0x1 << 21)
+#define MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS		(0x1 << 25)
+#define MX5_CCM_CLPCR_BYPASS_SDMA_LPM_HS	(0x1 << 20)
+#define MX5_CCM_CLPCR_BYPASS_EMI_LPM_HS		(0x1 << 19)
+#define MX5_CCM_CLPCR_BYPASS_IPU_LPM_HS		(0x1 << 18)
+#define MX5_CCM_CLPCR_BYPASS_RTIC_LPM_HS	(0x1 << 17)
+#define MX5_CCM_CLPCR_BYPASS_RNGC_LPM_HS	(0x1 << 16)
+#define MX5_CCM_CLPCR_COSC_PWRDOWN		(0x1 << 11)
+#define MX5_CCM_CLPCR_STBY_COUNT_OFFSET		(9)
+#define MX5_CCM_CLPCR_STBY_COUNT_MASK		(0x3 << 9)
+#define MX5_CCM_CLPCR_VSTBY			(0x1 << 8)
+#define MX5_CCM_CLPCR_DIS_REF_OSC		(0x1 << 7)
+#define MX5_CCM_CLPCR_SBYOS			(0x1 << 6)
+#define MX5_CCM_CLPCR_ARM_CLK_DIS_ON_LPM	(0x1 << 5)
+#define MX5_CCM_CLPCR_LPSR_CLK_SEL_OFFSET	(3)
+#define MX5_CCM_CLPCR_LPSR_CLK_SEL_MASK		(0x3 << 3)
+#define MX5_CCM_CLPCR_LPM_OFFSET		(0)
+#define MX5_CCM_CLPCR_LPM_MASK			(0x3)
+
+/* Define the bits in register CISR */
+#define MX5_CCM_CISR_ARM_PODF_LOADED			(0x1 << 25)
+#define MX5_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED	(0x1 << 21)
+#define MX5_CCM_CISR_AHB_PODF_LOADED			(0x1 << 20)
+#define MX5_CCM_CISR_EMI_PODF_LOADED			(0x1 << 19)
+#define MX5_CCM_CISR_AXI_B_PODF_LOADED			(0x1 << 18)
+#define MX5_CCM_CISR_AXI_A_PODF_LOADED			(0x1 << 17)
+#define MX5_CCM_CISR_DIVIDER_LOADED			(0x1 << 16)
+#define MX5_CCM_CISR_COSC_READY				(0x1 << 6)
+#define MX5_CCM_CISR_CKIH2_READY			(0x1 << 5)
+#define MX5_CCM_CISR_CKIH_READY				(0x1 << 4)
+#define MX5_CCM_CISR_FPM_READY				(0x1 << 3)
+#define MX5_CCM_CISR_LRF_PLL3				(0x1 << 2)
+#define MX5_CCM_CISR_LRF_PLL2				(0x1 << 1)
+#define MX5_CCM_CISR_LRF_PLL1				(0x1)
+
+/* Define the bits in register CIMR */
+#define MX5_CCM_CIMR_MASK_ARM_PODF_LOADED		(0x1 << 25)
+#define MX5_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED	(0x1 << 21)
+#define MX5_CCM_CIMR_MASK_EMI_PODF_LOADED		(0x1 << 20)
+#define MX5_CCM_CIMR_MASK_AXI_C_PODF_LOADED		(0x1 << 19)
+#define MX5_CCM_CIMR_MASK_AXI_B_PODF_LOADED		(0x1 << 18)
+#define MX5_CCM_CIMR_MASK_AXI_A_PODF_LOADED		(0x1 << 17)
+#define MX5_CCM_CIMR_MASK_DIVIDER_LOADED		(0x1 << 16)
+#define MX5_CCM_CIMR_MASK_COSC_READY			(0x1 << 5)
+#define MX5_CCM_CIMR_MASK_CKIH_READY			(0x1 << 4)
+#define MX5_CCM_CIMR_MASK_FPM_READY			(0x1 << 3)
+#define MX5_CCM_CIMR_MASK_LRF_PLL3			(0x1 << 2)
+#define MX5_CCM_CIMR_MASK_LRF_PLL2			(0x1 << 1)
+#define MX5_CCM_CIMR_MASK_LRF_PLL1			(0x1)
+
+/* Define the bits in register CCOSR */
+#define MX5_CCM_CCOSR_CKO2_EN_OFFSET			(0x1 << 24)
+#define MX5_CCM_CCOSR_CKO2_DIV_OFFSET			(21)
+#define MX5_CCM_CCOSR_CKO2_DIV_MASK			(0x7 << 21)
+#define MX5_CCM_CCOSR_CKO2_SEL_OFFSET			(16)
+#define MX5_CCM_CCOSR_CKO2_SEL_MASK			(0x1F << 16)
+#define MX5_CCM_CCOSR_CKOL_EN				(0x1 << 7)
+#define MX5_CCM_CCOSR_CKOL_DIV_OFFSET			(4)
+#define MX5_CCM_CCOSR_CKOL_DIV_MASK			(0x7 << 4)
+#define MX5_CCM_CCOSR_CKOL_SEL_OFFSET			(0)
+#define MX5_CCM_CCOSR_CKOL_SEL_MASK			(0xF)
+
+/* Define the bits in registers CGPR */
+#define MX5_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE		(0x1 << 4)
+#define MX5_CCM_CGPR_FPM_SEL				(0x1 << 3)
+#define MX5_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET		(0)
+#define MX5_CCM_CGPR_VL_L2BIST_CLKDIV_MASK		(0x7)
+
+/* Define the bits in registers CCGRx */
+#define MX5_CCM_CCGRx_CG_MASK				0x3
+#define MX5_CCM_CCGRx_MOD_OFF				0x0
+#define MX5_CCM_CCGRx_MOD_ON				0x3
+#define MX5_CCM_CCGRx_MOD_IDLE				0x1
+
+#define MX5_CCM_CCGRx_CG15_MASK				(0x3 << 30)
+#define MX5_CCM_CCGRx_CG14_MASK				(0x3 << 28)
+#define MX5_CCM_CCGRx_CG13_MASK				(0x3 << 26)
+#define MX5_CCM_CCGRx_CG12_MASK				(0x3 << 24)
+#define MX5_CCM_CCGRx_CG11_MASK				(0x3 << 22)
+#define MX5_CCM_CCGRx_CG10_MASK				(0x3 << 20)
+#define MX5_CCM_CCGRx_CG9_MASK				(0x3 << 18)
+#define MX5_CCM_CCGRx_CG8_MASK				(0x3 << 16)
+#define MX5_CCM_CCGRx_CG5_MASK				(0x3 << 10)
+#define MX5_CCM_CCGRx_CG4_MASK				(0x3 << 8)
+#define MX5_CCM_CCGRx_CG3_MASK				(0x3 << 6)
+#define MX5_CCM_CCGRx_CG2_MASK				(0x3 << 4)
+#define MX5_CCM_CCGRx_CG1_MASK				(0x3 << 2)
+#define MX5_CCM_CCGRx_CG0_MASK				(0x3 << 0)
+
+#define MX5_CCM_CCGRx_CG15_OFFSET			30
+#define MX5_CCM_CCGRx_CG14_OFFSET			28
+#define MX5_CCM_CCGRx_CG13_OFFSET			26
+#define MX5_CCM_CCGRx_CG12_OFFSET			24
+#define MX5_CCM_CCGRx_CG11_OFFSET			22
+#define MX5_CCM_CCGRx_CG10_OFFSET			20
+#define MX5_CCM_CCGRx_CG9_OFFSET			18
+#define MX5_CCM_CCGRx_CG8_OFFSET			16
+#define MX5_CCM_CCGRx_CG7_OFFSET			14
+#define MX5_CCM_CCGRx_CG6_OFFSET			12
+#define MX5_CCM_CCGRx_CG5_OFFSET			10
+#define MX5_CCM_CCGRx_CG4_OFFSET			8
+#define MX5_CCM_CCGRx_CG3_OFFSET			6
+#define MX5_CCM_CCGRx_CG2_OFFSET			4
+#define MX5_CCM_CCGRx_CG1_OFFSET			2
+#define MX5_CCM_CCGRx_CG0_OFFSET			0
+
+#define MX5_DPTC_LP_BASE	(MX51_GPC_BASE + 0x80)
+#define MX5_DPTC_GP_BASE	(MX51_GPC_BASE + 0x100)
+#define MX5_DVFS_CORE_BASE	(MX51_GPC_BASE + 0x180)
+#define MX5_DPTC_PER_BASE	(MX51_GPC_BASE + 0x1C0)
+#define MX5_PGC_IPU_BASE	(MX51_GPC_BASE + 0x220)
+#define MX5_PGC_VPU_BASE	(MX51_GPC_BASE + 0x240)
+#define MX5_PGC_GPU_BASE	(MX51_GPC_BASE + 0x260)
+#define MX5_SRPG_NEON_BASE	(MX51_GPC_BASE + 0x280)
+#define MX5_SRPG_ARM_BASE	(MX51_GPC_BASE + 0x2A0)
+#define MX5_SRPG_EMPGC0_BASE	(MX51_GPC_BASE + 0x2C0)
+#define MX5_SRPG_EMPGC1_BASE	(MX51_GPC_BASE + 0x2D0)
+#define MX5_SRPG_MEGAMIX_BASE	(MX51_GPC_BASE + 0x2E0)
+#define MX5_SRPG_EMI_BASE	(MX51_GPC_BASE + 0x300)
+
+/* CORTEXA8 platform */
+#define MX5_CORTEXA8_PLAT_PVID		(MX51_CORTEXA8_BASE + 0x0)
+#define MX5_CORTEXA8_PLAT_GPC		(MX51_CORTEXA8_BASE + 0x4)
+#define MX5_CORTEXA8_PLAT_PIC		(MX51_CORTEXA8_BASE + 0x8)
+#define MX5_CORTEXA8_PLAT_LPC		(MX51_CORTEXA8_BASE + 0xC)
+#define MX5_CORTEXA8_PLAT_NEON_LPC	(MX51_CORTEXA8_BASE + 0x10)
+#define MX5_CORTEXA8_PLAT_ICGC		(MX51_CORTEXA8_BASE + 0x14)
+#define MX5_CORTEXA8_PLAT_AMC		(MX51_CORTEXA8_BASE + 0x18)
+#define MX5_CORTEXA8_PLAT_NMC		(MX51_CORTEXA8_BASE + 0x20)
+#define MX5_CORTEXA8_PLAT_NMS		(MX51_CORTEXA8_BASE + 0x24)
+
+/* DVFS CORE */
+#define MX5_DVFSTHRS		(MX5_DVFS_CORE_BASE + 0x00)
+#define MX5_DVFSCOUN		(MX5_DVFS_CORE_BASE + 0x04)
+#define MX5_DVFSSIG1		(MX5_DVFS_CORE_BASE + 0x08)
+#define MX5_DVFSSIG0		(MX5_DVFS_CORE_BASE + 0x0C)
+#define MX5_DVFSGPC0		(MX5_DVFS_CORE_BASE + 0x10)
+#define MX5_DVFSGPC1		(MX5_DVFS_CORE_BASE + 0x14)
+#define MX5_DVFSGPBT		(MX5_DVFS_CORE_BASE + 0x18)
+#define MX5_DVFSEMAC		(MX5_DVFS_CORE_BASE + 0x1C)
+#define MX5_DVFSCNTR		(MX5_DVFS_CORE_BASE + 0x20)
+#define MX5_DVFSLTR0_0		(MX5_DVFS_CORE_BASE + 0x24)
+#define MX5_DVFSLTR0_1		(MX5_DVFS_CORE_BASE + 0x28)
+#define MX5_DVFSLTR1_0		(MX5_DVFS_CORE_BASE + 0x2C)
+#define MX5_DVFSLTR1_1		(MX5_DVFS_CORE_BASE + 0x30)
+#define MX5_DVFSPT0 		(MX5_DVFS_CORE_BASE + 0x34)
+#define MX5_DVFSPT1 		(MX5_DVFS_CORE_BASE + 0x38)
+#define MX5_DVFSPT2 		(MX5_DVFS_CORE_BASE + 0x3C)
+#define MX5_DVFSPT3 		(MX5_DVFS_CORE_BASE + 0x40)
+
+/* GPC */
+#define MX5_GPC_CNTR		(MX51_GPC_BASE + 0x0)
+#define MX5_GPC_PGR		(MX51_GPC_BASE + 0x4)
+#define MX5_GPC_VCR		(MX51_GPC_BASE + 0x8)
+#define MX5_GPC_ALL_PU		(MX51_GPC_BASE + 0xC)
+#define MX5_GPC_NEON		(MX51_GPC_BASE + 0x10)
+#define MX5_GPC_PGR_ARMPG_OFFSET	8
+#define MX5_GPC_PGR_ARMPG_MASK		(3 << 8)
+
+/* PGC */
+#define MX5_PGC_IPU_PGCR	(MX5_PGC_IPU_BASE + 0x0)
+#define MX5_PGC_IPU_PGSR	(MX5_PGC_IPU_BASE + 0xC)
+#define MX5_PGC_VPU_PGCR	(MX5_PGC_VPU_BASE + 0x0)
+#define MX5_PGC_VPU_PGSR	(MX5_PGC_VPU_BASE + 0xC)
+#define MX5_PGC_GPU_PGCR	(MX5_PGC_GPU_BASE + 0x0)
+#define MX5_PGC_GPU_PGSR	(MX5_PGC_GPU_BASE + 0xC)
+
+#define MX5_PGCR_PCR		1
+#define MX5_SRPGCR_PCR		1
+#define MX5_EMPGCR_PCR		1
+#define MX5_PGSR_PSR		1
+
+
+#define MX5_CORTEXA8_PLAT_LPC_DSM	(1 << 0)
+#define MX5_CORTEXA8_PLAT_LPC_DBG_DSM	(1 << 1)
+
+/* SRPG */
+#define MX5_SRPG_NEON_SRPGCR	(MX5_SRPG_NEON_BASE + 0x0)
+#define MX5_SRPG_NEON_PUPSCR	(MX5_SRPG_NEON_BASE + 0x4)
+#define MX5_SRPG_NEON_PDNSCR	(MX5_SRPG_NEON_BASE + 0x8)
+
+#define MX5_SRPG_ARM_SRPGCR	(MX5_SRPG_ARM_BASE + 0x0)
+#define MX5_SRPG_ARM_PUPSCR	(MX5_SRPG_ARM_BASE + 0x4)
+#define MX5_SRPG_ARM_PDNSCR	(MX5_SRPG_ARM_BASE + 0x8)
+
+#define MX5_SRPG_EMPGC0_SRPGCR	(MX5_SRPG_EMPGC0_BASE + 0x0)
+#define MX5_SRPG_EMPGC0_PUPSCR	(MX5_SRPG_EMPGC0_BASE + 0x4)
+#define MX5_SRPG_EMPGC0_PDNSCR	(MX5_SRPG_EMPGC0_BASE + 0x8)
+
+#define MX5_SRPG_EMPGC1_SRPGCR	(MX5_SRPG_EMPGC1_BASE + 0x0)
+#define MX5_SRPG_EMPGC1_PUPSCR	(MX5_SRPG_EMPGC1_BASE + 0x4)
+#define MX5_SRPG_EMPGC1_PDNSCR	(MX5_SRPG_EMPGC1_BASE + 0x8)
+
+#define MX5_SRPG_MEGAMIX_SRPGCR		(MX5_SRPG_MEGAMIX_BASE + 0x0)
+#define MX5_SRPG_MEGAMIX_PUPSCR		(MX5_SRPG_MEGAMIX_BASE + 0x4)
+#define MX5_SRPG_MEGAMIX_PDNSCR		(MX5_SRPG_MEGAMIX_BASE + 0x8)
+
+#define MX5_SRPGC_EMI_SRPGCR	(MX5_SRPGC_EMI_BASE + 0x0)
+#define MX5_SRPGC_EMI_PUPSCR	(MX5_SRPGC_EMI_BASE + 0x4)
+#define MX5_SRPGC_EMI_PDNSCR	(MX5_SRPGC_EMI_BASE + 0x8)
+
+
+/* Assuming 24MHz input clock with doubler ON */
+/*                            MFI         PDF */
+#define MX5_PLL_DP_OP_1000	((10 << 4) + ((1 - 1)  << 0))
+#define MX5_PLL_DP_MFD_1000	(12 - 1)
+#define MX5_PLL_DP_MFN_1000	5
+
+#define MX5_PLL_DP_OP_850	((8 << 4) + ((1 - 1)  << 0))
+#define MX5_PLL_DP_MFD_850	(48 - 1)
+#define MX5_PLL_DP_MFN_850	41
+
+#define MX5_PLL_DP_OP_800	((8 << 4) + ((1 - 1)  << 0))
+#define MX5_PLL_DP_MFD_800	(3 - 1)
+#define MX5_PLL_DP_MFN_800	1
+
+#define MX5_PLL_DP_OP_700	((7 << 4) + ((1 - 1)  << 0))
+#define MX5_PLL_DP_MFD_700	(24 - 1)
+#define MX5_PLL_DP_MFN_700	7
+
+#define MX5_PLL_DP_OP_665	((6 << 4) + ((1 - 1)  << 0))
+#define MX5_PLL_DP_MFD_665	(96 - 1)
+#define MX5_PLL_DP_MFN_665	89
+
+#define MX5_PLL_DP_OP_532	((5 << 4) + ((1 - 1)  << 0))
+#define MX5_PLL_DP_MFD_532	(24 - 1)
+#define MX5_PLL_DP_MFN_532	13
+
+#define MX5_PLL_DP_OP_400	((8 << 4) + ((2 - 1)  << 0))
+#define MX5_PLL_DP_MFD_400	(3 - 1)
+#define MX5_PLL_DP_MFN_400	1
+
+#define MX5_PLL_DP_OP_216	((6 << 4) + ((3 - 1)  << 0))
+#define MX5_PLL_DP_MFD_216	(4 - 1)
+#define MX5_PLL_DP_MFN_216	3
+
+#endif				/* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
+
+
diff --git a/arch/arm/mach-imx/include/mach/devices-imx1.h b/arch/arm/mach-imx/include/mach/devices-imx1.h
new file mode 100644
index 0000000000..a45363f61d
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/devices-imx1.h
@@ -0,0 +1,11 @@
+#include <mach/devices.h>
+
+static inline struct device_d *imx1_add_uart0(void)
+{
+	return imx_add_uart((void *)IMX_UART1_BASE, 0);
+}
+
+static inline struct device_d *imx1_add_uart1(void)
+{
+	return imx_add_uart((void *)IMX_UART2_BASE, 1);
+}
diff --git a/arch/arm/mach-imx/include/mach/devices-imx53.h b/arch/arm/mach-imx/include/mach/devices-imx53.h
new file mode 100644
index 0000000000..41572a73dd
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/devices-imx53.h
@@ -0,0 +1,58 @@
+
+#include <mach/devices.h>
+
+static inline struct device_d *imx53_add_spi0(struct spi_imx_master *pdata)
+{
+	return imx_add_spi((void *)MX53_ECSPI1_BASE_ADDR, 0, pdata);
+}
+
+static inline struct device_d *imx53_add_spi1(struct spi_imx_master *pdata)
+{
+	return imx_add_spi((void *)MX53_ECSPI2_BASE_ADDR, 1, pdata);
+}
+
+static inline struct device_d *imx53_add_i2c0(struct i2c_platform_data *pdata)
+{
+	return imx_add_i2c((void *)MX53_I2C1_BASE_ADDR, 0, pdata);
+}
+
+static inline struct device_d *imx53_add_i2c1(struct i2c_platform_data *pdata)
+{
+	return imx_add_i2c((void *)MX53_I2C2_BASE_ADDR, 1, pdata);
+}
+
+static inline struct device_d *imx53_add_uart0(void)
+{
+	return imx_add_uart((void *)MX53_UART1_BASE_ADDR, 0);
+}
+
+static inline struct device_d *imx53_add_uart1(void)
+{
+	return imx_add_uart((void *)MX53_UART2_BASE_ADDR, 1);
+}
+
+static inline struct device_d *imx53_add_fec(struct fec_platform_data *pdata)
+{
+	return imx_add_fec((void *)MX53_FEC_BASE_ADDR, pdata);
+}
+
+static inline struct device_d *imx53_add_mmc0(void *pdata)
+{
+	return imx_add_esdhc((void *)MX53_ESDHC1_BASE_ADDR, 0, pdata);
+}
+
+static inline struct device_d *imx53_add_mmc1(void *pdata)
+{
+	return imx_add_esdhc((void *)MX53_ESDHC2_BASE_ADDR, 0, pdata);
+}
+
+static inline struct device_d *imx53_add_mmc2(void *pdata)
+{
+	return imx_add_esdhc((void *)MX53_ESDHC3_BASE_ADDR, 0, pdata);
+}
+
+static inline struct device_d *imx53_add_nand(struct imx_nand_platform_data *pdata)
+{
+	return imx_add_nand((void *)MX53_NFC_AXI_BASE_ADDR, pdata);
+}
+
diff --git a/arch/arm/mach-imx/include/mach/generic.h b/arch/arm/mach-imx/include/mach/generic.h
index 29260361a2..8ff04fbc81 100644
--- a/arch/arm/mach-imx/include/mach/generic.h
+++ b/arch/arm/mach-imx/include/mach/generic.h
@@ -51,5 +51,11 @@ u64 imx_uid(void);
 #define cpu_is_mx51()	(0)
 #endif
 
+#ifdef CONFIG_ARCH_IMX53
+#define cpu_is_mx53()	(1)
+#else
+#define cpu_is_mx53()	(0)
+#endif
+
 #define cpu_is_mx23()	(0)
 #define cpu_is_mx28()	(0)
diff --git a/arch/arm/mach-imx/include/mach/iim.h b/arch/arm/mach-imx/include/mach/iim.h
index 03ff485b6d..b97c742a66 100644
--- a/arch/arm/mach-imx/include/mach/iim.h
+++ b/arch/arm/mach-imx/include/mach/iim.h
@@ -24,6 +24,7 @@
 #define __MACH_IMX_IIM_H
 
 #include <errno.h>
+#include <net.h>
 
 #define IIM_STAT	0x0000
 #define IIM_STATM	0x0004
@@ -46,12 +47,47 @@ struct imx_iim_platform_data {
 };
 
 #ifdef CONFIG_IMX_IIM
+int imx_iim_read(unsigned int bank, int offset, void *buf, int count);
 int imx_iim_get_mac(unsigned char *mac);
 #else
-static inline int imx_iim_get_mac(unsigned char *mac)
+static inline int imx_iim_read(unsigned int bank, int offset, void *buf,
+		int count)
 {
 	return -EINVAL;
 }
 #endif /* CONFIG_IMX_IIM */
 
+static inline int imx51_iim_register_fec_ethaddr(void)
+{
+	int ret;
+	u8 buf[6];
+
+	ret = imx_iim_read(1, 9, buf, 6);
+	if (ret != 6)
+		return -EINVAL;
+
+	eth_register_ethaddr(0, buf);
+
+	return 0;
+}
+
+static inline int imx53_iim_register_fec_ethaddr(void)
+{
+	return imx51_iim_register_fec_ethaddr();
+}
+
+static inline int imx25_iim_register_fec_ethaddr(void)
+{
+	int ret;
+	u8 buf[6];
+
+	ret = imx_iim_read(0, 26, buf, 6);
+	if (ret != 6)
+		return -EINVAL;
+
+	eth_register_ethaddr(0, buf);
+
+	return 0;
+}
+
 #endif /* __MACH_IMX_IIM_H */
diff --git a/arch/arm/mach-imx/include/mach/imx-flash-header.h b/arch/arm/mach-imx/include/mach/imx-flash-header.h
index b8f51767de..874426252a 100644
--- a/arch/arm/mach-imx/include/mach/imx-flash-header.h
+++ b/arch/arm/mach-imx/include/mach/imx-flash-header.h
@@ -49,6 +49,11 @@ struct imx_dcd_entry {
 	unsigned long val;
 };
 
+struct imx_dcd_v2_entry {
+	__be32 addr;
+	__be32 val;
+};
+
 #define DCD_BARKER	0xb17219e9
 
 struct imx_rsa_public_key {
@@ -73,4 +78,51 @@ struct imx_flash_header {
 	unsigned long			dcd_block_len;
 };
 
+#define IVT_HEADER_TAG		0xd1
+#define IVT_VERSION		0x40
+
+#define DCD_HEADER_TAG		0xd2
+#define DCD_VERSION		0x40
+
+#define DCD_COMMAND_WRITE_TAG	0xcc
+#define DCD_COMMAND_WRITE_PARAM	0x04
+
+struct imx_ivt_header {
+	uint8_t tag;
+	__be16 length;
+	uint8_t version;
+} __attribute__((packed));
+
+struct imx_dcd_command {
+	uint8_t tag;
+	__be16 length;
+	uint8_t param;
+} __attribute__((packed));
+
+struct imx_dcd {
+	struct imx_ivt_header header;
+	struct imx_dcd_command command;
+};
+
+struct imx_boot_data {
+	uint32_t start;
+	uint32_t size;
+	uint32_t plugin;
+};
+
+struct imx_flash_header_v2 {
+	struct imx_ivt_header header;
+
+	uint32_t entry;
+	uint32_t reserved1;
+	uint32_t dcd_ptr;
+	uint32_t boot_data_ptr;
+	uint32_t self;
+	uint32_t csf;
+	uint32_t reserved2;
+
+	struct imx_boot_data boot_data;
+	struct imx_dcd dcd;
+};
+
 #endif /* __MACH_FLASH_HEADER_H */
diff --git a/arch/arm/mach-imx/include/mach/imx-regs.h b/arch/arm/mach-imx/include/mach/imx-regs.h
index a234621374..a272ddab82 100644
--- a/arch/arm/mach-imx/include/mach/imx-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx-regs.h
@@ -52,7 +52,9 @@
 #elif defined CONFIG_ARCH_IMX25
 # include <mach/imx25-regs.h>
 #elif defined CONFIG_ARCH_IMX51
-#include <mach/imx51-regs.h>
+# include <mach/imx51-regs.h>
+#elif defined CONFIG_ARCH_IMX53
+# include <mach/imx53-regs.h>
 #else
 # error "unknown i.MX soc type"
 #endif
diff --git a/arch/arm/mach-imx/include/mach/imx27-regs.h b/arch/arm/mach-imx/include/mach/imx27-regs.h
index e87d5bf241..570b43025c 100644
--- a/arch/arm/mach-imx/include/mach/imx27-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx27-regs.h
@@ -29,6 +29,7 @@
 #define IMX_FB_BASE                (0x21000 + IMX_IO_BASE)
 #define IMX_PLL_BASE               (0x27000 + IMX_IO_BASE)
 #define IMX_SYSTEM_CTL_BASE        (0x27800 + IMX_IO_BASE)
+#define IMX_IIM_BASE               (0x28000 + IMX_IO_BASE)
 #define IMX_OTG_BASE               (0x24000 + IMX_IO_BASE)
 #define IMX_FEC_BASE               (0x2b000 + IMX_IO_BASE)
 
diff --git a/arch/arm/mach-imx/include/mach/imx53-regs.h b/arch/arm/mach-imx/include/mach/imx53-regs.h
new file mode 100644
index 0000000000..8fefc5463e
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/imx53-regs.h
@@ -0,0 +1,139 @@
+#ifndef __MACH_IMX53_REGS_H
+#define __MACH_IMX53_REGS_H
+
+#define IMX_TIM1_BASE			0X53FA0000
+#define IMX_WDT_BASE			0X53F98000
+#define IMX_IOMUXC_BASE			0X53FA8000
+
+#define GPT_TCTL	0x00
+#define GPT_TPRER	0x04
+#define GPT_TCMP	0x10
+#define GPT_TCR		0x1c
+#define GPT_TCN		0x24
+#define GPT_TSTAT	0x08
+
+/* Part 2: Bitfields */
+#define TCTL_SWR	(1<<15)	/* Software reset */
+#define TCTL_FRR	(1<<9)	/* Freerun / restart */
+#define TCTL_CAP	(3<<6)	/* Capture Edge */
+#define TCTL_OM		(1<<5)	/* output mode */
+#define TCTL_IRQEN	(1<<4)	/* interrupt enable */
+#define TCTL_CLKSOURCE	(6)	/* Clock source bit position */
+#define TCTL_TEN	(1)	/* Timer enable */
+#define TPRER_PRES	(0xff)	/* Prescale */
+#define TSTAT_CAPT	(1<<1)	/* Capture event */
+#define TSTAT_COMP	(1)	/* Compare event */
+
+#define MX53_IROM_BASE_ADDR	0x0
+
+/*
+ * SPBA global module enabled #0
+ */
+#define MX53_SPBA0_BASE_ADDR		0x50000000
+#define MX53_SPBA0_SIZE		SZ_1M
+
+#define MX53_ESDHC1_BASE_ADDR	(MX53_SPBA0_BASE_ADDR + 0x00004000)
+#define MX53_ESDHC2_BASE_ADDR	(MX53_SPBA0_BASE_ADDR + 0x00008000)
+#define MX53_UART3_BASE_ADDR		(MX53_SPBA0_BASE_ADDR + 0x0000C000)
+#define MX53_ECSPI1_BASE_ADDR		(MX53_SPBA0_BASE_ADDR + 0x00010000)
+#define MX53_SSI2_BASE_ADDR		(MX53_SPBA0_BASE_ADDR + 0x00014000)
+#define MX53_ESDHC3_BASE_ADDR	(MX53_SPBA0_BASE_ADDR + 0x00020000)
+#define MX53_ESDHC4_BASE_ADDR	(MX53_SPBA0_BASE_ADDR + 0x00024000)
+#define MX53_SPDIF_BASE_ADDR		(MX53_SPBA0_BASE_ADDR + 0x00028000)
+#define MX53_ASRC_BASE_ADDR		(MX53_SPBA0_BASE_ADDR + 0x0002C000)
+#define MX53_ATA_DMA_BASE_ADDR	(MX53_SPBA0_BASE_ADDR + 0x00030000)
+#define MX53_SLIM_DMA_BASE_ADDR	(MX53_SPBA0_BASE_ADDR + 0x00034000)
+#define MX53_HSI2C_DMA_BASE_ADDR	(MX53_SPBA0_BASE_ADDR + 0x00038000)
+#define MX53_SPBA_CTRL_BASE_ADDR	(MX53_SPBA0_BASE_ADDR + 0x0003C000)
+
+/*
+ * AIPS 1
+ */
+#define MX53_AIPS1_BASE_ADDR 	0x53F00000
+#define MX53_AIPS1_SIZE		SZ_1M
+
+#define MX53_OTG_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x00080000)
+#define MX53_GPIO1_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x00084000)
+#define MX53_GPIO2_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x00088000)
+#define MX53_GPIO3_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x0008C000)
+#define MX53_GPIO4_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x00090000)
+#define MX53_KPP_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x00094000)
+#define MX53_WDOG1_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x00098000)
+#define MX53_WDOG2_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x0009C000)
+#define MX53_GPT1_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000A0000)
+#define MX53_SRTC_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000A4000)
+#define MX53_IOMUXC_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000A8000)
+#define MX53_EPIT1_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000AC000)
+#define MX53_EPIT2_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000B0000)
+#define MX53_PWM1_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000B4000)
+#define MX53_PWM2_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000B8000)
+#define MX53_UART1_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000BC000)
+#define MX53_UART2_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000C0000)
+#define MX53_SRC_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000D0000)
+#define MX53_CCM_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000D4000)
+#define MX53_GPC_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000D8000)
+#define MX53_GPIO5_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000DC000)
+#define MX53_GPIO6_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000E0000)
+#define MX53_GPIO7_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000E4000)
+#define MX53_ATA_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000E8000)
+#define MX53_I2C3_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000EC000)
+#define MX53_UART4_BASE_ADDR	(MX53_AIPS1_BASE_ADDR + 0x000F0000)
+
+/*
+ * AIPS 2
+ */
+#define MX53_AIPS2_BASE_ADDR		0x63F00000
+#define MX53_AIPS2_SIZE			SZ_1M
+
+#define MX53_PLL1_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x00080000)
+#define MX53_PLL2_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x00084000)
+#define MX53_PLL3_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x00088000)
+#define MX53_PLL4_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x0008C000)
+#define MX53_UART5_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x00090000)
+#define MX53_AHBMAX_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x00094000)
+#define MX53_IIM_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x00098000)
+#define MX53_CSU_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x0009C000)
+#define MX53_ARM_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000A0000)
+#define MX53_OWIRE_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000A4000)
+#define MX53_FIRI_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000A8000)
+#define MX53_ECSPI2_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000AC000)
+#define MX53_SDMA_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000B0000)
+#define MX53_SCC_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000B4000)
+#define MX53_ROMCP_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000B8000)
+#define MX53_RTIC_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000BC000)
+#define MX53_CSPI_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000C0000)
+#define MX53_I2C2_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000C4000)
+#define MX53_I2C1_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000C8000)
+#define MX53_SSI1_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000CC000)
+#define MX53_AUDMUX_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000D0000)
+#define MX53_RTC_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000D4000)
+#define MX53_M4IF_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000D8000)
+#define MX53_ESDCTL_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000D9000)
+#define MX53_WEIM_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000DA000)
+#define MX53_NFC_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000DB000)
+#define MX53_EMI_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000DBF00)
+#define MX53_MIPI_HSC_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000DC000)
+#define MX53_MLB_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000E4000)
+#define MX53_SSI3_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000E8000)
+#define MX53_FEC_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000EC000)
+#define MX53_TVE_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000F0000)
+#define MX53_VPU_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000F4000)
+#define MX53_SAHARA_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000F8000)
+#define MX53_PTP_BASE_ADDR	(MX53_AIPS2_BASE_ADDR + 0x000FC000)
+
+#define MX53_NFC_AXI_BASE_ADDR	0xF7FF0000
+
+/*
+ * Memory regions and CS
+ */
+#define MX53_CSD0_BASE_ADDR		0x70000000
+#define MX53_CSD1_BASE_ADDR		0xB0000000
+#define MX53_CS0_BASE_ADDR		0xF0000000
+#define MX53_CS1_32MB_BASE_ADDR		0xF2000000
+#define MX53_CS1_64MB_BASE_ADDR		0xF4000000
+#define MX53_CS2_64MB_BASE_ADDR		0xF4000000
+#define MX53_CS2_96MB_BASE_ADDR		0xF6000000
+#define MX53_CS3_BASE_ADDR		0xF6000000
+
+#endif /* __MACH_IMX53_REGS_H */
+
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx53.h b/arch/arm/mach-imx/include/mach/iomux-mx53.h
new file mode 100644
index 0000000000..87a9deb870
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/iomux-mx53.h
@@ -0,0 +1,1203 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc..
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __MACH_IOMUX_MX53_H__
+#define __MACH_IOMUX_MX53_H__
+
+#include <mach/iomux-v3.h>
+
+/* These 2 defines are for pins that may not have a mux register, but could
+ * have a pad setting register, and vice-versa. */
+#define NON_PAD_I	0x00
+
+#define MX53_UART_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define MX53_SDHC_PAD_CTRL 	(PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)
+
+#define MX53_PAD_GPIO_19__KPP_COL_5			IOMUX_PAD(0x348, 0x20, 0, 0x840, 0, 0)
+#define MX53_PAD_GPIO_19__GPIO4_5			IOMUX_PAD(0x348, 0x20, 1, 0x0, 0, 0)
+#define MX53_PAD_GPIO_19__CCM_CLKO			IOMUX_PAD(0x348, 0x20, 2, 0x0, 0, 0)
+#define MX53_PAD_GPIO_19__SPDIF_OUT1			IOMUX_PAD(0x348, 0x20, 3, 0x0, 0, 0)
+#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2		IOMUX_PAD(0x348, 0x20, 4, 0x0, 0, 0)
+#define MX53_PAD_GPIO_19__ECSPI1_RDY			IOMUX_PAD(0x348, 0x20, 5, 0x0, 0, 0)
+#define MX53_PAD_GPIO_19__FEC_TDATA_3			IOMUX_PAD(0x348, 0x20, 6, 0x0, 0, 0)
+#define MX53_PAD_GPIO_19__SRC_INT_BOOT			IOMUX_PAD(0x348, 0x20,7, 0x0, 0, 0)
+#define MX53_PAD_KEY_COL0__KPP_COL_0			IOMUX_PAD(0x34C, 0x24, o, 0x0, 0, 0)
+#define MX53_PAD_KEY_COL0__GPIO4_6			IOMUX_PAD(0x34C, 0x24, 1, 0x0, 0, 0)
+#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC		IOMUX_PAD(0x34C, 0x24, 2, 0x758, 0, 0)
+#define MX53_PAD_KEY_COL0__UART4_TXD_MUX		IOMUX_PAD(0x34C, 0x24, 4, 0x890, 0, 0)
+#define MX53_PAD_KEY_COL0__ECSPI1_SCLK			IOMUX_PAD(0x34C, 0x24, 5, 0x79C, 0, 0)
+#define MX53_PAD_KEY_COL0__FEC_RDATA_3			IOMUX_PAD(0x34C, 0x24, 6, 0x0, 0, 0)
+#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST		IOMUX_PAD(0x34C, 0x24, 7, 0x0, 0, 0)
+#define MX53_PAD_KEY_ROW0__KPP_ROW_0			IOMUX_PAD(0x350, 0x28, 0, 0x0, 0, 0)
+#define MX53_PAD_KEY_ROW0__GPIO4_7			IOMUX_PAD(0x350, 0x28, 1, 0x0, 0, 0)
+#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD		IOMUX_PAD(0x350, 0x28, 2, 0x74C, 0, 0)
+#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX		IOMUX_PAD(0x350, 0x28, 4, 0x890, 1, 0)
+#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI			IOMUX_PAD(0x350, 0x28, 5, 0x7A4, 0, 0)
+#define MX53_PAD_KEY_ROW0__FEC_TX_ER			IOMUX_PAD(0x350, 0x28, 6, 0x0, 0, 0)
+#define MX53_PAD_KEY_COL1__KPP_COL_1			IOMUX_PAD(0x354, 0x2C, 0, 0x0, 0, 0)
+#define MX53_PAD_KEY_COL1__GPIO4_8			IOMUX_PAD(0x354, 0x2C, 1, 0x0, 0, 0)
+#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS		IOMUX_PAD(0x354, 0x2C, 2, 0x75C, 0, 0)
+#define MX53_PAD_KEY_COL1__UART5_TXD_MUX		IOMUX_PAD(0x354, 0x2C, 4, 0x898, 0, 0)
+#define MX53_PAD_KEY_COL1__ECSPI1_MISO			IOMUX_PAD(0x354, 0x2C, 5, 0x7A0, 0, 0)
+#define MX53_PAD_KEY_COL1__FEC_RX_CLK			IOMUX_PAD(0x354, 0x2C, 6, 0x808, 0, 0)
+#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY		IOMUX_PAD(0x354, 0x2C, 7, 0x0, 0, 0)
+#define MX53_PAD_KEY_ROW1__KPP_ROW_1			IOMUX_PAD(0x358, 0x30, 0, 0x0, 0, 0)
+#define MX53_PAD_KEY_ROW1__GPIO4_9			IOMUX_PAD(0x358, 0x30, 1, 0x0, 0, 0)
+#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD		IOMUX_PAD(0x358, 0x30, 2, 0x748, 0, 0)
+#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX		IOMUX_PAD(0x358, 0x30, 4, 0x898, 1, 0)
+#define MX53_PAD_KEY_ROW1__ECSPI1_SS0			IOMUX_PAD(0x358, 0x30, 5, 0x7A8, 0, 0)
+#define MX53_PAD_KEY_ROW1__FEC_COL			IOMUX_PAD(0x358, 0x30, 6, 0x800, 0, 0)
+#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID		IOMUX_PAD(0x358, 0x30, 7, 0x0, 0, 0)
+#define MX53_PAD_KEY_COL2__KPP_COL_2			IOMUX_PAD(0x35C, 0x34, 0, 0x0, 0, 0)
+#define MX53_PAD_KEY_COL2__GPIO4_10			IOMUX_PAD(0x35C, 0x34, 1, 0x0, 0, 0)
+#define MX53_PAD_KEY_COL2__CAN1_TXCAN			IOMUX_PAD(0x35C, 0x34, 2, 0x0, 0, 0)
+#define MX53_PAD_KEY_COL2__FEC_MDIO			IOMUX_PAD(0x35C, 0x34, 4, 0x804, 0, 0)
+#define MX53_PAD_KEY_COL2__ECSPI1_SS1			IOMUX_PAD(0x35C, 0x34, 5, 0x7AC, 0, 0)
+#define MX53_PAD_KEY_COL2__FEC_RDATA_2			IOMUX_PAD(0x35C, 0x34, 6, 0x0, 0, 0)
+#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE		IOMUX_PAD(0x35C, 0x34, 7, 0x0, 0, 0)
+#define MX53_PAD_KEY_ROW2__KPP_ROW_2			IOMUX_PAD(0x360, 0x38, 0, 0x0, 0, 0)
+#define MX53_PAD_KEY_ROW2__GPIO4_11			IOMUX_PAD(0x360, 0x38, 1, 0x0, 0, 0)
+#define MX53_PAD_KEY_ROW2__CAN1_RXCAN			IOMUX_PAD(0x360, 0x38, 2, 0x760, 0, 0)
+#define MX53_PAD_KEY_ROW2__FEC_MDC			IOMUX_PAD(0x360, 0x38, 4, 0x0, 0, 0)
+#define MX53_PAD_KEY_ROW2__ECSPI1_SS2			IOMUX_PAD(0x360, 0x38, 5, 0x7B0, 0, 0)
+#define MX53_PAD_KEY_ROW2__FEC_TDATA_2			IOMUX_PAD(0x360, 0x38, 6, 0x0, 0, 0)
+#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR		IOMUX_PAD(0x360, 0x38, 7, 0x0, 0, 0)
+#define MX53_PAD_KEY_COL3__KPP_COL_3			IOMUX_PAD(0x364, 0x3C, 0, 0x0, 0, 0)
+#define MX53_PAD_KEY_COL3__GPIO4_12			IOMUX_PAD(0x364, 0x3C, 1, 0x0, 0, 0)
+#define MX53_PAD_KEY_COL3__USBOH3_H2_DP			IOMUX_PAD(0x364, 0x3C, 2, 0x0, 0, 0)
+#define MX53_PAD_KEY_COL3__SPDIF_IN1			IOMUX_PAD(0x364, 0x3C, 3, 0x870, 0, 0)
+#define MX53_PAD_KEY_COL3__I2C2_SCL			IOMUX_PAD(0x364, 0x3C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, 0)
+#define MX53_PAD_KEY_COL3__ECSPI1_SS3			IOMUX_PAD(0x364, 0x3C, 5, 0x7B4, 0, 0)
+#define MX53_PAD_KEY_COL3__FEC_CRS			IOMUX_PAD(0x364, 0x3C, 6, 0x0, 0, 0)
+#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK		IOMUX_PAD(0x364, 0x3C, 7, 0x0, 0, 0)
+#define MX53_PAD_KEY_ROW3__KPP_ROW_3			IOMUX_PAD(0x368, 0x40, 0, 0x0, 0, 0)
+#define MX53_PAD_KEY_ROW3__GPIO4_13			IOMUX_PAD(0x368, 0x40, 1, 0x0, 0, 0)
+#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM			IOMUX_PAD(0x368, 0x40, 2, 0x0, 0, 0)
+#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK		IOMUX_PAD(0x368, 0x40, 3, 0x768, 0, 0)
+#define MX53_PAD_KEY_ROW3__I2C2_SDA			IOMUX_PAD(0x368, 0x40, 4 | IOMUX_CONFIG_SION, 0x820, 0, 0)
+#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT		IOMUX_PAD(0x368, 0x40, 5, 0x0, 0, 0)
+#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP			IOMUX_PAD(0x368, 0x40, 6, 0x77C, 0, 0)
+#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0		IOMUX_PAD(0x368, 0x40, 7, 0x0, 0, 0)
+#define MX53_PAD_KEY_COL4__KPP_COL_4			IOMUX_PAD(0x36C, 0x44, 0, 0x0, 0, 0)
+#define MX53_PAD_KEY_COL4__GPIO4_14			IOMUX_PAD(0x36C, 0x44, 1, 0x0, 0, 0)
+#define MX53_PAD_KEY_COL4__CAN2_TXCAN			IOMUX_PAD(0x36C, 0x44, 2, 0x0, 0, 0)
+#define MX53_PAD_KEY_COL4__IPU_SISG_4			IOMUX_PAD(0x36C, 0x44, 3, 0x0, 0, 0)
+#define MX53_PAD_KEY_COL4__UART5_RTS			IOMUX_PAD(0x36C, 0x44, 4, 0x894, 0, 0)
+#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC		IOMUX_PAD(0x36C, 0x44, 5, 0x89C, 0, 0)
+#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1		IOMUX_PAD(0x36C, 0x44, 7, 0x0, 0, 0)
+#define MX53_PAD_KEY_ROW4__KPP_ROW_4			IOMUX_PAD(0x370, 0x48, 0, 0x0, 0, 0)
+#define MX53_PAD_KEY_ROW4__GPIO4_15			IOMUX_PAD(0x370, 0x48, 1, 0x0, 0, 0)
+#define MX53_PAD_KEY_ROW4__CAN2_RXCAN			IOMUX_PAD(0x370, 0x48, 2, 0x764, 0, 0)
+#define MX53_PAD_KEY_ROW4__IPU_SISG_5			IOMUX_PAD(0x370, 0x48, 3, 0x0, 0, 0)
+#define MX53_PAD_KEY_ROW4__UART5_CTS			IOMUX_PAD(0x370, 0x48, 4, 0x894, 1, 0)
+#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR		IOMUX_PAD(0x370, 0x48, 5, 0x0, 0, 0)
+#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID		IOMUX_PAD(0x370, 0x48, 7, 0x0, 0, 0)
+#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK		IOMUX_PAD(0x378, 0x4C, 0, 0x0, 0, 0)
+#define MX53_PAD_DI0_DISP_CLK__GPIO4_16			IOMUX_PAD(0x378, 0x4C, 1, 0x0, 0, 0)
+#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR		IOMUX_PAD(0x378, 0x4C, 2, 0x0, 0, 0)
+#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0	IOMUX_PAD(0x378, 0x4C, 5, 0x0, 0, 0)
+#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0		IOMUX_PAD(0x378, 0x4C, 6, 0x0, 0, 0)
+#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID		IOMUX_PAD(0x378, 0x4C, 7, 0x0, 0, 0)
+#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15		IOMUX_PAD(0x37C, 0x50, 0, 0x0, 0, 0)
+#define MX53_PAD_DI0_PIN15__GPIO4_17			IOMUX_PAD(0x37C, 0x50, 1, 0x0, 0, 0)
+#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC		IOMUX_PAD(0x37C, 0x50, 2, 0x0, 0, 0)
+#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1	IOMUX_PAD(0x37C, 0x50, 5, 0x0, 0, 0)
+#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1		IOMUX_PAD(0x37C, 0x50, 6, 0x0, 0, 0)
+#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID		IOMUX_PAD(0x37C, 0x50, 7, 0x0, 0, 0)
+#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2			IOMUX_PAD(0x380, 0x54, 0, 0x0, 0, 0)
+#define MX53_PAD_DI0_PIN2__GPIO4_18			IOMUX_PAD(0x380, 0x54, 1, 0x0, 0, 0)
+#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD		IOMUX_PAD(0x380, 0x54, 2, 0x0, 0, 0)
+#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2	IOMUX_PAD(0x380, 0x54, 5, 0x0, 0, 0)
+#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2		IOMUX_PAD(0x380, 0x54, 6, 0x0, 0, 0)
+#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION		IOMUX_PAD(0x380, 0x54, 7, 0x0, 0, 0)
+#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3			IOMUX_PAD(0x384, 0x58, 0, 0x0, 0, 0)
+#define MX53_PAD_DI0_PIN3__GPIO4_19			IOMUX_PAD(0x384, 0x58, 1, 0x0, 0, 0)
+#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS		IOMUX_PAD(0x384, 0x58, 2, 0x0, 0, 0)
+#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3	IOMUX_PAD(0x384, 0x58, 5, 0x0, 0, 0)
+#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3		IOMUX_PAD(0x384, 0x58, 6, 0x0, 0, 0)
+#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG		IOMUX_PAD(0x384, 0x58, 7, 0x0, 0, 0)
+#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4			IOMUX_PAD(0x388, 0x5C, 0, 0x0, 0, 0)
+#define MX53_PAD_DI0_PIN4__GPIO4_20			IOMUX_PAD(0x388, 0x5C, 1, 0x0, 0, 0)
+#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD		IOMUX_PAD(0x388, 0x5C, 2, 0x0, 0, 0)
+#define MX53_PAD_DI0_PIN4__ESDHC1_WP			IOMUX_PAD(0x388, 0x5C, 3, 0x7FC, 0, 0)
+#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD		IOMUX_PAD(0x388, 0x5C, 5, 0x0, 0, 0)
+#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4		IOMUX_PAD(0x388, 0x5C, 6, 0x0, 0, 0)
+#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT	IOMUX_PAD(0x388, 0x5C, 7, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0		IOMUX_PAD(0x38C, 0x60, 0, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT0__GPIO4_21			IOMUX_PAD(0x38C, 0x60, 1, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT0__CSPI_SCLK			IOMUX_PAD(0x38C, 0x60, 2, 0x780, 0, 0)
+#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0	IOMUX_PAD(0x38C, 0x60, 3, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN	IOMUX_PAD(0x38C, 0x60, 5, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5		IOMUX_PAD(0x38C, 0x60, 6, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY		IOMUX_PAD(0x38C, 0x60, 7, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1		IOMUX_PAD(0x390, 0x64, 0, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT1__GPIO4_22			IOMUX_PAD(0x390, 0x64, 1, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT1__CSPI_MOSI			IOMUX_PAD(0x390, 0x64, 2, 0x788, 0, 0)
+#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1	IOMUX_PAD(0x390, 0x64, 3, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL	IOMUX_PAD(0x390, 0x64, 5, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6		IOMUX_PAD(0x390, 0x64, 6, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID		IOMUX_PAD(0x390, 0x64, 7, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2		IOMUX_PAD(0x394, 0x68, 0, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT2__GPIO4_23			IOMUX_PAD(0x394, 0x68, 1, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT2__CSPI_MISO			IOMUX_PAD(0x394, 0x68, 2, 0x784, 0, 0)
+#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2	IOMUX_PAD(0x394, 0x68, 3, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE		IOMUX_PAD(0x394, 0x68, 5, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7		IOMUX_PAD(0x394, 0x68, 6, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE		IOMUX_PAD(0x394, 0x68, 7, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3		IOMUX_PAD(0x398, 0x6C, 0, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT3__GPIO4_24			IOMUX_PAD(0x398, 0x6C, 1, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT3__CSPI_SS0			IOMUX_PAD(0x398, 0x6C, 2, 0x78C, 0, 0)
+#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3	IOMUX_PAD(0x398, 0x6C, 3, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR	IOMUX_PAD(0x398, 0x6C, 5, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8		IOMUX_PAD(0x398, 0x6C, 6, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR		IOMUX_PAD(0x398, 0x6C, 7, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4		IOMUX_PAD(0x39C, 0x70, 0, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT4__GPIO4_25			IOMUX_PAD(0x39C, 0x70, 1, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT4__CSPI_SS1			IOMUX_PAD(0x39C, 0x70, 2, 0x790, 0, 0)
+#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4	IOMUX_PAD(0x39C, 0x70, 3, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB		IOMUX_PAD(0x39C, 0x70, 5, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9		IOMUX_PAD(0x39C, 0x70, 6, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK		IOMUX_PAD(0x39C, 0x70, 7, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5		IOMUX_PAD(0x3A0, 0x74, 0, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT5__GPIO4_26			IOMUX_PAD(0x3A0, 0x74, 1, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT5__CSPI_SS2			IOMUX_PAD(0x3A0, 0x74, 2, 0x794, 0, 0)
+#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5	IOMUX_PAD(0x3A0, 0x74, 3, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS	IOMUX_PAD(0x3A0, 0x74, 5, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10		IOMUX_PAD(0x3A0, 0x74, 6, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0	IOMUX_PAD(0x3A0, 0x74, 7, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6		IOMUX_PAD(0x3A4, 0x78, 0, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT6__GPIO4_27			IOMUX_PAD(0x3A4, 0x78, 1, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT6__CSPI_SS3			IOMUX_PAD(0x3A4, 0x78, 2, 0x798, 0, 0)
+#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6	IOMUX_PAD(0x3A4, 0x78, 3, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE	IOMUX_PAD(0x3A4, 0x78, 5, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11		IOMUX_PAD(0x3A4, 0x78, 6, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1	IOMUX_PAD(0x3A4, 0x78, 7, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7		IOMUX_PAD(0x3A8, 0x7C, 0, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT7__GPIO4_28			IOMUX_PAD(0x3A8, 0x7C, 1, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT7__CSPI_RDY			IOMUX_PAD(0x3A8, 0x7C, 2, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7	IOMUX_PAD(0x3A8, 0x7C, 3, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0	IOMUX_PAD(0x3A8, 0x7C, 5, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12		IOMUX_PAD(0x3A8, 0x7C, 6, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID		IOMUX_PAD(0x3A8, 0x7C, 7, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8		IOMUX_PAD(0x3AC, 0x80, 0, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT8__GPIO4_29			IOMUX_PAD(0x3AC, 0x80, 1, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT8__PWM1_PWMO			IOMUX_PAD(0x3AC, 0x80, 2, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B		IOMUX_PAD(0x3AC, 0x80, 3, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1	IOMUX_PAD(0x3AC, 0x80, 5, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13		IOMUX_PAD(0x3AC, 0x80, 6, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID		IOMUX_PAD(0x3AC, 0x80, 7, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9		IOMUX_PAD(0x3B0, 0x84, 0, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT9__GPIO4_30			IOMUX_PAD(0x3B0, 0x84, 1, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT9__PWM2_PWMO			IOMUX_PAD(0x3B0, 0x84, 2, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B		IOMUX_PAD(0x3B0, 0x84, 3, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2	IOMUX_PAD(0x3B0, 0x84, 5, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14		IOMUX_PAD(0x3B0, 0x84, 6, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0		IOMUX_PAD(0x3B0, 0x84, 7, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10		IOMUX_PAD(0x3B4, 0x88, 0, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT10__GPIO4_31			IOMUX_PAD(0x3B4, 0x88, 1, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP		IOMUX_PAD(0x3B4, 0x88, 2, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3	IOMUX_PAD(0x3B4, 0x88, 5, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15		IOMUX_PAD(0x3B4, 0x88, 6, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1		IOMUX_PAD(0x3B4, 0x88, 7, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11		IOMUX_PAD(0x3B8, 0x8C, 0, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT11__GPIO5_5			IOMUX_PAD(0x3B8, 0x8C, 1, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT		IOMUX_PAD(0x3B8, 0x8C, 2, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4	IOMUX_PAD(0x3B8, 0x8C, 5, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16		IOMUX_PAD(0x3B8, 0x8C, 6, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2		IOMUX_PAD(0x3B8, 0x8C, 7, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12		IOMUX_PAD(0x3BC, 0x90, 0, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT12__GPIO5_6			IOMUX_PAD(0x3BC, 0x90, 1, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK		IOMUX_PAD(0x3BC, 0x90, 2, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5	IOMUX_PAD(0x3BC, 0x90, 5, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17		IOMUX_PAD(0x3BC, 0x90, 6, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3		IOMUX_PAD(0x3BC, 0x90, 7, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13		IOMUX_PAD(0x3C0, 0x94, 0, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT13__GPIO5_7			IOMUX_PAD(0x3C0, 0x94, 1, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS		IOMUX_PAD(0x3C0, 0x94, 3, 0x754, 0, 0)
+#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0	IOMUX_PAD(0x3C0, 0x94, 5, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18		IOMUX_PAD(0x3C0, 0x94, 6, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4		IOMUX_PAD(0x3C0, 0x94, 7, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14		IOMUX_PAD(0x3C4, 0x98, 0, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT14__GPIO5_8			IOMUX_PAD(0x3C4, 0x98, 1, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC		IOMUX_PAD(0x3C4, 0x98, 3, 0x750, 0, 0)
+#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1	IOMUX_PAD(0x3C4, 0x98, 5, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19		IOMUX_PAD(0x3C4, 0x98, 6, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5		IOMUX_PAD(0x3C4, 0x98, 7, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15		IOMUX_PAD(0x3C8, 0x9C, 0, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT15__GPIO5_9			IOMUX_PAD(0x3C8, 0x9C, 1, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1		IOMUX_PAD(0x3C8, 0x9C, 2, 0x7AC, 1, 0)
+#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1		IOMUX_PAD(0x3C8, 0x9C, 3, 0x7C8, 0, 0)
+#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2	IOMUX_PAD(0x3C8, 0x9C, 5, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20		IOMUX_PAD(0x3C8, 0x9C, 6, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6		IOMUX_PAD(0x3C8, 0x9C, 7, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16		IOMUX_PAD(0x3CC, 0xA0, 0, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT16__GPIO5_10			IOMUX_PAD(0x3CC, 0xA0, 1, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI		IOMUX_PAD(0x3CC, 0xA0, 2, 0x7C0, 0, 0)
+#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC		IOMUX_PAD(0x3CC, 0xA0, 3, 0x758, 1, 0)
+#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0		IOMUX_PAD(0x3CC, 0xA0, 4, 0x868, 0, 0)
+#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3	IOMUX_PAD(0x3CC, 0xA0, 5, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21		IOMUX_PAD(0x3CC, 0xA0, 6, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7		IOMUX_PAD(0x3CC, 0xA0, 7, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17		IOMUX_PAD(0x3D0, 0xA4, 0, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT17__GPIO5_11			IOMUX_PAD(0x3D0, 0xA4, 1, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO		IOMUX_PAD(0x3D0, 0xA4, 2, 0x7BC, 0, 0)
+#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD		IOMUX_PAD(0x3D0, 0xA4, 3, 0x74C, 1, 0)
+#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1		IOMUX_PAD(0x3D0, 0xA4, 4, 0x86C, 0, 0)
+#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4	IOMUX_PAD(0x3D0, 0xA4, 5, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22		IOMUX_PAD(0x3D0, 0xA4, 6, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18		IOMUX_PAD(0x3D4, 0xA8, 0, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT18__GPIO5_12			IOMUX_PAD(0x3D4, 0xA8, 1, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0		IOMUX_PAD(0x3D4, 0xA8, 2, 0x7C4, 0, 0)
+#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS		IOMUX_PAD(0x3D4, 0xA8, 3, 0x75C, 1, 0)
+#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS		IOMUX_PAD(0x3D4, 0xA8, 4, 0x73C, 0, 0)
+#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5	IOMUX_PAD(0x3D4, 0xA8, 5, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23		IOMUX_PAD(0x3D4, 0xA8, 6, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2		IOMUX_PAD(0x3D4, 0xA8, 7, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19		IOMUX_PAD(0x3D8, 0xAC, 0, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT19__GPIO5_13			IOMUX_PAD(0x3D8, 0xAC, 1, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK		IOMUX_PAD(0x3D8, 0xAC, 2, 0x7B8, 0, 0)
+#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD		IOMUX_PAD(0x3D8, 0xAC, 3, 0x748, 1, 0)
+#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC		IOMUX_PAD(0x3D8, 0xAC, 4, 0x738, 0, 0)
+#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6	IOMUX_PAD(0x3D8, 0xAC, 5, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24		IOMUX_PAD(0x3D8, 0xAC, 6, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3		IOMUX_PAD(0x3D8, 0xAC, 7, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20		IOMUX_PAD(0x3DC, 0xB0, 0, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT20__GPIO5_14			IOMUX_PAD(0x3DC, 0xB0, 1, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK		IOMUX_PAD(0x3DC, 0xB0, 2, 0x79C, 1, 0)
+#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC		IOMUX_PAD(0x3DC, 0xB0, 3, 0x740, 0, 0)
+#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7	IOMUX_PAD(0x3DC, 0xB0, 5, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25		IOMUX_PAD(0x3DC, 0xB0, 6, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI		IOMUX_PAD(0x3DC, 0xB0, 7, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21		IOMUX_PAD(0x3E0, 0xB4, 0, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT21__GPIO5_15			IOMUX_PAD(0x3E0, 0xB4, 1, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI		IOMUX_PAD(0x3E0, 0xB4, 2, 0x7A4, 1, 0)
+#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD		IOMUX_PAD(0x3E0, 0xB4, 3, 0x734, 0, 0)
+#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0	IOMUX_PAD(0x3E0, 0xB4, 5, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26		IOMUX_PAD(0x3E0, 0xB4, 6, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO		IOMUX_PAD(0x3E0, 0xB4, 7, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22		IOMUX_PAD(0x3E4, 0xB8, 0, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT22__GPIO5_16			IOMUX_PAD(0x3E4, 0xB8, 1, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO		IOMUX_PAD(0x3E4, 0xB8, 2, 0x7A0, 1, 0)
+#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS		IOMUX_PAD(0x3E4, 0xB8, 3, 0x744, 0, 0)
+#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1	IOMUX_PAD(0x3E4, 0xB8, 5, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27		IOMUX_PAD(0x3E4, 0xB8, 6, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK		IOMUX_PAD(0x3E4, 0xB8, 7, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23		IOMUX_PAD(0x3E8, 0xBC, 0, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT23__GPIO5_17			IOMUX_PAD(0x3E8, 0xBC, 1, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0		IOMUX_PAD(0x3E8, 0xBC, 2, 0x7A8, 1, 0)
+#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD		IOMUX_PAD(0x3E8, 0xBC, 3, 0x730, 0, 0)
+#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2	IOMUX_PAD(0x3E8, 0xBC, 5, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28		IOMUX_PAD(0x3E8, 0xBC, 6, 0x0, 0, 0)
+#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS		IOMUX_PAD(0x3E8, 0xBC, 7, 0x0, 0, 0)
+#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK		IOMUX_PAD(0x3EC, 0xC0, 0, 0x0, 0, 0)
+#define MX53_PAD_CSI0_PIXCLK__GPIO5_18			IOMUX_PAD(0x3EC, 0xC0, 1, 0x0, 0, 0)
+#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0		IOMUX_PAD(0x3EC, 0xC0, 5, 0x0, 0, 0)
+#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29		IOMUX_PAD(0x3EC, 0xC0, 6, 0x0, 0, 0)
+#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC		IOMUX_PAD(0x3F0, 0xC4, 0, 0x0, 0, 0)
+#define MX53_PAD_CSI0_MCLK__GPIO5_19			IOMUX_PAD(0x3F0, 0xC4, 1, 0x0, 0, 0)
+#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK		IOMUX_PAD(0x3F0, 0xC4, 2, 0x0, 0, 0)
+#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1		IOMUX_PAD(0x3F0, 0xC4, 5, 0x0, 0, 0)
+#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30		IOMUX_PAD(0x3F0, 0xC4, 6, 0x0, 0, 0)
+#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL			IOMUX_PAD(0x3F0, 0xC4, 7, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN		IOMUX_PAD(0x3F4, 0xC8, 0, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DATA_EN__GPIO5_20			IOMUX_PAD(0x3F4, 0xC8, 1, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2		IOMUX_PAD(0x3F4, 0xC8, 5, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31		IOMUX_PAD(0x3F4, 0xC8, 6, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK		IOMUX_PAD(0x3F4, 0xC8, 7, 0x0, 0, 0)
+#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC		IOMUX_PAD(0x3F8, 0xCC, 0, 0x0, 0, 0)
+#define MX53_PAD_CSI0_VSYNC__GPIO5_21			IOMUX_PAD(0x3F8, 0xCC, 1, 0x0, 0, 0)
+#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3		IOMUX_PAD(0x3F8, 0xCC, 5, 0x0, 0, 0)
+#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32		IOMUX_PAD(0x3F8, 0xCC, 6, 0x0, 0, 0)
+#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0		IOMUX_PAD(0x3F8, 0xCC, 7, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4		IOMUX_PAD(0x3FC, 0xD0, 0, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT4__GPIO5_22			IOMUX_PAD(0x3FC, 0xD0, 1, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT4__KPP_COL_5			IOMUX_PAD(0x3FC, 0xD0, 2, 0x840, 1, 0)
+#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK			IOMUX_PAD(0x3FC, 0xD0, 3, 0x79C, 2, 0)
+#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP		IOMUX_PAD(0x3FC, 0xD0, 4, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC		IOMUX_PAD(0x3FC, 0xD0, 5, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33		IOMUX_PAD(0x3FC, 0xD0, 6, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1		IOMUX_PAD(0x3FC, 0xD0, 7, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5		IOMUX_PAD(0x400, 0xD4, 0, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT5__GPIO5_23			IOMUX_PAD(0x400, 0xD4, 1, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT5__KPP_ROW_5			IOMUX_PAD(0x400, 0xD4, 2, 0x84C, 0, 0)
+#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI			IOMUX_PAD(0x400, 0xD4, 3, 0x7A4, 2, 0)
+#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT		IOMUX_PAD(0x400, 0xD4, 4, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD		IOMUX_PAD(0x400, 0xD4, 5, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34		IOMUX_PAD(0x400, 0xD4, 6, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2		IOMUX_PAD(0x400, 0xD4, 7, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6		IOMUX_PAD(0x404, 0xD8, 0, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT6__GPIO5_24			IOMUX_PAD(0x404, 0xD8, 1, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT6__KPP_COL_6			IOMUX_PAD(0x404, 0xD8, 2, 0x844, 0, 0)
+#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO			IOMUX_PAD(0x404, 0xD8, 3, 0x7A0, 2, 0)
+#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK		IOMUX_PAD(0x404, 0xD8, 4, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS		IOMUX_PAD(0x404, 0xD8, 5, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35		IOMUX_PAD(0x404, 0xD8, 6, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3		IOMUX_PAD(0x404, 0xD8, 7, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7		IOMUX_PAD(0x408, 0xDC, 0, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT7__GPIO5_25			IOMUX_PAD(0x408, 0xDC, 1, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT7__KPP_ROW_6			IOMUX_PAD(0x408, 0xDC, 2, 0x850, 0, 0)
+#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0			IOMUX_PAD(0x408, 0xDC, 3, 0x7A8, 2, 0)
+#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR		IOMUX_PAD(0x408, 0xDC, 4, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD		IOMUX_PAD(0x408, 0xDC, 5, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36		IOMUX_PAD(0x408, 0xDC, 6, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4		IOMUX_PAD(0x408, 0xDC, 7, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8		IOMUX_PAD(0x40C, 0xE0, 0, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT8__GPIO5_26			IOMUX_PAD(0x40C, 0xE0, 1, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT8__KPP_COL_7			IOMUX_PAD(0x40C, 0xE0, 2, 0x848, 0, 0)
+#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK			IOMUX_PAD(0x40C, 0xE0, 3, 0x7B8, 1, 0)
+#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC		IOMUX_PAD(0x40C, 0xE0, 4, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT8__I2C1_SDA			IOMUX_PAD(0x40C, 0xE0, 5 | IOMUX_CONFIG_SION, 0x818, 0, 0)
+#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37		IOMUX_PAD(0x40C, 0xE0, 6, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5		IOMUX_PAD(0x40C, 0xE0, 7, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9		IOMUX_PAD(0x410, 0xE4, 0, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT9__GPIO5_27			IOMUX_PAD(0x410, 0xE4, 1, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT9__KPP_ROW_7			IOMUX_PAD(0x410, 0xE4, 2, 0x854, 0, 0)
+#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI			IOMUX_PAD(0x410, 0xE4, 3, 0x7C0, 1, 0)
+#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR		IOMUX_PAD(0x410, 0xE4, 4, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT9__I2C1_SCL			IOMUX_PAD(0x410, 0xE4, 5 | IOMUX_CONFIG_SION, 0x814, 0, 0)
+#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38		IOMUX_PAD(0x410, 0xE4, 6, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6		IOMUX_PAD(0x410, 0xE4, 7, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10		IOMUX_PAD(0x414, 0xE8, 0, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT10__GPIO5_28			IOMUX_PAD(0x414, 0xE8, 1, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX		IOMUX_PAD(0x414, 0xE8, 2, 0x878, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO		IOMUX_PAD(0x414, 0xE8, 3, 0x7BC, 1, 0)
+#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC		IOMUX_PAD(0x414, 0xE8, 4, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4		IOMUX_PAD(0x414, 0xE8, 5, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39		IOMUX_PAD(0x414, 0xE8, 6, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7		IOMUX_PAD(0x414, 0xE8, 7, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11		IOMUX_PAD(0x418, 0xEC, 0, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT11__GPIO5_29			IOMUX_PAD(0x418, 0xEC, 1, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX		IOMUX_PAD(0x418, 0xEC, 2, 0x878, 1, MX53_UART_PAD_CTRL)
+#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0			IOMUX_PAD(0x418, 0xEC, 3, 0x7C4, 1, 0)
+#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS		IOMUX_PAD(0x418, 0xEC, 4, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5		IOMUX_PAD(0x418, 0xEC, 5, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40		IOMUX_PAD(0x418, 0xEC, 6, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8		IOMUX_PAD(0x418, 0xEC, 7, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12		IOMUX_PAD(0x41C, 0xF0, 0, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT12__GPIO5_30			IOMUX_PAD(0x41C, 0xF0, 1, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX		IOMUX_PAD(0x41C, 0xF0, 2, 0x890, 2, 0)
+#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0	IOMUX_PAD(0x41C, 0xF0, 4, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6		IOMUX_PAD(0x41C, 0xF0, 5, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41		IOMUX_PAD(0x41C, 0xF0, 6, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9		IOMUX_PAD(0x41C, 0xF0, 7, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13		IOMUX_PAD(0x420, 0xF4, 0, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT13__GPIO5_31			IOMUX_PAD(0x420, 0xF4, 1, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX		IOMUX_PAD(0x420, 0xF4, 2, 0x890, 3, 0)
+#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1	IOMUX_PAD(0x420, 0xF4, 4, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7		IOMUX_PAD(0x420, 0xF4, 5, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42		IOMUX_PAD(0x420, 0xF4, 6, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10		IOMUX_PAD(0x420, 0xF4, 7, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14		IOMUX_PAD(0x424, 0xF8, 0, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT14__GPIO6_0			IOMUX_PAD(0x424, 0xF8, 1, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX		IOMUX_PAD(0x424, 0xF8, 2, 0x898, 2, 0)
+#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2	IOMUX_PAD(0x424, 0xF8, 4, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8		IOMUX_PAD(0x424, 0xF8, 5, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43		IOMUX_PAD(0x424, 0xF8, 6, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11		IOMUX_PAD(0x424, 0xF8, 7, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15		IOMUX_PAD(0x428, 0xFC, 0, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT15__GPIO6_1			IOMUX_PAD(0x428, 0xFC, 1, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX		IOMUX_PAD(0x428, 0xFC, 2, 0x898, 3, 0)
+#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3	IOMUX_PAD(0x428, 0xFC, 4, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9		IOMUX_PAD(0x428, 0xFC, 5, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44		IOMUX_PAD(0x428, 0xFC, 6, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12		IOMUX_PAD(0x428, 0xFC, 7, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16		IOMUX_PAD(0x42C, 0x100, 0, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT16__GPIO6_2			IOMUX_PAD(0x42C, 0x100, 1, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT16__UART4_RTS			IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, 0)
+#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4	IOMUX_PAD(0x42C, 0x100, 4, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10		IOMUX_PAD(0x42C, 0x100, 5, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45		IOMUX_PAD(0x42C, 0x100, 6, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13		IOMUX_PAD(0x42C, 0x100, 7, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17		IOMUX_PAD(0x430, 0x104, 0, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT17__GPIO6_3			IOMUX_PAD(0x430, 0x104, 1, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT17__UART4_CTS			IOMUX_PAD(0x430, 0x104, 2, 0x88C, 1, 0)
+#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5	IOMUX_PAD(0x430, 0x104, 4, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11		IOMUX_PAD(0x430, 0x104, 5, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46		IOMUX_PAD(0x430, 0x104, 6, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14		IOMUX_PAD(0x430, 0x104, 7, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18		IOMUX_PAD(0x434, 0x108, 0, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT18__GPIO6_4			IOMUX_PAD(0x434, 0x108, 1, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT18__UART5_RTS			IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, 0)
+#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6	IOMUX_PAD(0x434, 0x108, 4, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12		IOMUX_PAD(0x434, 0x108, 5, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47		IOMUX_PAD(0x434, 0x108, 6, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15		IOMUX_PAD(0x434, 0x108, 7, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19		IOMUX_PAD(0x438, 0x10C, 0, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT19__GPIO6_5			IOMUX_PAD(0x438, 0x10C, 1, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT19__UART5_CTS			IOMUX_PAD(0x438, 0x10C, 2, 0x894, 3, 0)
+#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7	IOMUX_PAD(0x438, 0x10C, 4, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13		IOMUX_PAD(0x438, 0x10C, 5, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48		IOMUX_PAD(0x438, 0x10C, 6, 0x0, 0, 0)
+#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK		IOMUX_PAD(0x438, 0x10C, 7, 0x0, 0, 0)
+#define MX53_PAD_EIM_A25__EMI_WEIM_A_25			IOMUX_PAD(0x458, 0x110, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_A25__GPIO5_2			IOMUX_PAD(0x458, 0x110, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_A25__ECSPI2_RDY			IOMUX_PAD(0x458, 0x110, 2, 0x0, 0, 0)
+#define MX53_PAD_EIM_A25__IPU_DI1_PIN12			IOMUX_PAD(0x458, 0x110, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_A25__CSPI_SS1			IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, 0)
+#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS			IOMUX_PAD(0x458, 0x110, 6, 0x0, 0, 0)
+#define MX53_PAD_EIM_A25__USBPHY1_BISTOK		IOMUX_PAD(0x458, 0x110, 7, 0x0, 0, 0)
+#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2			IOMUX_PAD(0x45C, 0x114, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_EB2__GPIO2_30			IOMUX_PAD(0x45C, 0x114, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK		IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, 0)
+#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS		IOMUX_PAD(0x45C, 0x114, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_EB2__ECSPI1_SS0			IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, 0)
+#define MX53_PAD_EIM_EB2__I2C2_SCL			IOMUX_PAD(0x45C, 0x114, 5 | IOMUX_CONFIG_SION, 0x81C, 1, 0)
+#define MX53_PAD_EIM_D16__EMI_WEIM_D_16			IOMUX_PAD(0x460, 0x118, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_D16__GPIO3_16			IOMUX_PAD(0x460, 0x118, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_D16__IPU_DI0_PIN5			IOMUX_PAD(0x460, 0x118, 2, 0x0, 0, 0)
+#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK		IOMUX_PAD(0x460, 0x118, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_D16__ECSPI1_SCLK			IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, 0)
+#define MX53_PAD_EIM_D16__I2C2_SDA			IOMUX_PAD(0x460, 0x118, 5, 0x820, 1, 0)
+#define MX53_PAD_EIM_D17__EMI_WEIM_D_17			IOMUX_PAD(0x464, 0x11C, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_D17__GPIO3_17			IOMUX_PAD(0x464, 0x11C, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_D17__IPU_DI0_PIN6			IOMUX_PAD(0x464, 0x11C, 2, 0x0, 0, 0)
+#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN		IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, 0)
+#define MX53_PAD_EIM_D17__ECSPI1_MISO			IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, 0)
+#define MX53_PAD_EIM_D17__I2C3_SCL			IOMUX_PAD(0x464, 0x11C, 5, 0x824, 0, 0)
+#define MX53_PAD_EIM_D18__EMI_WEIM_D_18			IOMUX_PAD(0x468, 0x120, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_D18__GPIO3_18			IOMUX_PAD(0x468, 0x120, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_D18__IPU_DI0_PIN7			IOMUX_PAD(0x468, 0x120, 2, 0x0, 0, 0)
+#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO		IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, 0)
+#define MX53_PAD_EIM_D18__ECSPI1_MOSI			IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, 0)
+#define MX53_PAD_EIM_D18__I2C3_SDA			IOMUX_PAD(0x468, 0x120, 5, 0x828, 0, 0)
+#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS			IOMUX_PAD(0x468, 0x120, 6, 0x0, 0, 0)
+#define MX53_PAD_EIM_D19__EMI_WEIM_D_19			IOMUX_PAD(0x46C, 0x124, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_D19__GPIO3_19			IOMUX_PAD(0x46C, 0x124, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_D19__IPU_DI0_PIN8			IOMUX_PAD(0x46C, 0x124, 2, 0x0, 0, 0)
+#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS		IOMUX_PAD(0x46C, 0x124, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_D19__ECSPI1_SS1			IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, 0)
+#define MX53_PAD_EIM_D19__EPIT1_EPITO			IOMUX_PAD(0x46C, 0x124, 5, 0x0, 0, 0)
+#define MX53_PAD_EIM_D19__UART1_CTS			IOMUX_PAD(0x46C, 0x124, 6, 0x874, 0, 0)
+#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC		IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, 0)
+#define MX53_PAD_EIM_D20__EMI_WEIM_D_20			IOMUX_PAD(0x470, 0x128, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_D20__GPIO3_20			IOMUX_PAD(0x470, 0x128, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_D20__IPU_DI0_PIN16			IOMUX_PAD(0x470, 0x128, 2, 0x0, 0, 0)
+#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS		IOMUX_PAD(0x470, 0x128, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_D20__CSPI_SS0			IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, 0)
+#define MX53_PAD_EIM_D20__EPIT2_EPITO			IOMUX_PAD(0x470, 0x128, 5, 0x0, 0, 0)
+#define MX53_PAD_EIM_D20__UART1_RTS			IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, 0)
+#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR		IOMUX_PAD(0x470, 0x128, 7, 0x0, 0, 0)
+#define MX53_PAD_EIM_D21__EMI_WEIM_D_21			IOMUX_PAD(0x474, 0x12C, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_D21__GPIO3_21			IOMUX_PAD(0x474, 0x12C, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_D21__IPU_DI0_PIN17			IOMUX_PAD(0x474, 0x12C, 2, 0x0, 0, 0)
+#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK		IOMUX_PAD(0x474, 0x12C, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_D21__CSPI_SCLK			IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, 0)
+#define MX53_PAD_EIM_D21__I2C1_SCL			IOMUX_PAD(0x474, 0x12C, 5, 0x814, 1, 0)
+#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC		IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, 0)
+#define MX53_PAD_EIM_D22__EMI_WEIM_D_22			IOMUX_PAD(0x478, 0x130, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_D22__GPIO3_22			IOMUX_PAD(0x478, 0x130, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_D22__IPU_DI0_PIN1			IOMUX_PAD(0x478, 0x130, 2, 0x0, 0, 0)
+#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN		IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, 0)
+#define MX53_PAD_EIM_D22__CSPI_MISO			IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, 0)
+#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR		IOMUX_PAD(0x478, 0x130, 6, 0x0, 0, 0)
+#define MX53_PAD_EIM_D23__EMI_WEIM_D_23			IOMUX_PAD(0x47C, 0x134, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_D23__GPIO3_23			IOMUX_PAD(0x47C, 0x134, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_D23__UART3_CTS			IOMUX_PAD(0x47C, 0x134, 2, 0x884, 0, 0)
+#define MX53_PAD_EIM_D23__UART1_DCD			IOMUX_PAD(0x47C, 0x134, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS			IOMUX_PAD(0x47C, 0x134, 4, 0x0, 0, 0)
+#define MX53_PAD_EIM_D23__IPU_DI1_PIN2			IOMUX_PAD(0x47C, 0x134, 5, 0x0, 0, 0)
+#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN		IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, 0)
+#define MX53_PAD_EIM_D23__IPU_DI1_PIN14			IOMUX_PAD(0x47C, 0x134, 7, 0x0, 0, 0)
+#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3			IOMUX_PAD(0x480, 0x138, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_EB3__GPIO2_31			IOMUX_PAD(0x480, 0x138, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_EB3__UART3_RTS			IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, 0)
+#define MX53_PAD_EIM_EB3__UART1_RI			IOMUX_PAD(0x480, 0x138, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3			IOMUX_PAD(0x480, 0x138, 5, 0x0, 0, 0)
+#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC		IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, 0)
+#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16			IOMUX_PAD(0x480, 0x138, 7, 0x0, 0, 0)
+#define MX53_PAD_EIM_D24__EMI_WEIM_D_24			IOMUX_PAD(0x484, 0x13C, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_D24__GPIO3_24			IOMUX_PAD(0x484, 0x13C, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_D24__UART3_TXD_MUX			IOMUX_PAD(0x484, 0x13C, 2, 0x888, 0, 0)
+#define MX53_PAD_EIM_D24__ECSPI1_SS2			IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, 0)
+#define MX53_PAD_EIM_D24__CSPI_SS2			IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, 0)
+#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS		IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, 0)
+#define MX53_PAD_EIM_D24__ECSPI2_SS2			IOMUX_PAD(0x484, 0x13C, 6, 0x0, 0, 0)
+#define MX53_PAD_EIM_D24__UART1_DTR			IOMUX_PAD(0x484, 0x13C, 7, 0x0, 0, 0)
+#define MX53_PAD_EIM_D25__EMI_WEIM_D_25			IOMUX_PAD(0x488, 0x140, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_D25__GPIO3_25			IOMUX_PAD(0x488, 0x140, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_D25__UART3_RXD_MUX			IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, 0)
+#define MX53_PAD_EIM_D25__ECSPI1_SS3			IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, 0)
+#define MX53_PAD_EIM_D25__CSPI_SS3			IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, 0)
+#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC		IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, 0)
+#define MX53_PAD_EIM_D25__ECSPI2_SS3			IOMUX_PAD(0x488, 0x140, 6, 0x0, 0, 0)
+#define MX53_PAD_EIM_D25__UART1_DSR			IOMUX_PAD(0x488, 0x140, 7, 0x0, 0, 0)
+#define MX53_PAD_EIM_D26__EMI_WEIM_D_26			IOMUX_PAD(0x48C, 0x144, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_D26__GPIO3_26			IOMUX_PAD(0x48C, 0x144, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_D26__UART2_TXD_MUX			IOMUX_PAD(0x48C, 0x144, 2, 0x880, 0, 0)
+#define MX53_PAD_EIM_D26__FIRI_RXD			IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, 0)
+#define MX53_PAD_EIM_D26__IPU_CSI0_D_1			IOMUX_PAD(0x48C, 0x144, 4, 0x0, 0, 0)
+#define MX53_PAD_EIM_D26__IPU_DI1_PIN11			IOMUX_PAD(0x48C, 0x144, 5, 0x0, 0, 0)
+#define MX53_PAD_EIM_D26__IPU_SISG_2			IOMUX_PAD(0x48C, 0x144, 6, 0x0, 0, 0)
+#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22		IOMUX_PAD(0x48C, 0x144, 7, 0x0, 0, 0)
+#define MX53_PAD_EIM_D27__EMI_WEIM_D_27			IOMUX_PAD(0x490, 0x148, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_D27__GPIO3_27			IOMUX_PAD(0x490, 0x148, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_D27__UART2_RXD_MUX			IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, 0)
+#define MX53_PAD_EIM_D27__FIRI_TXD			IOMUX_PAD(0x490, 0x148, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_D27__IPU_CSI0_D_0			IOMUX_PAD(0x490, 0x148, 4, 0x0, 0, 0)
+#define MX53_PAD_EIM_D27__IPU_DI1_PIN13			IOMUX_PAD(0x490, 0x148, 5, 0x0, 0, 0)
+#define MX53_PAD_EIM_D27__IPU_SISG_3			IOMUX_PAD(0x490, 0x148, 6, 0x0, 0, 0)
+#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23		IOMUX_PAD(0x490, 0x148, 7, 0x0, 0, 0)
+#define MX53_PAD_EIM_D28__EMI_WEIM_D_28			IOMUX_PAD(0x494, 0x14C, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_D28__GPIO3_28			IOMUX_PAD(0x494, 0x14C, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_D28__UART2_CTS			IOMUX_PAD(0x494, 0x14C, 2, 0x87C, 0, 0)
+#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO		IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, 0)
+#define MX53_PAD_EIM_D28__CSPI_MOSI			IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, 0)
+#define MX53_PAD_EIM_D28__I2C1_SDA			IOMUX_PAD(0x494, 0x14C, 5, 0x818, 1, 0)
+#define MX53_PAD_EIM_D28__IPU_EXT_TRIG			IOMUX_PAD(0x494, 0x14C, 6, 0x0, 0, 0)
+#define MX53_PAD_EIM_D28__IPU_DI0_PIN13			IOMUX_PAD(0x494, 0x14C, 7, 0x0, 0, 0)
+#define MX53_PAD_EIM_D29__EMI_WEIM_D_29			IOMUX_PAD(0x498, 0x150, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_D29__GPIO3_29			IOMUX_PAD(0x498, 0x150, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_D29__UART2_RTS			IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, 0)
+#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS		IOMUX_PAD(0x498, 0x150, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_D29__CSPI_SS0			IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, 0)
+#define MX53_PAD_EIM_D29__IPU_DI1_PIN15			IOMUX_PAD(0x498, 0x150, 5, 0x0, 0, 0)
+#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC		IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, 0)
+#define MX53_PAD_EIM_D29__IPU_DI0_PIN14			IOMUX_PAD(0x498, 0x150, 7, 0x0, 0, 0)
+#define MX53_PAD_EIM_D30__EMI_WEIM_D_30			IOMUX_PAD(0x49C, 0x154, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_D30__GPIO3_30			IOMUX_PAD(0x49C, 0x154, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_D30__UART3_CTS			IOMUX_PAD(0x49C, 0x154, 2, 0x884, 2, 0)
+#define MX53_PAD_EIM_D30__IPU_CSI0_D_3			IOMUX_PAD(0x49C, 0x154, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_D30__IPU_DI0_PIN11			IOMUX_PAD(0x49C, 0x154, 4, 0x0, 0, 0)
+#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21		IOMUX_PAD(0x49C, 0x154, 5, 0x0, 0, 0)
+#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC		IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, 0)
+#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC		IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, 0)
+#define MX53_PAD_EIM_D31__EMI_WEIM_D_31			IOMUX_PAD(0x4A0, 0x158, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_D31__GPIO3_31			IOMUX_PAD(0x4A0, 0x158, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_D31__UART3_RTS			IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, 0)
+#define MX53_PAD_EIM_D31__IPU_CSI0_D_2			IOMUX_PAD(0x4A0, 0x158, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_D31__IPU_DI0_PIN12			IOMUX_PAD(0x4A0, 0x158, 4, 0x0, 0, 0)
+#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20		IOMUX_PAD(0x4A0, 0x158, 5, 0x0, 0, 0)
+#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR		IOMUX_PAD(0x4A0, 0x158, 6, 0x0, 0, 0)
+#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR		IOMUX_PAD(0x4A0, 0x158, 7, 0x0, 0, 0)
+#define MX53_PAD_EIM_A24__EMI_WEIM_A_24			IOMUX_PAD(0x4A8, 0x15C, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_A24__GPIO5_4			IOMUX_PAD(0x4A8, 0x15C, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19		IOMUX_PAD(0x4A8, 0x15C, 2, 0x0, 0, 0)
+#define MX53_PAD_EIM_A24__IPU_CSI1_D_19			IOMUX_PAD(0x4A8, 0x15C, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_A24__IPU_SISG_2			IOMUX_PAD(0x4A8, 0x15C, 6, 0x0, 0, 0)
+#define MX53_PAD_EIM_A24__USBPHY2_BVALID		IOMUX_PAD(0x4A8, 0x15C, 7, 0x0, 0, 0)
+#define MX53_PAD_EIM_A23__EMI_WEIM_A_23			IOMUX_PAD(0x4AC, 0x160, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_A23__GPIO6_6			IOMUX_PAD(0x4AC, 0x160, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18		IOMUX_PAD(0x4AC, 0x160, 2, 0x0, 0, 0)
+#define MX53_PAD_EIM_A23__IPU_CSI1_D_18			IOMUX_PAD(0x4AC, 0x160, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_A23__IPU_SISG_3			IOMUX_PAD(0x4AC, 0x160, 6, 0x0, 0, 0)
+#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION		IOMUX_PAD(0x4AC, 0x160, 7, 0x0, 0, 0)
+#define MX53_PAD_EIM_A22__EMI_WEIM_A_22			IOMUX_PAD(0x4B0, 0x164, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_A22__GPIO2_16			IOMUX_PAD(0x4B0, 0x164, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17		IOMUX_PAD(0x4B0, 0x164, 2, 0x0, 0, 0)
+#define MX53_PAD_EIM_A22__IPU_CSI1_D_17			IOMUX_PAD(0x4B0, 0x164, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7			IOMUX_PAD(0x4B0, 0x164, 7, 0x0, 0, 0)
+#define MX53_PAD_EIM_A21__EMI_WEIM_A_21			IOMUX_PAD(0x4B4, 0x168, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_A21__GPIO2_17			IOMUX_PAD(0x4B4, 0x168, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16		IOMUX_PAD(0x4B4, 0x168, 2, 0x0, 0, 0)
+#define MX53_PAD_EIM_A21__IPU_CSI1_D_16			IOMUX_PAD(0x4B4, 0x168, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6			IOMUX_PAD(0x4B4, 0x168, 7, 0x0, 0, 0)
+#define MX53_PAD_EIM_A20__EMI_WEIM_A_20			IOMUX_PAD(0x4B8, 0x16C, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_A20__GPIO2_18			IOMUX_PAD(0x4B8, 0x16C, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15		IOMUX_PAD(0x4B8, 0x16C, 2, 0x0, 0, 0)
+#define MX53_PAD_EIM_A20__IPU_CSI1_D_15			IOMUX_PAD(0x4B8, 0x16C, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5			IOMUX_PAD(0x4B8, 0x16C, 7, 0x0, 0, 0)
+#define MX53_PAD_EIM_A19__EMI_WEIM_A_19			IOMUX_PAD(0x4BC, 0x170, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_A19__GPIO2_19			IOMUX_PAD(0x4BC, 0x170, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14		IOMUX_PAD(0x4BC, 0x170, 2, 0x0, 0, 0)
+#define MX53_PAD_EIM_A19__IPU_CSI1_D_14			IOMUX_PAD(0x4BC, 0x170, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4			IOMUX_PAD(0x4BC, 0x170, 7, 0x0, 0, 0)
+#define MX53_PAD_EIM_A18__EMI_WEIM_A_18			IOMUX_PAD(0x4C0, 0x174, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_A18__GPIO2_20			IOMUX_PAD(0x4C0, 0x174, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13		IOMUX_PAD(0x4C0, 0x174, 2, 0x0, 0, 0)
+#define MX53_PAD_EIM_A18__IPU_CSI1_D_13			IOMUX_PAD(0x4C0, 0x174, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3			IOMUX_PAD(0x4C0, 0x174, 7, 0x0, 0, 0)
+#define MX53_PAD_EIM_A17__EMI_WEIM_A_17			IOMUX_PAD(0x4C4, 0x178, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_A17__GPIO2_21			IOMUX_PAD(0x4C4, 0x178, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12		IOMUX_PAD(0x4C4, 0x178, 2, 0x0, 0, 0)
+#define MX53_PAD_EIM_A17__IPU_CSI1_D_12			IOMUX_PAD(0x4C4, 0x178, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2			IOMUX_PAD(0x4C4, 0x178, 7, 0x0, 0, 0)
+#define MX53_PAD_EIM_A16__EMI_WEIM_A_16			IOMUX_PAD(0x4C8, 0x17C, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_A16__GPIO2_22			IOMUX_PAD(0x4C8, 0x17C, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK		IOMUX_PAD(0x4C8, 0x17C, 2, 0x0, 0, 0)
+#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK		IOMUX_PAD(0x4C8, 0x17C, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1			IOMUX_PAD(0x4C8, 0x17C, 7, 0x0, 0, 0)
+#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0			IOMUX_PAD(0x4CC, 0x180, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_CS0__GPIO2_23			IOMUX_PAD(0x4CC, 0x180, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_CS0__ECSPI2_SCLK			IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, 0)
+#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5			IOMUX_PAD(0x4CC, 0x180, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1			IOMUX_PAD(0x4D0, 0x184, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_CS1__GPIO2_24			IOMUX_PAD(0x4D0, 0x184, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_CS1__ECSPI2_MOSI			IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, 0)
+#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6			IOMUX_PAD(0x4D0, 0x184, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_OE__EMI_WEIM_OE			IOMUX_PAD(0x4D4, 0x188, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_OE__GPIO2_25			IOMUX_PAD(0x4D4, 0x188, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_OE__ECSPI2_MISO			IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, 0)
+#define MX53_PAD_EIM_OE__IPU_DI1_PIN7			IOMUX_PAD(0x4D4, 0x188, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_OE__USBPHY2_IDDIG			IOMUX_PAD(0x4D4, 0x188, 7, 0x0, 0, 0)
+#define MX53_PAD_EIM_RW__EMI_WEIM_RW			IOMUX_PAD(0x4D8, 0x18C, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_RW__GPIO2_26			IOMUX_PAD(0x4D8, 0x18C, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_RW__ECSPI2_SS0			IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, 0)
+#define MX53_PAD_EIM_RW__IPU_DI1_PIN8			IOMUX_PAD(0x4D8, 0x18C, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT		IOMUX_PAD(0x4D8, 0x18C, 7, 0x0, 0, 0)
+#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA			IOMUX_PAD(0x4DC, 0x190, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_LBA__GPIO2_27			IOMUX_PAD(0x4DC, 0x190, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_LBA__ECSPI2_SS1			IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, 0)
+#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17			IOMUX_PAD(0x4DC, 0x190, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0			IOMUX_PAD(0x4DC, 0x190, 7, 0x0, 0, 0)
+#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0			IOMUX_PAD(0x4E4, 0x194, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_EB0__GPIO2_28			IOMUX_PAD(0x4E4, 0x194, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11		IOMUX_PAD(0x4E4, 0x194, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11			IOMUX_PAD(0x4E4, 0x194, 4, 0x0, 0, 0)
+#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY			IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, 0)
+#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7			IOMUX_PAD(0x4E4, 0x194, 7, 0x0, 0, 0)
+#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1			IOMUX_PAD(0x4E8, 0x198, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_EB1__GPIO2_29			IOMUX_PAD(0x4E8, 0x198, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10		IOMUX_PAD(0x4E8, 0x198, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10			IOMUX_PAD(0x4E8, 0x198, 4, 0x0, 0, 0)
+#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6			IOMUX_PAD(0x4E8, 0x198, 7, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0		IOMUX_PAD(0x4EC, 0x19C, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA0__GPIO3_0			IOMUX_PAD(0x4EC, 0x19C, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9		IOMUX_PAD(0x4EC, 0x19C, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9			IOMUX_PAD(0x4EC, 0x19C, 4, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5			IOMUX_PAD(0x4EC, 0x19C, 7, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1		IOMUX_PAD(0x4F0, 0x1A0, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA1__GPIO3_1			IOMUX_PAD(0x4F0, 0x1A0, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8		IOMUX_PAD(0x4F0, 0x1A0, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8			IOMUX_PAD(0x4F0, 0x1A0, 4, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4			IOMUX_PAD(0x4F0, 0x1A0, 7, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2		IOMUX_PAD(0x4F4, 0x1A4, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA2__GPIO3_2			IOMUX_PAD(0x4F4, 0x1A4, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7		IOMUX_PAD(0x4F4, 0x1A4, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7			IOMUX_PAD(0x4F4, 0x1A4, 4, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3			IOMUX_PAD(0x4F4, 0x1A4, 7, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3		IOMUX_PAD(0x4F8, 0x1A8, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA3__GPIO3_3			IOMUX_PAD(0x4F8, 0x1A8, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6		IOMUX_PAD(0x4F8, 0x1A8, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6			IOMUX_PAD(0x4F8, 0x1A8, 4, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2			IOMUX_PAD(0x4F8, 0x1A8, 7, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4		IOMUX_PAD(0x4FC, 0x1AC, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA4__GPIO3_4			IOMUX_PAD(0x4FC, 0x1AC, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5		IOMUX_PAD(0x4FC, 0x1AC, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5			IOMUX_PAD(0x4FC, 0x1AC, 4, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7			IOMUX_PAD(0x4FC, 0x1AC, 7, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5		IOMUX_PAD(0x500, 0x1B0, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA5__GPIO3_5			IOMUX_PAD(0x500, 0x1B0, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4		IOMUX_PAD(0x500, 0x1B0, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4			IOMUX_PAD(0x500, 0x1B0, 4, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6			IOMUX_PAD(0x500, 0x1B0, 17, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6		IOMUX_PAD(0x504, 0x1B4, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA6__GPIO3_6			IOMUX_PAD(0x504, 0x1B4, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3		IOMUX_PAD(0x504, 0x1B4, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3			IOMUX_PAD(0x504, 0x1B4, 4, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5			IOMUX_PAD(0x504, 0x1B4, 7, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7		IOMUX_PAD(0x508, 0x1B8, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA7__GPIO3_7			IOMUX_PAD(0x508, 0x1B8, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2		IOMUX_PAD(0x508, 0x1B8, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2			IOMUX_PAD(0x508, 0x1B8, 4, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4			IOMUX_PAD(0x508, 0x1B8, 7, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8		IOMUX_PAD(0x50C, 0x1BC, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA8__GPIO3_8			IOMUX_PAD(0x50C, 0x1BC, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1		IOMUX_PAD(0x50C, 0x1BC, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1			IOMUX_PAD(0x50C, 0x1BC, 4, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3			IOMUX_PAD(0x50C, 0x1BC, 7, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9		IOMUX_PAD(0x510, 0x1C0, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA9__GPIO3_9			IOMUX_PAD(0x510, 0x1C0, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0		IOMUX_PAD(0x510, 0x1C0, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0			IOMUX_PAD(0x510, 0x1C0, 4, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2			IOMUX_PAD(0x510, 0x1C0, 7, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10		IOMUX_PAD(0x514, 0x1C4, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA10__GPIO3_10			IOMUX_PAD(0x514, 0x1C4, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15		IOMUX_PAD(0x514, 0x1C4, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN		IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, 0)
+#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1		IOMUX_PAD(0x514, 0x1C4, 7, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11		IOMUX_PAD(0x518, 0x1C8, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA11__GPIO3_11			IOMUX_PAD(0x518, 0x1C8, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2			IOMUX_PAD(0x518, 0x1C8, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC		IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, 0)
+#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12		IOMUX_PAD(0x51C, 0x1CC, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA12__GPIO3_12			IOMUX_PAD(0x51C, 0x1CC, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3			IOMUX_PAD(0x51C, 0x1CC, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC		IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, 0)
+#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13		IOMUX_PAD(0x520, 0x1D0, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA13__GPIO3_13			IOMUX_PAD(0x520, 0x1D0, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS		IOMUX_PAD(0x520, 0x1D0, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK		IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, 0)
+#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14		IOMUX_PAD(0x524, 0x1D4, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA14__GPIO3_14			IOMUX_PAD(0x524, 0x1D4, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS		IOMUX_PAD(0x524, 0x1D4, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK		IOMUX_PAD(0x524, 0x1D4, 4, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15		IOMUX_PAD(0x528, 0x1D8, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA15__GPIO3_15			IOMUX_PAD(0x528, 0x1D8, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1			IOMUX_PAD(0x528, 0x1D8, 3, 0x0, 0, 0)
+#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4			IOMUX_PAD(0x528, 0x1D8, 4, 0x0, 0, 0)
+#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B		IOMUX_PAD(0x52C, 0x1DC, 0, 0x0, 0, 0)
+#define MX53_PAD_NANDF_WE_B__GPIO6_12			IOMUX_PAD(0x52C, 0x1DC, 1, 0x0, 0, 0)
+#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B		IOMUX_PAD(0x530, 0x1E0, 0, 0x0, 0, 0)
+#define MX53_PAD_NANDF_RE_B__GPIO6_13			IOMUX_PAD(0x530, 0x1E0, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT		IOMUX_PAD(0x534, 0x1E4, 0, 0x0, 0, 0)
+#define MX53_PAD_EIM_WAIT__GPIO5_0			IOMUX_PAD(0x534, 0x1E4, 1, 0x0, 0, 0)
+#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B		IOMUX_PAD(0x534, 0x1E4, 2, 0x0, 0, 0)
+#define MX53_PAD_LVDS1_TX3_P__GPIO6_22			IOMUX_PAD(NON_PAD_I, 0x1EC, 0, 0x0, 0, 0)
+#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3		IOMUX_PAD(NON_PAD_I, 0x1EC, 1, 0x0, 0, 0)
+#define MX53_PAD_LVDS1_TX2_P__GPIO6_24			IOMUX_PAD(NON_PAD_I, 0x1F0, 0, 0x0, 0, 0)
+#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2		IOMUX_PAD(NON_PAD_I, 0x1F0, 1, 0x0, 0, 0)
+#define MX53_PAD_LVDS1_CLK_P__GPIO6_26			IOMUX_PAD(NON_PAD_I, 0x1F4, 0, 0x0, 0, 0)
+#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK		IOMUX_PAD(NON_PAD_I, 0x1F4, 1, 0x0, 0, 0)
+#define MX53_PAD_LVDS1_TX1_P__GPIO6_28			IOMUX_PAD(NON_PAD_I, 0x1F8, 0, 0x0, 0, 0)
+#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1		IOMUX_PAD(NON_PAD_I, 0x1F8, 1, 0x0, 0, 0)
+#define MX53_PAD_LVDS1_TX0_P__GPIO6_30			IOMUX_PAD(NON_PAD_I, 0x1FC, 0, 0x0, 0, 0)
+#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0		IOMUX_PAD(NON_PAD_I, 0x1FC, 1, 0x0, 0, 0)
+#define MX53_PAD_LVDS0_TX3_P__GPIO7_22			IOMUX_PAD(NON_PAD_I, 0x200, 0, 0x0, 0, 0)
+#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3		IOMUX_PAD(NON_PAD_I, 0x200, 1, 0x0, 0, 0)
+#define MX53_PAD_LVDS0_CLK_P__GPIO7_24			IOMUX_PAD(NON_PAD_I, 0x204, 0, 0x0, 0, 0)
+#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK		IOMUX_PAD(NON_PAD_I, 0x204, 1, 0x0, 0, 0)
+#define MX53_PAD_LVDS0_TX2_P__GPIO7_26			IOMUX_PAD(NON_PAD_I, 0x208, 0, 0x0, 0, 0)
+#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2		IOMUX_PAD(NON_PAD_I, 0x208, 1, 0x0, 0, 0)
+#define MX53_PAD_LVDS0_TX1_P__GPIO7_28			IOMUX_PAD(NON_PAD_I, 0x20C, 0, 0x0, 0, 0)
+#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1		IOMUX_PAD(NON_PAD_I, 0x20C, 1, 0x0, 0, 0)
+#define MX53_PAD_LVDS0_TX0_P__GPIO7_30			IOMUX_PAD(NON_PAD_I, 0x210, 0, 0x0, 0, 0)
+#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0		IOMUX_PAD(NON_PAD_I, 0x210, 1, 0x0, 0, 0)
+#define MX53_PAD_GPIO_10__GPIO4_0			IOMUX_PAD(0x540, 0x214, 0, 0x0, 0, 0)
+#define MX53_PAD_GPIO_10__OSC32k_32K_OUT		IOMUX_PAD(0x540, 0x214, 1, 0x0, 0, 0)
+#define MX53_PAD_GPIO_11__GPIO4_1			IOMUX_PAD(0x544, 0x218, 0, 0x0, 0, 0)
+#define MX53_PAD_GPIO_12__GPIO4_2			IOMUX_PAD(0x548, 0x21C, 0, 0x0, 0, 0)
+#define MX53_PAD_GPIO_13__GPIO4_3			IOMUX_PAD(0x54C, 0x220, 0, 0x0, 0, 0)
+#define MX53_PAD_GPIO_14__GPIO4_4			IOMUX_PAD(0x550, 0x224, 0, 0x0, 0, 0)
+#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE		IOMUX_PAD(0x5A0, 0x228, 0, 0x0, 0, 0)
+#define MX53_PAD_NANDF_CLE__GPIO6_7			IOMUX_PAD(0x5A0, 0x228, 1, 0x0, 0, 0)
+#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0		IOMUX_PAD(0x5A0, 0x228, 7, 0x0, 0, 0)
+#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE		IOMUX_PAD(0x5A4, 0x22C, 0, 0x0, 0, 0)
+#define MX53_PAD_NANDF_ALE__GPIO6_8			IOMUX_PAD(0x5A4, 0x22C, 1, 0x0, 0, 0)
+#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1		IOMUX_PAD(0x5A4, 0x22C, 7, 0x0, 0, 0)
+#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B		IOMUX_PAD(0x5A8, 0x230, 0, 0x0, 0, 0)
+#define MX53_PAD_NANDF_WP_B__GPIO6_9			IOMUX_PAD(0x5A8, 0x230, 1, 0x0, 0, 0)
+#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2		IOMUX_PAD(0x5A8, 0x230, 7, 0x0, 0, 0)
+#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0		IOMUX_PAD(0x5AC, 0x234, 0, 0x0, 0, 0)
+#define MX53_PAD_NANDF_RB0__GPIO6_10			IOMUX_PAD(0x5AC, 0x234, 1, 0x0, 0, 0)
+#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3		IOMUX_PAD(0x5AC, 0x234, 7, 0x0, 0, 0)
+#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0		IOMUX_PAD(0x5B0, 0x238, 0, 0x0, 0, 0)
+#define MX53_PAD_NANDF_CS0__GPIO6_11			IOMUX_PAD(0x5B0, 0x238, 1, 0x0, 0, 0)
+#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4		IOMUX_PAD(0x5B0, 0x238, 7, 0x0, 0, 0)
+#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1		IOMUX_PAD(0x5B4, 0x23C, 0, 0x0, 0, 0)
+#define MX53_PAD_NANDF_CS1__GPIO6_14			IOMUX_PAD(0x5B4, 0x23C, 1, 0x0, 0, 0)
+#define MX53_PAD_NANDF_CS1__MLB_MLBCLK			IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, 0)
+#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5		IOMUX_PAD(0x5B4, 0x23C, 7, 0x0, 0, 0)
+#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2		IOMUX_PAD(0x5B8, 0x240, 0, 0x0, 0, 0)
+#define MX53_PAD_NANDF_CS2__GPIO6_15			IOMUX_PAD(0x5B8, 0x240, 1, 0x0, 0, 0)
+#define MX53_PAD_NANDF_CS2__IPU_SISG_0			IOMUX_PAD(0x5B8, 0x240, 2, 0x0, 0, 0)
+#define MX53_PAD_NANDF_CS2__ESAI1_TX0			IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, 0)
+#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE		IOMUX_PAD(0x5B8, 0x240, 4, 0x0, 0, 0)
+#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK		IOMUX_PAD(0x5B8, 0x240, 5, 0x0, 0, 0)
+#define MX53_PAD_NANDF_CS2__MLB_MLBSIG			IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, 0)
+#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6		IOMUX_PAD(0x5B8, 0x240, 7, 0x0, 0, 0)
+#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3		IOMUX_PAD(0x5BC, 0x244, 0, 0x0, 0, 0)
+#define MX53_PAD_NANDF_CS3__GPIO6_16			IOMUX_PAD(0x5BC, 0x244, 1, 0x0, 0, 0)
+#define MX53_PAD_NANDF_CS3__IPU_SISG_1			IOMUX_PAD(0x5BC, 0x244, 2, 0x0, 0, 0)
+#define MX53_PAD_NANDF_CS3__ESAI1_TX1			IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, 0)
+#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26		IOMUX_PAD(0x5BC, 0x244, 4, 0x0, 0, 0)
+#define MX53_PAD_NANDF_CS3__MLB_MLBDAT			IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, 0)
+#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7		IOMUX_PAD(0x5BC, 0x244, 7, 0x0, 0, 0)
+#define MX53_PAD_FEC_MDIO__FEC_MDIO			IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, 0)
+#define MX53_PAD_FEC_MDIO__GPIO1_22			IOMUX_PAD(0x5C4, 0x248, 1, 0x0, 0, 0)
+#define MX53_PAD_FEC_MDIO__ESAI1_SCKR			IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, 0)
+#define MX53_PAD_FEC_MDIO__FEC_COL			IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, 0)
+#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2		IOMUX_PAD(0x5C4, 0x248, 4, 0x0, 0, 0)
+#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3	IOMUX_PAD(0x5C4, 0x248, 5, 0x0, 0, 0)
+#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49		IOMUX_PAD(0x5C4, 0x248, 6, 0x0, 0, 0)
+#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK		IOMUX_PAD(0x5C8, 0x24C, 0, 0x0, 0, 0)
+#define MX53_PAD_FEC_REF_CLK__GPIO1_23			IOMUX_PAD(0x5C8, 0x24C, 1, 0x0, 0, 0)
+#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR			IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, 0)
+#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4	IOMUX_PAD(0x5C8, 0x24C, 5, 0x0, 0, 0)
+#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50		IOMUX_PAD(0x5C8, 0x24C, 6, 0x0, 0, 0)
+#define MX53_PAD_FEC_RX_ER__FEC_RX_ER			IOMUX_PAD(0x5CC, 0x250, 0, 0x0, 0, 0)
+#define MX53_PAD_FEC_RX_ER__GPIO1_24			IOMUX_PAD(0x5CC, 0x250, 1, 0x0, 0, 0)
+#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR			IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, 0)
+#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK			IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, 0)
+#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3		IOMUX_PAD(0x5CC, 0x250, 4, 0x0, 0, 0)
+#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV			IOMUX_PAD(0x5D0, 0x254, 0, 0x0, 0, 0)
+#define MX53_PAD_FEC_CRS_DV__GPIO1_25			IOMUX_PAD(0x5D0, 0x254, 1, 0x0, 0, 0)
+#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT			IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, 0)
+#define MX53_PAD_FEC_RXD1__FEC_RDATA_1			IOMUX_PAD(0x5D4, 0x258, 0, 0x0, 0, 0)
+#define MX53_PAD_FEC_RXD1__GPIO1_26			IOMUX_PAD(0x5D4, 0x258, 1, 0x0, 0, 0)
+#define MX53_PAD_FEC_RXD1__ESAI1_FST			IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, 0)
+#define MX53_PAD_FEC_RXD1__MLB_MLBSIG			IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, 0)
+#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1		IOMUX_PAD(0x5D4, 0x258, 4, 0x0, 0, 0)
+#define MX53_PAD_FEC_RXD0__FEC_RDATA_0			IOMUX_PAD(0x5D8, 0x25C, 0, 0x0, 0, 0)
+#define MX53_PAD_FEC_RXD0__GPIO1_27			IOMUX_PAD(0x5D8, 0x25C, 1, 0x0, 0, 0)
+#define MX53_PAD_FEC_RXD0__ESAI1_HCKT			IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, 0)
+#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT		IOMUX_PAD(0x5D8, 0x25C, 3, 0x0, 0, 0)
+#define MX53_PAD_FEC_TX_EN__FEC_TX_EN			IOMUX_PAD(0x5DC, 0x260, 0, 0x0, 0, 0)
+#define MX53_PAD_FEC_TX_EN__GPIO1_28			IOMUX_PAD(0x5DC, 0x260, 1, 0x0, 0, 0)
+#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2		IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, 0)
+#define MX53_PAD_FEC_TXD1__FEC_TDATA_1			IOMUX_PAD(0x5E0, 0x264, 0, 0x0, 0, 0)
+#define MX53_PAD_FEC_TXD1__GPIO1_29			IOMUX_PAD(0x5E0, 0x264, 1, 0x0, 0, 0)
+#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3		IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, 0)
+#define MX53_PAD_FEC_TXD1__MLB_MLBCLK			IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, 0)
+#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK		IOMUX_PAD(0x5E0, 0x264, 4, 0x0, 0, 0)
+#define MX53_PAD_FEC_TXD0__FEC_TDATA_0			IOMUX_PAD(0x5E4, 0x268, 0, 0x0, 0, 0)
+#define MX53_PAD_FEC_TXD0__GPIO1_30			IOMUX_PAD(0x5E4, 0x268, 1, 0x0, 0, 0)
+#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1		IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, 0)
+#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0		IOMUX_PAD(0x5E4, 0x268, 7, 0x0, 0, 0)
+#define MX53_PAD_FEC_MDC__FEC_MDC			IOMUX_PAD(0x5E8, 0x26C, 0, 0x0, 0, 0)
+#define MX53_PAD_FEC_MDC__GPIO1_31			IOMUX_PAD(0x5E8, 0x26C, 1, 0x0, 0, 0)
+#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0			IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, 0)
+#define MX53_PAD_FEC_MDC__MLB_MLBDAT			IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, 0)
+#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG	IOMUX_PAD(0x5E8, 0x26C, 4, 0x0, 0, 0)
+#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1		IOMUX_PAD(0x5E8, 0x26C, 7, 0x0, 0, 0)
+#define MX53_PAD_PATA_DIOW__PATA_DIOW			IOMUX_PAD(0x5F0, 0x270, 0, 0x0, 0, 0)
+#define MX53_PAD_PATA_DIOW__GPIO6_17			IOMUX_PAD(0x5F0, 0x270, 1, 0x0, 0, 0)
+#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX		IOMUX_PAD(0x5F0, 0x270, 3, 0x878, 2, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2		IOMUX_PAD(0x5F0, 0x270, 7, 0x0, 0, 0)
+#define MX53_PAD_PATA_DMACK__PATA_DMACK			IOMUX_PAD(0x5F4, 0x274, 0, 0x0, 0, 0)
+#define MX53_PAD_PATA_DMACK__GPIO6_18			IOMUX_PAD(0x5F4, 0x274, 1, 0x0, 0, 0)
+#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX		IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3		IOMUX_PAD(0x5F4, 0x274, 7, 0x0, 0, 0)
+#define MX53_PAD_PATA_DMARQ__PATA_DMARQ			IOMUX_PAD(0x5F8, 0x278, 0, 0x0, 0, 0)
+#define MX53_PAD_PATA_DMARQ__GPIO7_0			IOMUX_PAD(0x5F8, 0x278, 1, 0x0, 0, 0)
+#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX		IOMUX_PAD(0x5F8, 0x278, 3, 0x880, 2, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0		IOMUX_PAD(0x5F8, 0x278, 5, 0x0, 0, 0)
+#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4		IOMUX_PAD(0x5F8, 0x278, 7, 0x0, 0, 0)
+#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN		IOMUX_PAD(0x5FC, 0x27C, 0, 0x0, 0, 0)
+#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1		IOMUX_PAD(0x5FC, 0x27C, 1, 0x0, 0, 0)
+#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX		IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1		IOMUX_PAD(0x5FC, 0x27C, 5, 0x0, 0, 0)
+#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5	IOMUX_PAD(0x5FC, 0x27C, 7, 0x0, 0, 0)
+#define MX53_PAD_PATA_INTRQ__PATA_INTRQ			IOMUX_PAD(0x600, 0x280, 0, 0x0, 0, 0)
+#define MX53_PAD_PATA_INTRQ__GPIO7_2			IOMUX_PAD(0x600, 0x280, 1, 0x0, 0, 0)
+#define MX53_PAD_PATA_INTRQ__UART2_CTS			IOMUX_PAD(0x600, 0x280, 3, 0x87C, 2, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN			IOMUX_PAD(0x600, 0x280, 4, 0x0, 0, 0)
+#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2		IOMUX_PAD(0x600, 0x280, 5, 0x0, 0, 0)
+#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6		IOMUX_PAD(0x600, 0x280, 7, 0x0, 0, 0)
+#define MX53_PAD_PATA_DIOR__PATA_DIOR			IOMUX_PAD(0x604, 0x284, 0, 0x0, 0, 0)
+#define MX53_PAD_PATA_DIOR__GPIO7_3			IOMUX_PAD(0x604, 0x284, 1, 0x0, 0, 0)
+#define MX53_PAD_PATA_DIOR__UART2_RTS			IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_DIOR__CAN1_RXCAN			IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, 0)
+#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7		IOMUX_PAD(0x604, 0x284, 7, 0x0, 0, 0)
+#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B	IOMUX_PAD(0x608, 0x288, 0, 0x0, 0, 0)
+#define MX53_PAD_PATA_RESET_B__GPIO7_4			IOMUX_PAD(0x608, 0x288, 1, 0x0, 0, 0)
+#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD		IOMUX_PAD(0x608, 0x288, 2, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_RESET_B__UART1_CTS		IOMUX_PAD(0x608, 0x288, 3, 0x874, 2, 0)
+#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN		IOMUX_PAD(0x608, 0x288, 4, 0x0, 0, 0)
+#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0	IOMUX_PAD(0x608, 0x288, 7, 0x0, 0, 0)
+#define MX53_PAD_PATA_IORDY__PATA_IORDY			IOMUX_PAD(0x60C, 0x28C, 0, 0x0, 0, 0)
+#define MX53_PAD_PATA_IORDY__GPIO7_5			IOMUX_PAD(0x60C, 0x28C, 1, 0x0, 0, 0)
+#define MX53_PAD_PATA_IORDY__ESDHC3_CLK			IOMUX_PAD(0x60C, 0x28C, 2, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_IORDY__UART1_RTS			IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, 0)
+#define MX53_PAD_PATA_IORDY__CAN2_RXCAN			IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, 0)
+#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1		IOMUX_PAD(0x60C, 0x28C, 7, 0x0, 0, 0)
+#define MX53_PAD_PATA_DA_0__PATA_DA_0			IOMUX_PAD(0x610, 0x290, 0, 0x0, 0, 0)
+#define MX53_PAD_PATA_DA_0__GPIO7_6			IOMUX_PAD(0x610, 0x290, 1, 0x0, 0, 0)
+#define MX53_PAD_PATA_DA_0__ESDHC3_RST			IOMUX_PAD(0x610, 0x290, 2, 0x0, 0, 0)
+#define MX53_PAD_PATA_DA_0__OWIRE_LINE			IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, 0)
+#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2		IOMUX_PAD(0x610, 0x290, 7, 0x0, 0, 0)
+#define MX53_PAD_PATA_DA_1__PATA_DA_1			IOMUX_PAD(0x614, 0x294, 0, 0x0, 0, 0)
+#define MX53_PAD_PATA_DA_1__GPIO7_7			IOMUX_PAD(0x614, 0x294, 1, 0x0, 0, 0)
+#define MX53_PAD_PATA_DA_1__ESDHC4_CMD			IOMUX_PAD(0x614, 0x294, 2, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DA_1__UART3_CTS			IOMUX_PAD(0x614, 0x294, 4, 0x884, 4, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3		IOMUX_PAD(0x614, 0x294, 7, 0x0, 0, 0)
+#define MX53_PAD_PATA_DA_2__PATA_DA_2			IOMUX_PAD(0x618, 0x298, 0, 0x0, 0, 0)
+#define MX53_PAD_PATA_DA_2__GPIO7_8			IOMUX_PAD(0x618, 0x298, 1, 0x0, 0, 0)
+#define MX53_PAD_PATA_DA_2__ESDHC4_CLK			IOMUX_PAD(0x618, 0x298, 2, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DA_2__UART3_RTS			IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4		IOMUX_PAD(0x618, 0x298, 7, 0x0, 0, 0)
+#define MX53_PAD_PATA_CS_0__PATA_CS_0			IOMUX_PAD(0x61C, 0x29C, 0, 0x0, 0, 0)
+#define MX53_PAD_PATA_CS_0__GPIO7_9			IOMUX_PAD(0x61C, 0x29C, 1, 0x0, 0, 0)
+#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX		IOMUX_PAD(0x61C, 0x29C, 4, 0x888, 2, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5		IOMUX_PAD(0x61C, 0x29C, 7, 0x0, 0, 0)
+#define MX53_PAD_PATA_CS_1__PATA_CS_1			IOMUX_PAD(0x620, 0x2A0, 0, 0x0, 0, 0)
+#define MX53_PAD_PATA_CS_1__GPIO7_10			IOMUX_PAD(0x620, 0x2A0, 1, 0x0, 0, 0)
+#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX		IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL)
+#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6		IOMUX_PAD(0x620, 0x2A0, 7, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA0__PATA_DATA_0		IOMUX_PAD(0x628, 0x2A4, 0, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA0__GPIO2_0			IOMUX_PAD(0x628, 0x2A4, 1, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0		IOMUX_PAD(0x628, 0x2A4, 3, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4		IOMUX_PAD(0x628, 0x2A4, 4, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0	IOMUX_PAD(0x628, 0x2A4, 5, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0		IOMUX_PAD(0x628, 0x2A4, 6, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7		IOMUX_PAD(0x628, 0x2A4, 7, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA1__PATA_DATA_1		IOMUX_PAD(0x62C, 0x2A8, 0, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA1__GPIO2_1			IOMUX_PAD(0x62C, 0x2A8, 1, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1		IOMUX_PAD(0x62C, 0x2A8, 3, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5		IOMUX_PAD(0x62C, 0x2A8, 4, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1	IOMUX_PAD(0x62C, 0x2A8, 5, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1		IOMUX_PAD(0x62C, 0x2A8, 6, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA2__PATA_DATA_2		IOMUX_PAD(0x630, 0x2AC, 0, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA2__GPIO2_2			IOMUX_PAD(0x630, 0x2AC, 1, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2		IOMUX_PAD(0x630, 0x2AC, 3, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6		IOMUX_PAD(0x630, 0x2AC, 4, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2	IOMUX_PAD(0x630, 0x2AC, 5, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2		IOMUX_PAD(0x630, 0x2AC, 6, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA3__PATA_DATA_3		IOMUX_PAD(0x634, 0x2B0, 0, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA3__GPIO2_3			IOMUX_PAD(0x634, 0x2B0, 1, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3		IOMUX_PAD(0x634, 0x2B0, 3, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7		IOMUX_PAD(0x634, 0x2B0, 4, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3	IOMUX_PAD(0x634, 0x2B0, 5, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3		IOMUX_PAD(0x634, 0x2B0, 6, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA4__PATA_DATA_4		IOMUX_PAD(0x638, 0x2B4, 0, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA4__GPIO2_4			IOMUX_PAD(0x638, 0x2B4, 1, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4		IOMUX_PAD(0x638, 0x2B4, 3, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4		IOMUX_PAD(0x638, 0x2B4, 4, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4	IOMUX_PAD(0x638, 0x2B4, 5, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4		IOMUX_PAD(0x638, 0x2B4, 6, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA5__PATA_DATA_5		IOMUX_PAD(0x63C, 0x2B8, 0, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA5__GPIO2_5			IOMUX_PAD(0x63C, 0x2B8, 1, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5		IOMUX_PAD(0x63C, 0x2B8, 3, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5		IOMUX_PAD(0x63C, 0x2B8, 4, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5	IOMUX_PAD(0x63C, 0x2B8, 5, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5		IOMUX_PAD(0x63C, 0x2B8, 6, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA6__PATA_DATA_6		IOMUX_PAD(0x640, 0x2BC, 0, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA6__GPIO2_6			IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6		IOMUX_PAD(0x640, 0x2BC, 3, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6		IOMUX_PAD(0x640, 0x2BC, 4, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6	IOMUX_PAD(0x640, 0x2BC, 5, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6		IOMUX_PAD(0x640, 0x2BC, 6, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA7__PATA_DATA_7		IOMUX_PAD(0x644, 0x2C0, 0, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA7__GPIO2_7			IOMUX_PAD(0x644, 0x2C0, 1, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7		IOMUX_PAD(0x644, 0x2C0, 3, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7		IOMUX_PAD(0x644, 0x2C0, 4, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7	IOMUX_PAD(0x644, 0x2C0, 5, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7		IOMUX_PAD(0x644, 0x2C0, 6, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA8__PATA_DATA_8		IOMUX_PAD(0x648, 0x2C4, 0, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA8__GPIO2_8			IOMUX_PAD(0x648, 0x2C4, 1, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4		IOMUX_PAD(0x648, 0x2C4, 2, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8		IOMUX_PAD(0x648, 0x2C4, 3, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0		IOMUX_PAD(0x648, 0x2C4, 4, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8	IOMUX_PAD(0x648, 0x2C4, 5, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8		IOMUX_PAD(0x648, 0x2C4, 6, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA9__PATA_DATA_9		IOMUX_PAD(0x64C, 0x2C8, 0, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA9__GPIO2_9			IOMUX_PAD(0x64C, 0x2C8, 1, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5		IOMUX_PAD(0x64C, 0x2C8, 2, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9		IOMUX_PAD(0x64C, 0x2C8, 3, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1		IOMUX_PAD(0x64C, 0x2C8, 4, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9	IOMUX_PAD(0x64C, 0x2C8, 5, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9		IOMUX_PAD(0x64C, 0x2C8, 6, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA10__PATA_DATA_10		IOMUX_PAD(0x650, 0x2CC, 0, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA10__GPIO2_10			IOMUX_PAD(0x650, 0x2CC, 1, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6		IOMUX_PAD(0x650, 0x2CC, 2, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10		IOMUX_PAD(0x650, 0x2CC, 3, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2		IOMUX_PAD(0x650, 0x2CC, 4, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10	IOMUX_PAD(0x650, 0x2CC, 5, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10		IOMUX_PAD(0x650, 0x2CC, 6, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA11__PATA_DATA_11		IOMUX_PAD(0x654, 0x2D0, 0, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA11__GPIO2_11			IOMUX_PAD(0x654, 0x2D0, 1, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7		IOMUX_PAD(0x654, 0x2D0, 2, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11		IOMUX_PAD(0x654, 0x2D0, 3, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3		IOMUX_PAD(0x654, 0x2D0, 4, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11	IOMUX_PAD(0x654, 0x2D0, 5, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11		IOMUX_PAD(0x654, 0x2D0, 6, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA12__PATA_DATA_12		IOMUX_PAD(0x658, 0x2D4, 0, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA12__GPIO2_12			IOMUX_PAD(0x658, 0x2D4, 1, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4		IOMUX_PAD(0x658, 0x2D4, 2, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12		IOMUX_PAD(0x658, 0x2D4, 3, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0		IOMUX_PAD(0x658, 0x2D4, 4, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12	IOMUX_PAD(0x658, 0x2D4, 5, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12		IOMUX_PAD(0x658, 0x2D4, 6, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA13__PATA_DATA_13		IOMUX_PAD(0x65C, 0x2D8, 0, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA13__GPIO2_13			IOMUX_PAD(0x65C, 0x2D8, 1, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5		IOMUX_PAD(0x65C, 0x2D8, 2, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13		IOMUX_PAD(0x65C, 0x2D8, 3, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1		IOMUX_PAD(0x65C, 0x2D8, 4, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13	IOMUX_PAD(0x65C, 0x2D8, 5, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13		IOMUX_PAD(0x65C, 0x2D8, 6, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA14__PATA_DATA_14		IOMUX_PAD(0x660, 0x2DC, 0, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA14__GPIO2_14			IOMUX_PAD(0x660, 0x2DC, 1, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6		IOMUX_PAD(0x660, 0x2DC, 2, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14		IOMUX_PAD(0x660, 0x2DC, 3, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2		IOMUX_PAD(0x660, 0x2DC, 4, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14	IOMUX_PAD(0x660, 0x2DC, 5, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14		IOMUX_PAD(0x660, 0x2DC, 6, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA15__PATA_DATA_15		IOMUX_PAD(0x664, 0x2E0, 0, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA15__GPIO2_15			IOMUX_PAD(0x664, 0x2E0, 1, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7		IOMUX_PAD(0x664, 0x2E0, 2, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15		IOMUX_PAD(0x664, 0x2E0, 3, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3		IOMUX_PAD(0x664, 0x2E0, 4, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15	IOMUX_PAD(0x664, 0x2E0, 5, 0x0, 0, 0)
+#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15		IOMUX_PAD(0x664, 0x2E0, 6, 0x0, 0, 0)
+#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0			IOMUX_PAD(0x66C, 0x2E4, 0, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD1_DATA0__GPIO1_16			IOMUX_PAD(0x66C, 0x2E4, 1, 0x0, 0, 0)
+#define MX53_PAD_SD1_DATA0__GPT_CAPIN1			IOMUX_PAD(0x66C, 0x2E4, 3, 0x0, 0, 0)
+#define MX53_PAD_SD1_DATA0__CSPI_MISO			IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, 0)
+#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP		IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, 0)
+#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1			IOMUX_PAD(0x670, 0x2E8, 0, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD1_DATA1__GPIO1_17			IOMUX_PAD(0x670, 0x2E8, 1, 0x0, 0, 0)
+#define MX53_PAD_SD1_DATA1__GPT_CAPIN2			IOMUX_PAD(0x670, 0x2E8, 3, 0x0, 0, 0)
+#define MX53_PAD_SD1_DATA1__CSPI_SS0			IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, 0)
+#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP		IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, 0)
+#define MX53_PAD_SD1_CMD__ESDHC1_CMD			IOMUX_PAD(0x674, 0x2EC,	IOMUX_CONFIG_SION, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD1_CMD__GPIO1_18			IOMUX_PAD(0x674, 0x2EC, 1, 0x0, 0, 0)
+#define MX53_PAD_SD1_CMD__GPT_CMPOUT1			IOMUX_PAD(0x674, 0x2EC, 3, 0x0, 0, 0)
+#define MX53_PAD_SD1_CMD__CSPI_MOSI			IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, 0)
+#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP			IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, 0)
+#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2			IOMUX_PAD(0x678, 0x2F0, 0, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD1_DATA2__GPIO1_19			IOMUX_PAD(0x678, 0x2F0, 1, 0x0, 0, 0)
+#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2			IOMUX_PAD(0x678, 0x2F0, 2, 0x0, 0, 0)
+#define MX53_PAD_SD1_DATA2__PWM2_PWMO			IOMUX_PAD(0x678, 0x2F0, 3, 0x0, 0, 0)
+#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B		IOMUX_PAD(0x678, 0x2F0, 4, 0x0, 0, 0)
+#define MX53_PAD_SD1_DATA2__CSPI_SS1			IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, 0)
+#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB	IOMUX_PAD(0x678, 0x2F0, 6, 0x0, 0, 0)
+#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP		IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, 0)
+#define MX53_PAD_SD1_CLK__ESDHC1_CLK			IOMUX_PAD(0x67C, 0x2F4, 0, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD1_CLK__GPIO1_20			IOMUX_PAD(0x67C, 0x2F4, 1, 0x0, 0, 0)
+#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT		IOMUX_PAD(0x67C, 0x2F4, 2, 0x0, 0, 0)
+#define MX53_PAD_SD1_CLK__GPT_CLKIN			IOMUX_PAD(0x67C, 0x2F4, 3, 0x0, 0, 0)
+#define MX53_PAD_SD1_CLK__CSPI_SCLK			IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, 0)
+#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0		IOMUX_PAD(0x67C, 0x2F4, 7, 0x0, 0, 0)
+#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3			IOMUX_PAD(0x680, 0x2F8, 0, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD1_DATA3__GPIO1_21			IOMUX_PAD(0x680, 0x2F8, 1, 0x0, 0, 0)
+#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3			IOMUX_PAD(0x680, 0x2F8, 2, 0x0, 0, 0)
+#define MX53_PAD_SD1_DATA3__PWM1_PWMO			IOMUX_PAD(0x680, 0x2F8, 3, 0x0, 0, 0)
+#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B		IOMUX_PAD(0x680, 0x2F8, 4, 0x0, 0, 0)
+#define MX53_PAD_SD1_DATA3__CSPI_SS2			IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, 0)
+#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB	IOMUX_PAD(0x680, 0x2F8, 6, 0x0, 0, 0)
+#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1		IOMUX_PAD(0x680, 0x2F8, 7, 0x0, 0, 0)
+#define MX53_PAD_SD2_CLK__ESDHC2_CLK			IOMUX_PAD(0x688, 0x2FC, 0, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD2_CLK__GPIO1_10			IOMUX_PAD(0x688, 0x2FC, 1, 0x0, 0, 0)
+#define MX53_PAD_SD2_CLK__KPP_COL_5			IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, 0)
+#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS		IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, 0)
+#define MX53_PAD_SD2_CLK__CSPI_SCLK			IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, 0)
+#define MX53_PAD_SD2_CLK__SCC_RANDOM_V			IOMUX_PAD(0x688, 0x2FC, 7, 0x0, 0, 0)
+#define MX53_PAD_SD2_CMD__ESDHC2_CMD			IOMUX_PAD(0x68C, 0x300, 0, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD2_CMD__GPIO1_11			IOMUX_PAD(0x68C, 0x300, 1, 0x0, 0, 0)
+#define MX53_PAD_SD2_CMD__KPP_ROW_5			IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, 0)
+#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC		IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, 0)
+#define MX53_PAD_SD2_CMD__CSPI_MOSI			IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, 0)
+#define MX53_PAD_SD2_CMD__SCC_RANDOM			IOMUX_PAD(0x68C, 0x300, 7, 0x0, 0, 0)
+#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3			IOMUX_PAD(0x690, 0x304, 0, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD2_DATA3__GPIO1_12			IOMUX_PAD(0x690, 0x304, 1, 0x0, 0, 0)
+#define MX53_PAD_SD2_DATA3__KPP_COL_6			IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, 0)
+#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC		IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, 0)
+#define MX53_PAD_SD2_DATA3__CSPI_SS2			IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, 0)
+#define MX53_PAD_SD2_DATA3__SJC_DONE			IOMUX_PAD(0x690, 0x304, 7, 0x0, 0, 0)
+#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2			IOMUX_PAD(0x694, 0x308, 0, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD2_DATA2__GPIO1_13			IOMUX_PAD(0x694, 0x308, 1, 0x0, 0, 0)
+#define MX53_PAD_SD2_DATA2__KPP_ROW_6			IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, 0)
+#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD		IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, 0)
+#define MX53_PAD_SD2_DATA2__CSPI_SS1			IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, 0)
+#define MX53_PAD_SD2_DATA2__SJC_FAIL			IOMUX_PAD(0x694, 0x308, 7, 0x0, 0, 0)
+#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1			IOMUX_PAD(0x698, 0x30C, 0, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD2_DATA1__GPIO1_14			IOMUX_PAD(0x698, 0x30C, 1, 0x0, 0, 0)
+#define MX53_PAD_SD2_DATA1__KPP_COL_7			IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, 0)
+#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS		IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, 0)
+#define MX53_PAD_SD2_DATA1__CSPI_SS0			IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, 0)
+#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO		IOMUX_PAD(0x698, 0x30C, 7, 0x0, 0, 0)
+#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0			IOMUX_PAD(0x69C, 0x310, 0, 0x0, 0, MX53_SDHC_PAD_CTRL)
+#define MX53_PAD_SD2_DATA0__GPIO1_15			IOMUX_PAD(0x69C, 0x310, 1, 0x0, 0, 0)
+#define MX53_PAD_SD2_DATA0__KPP_ROW_7			IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, 0)
+#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD		IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, 0)
+#define MX53_PAD_SD2_DATA0__CSPI_MISO			IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, 0)
+#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT		IOMUX_PAD(0x69C, 0x310, 7, 0x0, 0, 0)
+#define MX53_PAD_GPIO_0__CCM_CLKO			IOMUX_PAD(0x6A4, 0x314, 0, 0x0, 0, 0)
+#define MX53_PAD_GPIO_0__GPIO1_0			IOMUX_PAD(0x6A4, 0x314, 1, 0x0, 0, 0)
+#define MX53_PAD_GPIO_0__KPP_COL_5			IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, 0)
+#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK		IOMUX_PAD(0x6A4, 0x314, 3, 0x0, 0, 0)
+#define MX53_PAD_GPIO_0__EPIT1_EPITO			IOMUX_PAD(0x6A4, 0x314, 4, 0x0, 0, 0)
+#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB			IOMUX_PAD(0x6A4, 0x314, 5, 0x0, 0, 0)
+#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR		IOMUX_PAD(0x6A4, 0x314, 6, 0x0, 0, 0)
+#define MX53_PAD_GPIO_0__CSU_TD				IOMUX_PAD(0x6A4, 0x314, 7, 0x0, 0, 0)
+#define MX53_PAD_GPIO_1__ESAI1_SCKR			IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, 0)
+#define MX53_PAD_GPIO_1__GPIO1_1			IOMUX_PAD(0x6A8, 0x318, 1, 0x0, 0, 0)
+#define MX53_PAD_GPIO_1__KPP_ROW_5			IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, 0)
+#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK		IOMUX_PAD(0x6A8, 0x318, 3, 0x0, 0, 0)
+#define MX53_PAD_GPIO_1__PWM2_PWMO			IOMUX_PAD(0x6A8, 0x318, 4, 0x0, 0, 0)
+#define MX53_PAD_GPIO_1__WDOG2_WDOG_B			IOMUX_PAD(0x6A8, 0x318, 5, 0x0, 0, 0)
+#define MX53_PAD_GPIO_1__ESDHC1_CD			IOMUX_PAD(0x6A8, 0x318, 6, 0x0, 0, 0)
+#define MX53_PAD_GPIO_1__SRC_TESTER_ACK			IOMUX_PAD(0x6A8, 0x318, 7, 0x0, 0, 0)
+#define MX53_PAD_GPIO_9__ESAI1_FSR			IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, 0)
+#define MX53_PAD_GPIO_9__GPIO1_9			IOMUX_PAD(0x6AC, 0x31C, 1, 0x0, 0, 0)
+#define MX53_PAD_GPIO_9__KPP_COL_6			IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, 0)
+#define MX53_PAD_GPIO_9__CCM_REF_EN_B			IOMUX_PAD(0x6AC, 0x31C, 3, 0x0, 0, 0)
+#define MX53_PAD_GPIO_9__PWM1_PWMO			IOMUX_PAD(0x6AC, 0x31C, 4, 0x0, 0, 0)
+#define MX53_PAD_GPIO_9__WDOG1_WDOG_B			IOMUX_PAD(0x6AC, 0x31C, 5, 0x0, 0, 0)
+#define MX53_PAD_GPIO_9__ESDHC1_WP			IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, 0)
+#define MX53_PAD_GPIO_9__SCC_FAIL_STATE			IOMUX_PAD(0x6AC, 0x31C, 7, 0x0, 0, 0)
+#define MX53_PAD_GPIO_3__ESAI1_HCKR			IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, 0)
+#define MX53_PAD_GPIO_3__GPIO1_3			IOMUX_PAD(0x6B0, 0x320, 1, 0x0, 0, 0)
+#define MX53_PAD_GPIO_3__I2C3_SCL			IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, 0)
+#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN			IOMUX_PAD(0x6B0, 0x320, 3, 0x0, 0, 0)
+#define MX53_PAD_GPIO_3__CCM_CLKO2			IOMUX_PAD(0x6B0, 0x320, 4, 0x0, 0, 0)
+#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0	IOMUX_PAD(0x6B0, 0x320, 5, 0x0, 0, 0)
+#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC		IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, 0)
+#define MX53_PAD_GPIO_3__MLB_MLBCLK			IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, 0)
+#define MX53_PAD_GPIO_6__ESAI1_SCKT			IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, 0)
+#define MX53_PAD_GPIO_6__GPIO1_6			IOMUX_PAD(0x6B4, 0x324, 1, 0x0, 0, 0)
+#define MX53_PAD_GPIO_6__I2C3_SDA			IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, 0)
+#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0			IOMUX_PAD(0x6B4, 0x324, 3, 0x0, 0, 0)
+#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB		IOMUX_PAD(0x6B4, 0x324, 4, 0x0, 0, 0)
+#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1	IOMUX_PAD(0x6B4, 0x324, 5, 0x0, 0, 0)
+#define MX53_PAD_GPIO_6__ESDHC2_LCTL			IOMUX_PAD(0x6B4, 0x324, 6, 0x0, 0, 0)
+#define MX53_PAD_GPIO_6__MLB_MLBSIG			IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, 0)
+#define MX53_PAD_GPIO_2__ESAI1_FST			IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, 0)
+#define MX53_PAD_GPIO_2__GPIO1_2			IOMUX_PAD(0x6B8, 0x328, 1, 0x0, 0, 0)
+#define MX53_PAD_GPIO_2__KPP_ROW_6			IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, 0)
+#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1			IOMUX_PAD(0x6B8, 0x328, 3, 0x0, 0, 0)
+#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0		IOMUX_PAD(0x6B8, 0x328, 4, 0x0, 0, 0)
+#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2	IOMUX_PAD(0x6B8, 0x328, 5, 0x0, 0, 0)
+#define MX53_PAD_GPIO_2__ESDHC2_WP			IOMUX_PAD(0x6B8, 0x328, 6, 0x0, 0, 0)
+#define MX53_PAD_GPIO_2__MLB_MLBDAT			IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, 0)
+#define MX53_PAD_GPIO_4__ESAI1_HCKT			IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, 0)
+#define MX53_PAD_GPIO_4__GPIO1_4			IOMUX_PAD(0x6BC, 0x32C, 1, 0x0, 0, 0)
+#define MX53_PAD_GPIO_4__KPP_COL_7			IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, 0)
+#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2			IOMUX_PAD(0x6BC, 0x32C, 3, 0x0, 0, 0)
+#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1		IOMUX_PAD(0x6BC, 0x32C, 4, 0x0, 0, 0)
+#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3	IOMUX_PAD(0x6BC, 0x32C, 5, 0x0, 0, 0)
+#define MX53_PAD_GPIO_4__ESDHC2_CD			IOMUX_PAD(0x6BC, 0x32C, 6, 0x0, 0, 0)
+#define MX53_PAD_GPIO_4__SCC_SEC_STATE			IOMUX_PAD(0x6BC, 0x32C, 7, 0x0, 0, 0)
+#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3			IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, 0)
+#define MX53_PAD_GPIO_5__GPIO1_5			IOMUX_PAD(0x6C0, 0x330, 1, 0x0, 0, 0)
+#define MX53_PAD_GPIO_5__KPP_ROW_7			IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, 0)
+#define MX53_PAD_GPIO_5__CCM_CLKO			IOMUX_PAD(0x6C0, 0x330, 3, 0x0, 0, 0)
+#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2		IOMUX_PAD(0x6C0, 0x330, 4, 0x0, 0, 0)
+#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4	IOMUX_PAD(0x6C0, 0x330, 5, 0x0, 0, 0)
+#define MX53_PAD_GPIO_5__I2C3_SCL			IOMUX_PAD(0x6C0, 0x330, 6, 0x824, 2, 0)
+#define MX53_PAD_GPIO_5__CCM_PLL1_BYP			IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, 0)
+#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1			IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, 0)
+#define MX53_PAD_GPIO_7__GPIO1_7			IOMUX_PAD(0x6C4, 0x334, 1, 0x0, 0, 0)
+#define MX53_PAD_GPIO_7__EPIT1_EPITO			IOMUX_PAD(0x6C4, 0x334, 2, 0x0, 0, 0)
+#define MX53_PAD_GPIO_7__CAN1_TXCAN			IOMUX_PAD(0x6C4, 0x334, 3, 0x0, 0, 0)
+#define MX53_PAD_GPIO_7__UART2_TXD_MUX			IOMUX_PAD(0x6C4, 0x334, 4, 0x880, 4, 0)
+#define MX53_PAD_GPIO_7__FIRI_RXD			IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, 0)
+#define MX53_PAD_GPIO_7__SPDIF_PLOCK			IOMUX_PAD(0x6C4, 0x334, 6, 0x0, 0, 0)
+#define MX53_PAD_GPIO_7__CCM_PLL2_BYP			IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, 0)
+#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0			IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, 0)
+#define MX53_PAD_GPIO_8__GPIO1_8			IOMUX_PAD(0x6C8, 0x338, 1, 0x0, 0, 0)
+#define MX53_PAD_GPIO_8__EPIT2_EPITO			IOMUX_PAD(0x6C8, 0x338, 2, 0x0, 0, 0)
+#define MX53_PAD_GPIO_8__CAN1_RXCAN			IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 3, 0)
+#define MX53_PAD_GPIO_8__UART2_RXD_MUX			IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, 0)
+#define MX53_PAD_GPIO_8__FIRI_TXD			IOMUX_PAD(0x6C8, 0x338, 5, 0x0, 0, 0)
+#define MX53_PAD_GPIO_8__SPDIF_SRCLK			IOMUX_PAD(0x6C8, 0x338, 6, 0x0, 0, 0)
+#define MX53_PAD_GPIO_8__CCM_PLL3_BYP			IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, 0)
+#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2			IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, 0)
+#define MX53_PAD_GPIO_16__GPIO7_11			IOMUX_PAD(0x6CC, 0x33C, 1, 0x0, 0, 0)
+#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT		IOMUX_PAD(0x6CC, 0x33C, 2, 0x0, 0, 0)
+#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1		IOMUX_PAD(0x6CC, 0x33C, 4, 0x0, 0, 0)
+#define MX53_PAD_GPIO_16__SPDIF_IN1			IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, 0)
+#define MX53_PAD_GPIO_16__I2C3_SDA			IOMUX_PAD(0x6CC, 0x33C, 6 | IOMUX_CONFIG_SION, 0x828, 2, 0)
+#define MX53_PAD_GPIO_16__SJC_DE_B			IOMUX_PAD(0x6CC, 0x33C, 7, 0x0, 0, 0)
+#define MX53_PAD_GPIO_17__ESAI1_TX0			IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, 0)
+#define MX53_PAD_GPIO_17__GPIO7_12			IOMUX_PAD(0x6D0, 0x340, 1, 0x0, 0, 0)
+#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0		IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, 0)
+#define MX53_PAD_GPIO_17__GPC_PMIC_RDY			IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, 0)
+#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG		IOMUX_PAD(0x6D0, 0x340, 4, 0x0, 0, 0)
+#define MX53_PAD_GPIO_17__SPDIF_OUT1			IOMUX_PAD(0x6D0, 0x340, 5, 0x0, 0, 0)
+#define MX53_PAD_GPIO_17__IPU_SNOOP2			IOMUX_PAD(0x6D0, 0x340, 6, 0x0, 0, 0)
+#define MX53_PAD_GPIO_17__SJC_JTAG_ACT			IOMUX_PAD(0x6D0, 0x340, 7, 0x0, 0, 0)
+#define MX53_PAD_GPIO_18__ESAI1_TX1			IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, 0)
+#define MX53_PAD_GPIO_18__GPIO7_13			IOMUX_PAD(0x6D4, 0x344, 1, 0x0, 0, 0)
+#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1		IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, 0)
+#define MX53_PAD_GPIO_18__OWIRE_LINE			IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, 0)
+#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG	IOMUX_PAD(0x6D4, 0x344, 4, 0x0, 0, 0)
+#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK		IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, 0)
+#define MX53_PAD_GPIO_18__ESDHC1_LCTL			IOMUX_PAD(0x6D4, 0x344, 6, 0x0, 0, 0)
+#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST		IOMUX_PAD(0x6D4, 0x344, 7, 0x0, 0, 0)
+
+#endif	/* __MACH_IOMUX_MX53_H__ */
diff --git a/arch/arm/mach-imx/speed-imx51.c b/arch/arm/mach-imx/speed-imx51.c
index 99832971dc..f1fb74c474 100644
--- a/arch/arm/mach-imx/speed-imx51.c
+++ b/arch/arm/mach-imx/speed-imx51.c
@@ -2,7 +2,7 @@
 #include <asm/io.h>
 #include <asm-generic/div64.h>
 #include <mach/imx51-regs.h>
-#include "mach/clock-imx51.h"
+#include <mach/clock-imx51_53.h>
 
 static u32 ccm_readl(u32 ofs)
 {
@@ -31,30 +31,30 @@ static unsigned long pll_get_rate(void __iomem *pllbase)
 	u64 temp;
 	unsigned long parent_rate;
 
-	dp_ctl = readl(pllbase + MX51_PLL_DP_CTL);
+	dp_ctl = readl(pllbase + MX5_PLL_DP_CTL);
 
-	if ((dp_ctl & MX51_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0)
+	if ((dp_ctl & MX5_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0)
 		parent_rate = fpm_get_rate();
 	else
 		parent_rate = osc_get_rate();
 
-	pll_hfsm = dp_ctl & MX51_PLL_DP_CTL_HFSM;
-	dbl = dp_ctl & MX51_PLL_DP_CTL_DPDCK0_2_EN;
+	pll_hfsm = dp_ctl & MX5_PLL_DP_CTL_HFSM;
+	dbl = dp_ctl & MX5_PLL_DP_CTL_DPDCK0_2_EN;
 
 	if (pll_hfsm == 0) {
-		dp_op = readl(pllbase + MX51_PLL_DP_OP);
-		dp_mfd = readl(pllbase + MX51_PLL_DP_MFD);
-		dp_mfn = readl(pllbase + MX51_PLL_DP_MFN);
+		dp_op = readl(pllbase + MX5_PLL_DP_OP);
+		dp_mfd = readl(pllbase + MX5_PLL_DP_MFD);
+		dp_mfn = readl(pllbase + MX5_PLL_DP_MFN);
 	} else {
-		dp_op = readl(pllbase + MX51_PLL_DP_HFS_OP);
-		dp_mfd = readl(pllbase + MX51_PLL_DP_HFS_MFD);
-		dp_mfn = readl(pllbase + MX51_PLL_DP_HFS_MFN);
+		dp_op = readl(pllbase + MX5_PLL_DP_HFS_OP);
+		dp_mfd = readl(pllbase + MX5_PLL_DP_HFS_MFD);
+		dp_mfn = readl(pllbase + MX5_PLL_DP_HFS_MFN);
 	}
-	pdf = dp_op & MX51_PLL_DP_OP_PDF_MASK;
-	mfi = (dp_op & MX51_PLL_DP_OP_MFI_MASK) >> MX51_PLL_DP_OP_MFI_OFFSET;
+	pdf = dp_op & MX5_PLL_DP_OP_PDF_MASK;
+	mfi = (dp_op & MX5_PLL_DP_OP_MFI_MASK) >> MX5_PLL_DP_OP_MFI_OFFSET;
 	mfi = (mfi <= 5) ? 5 : mfi;
-	mfd = dp_mfd & MX51_PLL_DP_MFD_MASK;
-	mfn = mfn_abs = dp_mfn & MX51_PLL_DP_MFN_MASK;
+	mfd = dp_mfd & MX5_PLL_DP_MFD_MASK;
+	mfn = mfn_abs = dp_mfn & MX5_PLL_DP_MFN_MASK;
 	/* Sign extend to 32-bits */
 	if (mfn >= 0x04000000) {
 		mfn |= 0xFC000000;
@@ -117,11 +117,11 @@ unsigned long imx_get_uartclk(void)
 
 	parent_rate = pll2_sw_get_rate();
 
-	reg = ccm_readl(MX51_CCM_CSCDR1);
-	prediv = ((reg & MX51_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
-		  MX51_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1;
-	podf = ((reg & MX51_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
-		MX51_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
+	reg = ccm_readl(MX5_CCM_CSCDR1);
+	prediv = ((reg & MX5_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
+		  MX5_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1;
+	podf = ((reg & MX5_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
+		MX5_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
 
 	return parent_rate / (prediv * podf);
 }
@@ -130,7 +130,7 @@ static unsigned long imx_get_ahbclk(void)
 {
 	u32 reg, div;
 
-	reg = ccm_readl(MX51_CCM_CBCDR);
+	reg = ccm_readl(MX5_CCM_CBCDR);
 	div = ((reg >> 10) & 0x7) + 1;
 
 	return pll2_sw_get_rate() / div;
@@ -140,7 +140,7 @@ unsigned long imx_get_ipgclk(void)
 {
 	u32 reg, div;
 
-	reg = ccm_readl(MX51_CCM_CBCDR);
+	reg = ccm_readl(MX5_CCM_CBCDR);
 	div = ((reg >> 8) & 0x3) + 1;
 
 	return imx_get_ahbclk() / div;
@@ -160,20 +160,20 @@ unsigned long imx_get_mmcclk(void)
 {
 	u32 reg, prediv, podf, rate;
 
-	reg = ccm_readl(MX51_CCM_CSCMR1);
-	reg &= MX51_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK;
-	reg >>= MX51_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET;
+	reg = ccm_readl(MX5_CCM_CSCMR1);
+	reg &= MX5_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK;
+	reg >>= MX5_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET;
 	rate = get_rate_select(reg,
 			pll1_main_get_rate,
 			pll2_sw_get_rate,
 			pll3_sw_get_rate,
 			NULL);
 
-	reg = ccm_readl(MX51_CCM_CSCDR1);
-	prediv = ((reg & MX51_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK) >>
-			MX51_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET) + 1;
-	podf = ((reg & MX51_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK) >>
-			MX51_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET) + 1;
+	reg = ccm_readl(MX5_CCM_CSCDR1);
+	prediv = ((reg & MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK) >>
+			MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET) + 1;
+	podf = ((reg & MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK) >>
+			MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET) + 1;
 
 	return rate / (prediv * podf);
 }
diff --git a/arch/arm/mach-imx/speed-imx53.c b/arch/arm/mach-imx/speed-imx53.c
new file mode 100644
index 0000000000..7b099f5fa6
--- /dev/null
+++ b/arch/arm/mach-imx/speed-imx53.c
@@ -0,0 +1,204 @@
+#include <common.h>
+#include <asm/io.h>
+#include <asm-generic/div64.h>
+#include <mach/imx-regs.h>
+#include "mach/clock-imx51_53.h"
+
+static u32 ccm_readl(u32 ofs)
+{
+	return readl(MX53_CCM_BASE_ADDR + ofs);
+}
+
+static unsigned long ckil_get_rate(void)
+{
+	return 32768;
+}
+
+static unsigned long osc_get_rate(void)
+{
+	return 24000000;
+}
+
+static unsigned long fpm_get_rate(void)
+{
+	return ckil_get_rate() * 512;
+}
+
+static unsigned long pll_get_rate(void __iomem *pllbase)
+{
+	long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
+	unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
+	u64 temp;
+	unsigned long parent_rate;
+
+	dp_ctl = readl(pllbase + MX5_PLL_DP_CTL);
+
+	if ((dp_ctl & MX5_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0)
+		parent_rate = fpm_get_rate();
+	else
+		parent_rate = osc_get_rate();
+
+	pll_hfsm = dp_ctl & MX5_PLL_DP_CTL_HFSM;
+	dbl = dp_ctl & MX5_PLL_DP_CTL_DPDCK0_2_EN;
+
+	if (pll_hfsm == 0) {
+		dp_op = readl(pllbase + MX5_PLL_DP_OP);
+		dp_mfd = readl(pllbase + MX5_PLL_DP_MFD);
+		dp_mfn = readl(pllbase + MX5_PLL_DP_MFN);
+	} else {
+		dp_op = readl(pllbase + MX5_PLL_DP_HFS_OP);
+		dp_mfd = readl(pllbase + MX5_PLL_DP_HFS_MFD);
+		dp_mfn = readl(pllbase + MX5_PLL_DP_HFS_MFN);
+	}
+	pdf = dp_op & MX5_PLL_DP_OP_PDF_MASK;
+	mfi = (dp_op & MX5_PLL_DP_OP_MFI_MASK) >> MX5_PLL_DP_OP_MFI_OFFSET;
+	mfi = (mfi <= 5) ? 5 : mfi;
+	mfd = dp_mfd & MX5_PLL_DP_MFD_MASK;
+	mfn = mfn_abs = dp_mfn & MX5_PLL_DP_MFN_MASK;
+	/* Sign extend to 32-bits */
+	if (mfn >= 0x04000000) {
+		mfn |= 0xFC000000;
+		mfn_abs = -mfn;
+	}
+
+	ref_clk = 2 * parent_rate;
+	if (dbl != 0)
+		ref_clk *= 2;
+
+	ref_clk /= (pdf + 1);
+	temp = (u64)ref_clk * mfn_abs;
+	do_div(temp, mfd + 1);
+	if (mfn < 0)
+		temp = -temp;
+	temp = (ref_clk * mfi) + temp;
+
+	return temp;
+}
+
+static unsigned long pll1_main_get_rate(void)
+{
+	return pll_get_rate((void __iomem *)MX53_PLL1_BASE_ADDR);
+}
+
+static unsigned long pll2_sw_get_rate(void)
+{
+	return pll_get_rate((void __iomem *)MX53_PLL2_BASE_ADDR);
+}
+
+static unsigned long pll3_sw_get_rate(void)
+{
+	return pll_get_rate((void __iomem *)MX53_PLL3_BASE_ADDR);
+}
+
+static unsigned long pll4_sw_get_rate(void)
+{
+	return pll_get_rate((void __iomem *)MX53_PLL4_BASE_ADDR);
+}
+
+static unsigned long get_rate_select(int select,
+	unsigned long (* get_rate1)(void),
+	unsigned long (* get_rate2)(void),
+	unsigned long (* get_rate3)(void),
+	unsigned long (* get_rate4)(void))
+{
+	switch (select) {
+	case 0:
+		return get_rate1() ? get_rate1() : 0;
+	case 1:
+		return get_rate2() ? get_rate2() : 0;
+	case 2:
+		return get_rate3 ? get_rate3() : 0;
+	case 3:
+		return get_rate4 ? get_rate4() : 0;
+	}
+
+	return 0;
+}
+
+unsigned long imx_get_uartclk(void)
+{
+	u32 reg, prediv, podf;
+	unsigned long parent_rate;
+
+	reg = ccm_readl(MX5_CCM_CSCMR1);
+	reg &= MX5_CCM_CSCMR1_UART_CLK_SEL_MASK;
+	reg >>= MX5_CCM_CSCMR1_UART_CLK_SEL_OFFSET;
+
+	parent_rate = get_rate_select(reg,
+			pll1_main_get_rate,
+			pll2_sw_get_rate,
+			pll3_sw_get_rate,
+			pll4_sw_get_rate);
+
+	reg = ccm_readl(MX5_CCM_CSCDR1);
+	prediv = ((reg & MX5_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
+		  MX5_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1;
+	podf = ((reg & MX5_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
+		MX5_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
+
+	return parent_rate / (prediv * podf);
+}
+
+static unsigned long imx_get_ahbclk(void)
+{
+	u32 reg, div;
+
+	reg = ccm_readl(MX5_CCM_CBCDR);
+	div = ((reg >> 10) & 0x7) + 1;
+
+	return pll2_sw_get_rate() / div;
+}
+
+unsigned long imx_get_ipgclk(void)
+{
+	u32 reg, div;
+
+	reg = ccm_readl(MX5_CCM_CBCDR);
+	div = ((reg >> 8) & 0x3) + 1;
+
+	return imx_get_ahbclk() / div;
+}
+
+unsigned long imx_get_gptclk(void)
+{
+	return imx_get_ipgclk();
+}
+
+unsigned long imx_get_fecclk(void)
+{
+	return imx_get_ipgclk();
+}
+
+unsigned long imx_get_mmcclk(void)
+{
+	u32 reg, prediv, podf, rate;
+
+	reg = ccm_readl(MX5_CCM_CSCMR1);
+	reg &= MX5_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK;
+	reg >>= MX5_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET;
+	rate = get_rate_select(reg,
+			pll1_main_get_rate,
+			pll2_sw_get_rate,
+			pll3_sw_get_rate,
+			pll4_sw_get_rate);
+
+	reg = ccm_readl(MX5_CCM_CSCDR1);
+	prediv = ((reg & MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK) >>
+			MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET) + 1;
+	podf = ((reg & MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK) >>
+			MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET) + 1;
+
+	return rate / (prediv * podf);
+}
+
+void imx_dump_clocks(void)
+{
+	printf("pll1: %ld\n", pll1_main_get_rate());
+	printf("pll2: %ld\n", pll2_sw_get_rate());
+	printf("pll3: %ld\n", pll3_sw_get_rate());
+	printf("pll4: %ld\n", pll4_sw_get_rate());
+	printf("uart: %ld\n", imx_get_uartclk());
+	printf("ipg:  %ld\n", imx_get_ipgclk());
+	printf("fec:  %ld\n", imx_get_fecclk());
+	printf("gpt:  %ld\n", imx_get_gptclk());
+}
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index f9cefaf907..caef7e0225 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -39,7 +39,6 @@ config MACH_MX23EVK
 
 config MACH_CHUMBY
 	bool "Chumby Falconwing"
-	select HAVE_MMU
 	help
 	  Say Y here if you are using the "chumby one" aka falconwing from
 	  Chumby Industries
@@ -55,7 +54,6 @@ choice
 
 config MACH_TX28
 	bool "KARO tx28"
-	select HAVE_MMU
 	help
 	  Say Y here if you are using the KARO TX28 CPU module.
 
diff --git a/arch/arm/mach-netx/netx-cm.c b/arch/arm/mach-netx/netx-cm.c
index 58b204274a..ebf9901d19 100644
--- a/arch/arm/mach-netx/netx-cm.c
+++ b/arch/arm/mach-netx/netx-cm.c
@@ -245,7 +245,6 @@ unsigned short crc16(unsigned short crc, unsigned int data)
 
 int netx_cm_init(void)
 {
-	DECLARE_GLOBAL_DATA_PTR;
 	int i;
 	char buf[MAX_USER_ZONE_SIZE];
 	struct netx_cm_userarea *area;
diff --git a/arch/arm/mach-nomadik/8815.c b/arch/arm/mach-nomadik/8815.c
index 5844c68d0b..bcc34062b5 100644
--- a/arch/arm/mach-nomadik/8815.c
+++ b/arch/arm/mach-nomadik/8815.c
@@ -31,49 +31,25 @@ static struct clk st8815_clk_48 = {
        .rate = 48 * 1000 * 1000,
 };
 
-static struct memory_platform_data ram_pdata = {
-	.name = "ram0",
-	.flags = DEVFS_RDWR,
-};
-
-static struct device_d sdram_dev = {
-	.id = -1,
-	.name = "mem",
-	.map_base = 0x00000000,
-	.platform_data = &ram_pdata,
-};
-
 void st8815_add_device_sdram(u32 size)
 {
-	sdram_dev.size = size;
-	register_device(&sdram_dev);
-	armlinux_add_dram(&sdram_dev);
+	arm_add_mem_device("ram0", 0x00000000, size);
 }
 
-static struct device_d uart0_serial_device = {
-	.id = 0,
-	.name = "uart-pl011",
-	.map_base = NOMADIK_UART0_BASE,
-	.size = 4096,
-};
-
-static struct device_d uart1_serial_device = {
-	.id = 1,
-	.name = "uart-pl011",
-	.map_base = NOMADIK_UART1_BASE,
-	.size = 4096,
-};
-
 void st8815_register_uart(unsigned id)
 {
+	resource_size_t start;
+	struct device_d *dev;
+
 	switch (id) {
 	case 0:
-		nmdk_clk_create(&st8815_clk_48, dev_name(&uart0_serial_device));
-		register_device(&uart0_serial_device);
+		start = NOMADIK_UART1_BASE;
 		break;
 	case 1:
-		nmdk_clk_create(&st8815_clk_48, dev_name(&uart1_serial_device));
-		register_device(&uart1_serial_device);
+		start = NOMADIK_UART1_BASE;
 		break;
 	}
+	dev = add_generic_device("uart-pl011", id, NULL, start, 4096,
+			   IORESOURCE_MEM, NULL);
+	nmdk_clk_create(&st8815_clk_48, dev_name(dev));
 }
diff --git a/arch/arm/mach-nomadik/include/mach/nand.h b/arch/arm/mach-nomadik/include/mach/nand.h
index 265fe536e3..544f0e02c7 100644
--- a/arch/arm/mach-nomadik/include/mach/nand.h
+++ b/arch/arm/mach-nomadik/include/mach/nand.h
@@ -2,9 +2,6 @@
 #define __ASM_ARCH_NAND_H
 
 struct nomadik_nand_platform_data {
-	unsigned long data_va;
-	unsigned long cmd_va;
-	unsigned long addr_va;
 	int options;
 	int (*init) (void);
 };
diff --git a/arch/arm/mach-omap/Kconfig b/arch/arm/mach-omap/Kconfig
index f256310cef..1174df072f 100644
--- a/arch/arm/mach-omap/Kconfig
+++ b/arch/arm/mach-omap/Kconfig
@@ -140,7 +140,6 @@ config MACH_OMAP3EVM
 
 config MACH_PANDA
 	bool "Texas Instrument's Panda Board"
-	select HAVE_MMU
 	select HAVE_NOSHELL
 	select MACH_HAS_LOWLEVEL_INIT
 	help
@@ -148,7 +147,6 @@ config MACH_PANDA
 
 config MACH_PCM049
 	bool "Phytec phyCORE pcm049"
-	select HAVE_MMU
 	select HAVE_NOSHELL
 	depends on ARCH_OMAP4
 	select MACH_HAS_LOWLEVEL_INIT
diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile
index a4b9a55774..7204746000 100644
--- a/arch/arm/mach-omap/Makefile
+++ b/arch/arm/mach-omap/Makefile
@@ -25,4 +25,4 @@ obj-$(CONFIG_ARCH_OMAP3) += omap3_core.o omap3_generic.o
 obj-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o
 obj-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock_core.o omap3_clock.o
 obj-$(CONFIG_OMAP_GPMC) += gpmc.o devices-gpmc-nand.o
-obj-y += omap-uart.o gpio.o xload.o
+obj-y += gpio.o xload.o
diff --git a/arch/arm/mach-omap/devices-gpmc-nand.c b/arch/arm/mach-omap/devices-gpmc-nand.c
index c2a2b0d1b5..76ceb20024 100644
--- a/arch/arm/mach-omap/devices-gpmc-nand.c
+++ b/arch/arm/mach-omap/devices-gpmc-nand.c
@@ -70,15 +70,6 @@ static struct gpmc_nand_platform_data nand_plat = {
 	.priv = (void *)&nand_cfg,
 };
 
-/** NAND device definition */
-static struct device_d gpmc_generic_nand_nand_device = {
-	.id = -1,
-	.name = "gpmc_nand",
-	.map_base = OMAP_GPMC_BASE,
-	.size = 1024 * 4,	/* GPMC size */
-	.platform_data = (void *)&nand_plat,
-};
-
 /**
  * @brief gpmc_generic_nand_devices_init - init generic nand device
  *
@@ -99,5 +90,9 @@ int gpmc_generic_nand_devices_init(int cs, int width,
 
 	/* Configure GPMC CS before register */
 	gpmc_cs_config(nand_plat.cs, &nand_cfg);
-	return register_device(&gpmc_generic_nand_nand_device);
+
+	add_generic_device("gpmc_nand", -1, NULL, OMAP_GPMC_BASE, 1024 * 4,
+			   IORESOURCE_MEM, &nand_plat);
+
+	return 0;
 }
diff --git a/arch/arm/mach-omap/include/mach/syslib.h b/arch/arm/mach-omap/include/mach/syslib.h
index 6a7044adcc..65aca0297f 100644
--- a/arch/arm/mach-omap/include/mach/syslib.h
+++ b/arch/arm/mach-omap/include/mach/syslib.h
@@ -57,8 +57,4 @@ static inline void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value)
 u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound);
 void sdelay(unsigned long loops);
 
-/** All architectures need to implement these */
-void omap_uart_write(unsigned int val, unsigned long base,
-		     unsigned char reg_idx);
-unsigned int omap_uart_read(unsigned long base, unsigned char reg_idx);
 #endif /* __ASM_ARCH_OMAP_SYSLIB_H_ */
diff --git a/arch/arm/mach-omap/omap-uart.c b/arch/arm/mach-omap/omap-uart.c
deleted file mode 100644
index 477452d990..0000000000
--- a/arch/arm/mach-omap/omap-uart.c
+++ /dev/null
@@ -1,36 +0,0 @@
-#include <common.h>
-#include <asm/io.h>
-
-/**
- * @brief Uart port register read function for OMAP3
- *
- * @param base base address of UART
- * @param reg_idx register index
- *
- * @return character read from register
- */
-unsigned int omap_uart_read(unsigned long base, unsigned char reg_idx)
-{
-	unsigned int *reg_addr = (unsigned int *)base;
-	reg_addr += reg_idx;
-	return readb(reg_addr);
-}
-EXPORT_SYMBOL(omap_uart_read);
-
-/**
- * @brief Uart port register write function for OMAP3
- *
- * @param val value to write
- * @param base base address of UART
- * @param reg_idx register index
- *
- * @return void
- */
-void omap_uart_write(unsigned int val, unsigned long base,
-		     unsigned char reg_idx)
-{
-	unsigned int *reg_addr = (unsigned int *)base;
-	reg_addr += reg_idx;
-	writeb(val, reg_addr);
-}
-EXPORT_SYMBOL(omap_uart_write);
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index ee14f5f7b2..28582f7f26 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -42,53 +42,11 @@
 #include <mach/platform.h>
 #include <mach/init.h>
 
-static struct memory_platform_data ram_pdata = {
-	.name = "ram0",
-	.flags = DEVFS_RDWR,
-};
-
-static struct device_d sdram_dev = {
-	.id = -1,
-	.name = "mem",
-	.map_base = 0x00000000,
-	.platform_data	= &ram_pdata,
-};
-
 void versatile_add_sdram(u32 size)
 {
-	sdram_dev.size = size;
-	register_device(&sdram_dev);
-	armlinux_add_dram(&sdram_dev);
+	arm_add_mem_device("ram0", 0x00000000, size);
 }
 
-static struct device_d uart0_serial_device = {
-	.id = 0,
-	.name = "uart-pl011",
-	.map_base = VERSATILE_UART0_BASE,
-	.size = 4096,
-};
-
-static struct device_d uart1_serial_device = {
-	.id = 1,
-	.name = "uart-pl011",
-	.map_base = VERSATILE_UART1_BASE,
-	.size = 4096,
-};
-
-static struct device_d uart2_serial_device = {
-	.id = 2,
-	.name = "uart-pl011",
-	.map_base = VERSATILE_UART2_BASE,
-	.size = 4096,
-};
-
-static struct device_d uart3_serial_device = {
-	.id = 3,
-	.name = "uart-pl011",
-	.map_base = VERSATILE_UART3_BASE,
-	.size = 4096,
-};
-
 struct clk {
 	unsigned long rate;
 };
@@ -188,24 +146,28 @@ core_initcall(vpb_clocksource_init);
 
 void versatile_register_uart(unsigned id)
 {
+	resource_size_t start;
+	struct device_d *dev;
+
 	switch (id) {
 	case 0:
-		vpb_clk_create(&ref_clk_24, dev_name(&uart0_serial_device));
-		register_device(&uart0_serial_device);
+		start = VERSATILE_UART0_BASE;
 		break;
 	case 1:
-		vpb_clk_create(&ref_clk_24, dev_name(&uart1_serial_device));
-		register_device(&uart1_serial_device);
+		start = VERSATILE_UART1_BASE;
 		break;
 	case 2:
-		vpb_clk_create(&ref_clk_24, dev_name(&uart2_serial_device));
-		register_device(&uart2_serial_device);
+		start = VERSATILE_UART2_BASE;
 		break;
 	case 3:
-		vpb_clk_create(&ref_clk_24, dev_name(&uart3_serial_device));
-		register_device(&uart3_serial_device);
+		start = VERSATILE_UART3_BASE;
 		break;
+	default:
+		return;
 	}
+	dev = add_generic_device("uart-pl011", id, NULL, start, 4096,
+			   IORESOURCE_MEM, NULL);
+	vpb_clk_create(&ref_clk_24, dev_name(dev));
 }
 
 void __noreturn reset_cpu (unsigned long ignored)
diff --git a/arch/blackfin/boards/ipe337/ipe337.c b/arch/blackfin/boards/ipe337/ipe337.c
index 61bcd434f1..ee642d1824 100644
--- a/arch/blackfin/boards/ipe337/ipe337.c
+++ b/arch/blackfin/boards/ipe337/ipe337.c
@@ -5,36 +5,10 @@
 #include <partition.h>
 #include <fs.h>
 
-static struct device_d cfi_dev = {
-	.id	  = -1,
-	.name     = "cfi_flash",
-	.map_base = 0x20000000,
-	.size     = 32 * 1024 * 1024,
-};
-
-static struct memory_platform_data ram_pdata = {
-	.name = "ram0",
-	.flags = DEVFS_RDWR,
-};
-
-static struct device_d sdram_dev = {
-	.id	  = -1,
-	.name     = "mem",
-	.map_base = 0x0,
-	.size     = 128 * 1024 * 1024,
-	.platform_data = &ram_pdata,
-};
-
-static struct device_d smc911x_dev = {
-	.id	  = -1,
-	.name     = "smc911x",
-	.map_base = 0x24000000,
-	.size     = 4096,
-};
-
 static int ipe337_devices_init(void) {
-	register_device(&cfi_dev);
-	register_device(&sdram_dev);
+	add_cfi_flash_device(-1, 0x20000000, 32 * 1024 * 1024, 0);
+	add_mem_device("ram0", 0x0, 128 * 1024 * 1024,
+		       IORESOURCE_MEM_WRITEABLE);
 
 	/* Reset smc911x */
 	*pFIO0_DIR = (1<<12);
@@ -42,7 +16,8 @@ static int ipe337_devices_init(void) {
 	mdelay(100);
 	*pFIO0_FLAG_S = (1<<12);
 
-	register_device(&smc911x_dev);
+	add_generic_device("smc911x", -1, NULL, 0x24000000, 4096,
+			   IORESOURCE_MEM, NULL);
 
 	devfs_add_partition("nor0", 0x00000, 0x20000, PARTITION_FIXED, "self0");
 	devfs_add_partition("nor0", 0x20000, 0x20000, PARTITION_FIXED, "env0");
@@ -54,16 +29,10 @@ static int ipe337_devices_init(void) {
 
 device_initcall(ipe337_devices_init);
 
-static struct device_d blackfin_serial_device = {
-	.id	  = -1,
-	.name     = "blackfin_serial",
-	.map_base = 0,
-	.size     = 4096,
-};
-
 static int blackfin_console_init(void)
 {
-	register_device(&blackfin_serial_device);
+	add_generic_device("blackfin_serial", -1, NULL, 0, 4096,
+			   IORESOURCE_MEM, NULL);
 
 	return 0;
 }
diff --git a/arch/nios2/boards/generic/generic.c b/arch/nios2/boards/generic/generic.c
index 4f7e7479e2..0e3852b007 100644
--- a/arch/nios2/boards/generic/generic.c
+++ b/arch/nios2/boards/generic/generic.c
@@ -4,54 +4,39 @@
 #include <partition.h>
 #include <fs.h>
 
-static struct device_d cfi_dev = {
-	.id       = -1,
-	.name     = "cfi_flash",
-	.map_base = NIOS_SOPC_FLASH_BASE,
-	.size     = NIOS_SOPC_FLASH_SIZE,
-};
-
 static int phy_address = 1;
 
+static struct resource mac_resources[] = {
+	[0] = {
+		.start	= NIOS_SOPC_TSE_BASE,
+		.size	= 0x400,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= NIOS_SOPC_SGDMA_RX_BASE,
+		.size	= 0x40,
+		.flags	= IORESOURCE_MEM,
+	},
+	[2] = {
+		.start	= NIOS_SOPC_SGDMA_TX_BASE,
+		.size	= 0x40,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
 static struct device_d mac_dev = {
 	.id            = -1,
 	.name          = "altera_tse",
-	.map_base      = NIOS_SOPC_TSE_BASE,
-	.size          = 0x00000400,
+	.num_resources = ARRAY_SIZE(mac_resources),
+	.resource      = mac_resources,
 	.platform_data = &phy_address,
 };
 
-static struct memory_platform_data ram_pdata = {
-	.name  = "ram0",
-	.flags = DEVFS_RDWR,
-};
-
-static struct device_d ram_dev = {
-	.id            = -1,
-	.name          = "mem",
-	.map_base      = NIOS_SOPC_MEMORY_BASE,
-	.size          = NIOS_SOPC_MEMORY_SIZE,
-	.platform_data = &ram_pdata,
-};
-
-static struct device_d altera_serial_device = {
-	.id       = -1,
-	.name     = "altera_serial",
-	.map_base = NIOS_SOPC_UART_BASE,
-};
-
-/*
-static struct device_d epcs_flash_device = {
-	.id       = -1,
-	.name     = "epcs_flash",
-	.map_base = NIOS_SOPC_EPCS_BASE,
-};
-*/
-
 static int generic_devices_init(void)
 {
-	register_device(&cfi_dev);
-	register_device(&ram_dev);
+	add_cfi_flash_device(-1, NIOS_SOPC_FLASH_BASE, NIOS_SOPC_FLASH_SIZE, 0);
+	add_mem_device("ram0", NIOS_SOPC_MEMORY_BASE, NIOS_SOPC_MEMORY_SIZE,
+		       IORESOURCE_MEM_WRITEABLE);
 	register_device(&mac_dev);
 	/*register_device(&epcs_flash_device);*/
 
@@ -68,7 +53,8 @@ device_initcall(generic_devices_init);
 
 static int altera_console_init(void)
 {
-	register_device(&altera_serial_device);
+	add_generic_device("altera_serial", -1, NULL, NIOS_SOPC_UART_BASE, 0x20,
+			   IORESOURCE_MEM, NULL);
 
 	return 0;
 }
diff --git a/arch/ppc/boards/pcm030/pcm030.c b/arch/ppc/boards/pcm030/pcm030.c
index 8b43550942..ba59bfe101 100644
--- a/arch/ppc/boards/pcm030/pcm030.c
+++ b/arch/ppc/boards/pcm030/pcm030.c
@@ -37,42 +37,17 @@
 #include <mem_malloc.h>
 #include <reloc.h>
 
-struct device_d cfi_dev = {
-	.id	  = -1,
-	.name     = "cfi_flash",
-	.map_base = 0xff000000,
-	.size     = 16 * 1024 * 1024,
-};
-
-static struct memory_platform_data ram_pdata = {
-	.name = "ram0",
-	.flags = DEVFS_RDWR,
-};
-
-struct device_d sdram_dev = {
-	.id	  = -1,
-	.name     = "mem",
-	.map_base = 0x0,
-	.size     = 64 * 1024 * 1024,
-	.platform_data = &ram_pdata,
-};
-
 static struct mpc5xxx_fec_platform_data fec_info = {
 	.xcv_type = MII100,
 };
 
-struct device_d eth_dev = {
-	.id		= -1,
-	.name		= "fec_mpc5xxx",
-	.map_base	= MPC5XXX_FEC,
-	.platform_data	= &fec_info,
-};
-
 static int devices_init (void)
 {
-	register_device(&cfi_dev);
-	register_device(&sdram_dev);
-	register_device(&eth_dev);
+	add_cfi_flash_device(-1, 0xff000000, 16 * 1024 * 1024, 0);
+	add_mem_device("ram0", 0x0, 64 * 1024 * 1024,
+		       IORESOURCE_MEM_WRITEABLE);
+	add_generic_device("fec_mpc5xxx", -1, NULL, MPC5XXX_FEC, 0,
+			   IORESOURCE_MEM, &fec_info);
 
 	devfs_add_partition("nor0", 0x00f00000, 0x40000, PARTITION_FIXED, "self0");
 	devfs_add_partition("nor0", 0x00f60000, 0x20000, PARTITION_FIXED, "env0");
@@ -82,24 +57,12 @@ static int devices_init (void)
 
 device_initcall(devices_init);
 
-static struct device_d psc3 = {
-	.id	  = -1,
-	.name     = "mpc5xxx_serial",
-	.map_base = MPC5XXX_PSC3,
-	.size     = 4096,
-};
-
-static struct device_d psc6 = {
-	.id	  = -1,
-	.name     = "mpc5xxx_serial",
-	.map_base = MPC5XXX_PSC6,
-	.size     = 4096,
-};
-
 static int console_init(void)
 {
-	register_device(&psc3);
-	register_device(&psc6);
+	add_generic_device("mpc5xxx_serial", -1, NULL, MPC5XXX_PSC3, 4096,
+			   IORESOURCE_MEM, NULL);
+	add_generic_device("mpc5xxx_serial", -1, NULL, MPC5XXX_PSC6, 4096,
+			   IORESOURCE_MEM, NULL);
 	return 0;
 }
 
diff --git a/arch/ppc/include/asm/global_data.h b/arch/ppc/include/asm/global_data.h
deleted file mode 100644
index c36df9abbc..0000000000
--- a/arch/ppc/include/asm/global_data.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef	__ASM_GBL_DATA_H
-#define __ASM_GBL_DATA_H
-
-#include "asm/types.h"
-
-/*
- * The following data structure is placed in some memory wich is
- * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
- * some locked parts of the data cache) to allow for a minimum set of
- * global variables during system initialization (until we have set
- * up the memory controller so that we can use RAM).
- *
- * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t)
- */
-
-typedef	struct	global_data {
-	bd_t		*bd;
-	unsigned long	flags;
-	unsigned long	baudrate;
-	unsigned long	cpu_clk;	/* CPU clock in Hz!		*/
-	unsigned long	bus_clk;
-#if defined(CONFIG_CPM2)
-	/* There are many clocks on the MPC8260 - see page 9-5 */
-	unsigned long	vco_out;
-	unsigned long	cpm_clk;
-	unsigned long	scc_clk;
-	unsigned long	brg_clk;
-#endif
-#if defined(CONFIG_MPC83XX)
-	/* There are other clocks in the MPC83XX */
-	u32 csb_clk;
-#if defined (CONFIG_MPC8349)
-	u32 tsec1_clk;
-	u32 tsec2_clk;
-	u32 usbmph_clk;
-	u32 usbdr_clk;
-#endif /* CONFIG_MPC8349 */
-	u32 core_clk;
-	u32 i2c1_clk;
-	u32 i2c2_clk;
-	u32 enc_clk;
-	u32 lbiu_clk;
-	u32 lclk_clk;
-	u32 ddr_clk;
-	u32 pci_clk;
-#if defined(CONFIG_QE)
-	u32 qe_clk;
-	u32 brg_clk;
-	uint mp_alloc_base;
-	uint mp_alloc_top;
-#endif /* CONFIG_QE */
-#if defined (CONFIG_MPC8360)
-	u32  ddr_sec_clk;
-#endif /* CONFIG_MPC8360 */
-#endif
-#if defined(CONFIG_MPC5xxx)
-	unsigned long	ipb_clk;
-	unsigned long	pci_clk;
-#endif
-#if defined(CONFIG_MPC8220)
-	unsigned long   bExtUart;
-	unsigned long   inp_clk;
-	unsigned long   pci_clk;
-	unsigned long   vco_clk;
-	unsigned long   pev_clk;
-	unsigned long   flb_clk;
-#endif
-//	unsigned long	ram_size;	/* RAM size */
-	unsigned long	reloc_off;	/* Relocation Offset */
-	unsigned long	reset_status;	/* reset status register at boot	*/
-	unsigned long	env_addr;	/* Address  of Environment struct	*/
-	unsigned long	env_valid;	/* Checksum of Environment valid?	*/
-	unsigned long	have_console;	/* serial_init() was called		*/
-#if defined(CFG_ALLOC_DPRAM) || defined(CONFIG_CPM2)
-	unsigned int	dp_alloc_base;
-	unsigned int	dp_alloc_top;
-#endif
-#if defined(CFG_GT_6426x)
-	unsigned int	mirror_hack[16];
-#endif
-#if defined(CONFIG_A3000)	|| \
-    defined(CONFIG_HIDDEN_DRAGON)  || \
-    defined(CONFIG_MUSENKI)	||  \
-    defined(CONFIG_SANDPOINT)
-	void *		console_addr;
-#endif
-#ifdef CONFIG_AMIGAONEG3SE
-	unsigned long	relocaddr;	/* Start address of barebox in RAM */
-#endif
-#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
-	unsigned long	fb_base;	/* Base address of framebuffer memory	*/
-#endif
-#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
-	unsigned long	post_log_word;  /* Record POST activities */
-	unsigned long	post_init_f_time;  /* When post_init_f started */
-#endif
-#ifdef CONFIG_BOARD_TYPES
-	unsigned long	board_type;
-#endif
-#ifdef CONFIG_MODEM_SUPPORT
-	unsigned long do_mdm_init;
-	unsigned long be_quiet;
-#endif
-#ifdef CONFIG_LWMON
-	unsigned long kbd_status;
-#endif
-	void		**jt;		/* jump table */
-} gd_t;
-
-/*
- * Global Data Flags
- */
-#define	GD_FLG_RELOC	0x00001		/* Code was relocated to RAM		*/
-#define	GD_FLG_DEVINIT	0x00002		/* Devices have been initialized	*/
-#define	GD_FLG_SILENT	0x00004		/* Silent mode				*/
-
-#endif /* __ASM_GBL_DATA_H */
diff --git a/arch/ppc/lib/ppclinux.c b/arch/ppc/lib/ppclinux.c
index f27955d444..531c215817 100644
--- a/arch/ppc/lib/ppclinux.c
+++ b/arch/ppc/lib/ppclinux.c
@@ -6,7 +6,6 @@
 #include <image.h>
 #include <init.h>
 #include <environment.h>
-#include <asm/global_data.h>
 #include <asm/bitops.h>
 #include <boot.h>
 #include <errno.h>
diff --git a/arch/sandbox/board/hostfile.c b/arch/sandbox/board/hostfile.c
index b049baa0a1..f5452afac9 100644
--- a/arch/sandbox/board/hostfile.c
+++ b/arch/sandbox/board/hostfile.c
@@ -102,17 +102,7 @@ device_initcall(hf_init);
 
 int barebox_register_filedev(struct hf_platform_data *hf)
 {
-	struct device_d *dev;
-
-	dev = xzalloc(sizeof(struct device_d));
-
-	dev->platform_data = hf;
-
-	strcpy(dev->name, "hostfile");
-	dev->size = hf->size;
-	dev->id = -1;
-	dev->map_base = hf->map_base;
-
-	return register_device(dev);
+	return !add_generic_device("hostfile", -1, NULL, hf->base, hf->size,
+			   IORESOURCE_MEM, hf);
 }
 
diff --git a/arch/sandbox/include/asm/io.h b/arch/sandbox/include/asm/io.h
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/arch/sandbox/include/asm/io.h
diff --git a/arch/sandbox/mach-sandbox/include/mach/hostfile.h b/arch/sandbox/mach-sandbox/include/mach/hostfile.h
index f7aca7c0c9..7c4e67cf68 100644
--- a/arch/sandbox/mach-sandbox/include/mach/hostfile.h
+++ b/arch/sandbox/mach-sandbox/include/mach/hostfile.h
@@ -4,7 +4,7 @@
 struct hf_platform_data {
 	int fd;
 	size_t size;
-	unsigned long map_base;
+	unsigned long base;
 	char *filename;
 	char *name;
 };
diff --git a/arch/sandbox/os/common.c b/arch/sandbox/os/common.c
index dcaf0c837e..5074a06c80 100644
--- a/arch/sandbox/os/common.c
+++ b/arch/sandbox/os/common.c
@@ -236,10 +236,10 @@ static int add_image(char *str, char *name)
 	hf->name = strdup(name);
 
 	if (map) {
-		hf->map_base = (unsigned long)mmap(NULL, hf->size,
+		hf->base = (unsigned long)mmap(NULL, hf->size,
 				PROT_READ | (readonly ? 0 : PROT_WRITE),
 				MAP_SHARED, fd, 0);
-		if ((void *)hf->map_base == MAP_FAILED)
+		if ((void *)hf->base == MAP_FAILED)
 			printf("warning: mmapping %s failed\n", file);
 	}
 
diff --git a/arch/x86/boards/x86_generic/generic_pc.c b/arch/x86/boards/x86_generic/generic_pc.c
index bfa94b9453..7a93d9bc31 100644
--- a/arch/x86/boards/x86_generic/generic_pc.c
+++ b/arch/x86/boards/x86_generic/generic_pc.c
@@ -30,19 +30,6 @@
 #include <asm/syslib.h>
 #include <ns16550.h>
 
-static struct memory_platform_data ram_pdata = {
-	.name		= "ram0",
-	.flags		= DEVFS_RDWR,
-};
-
-static struct device_d sdram_dev = {
-	.id		= -1,
-	.name		= "mem",
-	.size		= 16 * 1024 * 1024,
-	.map_base	= 0,
-	.platform_data	= &ram_pdata,
-};
-
 static struct device_d bios_disk_dev = {
 	.id		= -1,
 	.name		= "biosdrive",
@@ -70,7 +57,8 @@ static int devices_init(void)
 	sdram_dev.size = bios_get_memsize();	/* extended memory only */
 	sdram_dev.size <<= 10;
 
-	register_device(&sdram_dev);
+	add_mem_device("ram0", 0x0, 16 * 1024 * 1024,
+		       IORESOURCE_MEM_WRITEABLE);
 	register_device(&bios_disk_dev);
 
 	if (pers_env_size != PATCH_AREA_PERS_SIZE_UNUSED) {
@@ -90,24 +78,16 @@ device_initcall(devices_init);
 
 static struct NS16550_plat serial_plat = {
        .clock = 1843200,
-       .f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR,
        .reg_read = x86_uart_read,
        .reg_write = x86_uart_write,
 };
 
-/* we are expecting always one serial interface */
-static struct device_d generic_pc_serial_device = {
-       .id = -1,
-       .name = "serial_ns16550",
-       .map_base = 0x3f8,
-       .size = 8,
-       .platform_data = (void *)&serial_plat,
-};
-
 static int pc_console_init(void)
 {
-       /* Register the serial port */
-       return register_device(&generic_pc_serial_device);
+	/* Register the serial port */
+	add_ns16550_device(-1, 0x3f8, 8, 0, &serial_plat);
+
+	return 0;
 }
 console_initcall(pc_console_init);
 
diff --git a/commands/Kconfig b/commands/Kconfig
index 5700dc2890..e9222601c4 100644
--- a/commands/Kconfig
+++ b/commands/Kconfig
@@ -97,6 +97,16 @@ endchoice
 
 endif
 
+config CMD_TIME
+	bool "time"
+	  help
+	  Just like the unix time command this command allows to measure the
+	  execution time of a command. Note: barebox does not use interrupts,
+	  so the system timer can overrun during the execution of the command
+	  resulting in incorrect results. The timer gets updated in the function
+	  checking for ctrl-c, so the time command can be used with commands
+	  which are interruptible with ctrl-c.
+
 endmenu
 
 menu "file commands                 "
diff --git a/commands/Makefile b/commands/Makefile
index 8ee4aba726..7c88b488f2 100644
--- a/commands/Makefile
+++ b/commands/Makefile
@@ -57,3 +57,4 @@ obj-$(CONFIG_CMD_LOGIN)		+= login.o
 obj-$(CONFIG_CMD_LED)		+= led.o
 obj-$(CONFIG_CMD_LED_TRIGGER)	+= trigger.o
 obj-$(CONFIG_CMD_USB)		+= usb.o
+obj-$(CONFIG_CMD_TIME)		+= time.o
diff --git a/commands/loads.c b/commands/loads.c
index 6e0dc7fabc..c6617a4e68 100644
--- a/commands/loads.c
+++ b/commands/loads.c
@@ -31,8 +31,6 @@
 #include <exports.h>
 #include <xyzModem.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 static ulong load_serial (ulong offset);
 static int read_record (char *buf, ulong len);
 static int do_echo = 1;
diff --git a/commands/mem.c b/commands/mem.c
index 8df5f0a89a..88af55c1b8 100644
--- a/commands/mem.c
+++ b/commands/mem.c
@@ -1,14 +1,12 @@
 /*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Copyright (c) 2011 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -17,7 +15,7 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  * MA 02111-1307 USA
  */
 
@@ -485,6 +483,9 @@ static int do_mem_cp(struct command *cmdtp, int argc, char *argv[])
 		}
 
 		count -= r;
+
+		if (ctrlc())
+			goto out;
 	}
 
 	if (count) {
@@ -589,14 +590,13 @@ static struct file_operations memops = {
 
 static int mem_probe(struct device_d *dev)
 {
-	struct memory_platform_data *pdata = dev->platform_data;
 	struct cdev *cdev;
 
 	cdev = xzalloc(sizeof (*cdev));
 	dev->priv = cdev;
 
-	cdev->name = pdata->name;
-	cdev->size = dev->size;
+	cdev->name = (char*)dev->resource[0].name;
+	cdev->size = (unsigned long)dev->resource[0].size;
 	cdev->ops = &memops;
 	cdev->dev = dev;
 
@@ -610,19 +610,6 @@ static struct driver_d mem_drv = {
 	.probe = mem_probe,
 };
 
-static struct memory_platform_data mem_dev_pdata = {
-	.name = "mem",
-	.flags = DEVFS_RDWR,
-};
-
-static struct device_d mem_dev = {
-	.id = -1,
-	.name  = "mem",
-	.map_base = 0,
-	.size   = ~0, /* FIXME: should be 0x100000000, ahem... */
-	.platform_data = &mem_dev_pdata,
-};
-
 static int mem_init(void)
 {
 	rw_buf = malloc(RW_BUF_SIZE);
@@ -631,8 +618,8 @@ static int mem_init(void)
 		return -1;
 	}
 
+	add_mem_device("mem", 0, ~0, IORESOURCE_MEM_WRITEABLE);
 	register_driver(&mem_drv);
-	register_device(&mem_dev);
 
 	return 0;
 }
diff --git a/commands/time.c b/commands/time.c
new file mode 100644
index 0000000000..9a769451aa
--- /dev/null
+++ b/commands/time.c
@@ -0,0 +1,57 @@
+#include <common.h>
+#include <command.h>
+#include <clock.h>
+#include <asm-generic/div64.h>
+#include <malloc.h>
+
+static int do_time(struct command *cmdtp, int argc, char *argv[])
+{
+	int i;
+	unsigned char *buf;
+	u64 start, end, diff64;
+	unsigned long diff;
+	int len = 0;
+
+	if (argc < 2)
+		return COMMAND_ERROR_USAGE;
+
+	for (i = 1; i < argc; i++)
+		len += strlen(argv[i]) + 1;
+
+	buf = xzalloc(len);
+
+	for (i = 1; i < argc; i++) {
+		strcat(buf, argv[i]);
+		strcat(buf, " ");
+	}
+
+	start = get_time_ns();
+
+	run_command(buf, 0);
+
+	end = get_time_ns();
+
+	diff64 = end - start;
+
+	do_div(diff64, 1000000);
+
+	diff = diff64;
+
+	printf("time: %ldms\n", diff);
+
+	free(buf);
+
+	return 0;
+}
+
+BAREBOX_CMD_HELP_START(time)
+BAREBOX_CMD_HELP_USAGE("time <command>\n")
+BAREBOX_CMD_HELP_SHORT("note: This command depends on <command> being interruptible,\n")
+BAREBOX_CMD_HELP_SHORT("Otherwise the timer may overrun resulting in incorrect results\n")
+BAREBOX_CMD_HELP_END
+
+BAREBOX_CMD_START(time)
+	.cmd		= do_time,
+	.usage		= "measure execution time of a command",
+	BAREBOX_CMD_HELP(cmd_time_help)
+BAREBOX_CMD_END
diff --git a/common/Kconfig b/common/Kconfig
index 7d2367b0c3..422d1856b1 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -70,12 +70,8 @@ config ENVIRONMENT_VARIABLES
 
 menu "memory layout                 "
 
-config HAVE_MMU
-	bool
-
 config MMU
 	bool "Enable MMU"
-	depends on HAVE_MMU
 	help
 	  Saying yes here enables the MMU. This is useful on some architectures
 	  to enable the data cache which depends on the MMU. See Documentation/mmu.txt
@@ -482,4 +478,14 @@ config ENABLE_DEVICE_NOISE
 	help
 	  Enable this to get noisy device handling routines
 
+config DEBUG_LL
+	bool
+	depends on HAS_DEBUG_LL
+	prompt "low level debug messages"
+	help
+	  Enable this to get low level debug messages during barebox initialization.
+
 endmenu
+
+config HAS_DEBUG_LL
+	bool
diff --git a/common/startup.c b/common/startup.c
index 00bc9a0038..bf67aef152 100644
--- a/common/startup.c
+++ b/common/startup.c
@@ -82,21 +82,11 @@ void early_init (void)
 #ifdef CONFIG_DEFAULT_ENVIRONMENT
 #include <generated/barebox_default_env.h>
 
-static struct memory_platform_data default_env_platform_data = {
-	.name = "defaultenv",
-};
-
-static struct device_d default_env_dev = {
-	.id		= -1,
-	.name		= "mem",
-	.platform_data	= &default_env_platform_data,
-};
-
 static int register_default_env(void)
 {
-	default_env_dev.map_base = (unsigned long)default_environment;
-	default_env_dev.size = sizeof(default_environment);
-	register_device(&default_env_dev);
+	add_mem_device("defaultenv", (unsigned long)default_environment,
+		       sizeof(default_environment),
+		       IORESOURCE_MEM_WRITEABLE);
 	return 0;
 }
 
@@ -134,13 +124,17 @@ void start_barebox (void)
 
 	for (initcall = __barebox_initcalls_start;
 			initcall < __barebox_initcalls_end; initcall++) {
+		PUTS_LL("<<");
 		PUTHEX_LL(*initcall);
-		PUTC_LL('\n');
 		result = (*initcall)();
+		PUTC_LL('>');
 		if (result)
 			hang();
+		PUTS_LL(">\n");
 	}
 
+	PUTS_LL("initcalls done\n");
+
 	display_meminfo();
 
 #ifdef CONFIG_ENV_HANDLING
diff --git a/drivers/Makefile b/drivers/Makefile
index 92b22bdaa9..16b3bb129f 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -1,3 +1,4 @@
+obj-y	+= base/
 obj-y	+= net/
 obj-y	+= serial/
 obj-y	+= mtd/
diff --git a/drivers/ata/bios.c b/drivers/ata/bios.c
index 3f419ccf27..6e2377c7ea 100644
--- a/drivers/ata/bios.c
+++ b/drivers/ata/bios.c
@@ -257,7 +257,7 @@ static int biosdisk_probe(struct device_d *dev)
 
 		strcpy(drive_dev->name, "biosdisk");
 		drive_dev->id = drive - 0x80;
-		drive_dev->map_base = 0;
+		drive_dev->resource[0].start = 0;
 		drive_dev->platform_data = p;
 
 		register_device(drive_dev);
diff --git a/drivers/ata/disk_drive.c b/drivers/ata/disk_drive.c
index 23837691da..523edfd8c1 100644
--- a/drivers/ata/disk_drive.c
+++ b/drivers/ata/disk_drive.c
@@ -197,7 +197,7 @@ static int disk_probe(struct device_d *dev)
 		dev_info(dev, "Drive size guessed to %u kiB\n", dev->size / 1024);
 	}
 #endif
-	atablk->blk.num_blocks = dev->size / SECTOR_SIZE;
+	atablk->blk.num_blocks = dev->resource[0].size / SECTOR_SIZE;
 	atablk->blk.ops = &ataops;
 	atablk->blk.blockbits = 9;
 	atablk->dev = dev;
diff --git a/drivers/base/Makefile b/drivers/base/Makefile
new file mode 100644
index 0000000000..957ca5ac2a
--- /dev/null
+++ b/drivers/base/Makefile
@@ -0,0 +1,3 @@
+obj-y	+= driver.o
+obj-y	+= platform.o
+obj-y	+= resource.o
diff --git a/lib/driver.c b/drivers/base/driver.c
index ff4730f3a0..84f9c81ecc 100644
--- a/lib/driver.c
+++ b/drivers/base/driver.c
@@ -213,6 +213,23 @@ int register_driver(struct driver_d *drv)
 }
 EXPORT_SYMBOL(register_driver);
 
+void __iomem *dev_get_mem_region(struct device_d *dev, int num)
+{
+	int i, n = 0;
+
+	for (i = 0; i < dev->num_resources; i++) {
+		struct resource *res = &dev->resource[i];
+		if (resource_type(res) == IORESOURCE_MEM) {
+			if (n == num)
+				return (void __force __iomem *)res->start;
+			n++;
+		}
+	}
+
+	return NULL;
+}
+EXPORT_SYMBOL(dev_get_mem_region);
+
 int dev_protect(struct device_d *dev, size_t count, unsigned long offset, int prot)
 {
 	printf("%s: currently broken\n", __func__);
@@ -226,7 +243,7 @@ int generic_memmap_ro(struct cdev *cdev, void **map, int flags)
 
 	if (flags & PROT_WRITE)
 		return -EACCES;
-	*map = (void *)cdev->dev->map_base;
+	*map = dev_get_mem_region(cdev->dev, 0);
 	return 0;
 }
 
@@ -235,7 +252,7 @@ int generic_memmap_rw(struct cdev *cdev, void **map, int flags)
 	if (!cdev->dev)
 		return -EINVAL;
 
-	*map = (void *)cdev->dev->map_base;
+	*map = dev_get_mem_region(cdev->dev, 0);
 	return 0;
 }
 
@@ -249,7 +266,7 @@ const char *dev_id(const struct device_d *dev)
 {
 	static char buf[MAX_DRIVER_NAME + 16];
 
-	snprintf(buf, sizeof(buf), FORMAT_DRIVER_MANE_ID, dev->name, dev->id);
+	snprintf(buf, sizeof(buf), FORMAT_DRIVER_NAME_ID, dev->name, dev->id);
 
 	return buf;
 }
@@ -302,6 +319,8 @@ static int do_devinfo(struct command *cmdtp, int argc, char *argv[])
 	struct device_d *dev;
 	struct driver_d *drv;
 	struct param_d *param;
+	int i;
+	struct resource *res;
 
 	if (argc == 1) {
 		printf("devices:\n");
@@ -322,9 +341,17 @@ static int do_devinfo(struct command *cmdtp, int argc, char *argv[])
 			return -1;
 		}
 
-		printf("base  : 0x%08x\nsize  : 0x%08x\ndriver: %s\n\n",
-			dev->map_base, dev->size,
-			dev->driver ? 
+		printf("resources:\n");
+		for (i = 0; i < dev->num_resources; i++) {
+			res = &dev->resource[i];
+			printf("num   : %d\n", i);
+			if (res->name)
+				printf("name  : %s\n", res->name);
+			printf("start : 0x%08x\nsize  : 0x%08x\n",
+			       res->start, res->size);
+		}
+
+		printf("driver: %s\n\n", dev->driver ?
 				dev->driver->name : "none");
 
 		if (dev->driver)
diff --git a/lib/bus.c b/drivers/base/platform.c
index e0dd9ea58e..e0dd9ea58e 100644
--- a/lib/bus.c
+++ b/drivers/base/platform.c
diff --git a/drivers/base/resource.c b/drivers/base/resource.c
new file mode 100644
index 0000000000..175beb9c2d
--- /dev/null
+++ b/drivers/base/resource.c
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <driver.h>
+#include <xfuncs.h>
+
+static struct device_d *alloc_device(const char* devname, int id, void *pdata)
+{
+	struct device_d *dev;
+
+	dev = xzalloc(sizeof(*dev));
+	strcpy(dev->name, devname);
+	dev->id = id;
+	dev->platform_data = pdata;
+
+	return dev;
+}
+
+struct device_d *add_generic_device(const char* devname, int id, const char *resname,
+		resource_size_t start, resource_size_t size, unsigned int flags,
+		void *pdata)
+{
+	struct device_d *dev;
+
+	dev = alloc_device(devname, id, pdata);
+	dev->resource = xzalloc(sizeof(struct resource));
+	dev->num_resources = 1;
+	if (resname)
+		dev->resource[0].name = xstrdup(resname);
+	dev->resource[0].start = start;
+	dev->resource[0].size = size;
+	dev->resource[0].flags = flags;
+
+	register_device(dev);
+
+	return dev;
+}
+EXPORT_SYMBOL(add_generic_device);
+
+#ifdef CONFIG_DRIVER_NET_DM9000
+struct device_d *add_dm9000_device(int id, resource_size_t base,
+		resource_size_t data, int flags, void *pdata)
+{
+	struct device_d *dev;
+	resource_size_t size;
+
+	dev = alloc_device("dm9000", id, pdata);
+	dev->resource = xzalloc(sizeof(struct resource) * 2);
+	dev->num_resources = 2;
+
+	switch (flags) {
+	case IORESOURCE_MEM_32BIT:
+		size = 8;
+		break;
+	case IORESOURCE_MEM_16BIT:
+		size = 4;
+		break;
+	case IORESOURCE_MEM_8BIT:
+		size = 2;
+		break;
+	default:
+		printf("dm9000: memory width flag missing\n");
+		return NULL;
+	}
+
+	dev->resource[0].start = base;
+	dev->resource[0].size = size;
+	dev->resource[0].flags = IORESOURCE_MEM | flags;
+	dev->resource[1].start = data;
+	dev->resource[1].size = size;
+	dev->resource[1].flags = IORESOURCE_MEM | flags;
+
+	register_device(dev);
+
+	return dev;
+}
+EXPORT_SYMBOL(add_dm9000_device);
+#endif
+
+#ifdef CONFIG_USB_EHCI
+struct device_d *add_usb_ehci_device(int id, resource_size_t hccr,
+		resource_size_t hcor, void *pdata)
+{
+	struct device_d *dev;
+
+	dev = alloc_device("ehci", id, pdata);
+	dev->resource = xzalloc(sizeof(struct resource) * 2);
+	dev->num_resources = 2;
+	dev->resource[0].start = hccr;
+	dev->resource[0].flags = IORESOURCE_MEM;
+	dev->resource[1].start = hcor;
+	dev->resource[1].flags = IORESOURCE_MEM;
+
+	register_device(dev);
+
+	return dev;
+}
+EXPORT_SYMBOL(add_usb_ehci_device);
+#endif
+
+#ifdef CONFIG_ARM
+#include <asm/armlinux.h>
+
+struct device_d *arm_add_mem_device(const char* name, resource_size_t start,
+				    resource_size_t size)
+{
+	struct device_d *dev;
+
+	dev = add_mem_device(name, start, size, IORESOURCE_MEM_WRITEABLE);
+	armlinux_add_dram(dev);
+
+	return dev;
+}
+#endif
diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index 93e978ed6c..2d075f72ca 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -102,6 +102,7 @@ static u16 i2c_clk_div[50][2] = {
 };
 
 struct imx_i2c_struct {
+	void __iomem		*base;
 	struct i2c_adapter	adapter;
 	unsigned int 		disable_delay;
 	int			stopped;
@@ -112,11 +113,11 @@ struct imx_i2c_struct {
 #ifdef CONFIG_I2C_DEBUG
 static void i2c_imx_dump_reg(struct i2c_adapter *adapter)
 {
-	unsigned long base = adapter->dev->map_base;
+	struct imx_i2c_struct *i2c_imx = to_imx_i2c_struct(adapter);
 	u32 reg_cr, reg_sr;
 
-	reg_cr = readb(base + IMX_I2C_I2CR);
-	reg_sr = readb(base + IMX_I2C_I2SR);
+	reg_cr = readb(i2c_imx->base + IMX_I2C_I2CR);
+	reg_sr = readb(i2c_imx->base + IMX_I2C_I2SR);
 
 	dev_dbg(adapter->dev, "CONTROL:\t"
 		"IEN =%d, IIEN=%d, MSTA=%d, MTX =%d, TXAK=%d, RSTA=%d\n",
@@ -140,7 +141,8 @@ static inline void i2c_imx_dump_reg(struct i2c_adapter *adapter)
 
 static int i2c_imx_bus_busy(struct i2c_adapter *adapter, int for_busy)
 {
-	unsigned long base = adapter->dev->map_base;
+	struct imx_i2c_struct *i2c_imx = to_imx_i2c_struct(adapter);
+	void __iomem *base = i2c_imx->base;
 	uint64_t start;
 	unsigned int temp;
 
@@ -164,7 +166,8 @@ static int i2c_imx_bus_busy(struct i2c_adapter *adapter, int for_busy)
 
 static int i2c_imx_trx_complete(struct i2c_adapter *adapter)
 {
-	unsigned long base = adapter->dev->map_base;
+	struct imx_i2c_struct *i2c_imx = to_imx_i2c_struct(adapter);
+	void __iomem *base = i2c_imx->base;
 	uint64_t start;
 
 	start = get_time_ns();
@@ -185,7 +188,8 @@ static int i2c_imx_trx_complete(struct i2c_adapter *adapter)
 
 static int i2c_imx_acked(struct i2c_adapter *adapter)
 {
-	unsigned long base = adapter->dev->map_base;
+	struct imx_i2c_struct *i2c_imx = to_imx_i2c_struct(adapter);
+	void __iomem *base = i2c_imx->base;
 	uint64_t start;
 
 	start = get_time_ns();
@@ -206,7 +210,7 @@ static int i2c_imx_acked(struct i2c_adapter *adapter)
 static int i2c_imx_start(struct i2c_adapter *adapter)
 {
 	struct imx_i2c_struct *i2c_imx = to_imx_i2c_struct(adapter);
-	unsigned long base = adapter->dev->map_base;
+	void __iomem *base = i2c_imx->base;
 	unsigned int temp = 0;
 	int result;
 
@@ -238,7 +242,7 @@ static int i2c_imx_start(struct i2c_adapter *adapter)
 static void i2c_imx_stop(struct i2c_adapter *adapter)
 {
 	struct imx_i2c_struct *i2c_imx = to_imx_i2c_struct(adapter);
-	unsigned long base = adapter->dev->map_base;
+	void __iomem *base = i2c_imx->base;
 	unsigned int temp = 0;
 
 	if (!i2c_imx->stopped) {
@@ -306,7 +310,8 @@ static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
 
 static int i2c_imx_write(struct i2c_adapter *adapter, struct i2c_msg *msgs)
 {
-	unsigned long base = adapter->dev->map_base;
+	struct imx_i2c_struct *i2c_imx = to_imx_i2c_struct(adapter);
+	void __iomem *base = i2c_imx->base;
 	int i, result;
 
 	dev_dbg(adapter->dev,
@@ -343,7 +348,7 @@ static int i2c_imx_write(struct i2c_adapter *adapter, struct i2c_msg *msgs)
 static int i2c_imx_read(struct i2c_adapter *adapter, struct i2c_msg *msgs)
 {
 	struct imx_i2c_struct *i2c_imx = to_imx_i2c_struct(adapter);
-	unsigned long base = adapter->dev->map_base;
+	void __iomem *base = i2c_imx->base;
 	int i, result;
 	unsigned int temp;
 
@@ -411,7 +416,8 @@ static int i2c_imx_read(struct i2c_adapter *adapter, struct i2c_msg *msgs)
 static int i2c_imx_xfer(struct i2c_adapter *adapter,
 			struct i2c_msg *msgs, int num)
 {
-	unsigned long base = adapter->dev->map_base;
+	struct imx_i2c_struct *i2c_imx = to_imx_i2c_struct(adapter);
+	void __iomem *base = i2c_imx->base;
 	unsigned int i, temp;
 	int result;
 
@@ -453,7 +459,6 @@ static int __init i2c_imx_probe(struct device_d *pdev)
 {
 	struct imx_i2c_struct *i2c_imx;
 	struct i2c_platform_data *pdata;
-	unsigned long base = pdev->map_base;
 	int ret;
 
 	pdata = pdev->platform_data;
@@ -464,6 +469,7 @@ static int __init i2c_imx_probe(struct device_d *pdev)
 	i2c_imx->adapter.master_xfer = i2c_imx_xfer;
 	i2c_imx->adapter.nr = pdev->id;
 	i2c_imx->adapter.dev = pdev;
+	i2c_imx->base = dev_request_mem_region(pdev, 0);
 
 	/* Set up clock divider */
 	if (pdata && pdata->bitrate)
@@ -472,8 +478,8 @@ static int __init i2c_imx_probe(struct device_d *pdev)
 		i2c_imx_set_clk(i2c_imx, IMX_I2C_BIT_RATE);
 
 	/* Set up chip registers to defaults */
-	writeb(0, base + IMX_I2C_I2CR);
-	writeb(0, base + IMX_I2C_I2SR);
+	writeb(0, i2c_imx->base + IMX_I2C_I2CR);
+	writeb(0, i2c_imx->base + IMX_I2C_I2SR);
 
 	/* Add I2C adapter */
 	ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 8e7a8b500c..95c4fdf782 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -716,7 +716,6 @@ i2c_omap_probe(struct device_d *pdev)
 {
 	struct omap_i2c_struct	*i2c_omap;
 	/* struct i2c_platform_data *pdata; */
-	/* unsigned long base = pdev->map_base; */
 	int r;
 	u32 speed = 0;
 
@@ -732,7 +731,7 @@ i2c_omap_probe(struct device_d *pdev)
 		speed = 100;	/* Defualt speed */
 
 	i2c_omap->speed = speed;
-	i2c_omap->base = (void*)pdev->map_base;
+	i2c_omap->base = dev_request_mem_region(pdev, 0);
 	printf ("I2C probe\n");
 	omap_i2c_unidle(i2c_omap);
 
diff --git a/drivers/mci/Kconfig b/drivers/mci/Kconfig
index 7b71b99a00..0d5a0e0814 100644
--- a/drivers/mci/Kconfig
+++ b/drivers/mci/Kconfig
@@ -55,7 +55,7 @@ config MCI_IMX
 
 config MCI_IMX_ESDHC
 	bool "i.MX esdhc"
-	depends on ARCH_IMX25 || ARCH_IMX35 || ARCH_IMX51
+	depends on ARCH_IMX25 || ARCH_IMX35 || ARCH_IMX51 || ARCH_IMX53
 	help
 	  Enable this entry to add support to read and write SD cards on a
 	  Freescale i.MX25/35/51 based system.
diff --git a/drivers/mci/atmel_mci.c b/drivers/mci/atmel_mci.c
index d8bcf8159b..b4489dd19e 100644
--- a/drivers/mci/atmel_mci.c
+++ b/drivers/mci/atmel_mci.c
@@ -456,7 +456,7 @@ static int mci_probe(struct device_d *hw_dev)
 	if (pd->bus_width == 8)
 		host->mci.host_caps |= MMC_MODE_8BIT;
 
-	host->base = (void __iomem *)hw_dev->map_base;
+	host->base = dev_request_mem_region(hw_dev, 0);
 	host->hw_dev = hw_dev;
 	hw_dev->priv = host;
 	host->clk = clk_get(hw_dev, "mci_clk");
diff --git a/drivers/mci/imx-esdhc.c b/drivers/mci/imx-esdhc.c
index 7595a9323c..e20b3b7a65 100644
--- a/drivers/mci/imx-esdhc.c
+++ b/drivers/mci/imx-esdhc.c
@@ -35,6 +35,7 @@
 #include <asm/io.h>
 #include <asm/mmu.h>
 #include <mach/clock.h>
+#include <mach/generic.h>
 
 #include "imx-esdhc.h"
 
@@ -75,6 +76,8 @@ struct fsl_esdhc_host {
 
 #define to_fsl_esdhc(mci)	container_of(mci, struct fsl_esdhc_host, mci)
 
+#define  SDHCI_CMD_ABORTCMD (0xC0 << 16)
+
 /* Return the XFERTYP flags for a given command and data packet */
 u32 esdhc_xfertyp(struct mci_cmd *cmd, struct mci_data *data)
 {
@@ -104,6 +107,8 @@ u32 esdhc_xfertyp(struct mci_cmd *cmd, struct mci_data *data)
 		xfertyp |= XFERTYP_RSPTYP_48_BUSY;
 	else if (cmd->resp_type & MMC_RSP_PRESENT)
 		xfertyp |= XFERTYP_RSPTYP_48;
+	if (cpu_is_mx53() && cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
+		xfertyp |= SDHCI_CMD_ABORTCMD;
 
 	return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
 }
@@ -233,20 +238,8 @@ esdhc_send_cmd(struct mci_host *mci, struct mci_cmd *cmd, struct mci_data *data)
 
 	esdhc_write32(&regs->irqstat, -1);
 
-	/* Wait for the bus to be idle */
-	while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
-			(esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
-		;
-
-	while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
-		;
-
 	/* Wait at least 8 SD clock cycles before the next command */
-	/*
-	 * Note: This is way more than 8 cycles, but 1ms seems to
-	 * resolve timing issues with some cards
-	 */
-	udelay(1000);
+	udelay(1);
 
 	/* Set up for a data transfer if we have one */
 	if (data) {
@@ -324,6 +317,14 @@ esdhc_send_cmd(struct mci_host *mci, struct mci_cmd *cmd, struct mci_data *data)
 
 	esdhc_write32(&regs->irqstat, -1);
 
+	/* Wait for the bus to be idle */
+	while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
+			(esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
+		;
+
+	while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
+		;
+
 	return 0;
 }
 
@@ -457,7 +458,7 @@ static int fsl_esdhc_probe(struct device_d *dev)
 	mci = &host->mci;
 
 	host->dev = dev;
-	host->regs = (struct fsl_esdhc *)dev->map_base;
+	host->regs = dev_request_mem_region(dev, 0);
 
 	/* First reset the eSDHC controller */
 	ret = esdhc_reset(host->regs);
diff --git a/drivers/mci/imx.c b/drivers/mci/imx.c
index 852569275b..1f96e96607 100644
--- a/drivers/mci/imx.c
+++ b/drivers/mci/imx.c
@@ -493,7 +493,7 @@ static int mxcmci_probe(struct device_d *dev)
 	host->mci.init = mxcmci_init;
 	host->mci.host_caps = MMC_MODE_4BIT;
 
-	host->base = (struct mxcmci_regs *)dev->map_base;
+	host->base = dev_request_mem_region(dev, 0);
 
 	host->mci.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 
diff --git a/drivers/mci/mci-core.c b/drivers/mci/mci-core.c
index 1c16cf15d7..fea26916c6 100644
--- a/drivers/mci/mci-core.c
+++ b/drivers/mci/mci-core.c
@@ -1175,7 +1175,6 @@ static int mci_card_probe(struct device_d *mci_dev)
 {
 	struct mci *mci = GET_MCI_DATA(mci_dev);
 	struct mci_host *host = GET_MCI_PDATA(mci_dev);
-	struct device_d *disk_dev;
 	struct ata_interface *p;
 	int rc;
 
@@ -1221,8 +1220,7 @@ static int mci_card_probe(struct device_d *mci_dev)
 	 * An MMC/SD card acts like an ordinary disk.
 	 * So, re-use the disk driver to gain access to this media
 	 */
-	disk_dev = xzalloc(sizeof(struct device_d) + sizeof(struct ata_interface));
-	p = (struct ata_interface*)&disk_dev[1];
+	p = xzalloc(sizeof(struct ata_interface));
 
 #ifdef CONFIG_MCI_WRITE
 	p->write = mci_sd_write;
@@ -1230,12 +1228,7 @@ static int mci_card_probe(struct device_d *mci_dev)
 	p->read = mci_sd_read;
 	p->priv = mci_dev;
 
-	strcpy(disk_dev->name, "disk");
-	disk_dev->size = mci->capacity;
-	disk_dev->map_base = 0;
-	disk_dev->platform_data = p;
-
-	register_device(disk_dev);
+	add_generic_device("disk", -1, NULL, 0, mci->capacity, IORESOURCE_MEM, p);
 
 	pr_debug("SD Card successfully added\n");
 
diff --git a/drivers/mci/mxs.c b/drivers/mci/mxs.c
index c6ae1cb1fd..a47762076c 100644
--- a/drivers/mci/mxs.c
+++ b/drivers/mci/mxs.c
@@ -702,7 +702,7 @@ static int mxs_mci_probe(struct device_d *hw_dev)
 	host->send_cmd = mxs_mci_request,
 	host->set_ios = mxs_mci_set_ios,
 	host->init = mxs_mci_initialize,
-	mxs_mci->regs = (void *)hw_dev->map_base;
+	mxs_mci->regs = dev_request_mem_region(dev, 0);
 
 	/* feed forward the platform specific values */
 	host->voltages = pd->voltages;
@@ -713,7 +713,7 @@ static int mxs_mci_probe(struct device_d *hw_dev)
 #endif
 #ifdef CONFIG_ARCH_IMX28
 	/* one dedicated clock per unit */
-	switch (hw_dev->map_base) {
+	switch (hw_dev->resource[0].start) {
 	case IMX_SSP0_BASE:
 		mxs_mci->index = 0;
 		break;
diff --git a/drivers/mci/omap_hsmmc.c b/drivers/mci/omap_hsmmc.c
index 07992978a6..f47f1907c2 100644
--- a/drivers/mci/omap_hsmmc.c
+++ b/drivers/mci/omap_hsmmc.c
@@ -558,7 +558,7 @@ static int omap_mmc_probe(struct device_d *dev)
 	hsmmc->mci.init = mmc_init_setup;
 	hsmmc->mci.host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
 
-	hsmmc->base = (struct hsmmc *)dev->map_base;
+	hsmmc->base = dev_request_mem_region(dev, 0);
 
 	hsmmc->mci.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 
diff --git a/drivers/mci/s3c.c b/drivers/mci/s3c.c
index 9810683f4b..c621445e5c 100644
--- a/drivers/mci/s3c.c
+++ b/drivers/mci/s3c.c
@@ -153,6 +153,7 @@
 #define SDIDATA 0x40
 
 struct s3c_mci_host {
+	void __iomem	*base;
 	int		bus_width:2; /* 0 = 1 bit, 1 = 4 bit, 2 = 8 bit */
 	unsigned	clock;	/* current clock in Hz */
 	unsigned	data_size;	/* data transfer in bytes */
@@ -211,6 +212,7 @@ static unsigned s3c_setup_clock_speed(struct device_d *hw_dev, unsigned nc)
 {
 	unsigned clock;
 	uint32_t mci_psc;
+	struct s3c_mci_host *host_data = GET_HOST_DATA(hw_dev);
 
 	if (nc == 0)
 		return 0;
@@ -224,7 +226,7 @@ static unsigned s3c_setup_clock_speed(struct device_d *hw_dev, unsigned nc)
 		pr_warning("SD/MMC clock might be too high!\n");
 	}
 
-	writel(mci_psc - 1, hw_dev->map_base + SDIPRE);
+	writel(mci_psc - 1, host_data->base + SDIPRE);
 
 	return clock / mci_psc;
 }
@@ -237,10 +239,12 @@ static unsigned s3c_setup_clock_speed(struct device_d *hw_dev, unsigned nc)
  */
 static void s3c_mci_reset(struct device_d *hw_dev)
 {
+	struct s3c_mci_host *host_data = GET_HOST_DATA(hw_dev);
+
 	/* reset the hardware */
-	writel(SDICON_SDRESET, hw_dev->map_base + SDICON);
+	writel(SDICON_SDRESET, host_data->base + SDICON);
 	/* wait until reset it finished */
-	while (readl(hw_dev->map_base + SDICON) & SDICON_SDRESET)
+	while (readl(host_data->base + SDICON) & SDICON_SDRESET)
 		;
 }
 
@@ -257,9 +261,9 @@ static int s3c_mci_initialize(struct device_d *hw_dev, struct device_d *mci_dev)
 
 	/* restore last settings */
 	host_data->clock = s3c_setup_clock_speed(hw_dev, host_data->clock);
-	writel(0x007FFFFF, hw_dev->map_base + SDITIMER);
-	writel(SDICON_MMCCLOCK, hw_dev->map_base + SDICON);
-	writel(512, hw_dev->map_base + SDIBSIZE);
+	writel(0x007FFFFF, host_data->base + SDITIMER);
+	writel(SDICON_MMCCLOCK, host_data->base + SDICON);
+	writel(512, host_data->base + SDIBSIZE);
 
 	return 0;
 }
@@ -335,11 +339,12 @@ static uint32_t s3c_prepare_data_setup(struct device_d *hw_dev, unsigned data_fl
 static int s3c_terminate_transfer(struct device_d *hw_dev)
 {
 	unsigned stoptries = 3;
+	struct s3c_mci_host *host_data = GET_HOST_DATA(hw_dev);
 
-	while (readl(hw_dev->map_base + SDIDSTA) & (SDIDSTA_TXDATAON | SDIDSTA_RXDATAON)) {
+	while (readl(host_data->base + SDIDSTA) & (SDIDSTA_TXDATAON | SDIDSTA_RXDATAON)) {
 		pr_debug("Transfer still in progress.\n");
 
-		writel(SDIDCON_STOP, hw_dev->map_base + SDIDCON);
+		writel(SDIDCON_STOP, host_data->base + SDIDCON);
 		s3c_mci_initialize(hw_dev, NULL);
 
 		if ((stoptries--) == 0) {
@@ -360,12 +365,13 @@ static int s3c_terminate_transfer(struct device_d *hw_dev)
 static int s3c_prepare_data_transfer(struct device_d *hw_dev, struct mci_data *data)
 {
 	uint32_t reg;
+	struct s3c_mci_host *host_data = GET_HOST_DATA(hw_dev);
 
-	writel(data->blocksize, hw_dev->map_base + SDIBSIZE);
+	writel(data->blocksize, host_data->base + SDIBSIZE);
 	reg = s3c_prepare_data_setup(hw_dev, data->flags);
 	reg |= data->blocks & SDIDCON_BLKNUM;
-	writel(reg, hw_dev->map_base + SDIDCON);
-	writel(0x007FFFFF, hw_dev->map_base + SDITIMER);
+	writel(reg, host_data->base + SDIDCON);
+	writel(0x007FFFFF, host_data->base + SDITIMER);
 
 	return 0;
 }
@@ -382,34 +388,35 @@ static int s3c_send_command(struct device_d *hw_dev, struct mci_cmd *cmd,
 {
 	uint32_t reg, t1;
 	int rc;
+	struct s3c_mci_host *host_data = GET_HOST_DATA(hw_dev);
 
-	writel(0x007FFFFF, hw_dev->map_base + SDITIMER);
+	writel(0x007FFFFF, host_data->base + SDITIMER);
 
 	/* setup argument */
-	writel(cmd->cmdarg, hw_dev->map_base + SDICMDARG);
+	writel(cmd->cmdarg, host_data->base + SDICMDARG);
 
 	/* setup command and transfer characteristic */
 	reg = s3c_prepare_command_setup(cmd->resp_type, data != NULL ? data->flags : 0);
 	reg |= cmd->cmdidx & SDICMDCON_INDEX;
 
 	/* run the command right now */
-	writel(reg | SDICMDCON_CMDSTART, hw_dev->map_base + SDICMDCON);
-	t1 = readl(hw_dev->map_base + SDICMDSTAT);
+	writel(reg | SDICMDCON_CMDSTART, host_data->base + SDICMDCON);
+	t1 = readl(host_data->base + SDICMDSTAT);
 	/* wait until command is done */
 	while (1) {
-		reg = readl(hw_dev->map_base + SDICMDSTAT);
+		reg = readl(host_data->base + SDICMDSTAT);
 		/* done? */
 		if (cmd->resp_type & MMC_RSP_PRESENT) {
 			if (reg & SDICMDSTAT_RSPFIN) {
 				writel(SDICMDSTAT_RSPFIN,
-					hw_dev->map_base + SDICMDSTAT);
+					host_data->base + SDICMDSTAT);
 				rc = 0;
 				break;
 			}
 		} else {
 			if (reg & SDICMDSTAT_CMDSENT) {
 					writel(SDICMDSTAT_CMDSENT,
-						hw_dev->map_base + SDICMDSTAT);
+						host_data->base + SDICMDSTAT);
 					rc = 0;
 					break;
 			}
@@ -417,17 +424,17 @@ static int s3c_send_command(struct device_d *hw_dev, struct mci_cmd *cmd,
 		/* timeout? */
 		if (reg & SDICMDSTAT_CMDTIMEOUT) {
 			writel(SDICMDSTAT_CMDTIMEOUT,
-				hw_dev->map_base + SDICMDSTAT);
+				host_data->base + SDICMDSTAT);
 			rc = -ETIMEDOUT;
 			break;
 		}
 	}
 
 	if ((rc == 0) && (cmd->resp_type & MMC_RSP_PRESENT)) {
-		cmd->response[0] = readl(hw_dev->map_base + SDIRSP0);
-		cmd->response[1] = readl(hw_dev->map_base + SDIRSP1);
-		cmd->response[2] = readl(hw_dev->map_base + SDIRSP2);
-		cmd->response[3] = readl(hw_dev->map_base + SDIRSP3);
+		cmd->response[0] = readl(host_data->base + SDIRSP0);
+		cmd->response[1] = readl(host_data->base + SDIRSP1);
+		cmd->response[2] = readl(host_data->base + SDIRSP2);
+		cmd->response[3] = readl(host_data->base + SDIRSP3);
 	}
 	/* do not disable the clock! */
 	return rc;
@@ -443,14 +450,15 @@ static int s3c_send_command(struct device_d *hw_dev, struct mci_cmd *cmd,
 static int s3c_prepare_engine(struct device_d *hw_dev)
 {
 	int rc;
+	struct s3c_mci_host *host_data = GET_HOST_DATA(hw_dev);
 
 	rc = s3c_terminate_transfer(hw_dev);
 	if (rc != 0)
 		return rc;
 
-	writel(-1, hw_dev->map_base + SDICMDSTAT);
-	writel(-1, hw_dev->map_base + SDIDSTA);
-	writel(-1, hw_dev->map_base + SDIFSTA);
+	writel(-1, host_data->base + SDICMDSTAT);
+	writel(-1, host_data->base + SDIDSTA);
+	writel(-1, host_data->base + SDIFSTA);
 
 	return 0;
 }
@@ -487,6 +495,7 @@ static int s3c_mci_read_block(struct device_d *hw_dev, struct mci_data *data)
 {
 	uint32_t *p;
 	unsigned cnt, data_size;
+	struct s3c_mci_host *host_data = GET_HOST_DATA(hw_dev);
 
 #define READ_REASON_TO_FAIL (SDIDSTA_CRCFAIL | SDIDSTA_RXCRCFAIL | SDIDSTA_DATATIMEOUT)
 
@@ -496,23 +505,23 @@ static int s3c_mci_read_block(struct device_d *hw_dev, struct mci_data *data)
 	while (data_size > 0) {
 
 		/* serious error? */
-		if (readl(hw_dev->map_base + SDIDSTA) & READ_REASON_TO_FAIL) {
+		if (readl(host_data->base + SDIDSTA) & READ_REASON_TO_FAIL) {
 			pr_err("Failed while reading data\n");
 			return -EIO;
 		}
 
 		/* now check the FIFO status */
-		if (readl(hw_dev->map_base + SDIFSTA) & SDIFSTA_FIFOFAIL) {
+		if (readl(host_data->base + SDIFSTA) & SDIFSTA_FIFOFAIL) {
 			pr_err("Data loss due to FIFO overflow when reading\n");
 			return -EIO;
 		}
 
 		/* we only want to read full words */
-		cnt = (readl(hw_dev->map_base + SDIFSTA) & SDIFSTA_COUNTMASK) >> 2;
+		cnt = (readl(host_data->base + SDIFSTA) & SDIFSTA_COUNTMASK) >> 2;
 
 		/* read one chunk of data from the FIFO */
 		while (cnt--) {
-			*p = readl(hw_dev->map_base + SDIDATA);
+			*p = readl(host_data->base + SDIDATA);
 			p++;
 			if (data_size >= 4)
 				data_size -= 4;
@@ -542,6 +551,7 @@ static int s3c_mci_write_block(struct device_d *hw_dev, struct mci_cmd *cmd,
 	const uint32_t *p = (const uint32_t*)data->src;
 	unsigned cnt, data_size;
 	uint32_t reg;
+	struct s3c_mci_host *host_data = GET_HOST_DATA(hw_dev);
 
 #define WRITE_REASON_TO_FAIL (SDIDSTA_CRCFAIL | SDIDSTA_DATATIMEOUT)
 
@@ -553,7 +563,7 @@ static int s3c_mci_write_block(struct device_d *hw_dev, struct mci_cmd *cmd,
 	 */
 	cnt = 16;
 	while (cnt--) {
-		writel(*p, hw_dev->map_base + SDIDATA);
+		writel(*p, host_data->base + SDIDATA);
 		p++;
 		if (data_size >= 4)
 			data_size -= 4;
@@ -566,7 +576,7 @@ static int s3c_mci_write_block(struct device_d *hw_dev, struct mci_cmd *cmd,
 	/* data is now in place and waits for transmitt. Start the command right now */
 	s3c_send_command(hw_dev, cmd, data);
 
-	if ((reg = readl(hw_dev->map_base + SDIFSTA)) & SDIFSTA_FIFOFAIL) {
+	if ((reg = readl(host_data->base + SDIFSTA)) & SDIFSTA_FIFOFAIL) {
 		pr_err("Command fails immediatly due to FIFO underrun when writing %08X\n",
 			reg);
 		return -EIO;
@@ -574,24 +584,24 @@ static int s3c_mci_write_block(struct device_d *hw_dev, struct mci_cmd *cmd,
 
 	while (data_size > 0) {
 
-		if (readl(hw_dev->map_base + SDIDSTA) & WRITE_REASON_TO_FAIL) {
+		if (readl(host_data->base + SDIDSTA) & WRITE_REASON_TO_FAIL) {
 			pr_err("Failed writing data\n");
 			return -EIO;
 		}
 
 		/* now check the FIFO status */
-		if ((reg = readl(hw_dev->map_base + SDIFSTA)) & SDIFSTA_FIFOFAIL) {
+		if ((reg = readl(host_data->base + SDIFSTA)) & SDIFSTA_FIFOFAIL) {
 			pr_err("Data loss due to FIFO underrun when writing %08X\n",
 					reg);
 			return -EIO;
 		}
 
 		/* we only want to write full words */
-		cnt = 16 - (((readl(hw_dev->map_base + SDIFSTA) & SDIFSTA_COUNTMASK) + 3) >> 2);
+		cnt = 16 - (((readl(host_data->base + SDIFSTA) & SDIFSTA_COUNTMASK) + 3) >> 2);
 
 		/* fill the FIFO if it has free entries */
 		while (cnt--) {
-			writel(*p, hw_dev->map_base + SDIDATA);
+			writel(*p, host_data->base + SDIDATA);
 			p++;
 			if (data_size >= 4)
 				data_size -= 4;
@@ -616,6 +626,7 @@ static int s3c_mci_adtc(struct device_d *hw_dev, struct mci_cmd *cmd,
 			struct mci_data *data)
 {
 	int rc;
+	struct s3c_mci_host *host_data = GET_HOST_DATA(hw_dev);
 
 	rc = s3c_prepare_engine(hw_dev);
 	if (rc != 0)
@@ -629,7 +640,7 @@ static int s3c_mci_adtc(struct device_d *hw_dev, struct mci_cmd *cmd,
 		s3c_send_command(hw_dev, cmd, data);
 		rc = s3c_mci_read_block(hw_dev, data);
 		if (rc == 0) {
-			while (!(readl(hw_dev->map_base + SDIDSTA) & SDIDSTA_XFERFINISH))
+			while (!(readl(host_data->base + SDIDSTA) & SDIDSTA_XFERFINISH))
 				;
 		} else
 			s3c_terminate_transfer(hw_dev);
@@ -638,12 +649,12 @@ static int s3c_mci_adtc(struct device_d *hw_dev, struct mci_cmd *cmd,
 	if (data->flags & MMC_DATA_WRITE) {
 		rc = s3c_mci_write_block(hw_dev, cmd, data);
 		if (rc == 0) {
-			while (!(readl(hw_dev->map_base + SDIDSTA) & SDIDSTA_XFERFINISH))
+			while (!(readl(host_data->base + SDIDSTA) & SDIDSTA_XFERFINISH))
 				;
 		} else
 			s3c_terminate_transfer(hw_dev);
 	}
-	writel(0, hw_dev->map_base + SDIDCON);
+	writel(0, host_data->base + SDIDCON);
 
 	return rc;
 }
@@ -674,11 +685,12 @@ static int mci_request(struct mci_host *mci_pdata, struct mci_cmd *cmd,
 			struct mci_data *data)
 {
 	struct device_d *hw_dev = mci_pdata->hw_dev;
+	struct s3c_mci_host *host_data = GET_HOST_DATA(hw_dev);
 	int rc;
 
 	/* enable clock */
-	writel(readl(hw_dev->map_base + SDICON) | SDICON_CLKEN,
-		hw_dev->map_base + SDICON);
+	writel(readl(host_data->base + SDICON) | SDICON_CLKEN,
+		host_data->base + SDICON);
 
 	if ((cmd->resp_type == 0) || (data == NULL))
 		rc = s3c_mci_std_cmds(hw_dev, cmd);
@@ -688,8 +700,8 @@ static int mci_request(struct mci_host *mci_pdata, struct mci_cmd *cmd,
 	s3c_finish_request(hw_dev);
 
 	/* disable clock */
-	writel(readl(hw_dev->map_base + SDICON) & ~SDICON_CLKEN,
-		hw_dev->map_base + SDICON);
+	writel(readl(host_data->base + SDICON) & ~SDICON_CLKEN,
+		host_data->base + SDICON);
 	return rc;
 }
 
@@ -720,7 +732,7 @@ static void mci_set_ios(struct mci_host *mci_pdata, struct device_d *mci_dev,
 		break;
 	}
 
-	reg = readl(hw_dev->map_base + SDICON);
+	reg = readl(host_data->base + SDICON);
 	if (clock) {
 		/* setup the IO clock frequency and enable it */
 		host->clock = host_data->clock = s3c_setup_clock_speed(hw_dev, clock);
@@ -729,7 +741,7 @@ static void mci_set_ios(struct mci_host *mci_pdata, struct device_d *mci_dev,
 		reg &= ~SDICON_CLKEN;	/* disable the clock */
 		host->clock = host_data->clock = 0;
 	}
-	writel(reg, hw_dev->map_base + SDICON);
+	writel(reg, host_data->base + SDICON);
 
 	pr_debug("IO settings: bus width=%d, frequency=%u Hz\n",
 		host->bus_width, host->clock);
@@ -783,6 +795,7 @@ static int s3c_mci_probe(struct device_d *hw_dev)
 	}
 
 	hw_dev->priv = &host_data;
+	host_data.base = dev_request_mem_region(hw_dev, 0);
 	mci_pdata.hw_dev = hw_dev;
 
 	/* feed forward the platform specific values */
@@ -795,7 +808,7 @@ static int s3c_mci_probe(struct device_d *hw_dev)
 	 * Start the clock to let the engine and the card finishes its startup
 	 */
 	host_data.clock = s3c_setup_clock_speed(hw_dev, mci_pdata.f_min);
-	writel(SDICON_FIFORESET | SDICON_MMCCLOCK, hw_dev->map_base + SDICON);
+	writel(SDICON_FIFORESET | SDICON_MMCCLOCK, host_data.base + SDICON);
 
 	return mci_register(&mci_pdata);
 }
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index e8f85fc621..f79be9a3c6 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -381,7 +381,7 @@ static int __init atmel_nand_probe(struct device_d *dev)
 	if (!host)
 		return -ENOMEM;
 
-	host->io_base = (void __iomem *)dev->map_base;
+	host->io_base = dev_request_mem_region(dev, 0);
 
 	mtd = &host->mtd;
 	nand_chip = &host->nand_chip;
diff --git a/drivers/mtd/nand/nand_imx.c b/drivers/mtd/nand/nand_imx.c
index a13f32150e..e471c8a719 100644
--- a/drivers/mtd/nand/nand_imx.c
+++ b/drivers/mtd/nand/nand_imx.c
@@ -1034,7 +1034,7 @@ static int __init imxnd_probe(struct device_d *dev)
 		return -ENOMEM;
 
 	host->data_buf = (uint8_t *)(host + 1);
-	host->base = (void __iomem *)dev->map_base;
+	host->base = dev_request_mem_region(dev, 0);
 
 	host->main_area0 = host->base;
 
diff --git a/drivers/mtd/nand/nand_omap_gpmc.c b/drivers/mtd/nand/nand_omap_gpmc.c
index 4a2d561dde..083aa57520 100644
--- a/drivers/mtd/nand/nand_omap_gpmc.c
+++ b/drivers/mtd/nand/nand_omap_gpmc.c
@@ -14,8 +14,8 @@
  * static struct device_d my_nand_device = {
  *	.name = "gpmc_nand",
  *	.id = some identifier you need to show.. e.g. "gpmc_nand0"
- *	.map_base = GPMC base address
- *	.size = GPMC address map size.
+ *	.resource[0].start = GPMC base address
+ *	.resource[0].size = GPMC address map size.
  *	.platform_data = platform data - required - explained below
  * };
  * platform data required:
@@ -97,7 +97,7 @@ struct gpmc_nand_info {
 	void *gpmc_command;
 	void *gpmc_address;
 	void *gpmc_data;
-	unsigned long gpmc_base;
+	void __iomem *gpmc_base;
 	unsigned char wait_mon_mask;
 	uint64_t timeout;
 	unsigned inuse:1;
@@ -672,7 +672,7 @@ static int gpmc_nand_probe(struct device_d *pdev)
 	struct gpmc_nand_platform_data *pdata;
 	struct nand_chip *nand;
 	struct mtd_info *minfo;
-	unsigned long cs_base;
+	void __iomem *cs_base;
 	int err;
 	struct nand_ecclayout *layout, *lsp, *llp;
 
@@ -703,7 +703,7 @@ static int gpmc_nand_probe(struct device_d *pdev)
 	}
 	/* Setup register specific data */
 	oinfo->gpmc_cs = pdata->cs;
-	oinfo->gpmc_base = pdev->map_base;
+	oinfo->gpmc_base = dev_request_mem_region(pdev, 0);
 	cs_base = oinfo->gpmc_base + GPMC_CONFIG1_0 +
 		(pdata->cs * GPMC_CONFIG_CS_SIZE);
 	oinfo->gpmc_command = (void *)(cs_base + GPMC_CS_NAND_COMMAND);
diff --git a/drivers/mtd/nand/nand_s3c2410.c b/drivers/mtd/nand/nand_s3c2410.c
index 88e89cd336..0ce20d42c3 100644
--- a/drivers/mtd/nand/nand_s3c2410.c
+++ b/drivers/mtd/nand/nand_s3c2410.c
@@ -422,7 +422,7 @@ static int s3c24x0_nand_probe(struct device_d *dev)
 		return -ENOMEM;
 
 	host->dev = dev;
-	host->base = IOMEM(dev->map_base);
+	host->base = dev_request_mem_region(dev, 0);
 
 	/* structures must be linked */
 	chip = &host->nand;
@@ -435,7 +435,7 @@ static int s3c24x0_nand_probe(struct device_d *dev)
 	chip->chip_delay = 50;
 	chip->priv = host;
 
-	chip->IO_ADDR_R = chip->IO_ADDR_W = IOMEM(dev->map_base + NFDATA);
+	chip->IO_ADDR_R = chip->IO_ADDR_W = host->base + NFDATA;
 
 #ifdef CONFIG_CPU_S3C2440
 	chip->read_buf = s3c2440_nand_read_buf;
diff --git a/drivers/mtd/nand/nomadik_nand.c b/drivers/mtd/nand/nomadik_nand.c
index 673fd88bab..3073011614 100644
--- a/drivers/mtd/nand/nomadik_nand.c
+++ b/drivers/mtd/nand/nomadik_nand.c
@@ -189,8 +189,8 @@ static int nomadik_nand_probe(struct device_d *dev)
 		goto err;
 	}
 
-	host->cmd_va = (void __iomem*)pdata->cmd_va;
-	host->addr_va = (void __iomem*)pdata->addr_va;
+	host->cmd_va = dev_request_mem_region(dev, 1);
+	host->addr_va = dev_request_mem_region(dev, 0);
 
 	/* Link all private pointers */
 	mtd = &host->mtd;
@@ -198,8 +198,7 @@ static int nomadik_nand_probe(struct device_d *dev)
 	mtd->priv = nand;
 	nand->priv = host;
 
-	nand->IO_ADDR_R = (void __iomem*)pdata->data_va;
-	nand->IO_ADDR_W = (void __iomem*)pdata->data_va;
+	nand->IO_ADDR_W = nand->IO_ADDR_R = dev_request_mem_region(dev, 2);
 	nand->cmd_ctrl = nomadik_cmd_ctrl;
 
 	nand->ecc.mode = NAND_ECC_HW;
diff --git a/drivers/net/altera_tse.c b/drivers/net/altera_tse.c
index ac8cd2de98..e7dabda5d1 100644
--- a/drivers/net/altera_tse.c
+++ b/drivers/net/altera_tse.c
@@ -221,7 +221,7 @@ static int alt_sgdma_do_async_transfer(struct alt_sgdma_registers *dev,
 static int tse_get_ethaddr(struct eth_device *edev, unsigned char *m)
 {
 	struct altera_tse_priv *priv = edev->priv;
-	struct alt_tse_mac *mac_dev = priv->mac_dev;
+	struct alt_tse_mac *mac_dev = priv->tse_regs;
 
 	m[5] = (readl(&mac_dev->mac_addr_1) >> 8)  && 0xFF;
 	m[4] = (readl(&mac_dev->mac_addr_1))       && 0xFF;
@@ -236,7 +236,7 @@ static int tse_get_ethaddr(struct eth_device *edev, unsigned char *m)
 static int tse_set_ethaddr(struct eth_device *edev, unsigned char *m)
 {
 	struct altera_tse_priv *priv = edev->priv;
-	struct alt_tse_mac *mac_dev = priv->mac_dev;
+	struct alt_tse_mac *mac_dev = priv->tse_regs;
 
 	debug("Setting MAC address to %02x:%02x:%02x:%02x:%02x:%02x\n",
 		m[0], m[1], m[2], m[3], m[4], m[5]);
@@ -250,10 +250,10 @@ static int tse_set_ethaddr(struct eth_device *edev, unsigned char *m)
 static int tse_phy_read(struct mii_device *mdev, int phy_addr, int reg)
 {
 	struct eth_device *edev = mdev->edev;
-	struct alt_tse_mac *mac_dev;
+	struct altera_tse_priv *priv = edev->priv;
+	struct alt_tse_mac *mac_dev = priv->tse_regs;
 	uint32_t *mdio_regs;
 
-	mac_dev = (struct alt_tse_mac *)edev->iobase;
 	writel(phy_addr, &mac_dev->mdio_phy1_addr);
 
 	mdio_regs = (uint32_t *)&mac_dev->mdio_phy1;
@@ -264,10 +264,10 @@ static int tse_phy_read(struct mii_device *mdev, int phy_addr, int reg)
 static int tse_phy_write(struct mii_device *mdev, int phy_addr, int reg, int val)
 {
 	struct eth_device *edev = mdev->edev;
-	struct alt_tse_mac *mac_dev;
+	struct altera_tse_priv *priv = edev->priv;
+	struct alt_tse_mac *mac_dev = priv->tse_regs;
 	uint32_t *mdio_regs;
 
-	mac_dev = (struct alt_tse_mac *)edev->iobase;
 	writel(phy_addr, &mac_dev->mdio_phy1_addr);
 
 	mdio_regs = (uint32_t *)&mac_dev->mdio_phy1;
@@ -281,11 +281,11 @@ static void tse_reset(struct eth_device *edev)
 {
 	/* stop sgdmas, disable tse receive */
 	struct altera_tse_priv *priv = edev->priv;
-	struct alt_tse_mac *mac_dev = priv->mac_dev;
-	struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx;
-	struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx;
-	struct alt_sgdma_descriptor *rx_desc = (struct alt_sgdma_descriptor *)&priv->rx_desc[0];
-	struct alt_sgdma_descriptor *tx_desc = (struct alt_sgdma_descriptor *)&priv->tx_desc[0];
+	struct alt_tse_mac *mac_dev = priv->tse_regs;
+	struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx_regs;
+	struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx_regs;
+	struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
+	struct alt_sgdma_descriptor *tx_desc = priv->tx_desc;
 	uint64_t start;
 	uint64_t tout;
 
@@ -358,10 +358,9 @@ static int tse_eth_send(struct eth_device *edev, void *packet, int length)
 {
 
 	struct altera_tse_priv *priv = edev->priv;
-	struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx;
-	struct alt_sgdma_descriptor *tx_desc = (struct alt_sgdma_descriptor *)priv->tx_desc;
-
-	struct alt_sgdma_descriptor *tx_desc_cur = (struct alt_sgdma_descriptor *)&tx_desc[0];
+	struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx_regs;
+	struct alt_sgdma_descriptor *tx_desc = priv->tx_desc;
+	struct alt_sgdma_descriptor *tx_desc_cur = tx_desc;
 
 	flush_dcache_range((uint32_t)packet, (uint32_t)packet + length);
 	alt_sgdma_construct_descriptor_burst(
@@ -386,8 +385,8 @@ static int tse_eth_send(struct eth_device *edev, void *packet, int length)
 static void tse_eth_halt(struct eth_device *edev)
 {
 	struct altera_tse_priv *priv = edev->priv;
-	struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx;
-	struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx;
+	struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx_regs;
+	struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx_regs;
 
 	writel(0, &rx_sgdma->control); /* Stop the controller and reset settings */
 	writel(0, &tx_sgdma->control); /* Stop the controller and reset settings */
@@ -398,9 +397,9 @@ static int tse_eth_rx(struct eth_device *edev)
 	uint16_t packet_length = 0;
 
 	struct altera_tse_priv *priv = edev->priv;
-	struct alt_sgdma_descriptor *rx_desc = (struct alt_sgdma_descriptor *)priv->rx_desc;
-	struct alt_sgdma_descriptor *rx_desc_cur = &rx_desc[0];
-	struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx;
+	struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
+	struct alt_sgdma_descriptor *rx_desc_cur = rx_desc;
+	struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx_regs;
 
 	if (rx_desc_cur->descriptor_status &
 		ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK) {
@@ -428,7 +427,7 @@ static int tse_eth_rx(struct eth_device *edev)
 		);
 
 		/* setup the sgdma */
-		alt_sgdma_do_async_transfer(priv->sgdma_rx, &rx_desc[0]);
+		alt_sgdma_do_async_transfer(priv->sgdma_rx_regs, rx_desc);
 	}
 
 	return 0;
@@ -437,12 +436,12 @@ static int tse_eth_rx(struct eth_device *edev)
 static int tse_init_dev(struct eth_device *edev)
 {
 	struct altera_tse_priv *priv = edev->priv;
-	struct alt_tse_mac *mac_dev = priv->mac_dev;
+	struct alt_tse_mac *mac_dev = priv->tse_regs;
 	struct alt_sgdma_descriptor *tx_desc = priv->tx_desc;
 	struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
 	struct alt_sgdma_descriptor *rx_desc_cur;
 
-	rx_desc_cur = (struct alt_sgdma_descriptor *)&rx_desc[0];
+	rx_desc_cur = rx_desc;
 
 	tse_reset(edev);
 
@@ -477,7 +476,7 @@ static int tse_init_dev(struct eth_device *edev)
 		);
 
 	/* start rx async transfer */
-	alt_sgdma_do_async_transfer(priv->sgdma_rx, rx_desc_cur);
+	alt_sgdma_do_async_transfer(priv->sgdma_rx_regs, rx_desc_cur);
 
 	/* Initialize MAC registers */
 	writel(PKTSIZE, &mac_dev->max_frame_length);
@@ -504,15 +503,13 @@ static int tse_probe(struct device_d *dev)
 #ifndef CONFIG_TSE_USE_DEDICATED_DESC_MEM
 	uint32_t dma_handle;
 #endif
-	edev = xzalloc(sizeof(struct eth_device) + sizeof(struct altera_tse_priv));
+	edev = xzalloc(sizeof(struct eth_device));
+	priv = xzalloc(sizeof(struct altera_tse_priv));
 	miidev = xzalloc(sizeof(struct mii_device));
 
 	dev->type_data = edev;
-	edev->priv = (struct altera_tse_priv *)(edev + 1);
-
-	edev->iobase = dev->map_base;
 
-	priv = edev->priv;
+	edev->priv = priv;
 
 	edev->init = tse_init_dev;
 	edev->open = tse_eth_open;
@@ -523,7 +520,7 @@ static int tse_probe(struct device_d *dev)
 	edev->set_ethaddr = tse_set_ethaddr;
 
 #ifdef CONFIG_TSE_USE_DEDICATED_DESC_MEM
-	tx_desc = (struct alt_sgdma_descriptor *)NIOS_SOPC_TSE_DESC_MEM_BASE;
+	tx_desc = dev_request_mem_region(dev, 3);
 	rx_desc = tx_desc + 2;
 #else
 	tx_desc = dma_alloc_coherent(sizeof(*tx_desc) * (3 + PKTBUFSRX), (unsigned long *)&dma_handle);
@@ -539,9 +536,9 @@ static int tse_probe(struct device_d *dev)
 	memset(rx_desc, 0, (sizeof *rx_desc) * (PKTBUFSRX + 1)); 
 	memset(tx_desc, 0, (sizeof *tx_desc) * 2);
 
-	priv->mac_dev = (struct alt_tse_mac *)dev->map_base;
-	priv->sgdma_rx = (struct alt_sgdma_registers *)NIOS_SOPC_SGDMA_RX_BASE;
-	priv->sgdma_tx = (struct alt_sgdma_registers *)NIOS_SOPC_SGDMA_TX_BASE;
+	priv->tse_regs = dev_request_mem_region(dev, 0);
+	priv->sgdma_rx_regs = dev_request_mem_region(dev, 1);
+	priv->sgdma_tx_regs = dev_request_mem_region(dev, 2);
 	priv->rx_desc = rx_desc;
 	priv->tx_desc = tx_desc;
 
diff --git a/drivers/net/altera_tse.h b/drivers/net/altera_tse.h
index c907c742db..866dbce8c3 100644
--- a/drivers/net/altera_tse.h
+++ b/drivers/net/altera_tse.h
@@ -287,16 +287,11 @@ struct alt_tse_mac {
 };
 
 struct altera_tse_priv {
-	struct alt_tse_mac *mac_dev;
-	struct alt_sgdma_registers *sgdma_rx;
-	struct alt_sgdma_registers *sgdma_tx;
-	unsigned int rx_sgdma_irq;
-	unsigned int tx_sgdma_irq;
-	unsigned int has_descriptor_mem;
-	unsigned int descriptor_mem_base;
-	unsigned int descriptor_mem_size;
-	struct alt_sgdma_descriptor *rx_desc;
-	struct alt_sgdma_descriptor *tx_desc;
+	void __iomem *tse_regs;
+	void __iomem *sgdma_rx_regs;
+	void __iomem *sgdma_tx_regs;
+	void __iomem *rx_desc;
+	void __iomem *tx_desc;
 	struct mii_device *miidev;
 };
 
diff --git a/drivers/net/cs8900.c b/drivers/net/cs8900.c
index de6d038674..d954e39d7b 100644
--- a/drivers/net/cs8900.c
+++ b/drivers/net/cs8900.c
@@ -441,7 +441,7 @@ static int cs8900_probe(struct device_d *dev)
 	debug("cs8900_init()\n");
 
 	priv = (struct cs8900_priv *)xmalloc(sizeof(*priv));
-	priv->regs = (u16 *)dev->map_base;
+	priv->regs = dev_request_mem_region(dev, 0);
 	if (cs8900_check_id(priv)) {
 		free(priv);
 		return -1;
diff --git a/drivers/net/dm9000.c b/drivers/net/dm9000.c
index c8d851781d..be14317eff 100644
--- a/drivers/net/dm9000.c
+++ b/drivers/net/dm9000.c
@@ -294,16 +294,16 @@ static int dm9000_eth_send (struct eth_device *edev,
 	writeb(DM9000_MWCMD, priv->iobase);
 
 	switch (priv->buswidth) {
-	case DM9000_WIDTH_8:
+	case IORESOURCE_MEM_8BIT:
 		for (i = 0; i < length; i++)
 			writeb(data_ptr[i] & 0xff, priv->iodata);
 		break;
-	case DM9000_WIDTH_16:
+	case IORESOURCE_MEM_16BIT:
 		tmplen = (length + 1) / 2;
 		for (i = 0; i < tmplen; i++)
 			writew(((u16 *)data_ptr)[i], priv->iodata);
 		break;
-	case DM9000_WIDTH_32:
+	case IORESOURCE_MEM_32BIT:
 		tmplen = (length + 3) / 4;
 		for (i = 0; i < tmplen; i++)
 			writel(((u32 *) data_ptr)[i], priv->iodata);
@@ -371,20 +371,20 @@ static int dm9000_eth_rx (struct eth_device *edev)
 	/* Move data from DM9000 */
 	/* Read received packet from RX SRAM */
 	switch (priv->buswidth) {
-	case DM9000_WIDTH_8:
+	case IORESOURCE_MEM_8BIT:
 		RxStatus = readb(priv->iodata) + (readb(priv->iodata) << 8);
 		RxLen = readb(priv->iodata) + (readb(priv->iodata) << 8);
 		for (i = 0; i < RxLen; i++)
 			rdptr[i] = readb(priv->iodata);
 		break;
-	case DM9000_WIDTH_16:
+	case IORESOURCE_MEM_16BIT:
 		RxStatus = readw(priv->iodata);
 		RxLen = readw(priv->iodata);
 		tmplen = (RxLen + 1) / 2;
 		for (i = 0; i < tmplen; i++)
 			((u16 *) rdptr)[i] = readw(priv->iodata);
 		break;
-	case DM9000_WIDTH_32:
+	case IORESOURCE_MEM_32BIT:
 		tmpdata = readl(priv->iodata);
 		RxStatus = tmpdata;
 		RxLen = tmpdata >> 16;
@@ -491,12 +491,19 @@ static int dm9000_probe(struct device_d *dev)
 		printf("dm9000: no platform_data\n");
 		return -ENODEV;
 	}
+
+	if (dev->num_resources < 2) {
+		printf("dm9000: need 2 resources base and data");
+		return -ENODEV;
+	}
+
 	pdata = dev->platform_data;
 
 	priv = edev->priv;
-	priv->buswidth = pdata->buswidth;
-	priv->iodata = (void *)pdata->iodata;
-	priv->iobase = (void *)pdata->iobase;
+
+	priv->buswidth = dev->resource[0].flags & IORESOURCE_MEM_TYPE_MASK;
+	priv->iodata = dev_request_mem_region(dev, 1);
+	priv->iobase = dev_request_mem_region(dev, 0);
 	priv->srom = pdata->srom;
 
 	edev->init = dm9000_init_dev;
diff --git a/drivers/net/fec_imx.c b/drivers/net/fec_imx.c
index c1aa594fe1..8b4f439745 100644
--- a/drivers/net/fec_imx.c
+++ b/drivers/net/fec_imx.c
@@ -200,25 +200,11 @@ static void imx28_fix_endianess_rd(uint32_t *buf, unsigned wlen)
 static int fec_rbd_init(struct fec_priv *fec, int count, int size)
 {
 	int ix;
-	static int once = 0;
-	unsigned long p = 0;
-
-	if (!once) {
-		/* reserve data memory and consider alignment */
-		p = (unsigned long)dma_alloc_coherent(size * count + DB_DATA_ALIGNMENT);
-		p += DB_DATA_ALIGNMENT - 1;
-		p &= ~(DB_DATA_ALIGNMENT - 1);
-	}
 
 	for (ix = 0; ix < count; ix++) {
-		if (!once) {
-			writel(virt_to_phys((void *)p), &fec->rbd_base[ix].data_pointer);
-			p += size;
-		}
 		writew(FEC_RBD_EMPTY, &fec->rbd_base[ix].status);
 		writew(0, &fec->rbd_base[ix].data_length);
 	}
-	once = 1;	/* malloc done now (and once) */
 	/*
 	 * mark the last RBD to close the ring
 	 */
@@ -269,11 +255,7 @@ static void fec_rbd_clean(int last, struct buffer_descriptor __iomem *pRbd)
 
 static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac)
 {
-#ifdef CONFIG_ARCH_MXS
 	return -1;
-#else
-	return imx_iim_get_mac(mac);
-#endif
 }
 
 static int fec_set_hwaddr(struct eth_device *dev, unsigned char *mac)
@@ -592,18 +574,36 @@ static int fec_recv(struct eth_device *dev)
 	return len;
 }
 
+static int fec_alloc_receive_packets(struct fec_priv *fec, int count, int size)
+{
+	void *p;
+	int i;
+
+	/* reserve data memory and consider alignment */
+	p = dma_alloc_coherent(size * count);
+	if (!p)
+		return -ENOMEM;
+
+	for (i = 0; i < count; i++) {
+		writel(virt_to_phys(p), &fec->rbd_base[i].data_pointer);
+		p += size;
+	}
+
+	return 0;
+}
+
 static int fec_probe(struct device_d *dev)
 {
         struct fec_platform_data *pdata = (struct fec_platform_data *)dev->platform_data;
         struct eth_device *edev;
 	struct fec_priv *fec;
-	uint32_t base;
+	void *base;
 #ifdef CONFIG_ARCH_IMX27
 	PCCR0 |= PCCR0_FEC_EN;
 #endif
-	edev = (struct eth_device *)xzalloc(sizeof(struct eth_device));
+	fec = xzalloc(sizeof(*fec));
+	edev = &fec->edev;
 	dev->type_data = edev;
-	fec = (struct fec_priv *)xzalloc(sizeof(*fec));
 	edev->priv = fec;
 	edev->open = fec_open;
 	edev->init = fec_init;
@@ -613,7 +613,7 @@ static int fec_probe(struct device_d *dev)
 	edev->get_ethaddr = fec_get_hwaddr;
 	edev->set_ethaddr = fec_set_hwaddr;
 
-	fec->regs = (void *)dev->map_base;
+	fec->regs = dev_request_mem_region(dev, 0);
 
 	/* Reset chip. */
 	writel(FEC_ECNTRL_RESET, fec->regs + FEC_ECNTRL);
@@ -625,18 +625,16 @@ static int fec_probe(struct device_d *dev)
 	 * reserve memory for both buffer descriptor chains at once
 	 * Datasheet forces the startaddress of each chain is 16 byte aligned
 	 */
-	base = (uint32_t)dma_alloc_coherent((2 + FEC_RBD_NUM) *
-			sizeof(struct buffer_descriptor) + 2 * DB_ALIGNMENT);
-	base += (DB_ALIGNMENT - 1);
-	base &= ~(DB_ALIGNMENT - 1);
-	fec->rbd_base = (struct buffer_descriptor __force __iomem *)base;
-	base += FEC_RBD_NUM * sizeof (struct buffer_descriptor) +
-		(DB_ALIGNMENT - 1);
-	base &= ~(DB_ALIGNMENT - 1);
-	fec->tbd_base = (struct buffer_descriptor __force __iomem *)base;
-
-	writel((uint32_t)virt_to_phys(fec->tbd_base), fec->regs + FEC_ETDSR);
-	writel((uint32_t)virt_to_phys(fec->rbd_base), fec->regs + FEC_ERDSR);
+	base = dma_alloc_coherent((2 + FEC_RBD_NUM) *
+			sizeof(struct buffer_descriptor));
+	fec->rbd_base = base;
+	base += FEC_RBD_NUM * sizeof(struct buffer_descriptor);
+	fec->tbd_base = base;
+
+	writel(virt_to_phys(fec->tbd_base), fec->regs + FEC_ETDSR);
+	writel(virt_to_phys(fec->rbd_base), fec->regs + FEC_ERDSR);
+
+	fec_alloc_receive_packets(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
 
 	fec->xcv_type = pdata->xcv_type;
 
@@ -664,7 +662,7 @@ static void fec_remove(struct device_d *dev)
 /**
  * Driver description for registering
  */
-static struct driver_d imx27_driver = {
+static struct driver_d fec_driver = {
         .name   = "fec_imx",
         .probe  = fec_probe,
 	.remove = fec_remove,
@@ -672,7 +670,7 @@ static struct driver_d imx27_driver = {
 
 static int fec_register(void)
 {
-        register_driver(&imx27_driver);
+        register_driver(&fec_driver);
         return 0;
 }
 
diff --git a/drivers/net/fec_imx.h b/drivers/net/fec_imx.h
index e07071a883..19f4709a77 100644
--- a/drivers/net/fec_imx.h
+++ b/drivers/net/fec_imx.h
@@ -144,6 +144,7 @@ struct buffer_descriptor {
  * @brief i.MX27-FEC private structure
  */
 struct fec_priv {
+	struct eth_device edev;
 	void __iomem *regs;
 	xceiver_type xcv_type;			/* transceiver type          */
 	struct buffer_descriptor __iomem *rbd_base;	/* RBD ring                  */
diff --git a/drivers/net/fec_mpc5200.c b/drivers/net/fec_mpc5200.c
index 7528316b37..4ebd9067c0 100644
--- a/drivers/net/fec_mpc5200.c
+++ b/drivers/net/fec_mpc5200.c
@@ -673,7 +673,7 @@ int mpc5xxx_fec_probe(struct device_d *dev)
 	edev->get_ethaddr = mpc5xxx_fec_get_ethaddr,
 	edev->set_ethaddr = mpc5xxx_fec_set_ethaddr,
 
-	fec->eth = (ethernet_regs *)dev->map_base;
+	fec->eth = dev_request_mem_region(dev, 0);
 	fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
 	fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
 
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index bc6618bb5b..95ad3d7289 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -85,7 +85,7 @@ struct macb_dma_desc {
 #define TXBUF_USED		0x80000000
 
 struct macb_device {
-	void			*regs;
+	void			__iomem *regs;
 
 	unsigned int		rx_tail;
 	unsigned int		tx_tail;
@@ -446,7 +446,7 @@ static int macb_probe(struct device_d *dev)
 	macb->rx_ring = xmalloc(CFG_MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc));
 	macb->tx_ring = xmalloc(sizeof(struct macb_dma_desc));
 
-	macb->regs = (void *)dev->map_base;
+	macb->regs = dev_request_mem_region(dev, 0);
 
 	/*
 	 * Do some basic initialization so that we at least can talk
diff --git a/drivers/net/smc91111.c b/drivers/net/smc91111.c
index 535e69a1d9..1c1ffea542 100644
--- a/drivers/net/smc91111.c
+++ b/drivers/net/smc91111.c
@@ -1317,7 +1317,7 @@ static int smc91c111_probe(struct device_d *dev)
 	priv->miidev.address = 0;
 	priv->miidev.flags = 0;
 	priv->miidev.edev = edev;
-	priv->base = IOMEM(dev->map_base);
+	priv->base = dev_request_mem_region(dev, 0);
 
 	smc91c111_reset(edev);
 
diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c
index dc5477b93c..8c6f9fc19e 100644
--- a/drivers/net/smc911x.c
+++ b/drivers/net/smc911x.c
@@ -368,8 +368,9 @@
 #define CHIP_9221	0x9221
 
 struct smc911x_priv {
+	struct eth_device edev;
 	struct mii_device miidev;
-	unsigned long base;
+	void __iomem *base;
 };
 
 struct chip_id {
@@ -528,8 +529,8 @@ static void smc911x_reset(struct eth_device *edev)
 			if ((readl(priv->base + PMT_CTRL) & PMT_CTRL_READY))
 				break;
 			if (is_timeout(start, 100 * USECOND)) {
-				printf(DRIVERNAME
-					": timeout waiting for PM restore\n");
+				dev_err(&edev->dev,
+						"timeout waiting for PM restore\n");
 				return;
 			}
 		}
@@ -545,7 +546,7 @@ static void smc911x_reset(struct eth_device *edev)
 		if (!(readl(priv->base + E2P_CMD) & E2P_CMD_EPC_BUSY))
 			break;
 		if (is_timeout(start, 10 * MSECOND)) {
-			printf(DRIVERNAME ": reset timeout\n");
+			dev_err(&edev->dev, "reset timeout\n");
 			return;
 		}
 	}
@@ -610,7 +611,7 @@ static int smc911x_eth_send(struct eth_device *edev, void *packet, int length)
 					TX_FIFO_INF_TSUSED) >> 16)
 			break;
 		if (is_timeout(start, 100 * MSECOND)) {
-			printf("TX timeout\n");
+			dev_err(&edev->dev, "TX timeout\n");
 			return -1;
 		}
 	}
@@ -625,7 +626,7 @@ static int smc911x_eth_send(struct eth_device *edev, void *packet, int length)
 	if(!status)
 		return 0;
 
-	printf(DRIVERNAME ": failed to send packet: %s%s%s%s%s\n",
+	dev_err(&edev->dev, "failed to send packet: %s%s%s%s%s\n",
 		status & TX_STS_LOC ? "TX_STS_LOC " : "",
 		status & TX_STS_LATE_COLL ? "TX_STS_LATE_COLL " : "",
 		status & TX_STS_MANY_COLL ? "TX_STS_MANY_COLL " : "",
@@ -663,8 +664,7 @@ static int smc911x_eth_rx(struct eth_device *edev)
 			*data++ = readl(priv->base + RX_DATA_FIFO);
 
 		if(status & RX_STS_ES)
-			printf(DRIVERNAME
-				": dropped bad packet. Status: 0x%08x\n",
+			dev_err(&edev->dev, "dropped bad packet. Status: 0x%08x\n",
 				status);
 		else
 			net_receive(NetRxPackets[0], pktlen);
@@ -691,34 +691,32 @@ static int smc911x_probe(struct device_d *dev)
 	struct smc911x_priv *priv;
 	uint32_t val;
 	int i;
+	void *base;
 
-	debug("smc911x_eth_init()\n");
+	base = dev_request_mem_region(dev, 0);
 
-	val = readl(dev->map_base + BYTE_TEST);
+	val = readl(base + BYTE_TEST);
 	if(val != 0x87654321) {
-		printf(DRIVERNAME
-			": no smc911x found on 0x%08x (byte_test=0x%08x)\n",
-			dev->map_base, val);
+		dev_err(dev, "no smc911x found on 0x%p (byte_test=0x%08x)\n",
+			base, val);
 		return -ENODEV;
 	}
 
-	val = readl(dev->map_base + ID_REV) >> 16;
+	val = readl(base + ID_REV) >> 16;
 	for(i = 0; chip_ids[i].id != 0; i++) {
 		if (chip_ids[i].id == val) break;
 	}
 	if (!chip_ids[i].id) {
-		printf(DRIVERNAME ": Unknown chip ID %04x\n", val);
+		dev_err(dev, "Unknown chip ID %04x\n", val);
 		return -ENODEV;
 	}
 
-	debug(DRIVERNAME ": detected %s controller\n", chip_ids[i].name);
+	dev_info(dev, "detected %s controller\n", chip_ids[i].name);
 
-	edev = xzalloc(sizeof(struct eth_device) +
-			sizeof(struct smc911x_priv));
+	priv = xzalloc(sizeof(*priv));
+	edev = &priv->edev;
 	dev->type_data = edev;
-	edev->priv = (struct smc911x_priv *)(edev + 1);
-
-	priv = edev->priv;
+	edev->priv = priv;
 
 	edev->init = smc911x_init_dev;
 	edev->open = smc911x_eth_open;
@@ -733,7 +731,7 @@ static int smc911x_probe(struct device_d *dev)
 	priv->miidev.address = 1;
 	priv->miidev.flags = 0;
 	priv->miidev.edev = edev;
-	priv->base = dev->map_base;
+	priv->base = base;
 
 	smc911x_reset(edev);
 	smc911x_phy_reset(edev);
diff --git a/drivers/nor/cfi_flash.c b/drivers/nor/cfi_flash.c
index 39c2bf18d8..461b0e6e46 100644
--- a/drivers/nor/cfi_flash.c
+++ b/drivers/nor/cfi_flash.c
@@ -283,7 +283,7 @@ static int flash_detect_cfi (struct flash_info *info, struct cfi_qry *qry)
 /*
  * The following code cannot be run from FLASH!
  */
-static ulong flash_get_size (struct flash_info *info, ulong base)
+static ulong flash_get_size (struct flash_info *info)
 {
 	int i, j;
 	flash_sect_t sect_cnt;
@@ -295,6 +295,7 @@ static ulong flash_get_size (struct flash_info *info, ulong base)
 	int erase_region_count;
 	int cur_offset = 0;
 	struct cfi_qry qry;
+	unsigned long base = (unsigned long)info->base;
 
 	memset(&qry, 0, sizeof(qry));
 
@@ -464,8 +465,9 @@ static int __cfi_erase(struct cdev *cdev, size_t count, unsigned long offset,
 
 	debug("%s: erase 0x%08lx (size %d)\n", __func__, offset, count);
 
-        start = find_sector(finfo, cdev->dev->map_base + offset);
-        end   = find_sector(finfo, cdev->dev->map_base + offset + count - 1);
+        start = find_sector(finfo, (unsigned long)finfo->base + offset);
+        end   = find_sector(finfo, (unsigned long)finfo->base + offset +
+			count - 1);
 
 	if (verbose)
 		init_progression_bar(end - start);
@@ -633,11 +635,11 @@ static int cfi_protect(struct cdev *cdev, size_t count, unsigned long offset, in
 	int i, ret = 0;
 	const char *action = (prot? "protect" : "unprotect");
 
-	printf("%s: %s 0x%08lx (size %d)\n", __FUNCTION__,
-	       action, cdev->dev->map_base + offset, count);
+	printf("%s: %s 0x%p (size %d)\n", __func__,
+	       action, finfo->base + offset, count);
 
-	start = find_sector(finfo, cdev->dev->map_base + offset);
-	end   = find_sector(finfo, cdev->dev->map_base + offset + count - 1);
+	start = find_sector(finfo, (unsigned long)finfo->base + offset);
+	end   = find_sector(finfo, (unsigned long)finfo->base + offset + count - 1);
 
 	for (i = start; i <= end; i++) {
 		ret = flash_real_protect (finfo, i, prot);
@@ -654,10 +656,10 @@ static ssize_t cfi_write(struct cdev *cdev, const void *buf, size_t count, unsig
         struct flash_info *finfo = (struct flash_info *)cdev->priv;
         int ret;
 
-	debug("cfi_write: buf=0x%p addr=0x%08lx count=0x%08x\n",buf, cdev->dev->map_base + offset, count);
+	debug("cfi_write: buf=0x%p addr=0x%08lx count=0x%08x\n",buf, finfo->base + offset, count);
 
-        ret = write_buff (finfo, buf, cdev->dev->map_base + offset, count);
-        return ret == 0 ? count : -1;
+	ret = write_buff(finfo, buf, (unsigned long)finfo->base + offset, count);
+	return ret == 0 ? count : -1;
 }
 
 static void cfi_info (struct device_d* dev)
@@ -978,25 +980,21 @@ static int cfi_probe (struct device_d *dev)
 
 	dev->priv = (void *)info;
 
-	printf("cfi_probe: %s base: 0x%08x size: 0x%08x\n", dev->name, dev->map_base, dev->size);
-
 	/* Init: no FLASHes known */
 	info->flash_id = FLASH_UNKNOWN;
 	info->cmd_reset = FLASH_CMD_RESET;
-	info->size = flash_get_size(info, dev->map_base);
-	info->base = (void __iomem *)dev->map_base;
-
-	if (dev->size == 0) {
-		printf("cfi_probe: size : 0x%08lx\n", info->size);
-		dev->size = info->size;
-	}
+	info->base = dev_request_mem_region(dev, 0);
+	info->size = flash_get_size(info);
 
 	if (info->flash_id == FLASH_UNKNOWN) {
 		printf ("## Unknown FLASH on Bank at 0x%08x - Size = 0x%08lx = %ld MB\n",
-			dev->map_base, info->size, info->size << 20);
+			dev->resource[0].start, info->size, info->size << 20);
 		return -ENODEV;
 	}
 
+	dev_info(dev, "found cfi flash at %p, size %ld\n",
+			info->base, info->size);
+
 	info->cdev.name = asprintf("nor%d", dev->id);
 	info->cdev.size = info->size;
 	info->cdev.dev = dev;
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index b8ae475784..c2bee79bb4 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -28,7 +28,7 @@ config DRIVER_SERIAL_NETX
 	default y
 	bool "Netx serial driver"
 
-config DRIVER_SERIAL_LINUX_COMSOLE
+config DRIVER_SERIAL_LINUX_CONSOLE
 	depends on LINUX
 	default y
 	bool "linux console driver"
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 8b56d15e94..411b8c535d 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -10,7 +10,7 @@ obj-$(CONFIG_DRIVER_SERIAL_IMX)			+= serial_imx.o
 obj-$(CONFIG_DRIVER_SERIAL_STM378X)		+= stm-serial.o
 obj-$(CONFIG_DRIVER_SERIAL_ATMEL)		+= atmel.o
 obj-$(CONFIG_DRIVER_SERIAL_NETX)		+= serial_netx.o
-obj-$(CONFIG_DRIVER_SERIAL_LINUX_COMSOLE)	+= linux_console.o
+obj-$(CONFIG_DRIVER_SERIAL_LINUX_CONSOLE)	+= linux_console.o
 obj-$(CONFIG_DRIVER_SERIAL_MPC5XXX)		+= serial_mpc5xxx.o
 obj-$(CONFIG_DRIVER_SERIAL_BLACKFIN)		+= serial_blackfin.o
 obj-$(CONFIG_DRIVER_SERIAL_NS16550)		+= serial_ns16550.o
diff --git a/drivers/serial/amba-pl011.c b/drivers/serial/amba-pl011.c
index 442dbc4cab..2b6d5d384c 100644
--- a/drivers/serial/amba-pl011.c
+++ b/drivers/serial/amba-pl011.c
@@ -40,6 +40,7 @@
  * We wrap our port structure around the generic console_device.
  */
 struct amba_uart_port {
+	void __iomem		*base;
 	struct console_device	uart;		/* uart */
 	struct clk		*clk;		/* uart clock */
 	u32			uartclk;
@@ -53,7 +54,6 @@ to_amba_uart_port(struct console_device *uart)
 
 static int pl011_setbaudrate(struct console_device *cdev, int baudrate)
 {
-	struct device_d *dev = cdev->dev;
 	struct amba_uart_port *uart = to_amba_uart_port(cdev);
 	unsigned int temp;
 	unsigned int divider;
@@ -72,37 +72,37 @@ static int pl011_setbaudrate(struct console_device *cdev, int baudrate)
 	temp = (8 * remainder) / baudrate;
 	fraction = (temp >> 1) + (temp & 1);
 
-	writel(divider, dev->map_base + UART011_IBRD);
-	writel(fraction, dev->map_base + UART011_FBRD);
+	writel(divider, uart->base + UART011_IBRD);
+	writel(fraction, uart->base + UART011_FBRD);
 
 	return 0;
 }
 
 static void pl011_putc(struct console_device *cdev, char c)
 {
-	struct device_d *dev = cdev->dev;
+	struct amba_uart_port *uart = to_amba_uart_port(cdev);
 
 	/* Wait until there is space in the FIFO */
-	while (readl(dev->map_base + UART01x_FR) & UART01x_FR_TXFF);
+	while (readl(uart->base + UART01x_FR) & UART01x_FR_TXFF);
 
 	/* Send the character */
-	writel(c, dev->map_base + UART01x_DR);
+	writel(c, uart->base + UART01x_DR);
 }
 
 static int pl011_getc(struct console_device *cdev)
 {
-	struct device_d *dev = cdev->dev;
+	struct amba_uart_port *uart = to_amba_uart_port(cdev);
 	unsigned int data;
 
 	/* Wait until there is data in the FIFO */
-	while (readl(dev->map_base + UART01x_FR) & UART01x_FR_RXFE);
+	while (readl(uart->base + UART01x_FR) & UART01x_FR_RXFE);
 
-	data = readl(dev->map_base + UART01x_DR);
+	data = readl(uart->base + UART01x_DR);
 
 	/* Check for an error flag */
 	if (data & 0xffffff00) {
 		/* Clear the error */
-		writel(0xffffffff, dev->map_base + UART01x_ECR);
+		writel(0xffffffff, uart->base + UART01x_ECR);
 		return -1;
 	}
 
@@ -111,9 +111,9 @@ static int pl011_getc(struct console_device *cdev)
 
 static int pl011_tstc(struct console_device *cdev)
 {
-	struct device_d *dev = cdev->dev;
+	struct amba_uart_port *uart = to_amba_uart_port(cdev);
 
-	return !(readl(dev->map_base + UART01x_FR) & UART01x_FR_RXFE);
+	return !(readl(uart->base + UART01x_FR) & UART01x_FR_RXFE);
 }
 
 int pl011_init_port (struct console_device *cdev)
@@ -121,10 +121,12 @@ int pl011_init_port (struct console_device *cdev)
 	struct device_d *dev = cdev->dev;
 	struct amba_uart_port *uart = to_amba_uart_port(cdev);
 
+	uart->base = dev_request_mem_region(dev, 0);
+
 	/*
 	 ** First, disable everything.
 	 */
-	writel(0x0, dev->map_base + UART011_CR);
+	writel(0x0, uart->base + UART011_CR);
 
 	/*
 	 * Try to enable the clock producer.
@@ -141,13 +143,13 @@ int pl011_init_port (struct console_device *cdev)
 	 ** Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled.
 	 */
 	writel((UART01x_LCRH_WLEN_8 | UART01x_LCRH_FEN),
-	       dev->map_base + UART011_LCRH);
+	       uart->base + UART011_LCRH);
 
 	/*
 	 ** Finally, enable the UART
 	 */
 	writel((UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_RXE),
-	       dev->map_base + UART011_CR);
+	       uart->base + UART011_CR);
 
 	return 0;
 }
diff --git a/drivers/serial/atmel.c b/drivers/serial/atmel.c
index 109895226f..ff0e75e2b3 100644
--- a/drivers/serial/atmel.c
+++ b/drivers/serial/atmel.c
@@ -313,6 +313,7 @@
  * We wrap our port structure around the generic console_device.
  */
 struct atmel_uart_port {
+	void __iomem		*base;
 	struct console_device	uart;		/* uart */
 	struct clk		*clk;		/* uart clock */
 	u32			uartclk;
@@ -326,31 +327,30 @@ to_atmel_uart_port(struct console_device *uart)
 
 static void atmel_serial_putc(struct console_device *cdev, char c)
 {
-	struct device_d *dev = cdev->dev;
+	struct atmel_uart_port *uart = to_atmel_uart_port(cdev);
 
-	while (!(readl(dev->map_base + USART3_CSR) & USART3_BIT(TXRDY)));
+	while (!(readl(uart->base + USART3_CSR) & USART3_BIT(TXRDY)));
 
-	writel(c, dev->map_base + USART3_THR);
+	writel(c, uart->base + USART3_THR);
 }
 
 static int atmel_serial_tstc(struct console_device *cdev)
 {
-	struct device_d *dev = cdev->dev;
+	struct atmel_uart_port *uart = to_atmel_uart_port(cdev);
 
-	return (readl(dev->map_base + USART3_CSR) & USART3_BIT(RXRDY)) != 0;
+	return (readl(uart->base + USART3_CSR) & USART3_BIT(RXRDY)) != 0;
 }
 
 static int atmel_serial_getc(struct console_device *cdev)
 {
-	struct device_d *dev = cdev->dev;
+	struct atmel_uart_port *uart = to_atmel_uart_port(cdev);
 
-	while (!(readl(dev->map_base + USART3_CSR) & USART3_BIT(RXRDY))) ;
-	return readl(dev->map_base + USART3_RHR);
+	while (!(readl(uart->base + USART3_CSR) & USART3_BIT(RXRDY))) ;
+	return readl(uart->base + USART3_RHR);
 }
 
 static int atmel_serial_setbaudrate(struct console_device *cdev, int baudrate)
 {
-	struct device_d *dev = cdev->dev;
 	struct atmel_uart_port *uart = to_atmel_uart_port(cdev);
 	unsigned long divisor;
 
@@ -360,7 +360,7 @@ static int atmel_serial_setbaudrate(struct console_device *cdev, int baudrate)
 	 *                16 * CD
 	 */
 	divisor = (uart->uartclk / 16 + baudrate / 2) / baudrate;
-	writel(USART3_BF(CD, divisor), dev->map_base + USART3_BRGR);
+	writel(USART3_BF(CD, divisor), uart->base + USART3_BRGR);
 
 	return 0;
 }
@@ -375,20 +375,21 @@ static int atmel_serial_init_port(struct console_device *cdev)
 	struct device_d *dev = cdev->dev;
 	struct atmel_uart_port *uart = to_atmel_uart_port(cdev);
 
+	uart->base = dev_request_mem_region(dev, 0);
 	uart->clk = clk_get(dev, "usart");
 	clk_enable(uart->clk);
 	uart->uartclk = clk_get_rate(uart->clk);
 
-	writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), dev->map_base + USART3_CR);
+	writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), uart->base + USART3_CR);
 
 	atmel_serial_setbaudrate(cdev, 115200);
 
-	writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), dev->map_base + USART3_CR);
+	writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), uart->base + USART3_CR);
 	writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL)
 			   | USART3_BF(USCLKS, USART3_USCLKS_MCK)
 			   | USART3_BF(CHRL, USART3_CHRL_8)
 			   | USART3_BF(PAR, USART3_PAR_NONE)
-			   | USART3_BF(NBSTOP, USART3_NBSTOP_1)), dev->map_base + USART3_MR);
+			   | USART3_BF(NBSTOP, USART3_NBSTOP_1)), uart->base + USART3_MR);
 
 	return 0;
 }
diff --git a/drivers/serial/serial_altera.c b/drivers/serial/serial_altera.c
index 54c717810e..1148564b9e 100644
--- a/drivers/serial/serial_altera.c
+++ b/drivers/serial/serial_altera.c
@@ -27,9 +27,17 @@
 #include <asm/io.h>
 #include <asm/nios2-io.h>
 
+struct altera_serial_priv {
+	struct console_device cdev;
+	void __iomem *regs;
+};
+
 static int altera_serial_setbaudrate(struct console_device *cdev, int baudrate)
 {
-	struct nios_uart *uart = (struct nios_uart *)cdev->dev->map_base;
+	struct altera_serial_priv *priv = container_of(cdev,
+		struct altera_serial_priv, cdev);
+
+	struct nios_uart *uart = priv->regs;
 	uint16_t div;
 
 	div = (CPU_FREQ / baudrate) - 1;
@@ -40,7 +48,10 @@ static int altera_serial_setbaudrate(struct console_device *cdev, int baudrate)
 
 static void altera_serial_putc(struct console_device *cdev, char c)
 {
-	struct nios_uart *uart = (struct nios_uart *)cdev->dev->map_base;
+	struct altera_serial_priv *priv = container_of(cdev,
+		struct altera_serial_priv, cdev);
+
+	struct nios_uart *uart = priv->regs;
 
 	while ((readw(&uart->status) & NIOS_UART_TRDY) == 0);
 
@@ -49,14 +60,20 @@ static void altera_serial_putc(struct console_device *cdev, char c)
 
 static int altera_serial_tstc(struct console_device *cdev)
 {
-	struct nios_uart *uart = (struct nios_uart *)cdev->dev->map_base;
+	struct altera_serial_priv *priv = container_of(cdev,
+		struct altera_serial_priv, cdev);
+
+	struct nios_uart *uart = priv->regs;
 
 	return readw(&uart->status) & NIOS_UART_RRDY;
 }
 
 static int altera_serial_getc(struct console_device *cdev)
 {
-	struct nios_uart *uart = (struct nios_uart *)cdev->dev->map_base;
+	struct altera_serial_priv *priv = container_of(cdev,
+		struct altera_serial_priv, cdev);
+
+	struct nios_uart *uart = priv->regs;
 
 	while (altera_serial_tstc(cdev) == 0);
 
@@ -66,8 +83,12 @@ static int altera_serial_getc(struct console_device *cdev)
 static int altera_serial_probe(struct device_d *dev)
 {
 	struct console_device *cdev;
+	struct altera_serial_priv *priv;
+
+	priv = xmalloc(sizeof(*priv));
+	cdev = &priv->cdev;
 
-	cdev = xmalloc(sizeof(struct console_device));
+	priv->regs = dev_request_mem_region(dev, 0);
 	dev->type_data = cdev;
 	cdev->dev = dev;
 	cdev->f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR;
diff --git a/drivers/serial/serial_altera_jtag.c b/drivers/serial/serial_altera_jtag.c
index 322f9e9324..2e34c894a4 100644
--- a/drivers/serial/serial_altera_jtag.c
+++ b/drivers/serial/serial_altera_jtag.c
@@ -30,6 +30,12 @@
 #include <asm/io.h>
 #include <asm/nios2-io.h>
 
+struct altera_serial_jtag_priv {
+	struct console_device cdev;
+	void __iomem *regs;
+};
+
+
 static int altera_serial_jtag_setbaudrate(struct console_device *cdev, int baudrate)
 {
 	return 0;
@@ -37,7 +43,10 @@ static int altera_serial_jtag_setbaudrate(struct console_device *cdev, int baudr
 
 static void altera_serial_jtag_putc(struct console_device *cdev, char c)
 {
-	struct nios_jtag *jtag = (struct nios_jtag *)cdev->dev->map_base;
+	struct altera_serial_jtag_priv *priv = container_of(cdev,
+		struct altera_serial_jtag_priv, cdev);
+
+	struct nios_jtag *jtag = priv->regs;
 	uint32_t st;
 
 	while (1) {
@@ -51,14 +60,20 @@ static void altera_serial_jtag_putc(struct console_device *cdev, char c)
 
 static int altera_serial_jtag_tstc(struct console_device *cdev)
 {
-	struct nios_jtag *jtag = (struct nios_jtag *)cdev->dev->map_base;
+	struct altera_serial_jtag_priv *priv = container_of(cdev,
+		struct altera_serial_jtag_priv, cdev);
+
+	struct nios_jtag *jtag = priv->regs;
 
 	return readl(&jtag->control) & NIOS_JTAG_RRDY;
 }
 
 static int altera_serial_jtag_getc(struct console_device *cdev)
 {
-	struct nios_jtag *jtag = (struct nios_jtag *)cdev->dev->map_base;
+	struct altera_serial_jtag_priv *priv = container_of(cdev,
+		struct altera_serial_jtag_priv, cdev);
+
+	struct nios_jtag *jtag = priv->regs;
 	uint32_t val;
 
 	while (1) {
@@ -73,8 +88,12 @@ static int altera_serial_jtag_getc(struct console_device *cdev)
 static int altera_serial_jtag_probe(struct device_d *dev) {
 
 	struct console_device *cdev;
+	struct altera_serial_jtag_priv *priv;
+
+	priv = xmalloc(sizeof(*priv));
+	cdev = &priv->cdev;
 
-	cdev = malloc(sizeof(struct console_device));
+	priv->regs = dev_request_mem_region(dev, 0);
 	dev->type_data = cdev;
 	cdev->dev = dev;
 	cdev->f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR;
diff --git a/drivers/serial/serial_imx.c b/drivers/serial/serial_imx.c
index 984d7f2f51..e3edac951f 100644
--- a/drivers/serial/serial_imx.c
+++ b/drivers/serial/serial_imx.c
@@ -161,7 +161,8 @@
 # define	UCR4_VAL UCR4_CTSTL_32
 #endif
 #if defined CONFIG_ARCH_IMX31 || defined CONFIG_ARCH_IMX35 || \
-	defined CONFIG_ARCH_IMX25 || defined CONFIG_ARCH_IMX51
+	defined CONFIG_ARCH_IMX25 || defined CONFIG_ARCH_IMX51 || \
+	defined CONFIG_ARCH_IMX53
 # define	UCR1_VAL (0)
 # define	UCR3_VAL (0x700 | UCR3_RXDMUXSEL)
 # define	UCR4_VAL UCR4_CTSTL_32
@@ -322,7 +323,7 @@ static int imx_serial_probe(struct device_d *dev)
 	priv = xmalloc(sizeof(*priv));
 	cdev = &priv->cdev;
 
-	priv->regs = (void __force __iomem *)dev->map_base;
+	priv->regs = dev_request_mem_region(dev, 0);
 	dev->type_data = cdev;
 	cdev->dev = dev;
 	cdev->f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR;
diff --git a/drivers/serial/serial_mpc5xxx.c b/drivers/serial/serial_mpc5xxx.c
index 2509708863..fb580cf1fd 100644
--- a/drivers/serial/serial_mpc5xxx.c
+++ b/drivers/serial/serial_mpc5xxx.c
@@ -64,7 +64,7 @@ static int __mpc5xxx_serial_setbaudrate(struct mpc5xxx_psc *psc, int baudrate)
 static int mpc5xxx_serial_setbaudrate(struct console_device *cdev, int baudrate)
 {
 	struct device_d *dev = cdev->dev;
-	struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev->map_base;
+	struct mpc5xxx_psc *psc = dev->priv;
 
 	__mpc5xxx_serial_setbaudrate(psc, baudrate);
 
@@ -108,7 +108,7 @@ static int __mpc5xxx_serial_init(struct mpc5xxx_psc *psc)
 static int mpc5xxx_serial_init(struct console_device *cdev)
 {
 	struct device_d *dev = cdev->dev;
-	struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev->map_base;
+	struct mpc5xxx_psc *psc = dev->priv;
 
 	__mpc5xxx_serial_init(psc);
 
@@ -118,7 +118,7 @@ static int mpc5xxx_serial_init(struct console_device *cdev)
 static void mpc5xxx_serial_putc (struct console_device *cdev, const char c)
 {
 	struct device_d *dev = cdev->dev;
-	struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev->map_base;
+	struct mpc5xxx_psc *psc = dev->priv;
 
 	/* Wait for last character to go. */
 	while (!(psc->psc_status & PSC_SR_TXEMP))
@@ -130,7 +130,7 @@ static void mpc5xxx_serial_putc (struct console_device *cdev, const char c)
 static int mpc5xxx_serial_getc (struct console_device *cdev)
 {
 	struct device_d *dev = cdev->dev;
-	struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev->map_base;
+	struct mpc5xxx_psc *psc = dev->priv;
 
 	/* Wait for a character to arrive. */
 	while (!(psc->psc_status & PSC_SR_RXRDY))
@@ -142,7 +142,7 @@ static int mpc5xxx_serial_getc (struct console_device *cdev)
 static int mpc5xxx_serial_tstc (struct console_device *cdev)
 {
 	struct device_d *dev = cdev->dev;
-	struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev->map_base;
+	struct mpc5xxx_psc *psc = dev->priv;
 
 	return (psc->psc_status & PSC_SR_RXRDY);
 }
@@ -153,6 +153,7 @@ static int mpc5xxx_serial_probe(struct device_d *dev)
 	
 	cdev = xzalloc(sizeof(struct console_device));
 	dev->type_data = cdev;
+	dev->priv = dev_request_mem_region(dev, 0);
 	cdev->dev = dev;
 	cdev->f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR;
 	cdev->tstc = mpc5xxx_serial_tstc;
diff --git a/drivers/serial/serial_netx.c b/drivers/serial/serial_netx.c
index 9d4b29efc6..fbbc4efdac 100644
--- a/drivers/serial/serial_netx.c
+++ b/drivers/serial/serial_netx.c
@@ -26,11 +26,7 @@
 #include <driver.h>
 #include <init.h>
 #include <malloc.h>
-
-#define IO_WRITE(addr, val) (*(volatile unsigned long *)(addr) = (val))
-#define IO_READ(addr) (*(volatile unsigned long *)(addr))
-
-unsigned long addr = 0x100a00;
+#include <asm/io.h>
 
 enum uart_regs {
 	UART_DR              = 0x00,
@@ -76,14 +72,15 @@ enum uart_regs {
 static int netx_serial_init_port(struct console_device *cdev)
 {
 	struct device_d *dev = cdev->dev;
+	void __iomem *base = dev->priv;
 	unsigned int divisor;
 
 	/* disable uart */
-	IO_WRITE( dev->map_base + UART_CR, 0);
+	writel(0, base + UART_CR);
 
-	IO_WRITE( dev->map_base + UART_LINE_CR, LINE_CR_8BIT | LINE_CR_FEN);
+	writel(LINE_CR_8BIT | LINE_CR_FEN, base + UART_LINE_CR);
 
-	IO_WRITE( dev->map_base + UART_DRV_ENABLE, DRV_ENABLE_TX | DRV_ENABLE_RTS );
+	writel(DRV_ENABLE_TX | DRV_ENABLE_RTS, base + UART_DRV_ENABLE);
 
 	/* set baud rate */
 	divisor = 115200 * 4096;
@@ -91,12 +88,12 @@ static int netx_serial_init_port(struct console_device *cdev)
 	divisor *= 256;
 	divisor /= 100000;
 
-	IO_WRITE( dev->map_base + UART_BAUDDIV_MSB, (divisor >> 8) & 0xff );
-	IO_WRITE( dev->map_base + UART_BAUDDIV_LSB, divisor & 0xff );
-	IO_WRITE( dev->map_base + UART_BRM_CR, BRM_CR_BAUD_RATE_MODE);
+	writel((divisor >> 8) & 0xff, base + UART_BAUDDIV_MSB);
+	writel(divisor & 0xff, base + UART_BAUDDIV_LSB);
+	writel(BRM_CR_BAUD_RATE_MODE, base + UART_BRM_CR);
 
 	/* Finally, enable the UART */
-	IO_WRITE( dev->map_base + UART_CR, CR_UARTEN);
+	writel(CR_UARTEN, base + UART_CR);
 
 	return 0;
 }
@@ -109,22 +106,24 @@ static int netx_serial_setbaudrate(struct console_device *cdev, int baudrate)
 static void netx_serial_putc(struct console_device *cdev, char c)
 {
 	struct device_d *dev = cdev->dev;
+	void __iomem *base = dev->priv;
 
-	while( IO_READ(dev->map_base + UART_FR) & FR_TXFF );
+	while (readl(base + UART_FR) & FR_TXFF );
 
-	IO_WRITE(dev->map_base + UART_DR, c);
+	writel(c, base + UART_DR);
 }
 
 static int netx_serial_getc(struct console_device *cdev)
 {
 	struct device_d *dev = cdev->dev;
+	void __iomem *base = dev->priv;
 	int c;
 
-	while( IO_READ(dev->map_base + UART_FR) & FR_RXFE );
+	while (readl(base + UART_FR) & FR_RXFE );
 
-	c = IO_READ(dev->map_base + UART_DR);
+	c = readl(base + UART_DR);
 
-	IO_READ(dev->map_base + UART_SR);
+	readl(base + UART_SR);
 
 	return c;
 }
@@ -132,8 +131,9 @@ static int netx_serial_getc(struct console_device *cdev)
 static int netx_serial_tstc(struct console_device *cdev)
 {
 	struct device_d *dev = cdev->dev;
+	void __iomem *base = dev->priv;
 
-	return (IO_READ(dev->map_base + UART_FR) & FR_RXFE) ? 0 : 1;
+	return (readl(base + UART_FR) & FR_RXFE) ? 0 : 1;
 }
 
 static int netx_serial_probe(struct device_d *dev)
@@ -142,6 +142,7 @@ static int netx_serial_probe(struct device_d *dev)
 
 	cdev = xmalloc(sizeof(struct console_device));
 	dev->type_data = cdev;
+	dev->priv = dev_request_mem_region(dev, 0);
 	cdev->dev = dev;
 	cdev->f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR;
 	cdev->tstc = netx_serial_tstc;
diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c
index 9a4b4dccc7..36d39cd125 100644
--- a/drivers/serial/serial_ns16550.c
+++ b/drivers/serial/serial_ns16550.c
@@ -49,6 +49,70 @@
 /*********** Private Functions **********************************/
 
 /**
+ * @brief read register
+ *
+ * @param[in] cdev pointer to console device
+ * @param[in] offset
+ *
+ * @return value
+ */
+static uint32_t ns16550_read(struct console_device *cdev, uint32_t off)
+{
+	struct device_d *dev = cdev->dev;
+	struct NS16550_plat *plat = (struct NS16550_plat *)dev->platform_data;
+	int width = dev->resource[0].flags & IORESOURCE_MEM_TYPE_MASK;
+
+	off <<= plat->shift;
+
+	if (plat->reg_read)
+		return plat->reg_read((unsigned long)dev->priv, off);
+
+	switch (width) {
+	case IORESOURCE_MEM_8BIT:
+		return readb(dev->priv + off);
+	case IORESOURCE_MEM_16BIT:
+		return readw(dev->priv + off);
+	case IORESOURCE_MEM_32BIT:
+		return readl(dev->priv + off);
+	}
+	return -1;
+}
+
+/**
+ * @brief write register
+ *
+ * @param[in] cdev pointer to console device
+ * @param[in] offset
+ * @param[in] val
+ */
+static void ns16550_write(struct console_device *cdev, uint32_t val,
+			  uint32_t off)
+{
+	struct device_d *dev = cdev->dev;
+	struct NS16550_plat *plat = (struct NS16550_plat *)dev->platform_data;
+	int width = dev->resource[0].flags & IORESOURCE_MEM_TYPE_MASK;
+
+	off <<= plat->shift;
+
+	if (plat->reg_write) {
+		plat->reg_write(val, (unsigned long)dev->priv, off);
+		return;
+	}
+
+	switch (width) {
+	case IORESOURCE_MEM_8BIT:
+		writeb(val & 0xff, dev->priv + off);
+		break;
+	case IORESOURCE_MEM_16BIT:
+		writew(val & 0xffff, dev->priv + off);
+		break;
+	case IORESOURCE_MEM_32BIT:
+		writel(val, dev->priv + off);
+		break;
+	}
+}
+
+/**
  * @brief Compute the divisor for a baud rate
  *
  * @param[in] cdev pointer to console device
@@ -74,27 +138,24 @@ static unsigned int ns16550_calc_divisor(struct console_device *cdev,
  */
 static void ns16550_serial_init_port(struct console_device *cdev)
 {
-	struct NS16550_plat *plat = (struct NS16550_plat *)
-	    cdev->dev->platform_data;
-	unsigned long base = cdev->dev->map_base;
 	unsigned int baud_divisor;
 
 	/* Setup the serial port with the defaults first */
 	baud_divisor = ns16550_calc_divisor(cdev, CONFIG_BAUDRATE);
 
 	/* initializing the device for the first time */
-	plat->reg_write(0x00, base, ier);
+	ns16550_write(cdev, 0x00, ier);
 #ifdef CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS
-	plat->reg_write(0x07, base, mdr1);	/* Disable */
+	ns16550_write(cdev, 0x07, mdr1);	/* Disable */
 #endif
-	plat->reg_write(LCR_BKSE | LCRVAL, base, lcr);
-	plat->reg_write(baud_divisor & 0xFF, base, dll);
-	plat->reg_write((baud_divisor >> 8) & 0xff, base, dlm);
-	plat->reg_write(LCRVAL, base, lcr);
-	plat->reg_write(MCRVAL, base, mcr);
-	plat->reg_write(FCRVAL, base, fcr);
+	ns16550_write(cdev, LCR_BKSE | LCRVAL, lcr);
+	ns16550_write(cdev, baud_divisor & 0xFF, dll);
+	ns16550_write(cdev, (baud_divisor >> 8) & 0xff, dlm);
+	ns16550_write(cdev, LCRVAL, lcr);
+	ns16550_write(cdev, MCRVAL, mcr);
+	ns16550_write(cdev, FCRVAL, fcr);
 #ifdef CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS
-	plat->reg_write(0x00, base, mdr1);
+	ns16550_write(cdev, 0x00,  mdr1);
 #endif
 }
 
@@ -108,12 +169,9 @@ static void ns16550_serial_init_port(struct console_device *cdev)
  */
 static void ns16550_putc(struct console_device *cdev, char c)
 {
-	struct NS16550_plat *plat = (struct NS16550_plat *)
-	    cdev->dev->platform_data;
-	unsigned long base = cdev->dev->map_base;
 	/* Loop Doing Nothing */
-	while ((plat->reg_read(base, lsr) & LSR_THRE) == 0) ;
-	plat->reg_write(c, base, thr);
+	while ((ns16550_read(cdev, lsr) & LSR_THRE) == 0) ;
+	ns16550_write(cdev, c, thr);
 }
 
 /**
@@ -125,12 +183,9 @@ static void ns16550_putc(struct console_device *cdev, char c)
  */
 static int ns16550_getc(struct console_device *cdev)
 {
-	struct NS16550_plat *plat = (struct NS16550_plat *)
-	    cdev->dev->platform_data;
-	unsigned long base = cdev->dev->map_base;
 	/* Loop Doing Nothing */
-	while ((plat->reg_read(base, lsr) & LSR_DR) == 0) ;
-	return plat->reg_read(base, rbr);
+	while ((ns16550_read(cdev, lsr) & LSR_DR) == 0) ;
+	return ns16550_read(cdev, rbr);
 }
 
 /**
@@ -142,10 +197,7 @@ static int ns16550_getc(struct console_device *cdev)
  */
 static int ns16550_tstc(struct console_device *cdev)
 {
-	struct NS16550_plat *plat = (struct NS16550_plat *)
-	    cdev->dev->platform_data;
-	unsigned long base = cdev->dev->map_base;
-	return ((plat->reg_read(base, lsr) & LSR_DR) != 0);
+	return ((ns16550_read(cdev, lsr) & LSR_DR) != 0);
 }
 
 /**
@@ -158,17 +210,15 @@ static int ns16550_tstc(struct console_device *cdev)
  */
 static int ns16550_setbaudrate(struct console_device *cdev, int baud_rate)
 {
-	struct NS16550_plat *plat = (struct NS16550_plat *)
-	    cdev->dev->platform_data;
-	unsigned long base = cdev->dev->map_base;
 	unsigned int baud_divisor = ns16550_calc_divisor(cdev, baud_rate);
-	plat->reg_write(0x00, base, ier);
-	plat->reg_write(LCR_BKSE, base, lcr);
-	plat->reg_write(baud_divisor & 0xff, base, dll);
-	plat->reg_write((baud_divisor >> 8) & 0xff, base, dlm);
-	plat->reg_write(LCRVAL, base, lcr);
-	plat->reg_write(MCRVAL, base, mcr);
-	plat->reg_write(FCRVAL, base, fcr);
+
+	ns16550_write(cdev, 0x00, ier);
+	ns16550_write(cdev, LCR_BKSE, lcr);
+	ns16550_write(cdev, baud_divisor & 0xff, dll);
+	ns16550_write(cdev, (baud_divisor >> 8) & 0xff, dlm);
+	ns16550_write(cdev, LCRVAL, lcr);
+	ns16550_write(cdev, MCRVAL, mcr);
+	ns16550_write(cdev, FCRVAL, fcr);
 	return 0;
 }
 
@@ -189,14 +239,16 @@ static int ns16550_probe(struct device_d *dev)
 	/* we do expect platform specific data */
 	if (plat == NULL)
 		return -EINVAL;
-	if ((plat->reg_read == NULL) || (plat->reg_write == NULL))
-		return -EINVAL;
+	dev->priv = dev_request_mem_region(dev, 0);
 
 	cdev = xzalloc(sizeof(*cdev));
 
 	dev->type_data = cdev;
 	cdev->dev = dev;
-	cdev->f_caps = plat->f_caps;
+	if (plat->f_caps)
+		cdev->f_caps = plat->f_caps;
+	else
+		cdev->f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR;
 	cdev->tstc = ns16550_tstc;
 	cdev->putc = ns16550_putc;
 	cdev->getc = ns16550_getc;
diff --git a/drivers/serial/serial_pl010.c b/drivers/serial/serial_pl010.c
index 7923ebb788..9f7b7d3b02 100644
--- a/drivers/serial/serial_pl010.c
+++ b/drivers/serial/serial_pl010.c
@@ -37,7 +37,7 @@
 
 static int pl010_setbaudrate(struct console_device *cdev, int baudrate)
 {
-	struct pl010_struct *pl010 = (struct pl010_struct *)cdev->dev->map_base;
+	struct pl010_struct *pl010 = cdev->dev->priv;
 	unsigned int divisor;
 
 	switch (baudrate) {
@@ -76,7 +76,7 @@ static int pl010_setbaudrate(struct console_device *cdev, int baudrate)
 
 static int pl010_init_port(struct console_device *cdev)
 {
-	struct pl010_struct *pl010 = (struct pl010_struct *)cdev->dev->map_base;
+	struct pl010_struct *pl010 = cdev->dev->priv;
 
 	/*
 	 * First, disable everything.
@@ -99,7 +99,7 @@ static int pl010_init_port(struct console_device *cdev)
 
 static void pl010_putc(struct console_device *cdev, char c)
 {
-	struct pl010_struct *pl010 = (struct pl010_struct *)cdev->dev->map_base;
+	struct pl010_struct *pl010 = cdev->dev->priv;
 
 	/* Wait until there is space in the FIFO */
 	while (readl(&pl010->flag) & UART_PL010_FR_TXFF)
@@ -111,7 +111,7 @@ static void pl010_putc(struct console_device *cdev, char c)
 
 static int pl010_getc(struct console_device *cdev)
 {
-	struct pl010_struct *pl010 = (struct pl010_struct *)cdev->dev->map_base;
+	struct pl010_struct *pl010 = cdev->dev->priv;
 	unsigned int data;
 
 	/* Wait until there is data in the FIFO */
@@ -132,7 +132,7 @@ static int pl010_getc(struct console_device *cdev)
 
 static int pl010_tstc(struct console_device *cdev)
 {
-	struct pl010_struct *pl010 = (struct pl010_struct *)cdev->dev->map_base;
+	struct pl010_struct *pl010 = cdev->dev->priv;
 
 	return !(readl(&pl010->flag) & UART_PL010_FR_RXFE);
 }
@@ -143,6 +143,7 @@ static int pl010_probe(struct device_d *dev)
 
 	cdev = xmalloc(sizeof(struct console_device));
 	dev->type_data = cdev;
+	dev->priv = dev_request_mem_region(dev, 0);
 	cdev->dev = dev;
 	cdev->f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR;
 	cdev->tstc = pl010_tstc;
diff --git a/drivers/serial/serial_s3c24x0.c b/drivers/serial/serial_s3c24x0.c
index 0a1796735f..21bca12f39 100644
--- a/drivers/serial/serial_s3c24x0.c
+++ b/drivers/serial/serial_s3c24x0.c
@@ -44,11 +44,12 @@
 static int s3c24x0_serial_setbaudrate(struct console_device *cdev, int baudrate)
 {
 	struct device_d *dev = cdev->dev;
+	void __iomem *base = dev->priv;
 	unsigned val;
 
 	/* value is calculated so : PCLK / (16 * baudrate) -1 */
 	val = s3c24xx_get_pclk() / (16 * baudrate) - 1;
-	writew(val, dev->map_base + UBRDIV);
+	writew(val, base + UBRDIV);
 
 	return 0;
 }
@@ -56,21 +57,22 @@ static int s3c24x0_serial_setbaudrate(struct console_device *cdev, int baudrate)
 static int s3c24x0_serial_init_port(struct console_device *cdev)
 {
 	struct device_d *dev = cdev->dev;
+	void __iomem *base = dev->priv;
 
 	/* FIFO enable, Tx/Rx FIFO clear */
-	writeb(0x07, dev->map_base + UFCON);
-	writeb(0x00, dev->map_base + UMCON);
+	writeb(0x07, base + UFCON);
+	writeb(0x00, base + UMCON);
 
 	/* Normal,No parity,1 stop,8 bit */
-	writeb(0x03, dev->map_base + ULCON);
+	writeb(0x03, base + ULCON);
 	/*
 	 * tx=level,rx=edge,disable timeout int.,enable rx error int.,
 	 * normal,interrupt or polling
 	 */
-	writew(0x0245, dev->map_base + UCON);
+	writew(0x0245, base + UCON);
 
 #ifdef CONFIG_DRIVER_SERIAL_S3C24X0_AUTOSYNC
-	writeb(0x01, dev->map_base + UMCON); /* RTS up */
+	writeb(0x01, base + UMCON); /* RTS up */
 #endif
 
 	return 0;
@@ -79,20 +81,22 @@ static int s3c24x0_serial_init_port(struct console_device *cdev)
 static void s3c24x0_serial_putc(struct console_device *cdev, char c)
 {
 	struct device_d *dev = cdev->dev;
+	void __iomem *base = dev->priv;
 
 	/* Wait for Tx FIFO not full */
-	while (!(readb(dev->map_base + UTRSTAT) & 0x2))
+	while (!(readb(base + UTRSTAT) & 0x2))
 		;
 
-	writeb(c, dev->map_base + UTXH);
+	writeb(c, base + UTXH);
 }
 
 static int s3c24x0_serial_tstc(struct console_device *cdev)
 {
 	struct device_d *dev = cdev->dev;
+	void __iomem *base = dev->priv;
 
 	/* If receive fifo is empty, return false */
-	if (readb(dev->map_base + UTRSTAT) & 0x1)
+	if (readb(base + UTRSTAT) & 0x1)
 		return 1;
 
 	return 0;
@@ -101,19 +105,21 @@ static int s3c24x0_serial_tstc(struct console_device *cdev)
 static int s3c24x0_serial_getc(struct console_device *cdev)
 {
 	struct device_d *dev = cdev->dev;
+	void __iomem *base = dev->priv;
 
 	/* wait for a character */
-	while (!(readb(dev->map_base + UTRSTAT) & 0x1))
+	while (!(readb(base + UTRSTAT) & 0x1))
 		;
 
-	return readb(dev->map_base + URXH);
+	return readb(base + URXH);
 }
 
 static void s3c24x0_serial_flush(struct console_device *cdev)
 {
 	struct device_d *dev = cdev->dev;
+	void __iomem *base = dev->priv;
 
-	while (!(readb(dev->map_base + UTRSTAT) & 0x4))
+	while (!(readb(base + UTRSTAT) & 0x4))
 		;
 }
 
@@ -123,6 +129,7 @@ static int s3c24x0_serial_probe(struct device_d *dev)
 
 	cdev = xmalloc(sizeof(struct console_device));
 	dev->type_data = cdev;
+	dev->priv = dev_request_mem_region(dev, 0);
 	cdev->dev = dev;
 	cdev->f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR;
 	cdev->tstc = s3c24x0_serial_tstc;
diff --git a/drivers/serial/stm-serial.c b/drivers/serial/stm-serial.c
index a225e30cdb..4264345182 100644
--- a/drivers/serial/stm-serial.c
+++ b/drivers/serial/stm-serial.c
@@ -52,123 +52,125 @@
 # define RXE (1 << 9)
 #define UARTDBGIMSC 0x38
 
-struct stm_serial_local {
+struct stm_priv {
 	struct console_device cdev;
 	int baudrate;
 	struct notifier_block notify;
+	void __iomem *base;
 };
 
 static void stm_serial_putc(struct console_device *cdev, char c)
 {
-	struct device_d *dev = cdev->dev;
+	struct stm_priv *priv = container_of(cdev, struct stm_priv, cdev);
 
 	/* Wait for room in TX FIFO */
-	while (readl(dev->map_base + UARTDBGFR) & TXFF)
+	while (readl(priv->base + UARTDBGFR) & TXFF)
 		;
 
-	writel(c, dev->map_base + UARTDBGDR);
+	writel(c, priv->base + UARTDBGDR);
 }
 
 static int stm_serial_tstc(struct console_device *cdev)
 {
-	struct device_d *dev = cdev->dev;
+	struct stm_priv *priv = container_of(cdev, struct stm_priv, cdev);
 
 	/* Check if RX FIFO is not empty */
-	return !(readl(dev->map_base + UARTDBGFR) & RXFE);
+	return !(readl(priv->base + UARTDBGFR) & RXFE);
 }
 
 static int stm_serial_getc(struct console_device *cdev)
 {
-	struct device_d *dev = cdev->dev;
+	struct stm_priv *priv = container_of(cdev, struct stm_priv, cdev);
 
 	/* Wait while TX FIFO is empty */
-	while (readl(dev->map_base + UARTDBGFR) & RXFE)
+	while (readl(priv->base + UARTDBGFR) & RXFE)
 		;
 
-	return readl(dev->map_base + UARTDBGDR) & 0xff;
+	return readl(priv->base + UARTDBGDR) & 0xff;
 }
 
 static void stm_serial_flush(struct console_device *cdev)
 {
-	struct device_d *dev = cdev->dev;
+	struct stm_priv *priv = container_of(cdev, struct stm_priv, cdev);
 
 	/* Wait for TX FIFO empty */
-	while (readl(dev->map_base + UARTDBGFR) & TXFF)
+	while (readl(priv->base + UARTDBGFR) & TXFF)
 		;
 }
 
 static int stm_serial_setbaudrate(struct console_device *cdev, int new_baudrate)
 {
-	struct device_d *dev = cdev->dev;
-	struct stm_serial_local *local = container_of(cdev, struct stm_serial_local, cdev);
+	struct stm_priv *priv = container_of(cdev, struct stm_priv, cdev);
 	uint32_t cr, lcr_h, quot;
 
 	/* Disable everything */
-	cr = readl(dev->map_base + UARTDBGCR);
-	writel(0, dev->map_base + UARTDBGCR);
+	cr = readl(priv->base + UARTDBGCR);
+	writel(0, priv->base + UARTDBGCR);
 
 	/* Calculate and set baudrate */
 	quot = (imx_get_xclk() * 4) / new_baudrate;
-	writel(quot & 0x3f, dev->map_base + UARTDBGFBRD);
-	writel(quot >> 6, dev->map_base + UARTDBGIBRD);
+	writel(quot & 0x3f, priv->base + UARTDBGFBRD);
+	writel(quot >> 6, priv->base + UARTDBGIBRD);
 
 	/* Set 8n1 mode, enable FIFOs */
 	lcr_h = WLEN8 | FEN;
-	writel(lcr_h, dev->map_base + UARTDBGLCR_H);
+	writel(lcr_h, priv->base + UARTDBGLCR_H);
 
 	/* Re-enable debug UART */
-	writel(cr, dev->map_base + UARTDBGCR);
+	writel(cr, priv->base + UARTDBGCR);
 
-	local->baudrate = new_baudrate;
+	priv->baudrate = new_baudrate;
 
 	return 0;
 }
 
 static int stm_clocksource_clock_change(struct notifier_block *nb, unsigned long event, void *data)
 {
-	struct stm_serial_local *local = container_of(nb, struct stm_serial_local, notify);
+	struct stm_priv *priv = container_of(nb, struct stm_priv, notify);
 
-	return stm_serial_setbaudrate(&local->cdev, local->baudrate);
+	return stm_serial_setbaudrate(&priv->cdev, priv->baudrate);
 }
 
-static int stm_serial_init_port(struct console_device *cdev)
+static int stm_serial_init_port(struct stm_priv *priv)
 {
-	struct device_d *dev = cdev->dev;
-
 	/* Disable UART */
-	writel(0, dev->map_base + UARTDBGCR);
+	writel(0, priv->base + UARTDBGCR);
 
 	/* Mask interrupts */
-	writel(0, dev->map_base + UARTDBGIMSC);
+	writel(0, priv->base + UARTDBGIMSC);
 
 	return 0;
 }
 
-static struct stm_serial_local stm_device = {
-	.cdev = {
-		.f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR,
-		.tstc = stm_serial_tstc,
-		.putc = stm_serial_putc,
-		.getc = stm_serial_getc,
-		.flush = stm_serial_flush,
-		.setbrg = stm_serial_setbaudrate,
-	},
-};
-
 static int stm_serial_probe(struct device_d *dev)
 {
-	stm_device.cdev.dev = dev;
-	dev->type_data = &stm_device.cdev;
+	struct stm_priv *priv;
+	struct console_device *cdev;
+
+	priv = xzalloc(sizeof *priv);
+
+	cdev = &priv->cdev;
+
+	cdev->f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR;
+	cdev->tstc = stm_serial_tstc;
+	cdev->putc = stm_serial_putc;
+	cdev->getc = stm_serial_getc;
+	cdev->flush = stm_serial_flush;
+	cdev->setbrg = stm_serial_setbaudrate;
+	cdev->dev = dev;
+
+	dev->type_data = cdev;
+	priv->base = dev_request_mem_region(dev, 0);
 
-	stm_serial_init_port(&stm_device.cdev);
-	stm_serial_setbaudrate(&stm_device.cdev, CONFIG_BAUDRATE);
+	stm_serial_init_port(priv);
+	stm_serial_setbaudrate(cdev, CONFIG_BAUDRATE);
 
 	/* Enable UART */
-	writel(TXE | RXE | UARTEN, dev->map_base + UARTDBGCR);
+	writel(TXE | RXE | UARTEN, priv->base + UARTDBGCR);
 
-	console_register(&stm_device.cdev);
-	stm_device.notify.notifier_call = stm_clocksource_clock_change;
-	clock_register_client(&stm_device.notify);
+	console_register(cdev);
+	priv->notify.notifier_call = stm_clocksource_clock_change;
+	clock_register_client(&priv->notify);
 
 	return 0;
 }
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index a88e179e5a..9ab03f619e 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -16,7 +16,7 @@ config DRIVER_SPI_IMX_0_0
 
 config DRIVER_SPI_IMX_2_3
 	bool
-	depends on ARCH_IMX51
+	depends on ARCH_IMX51 || ARCH_IMX53
 	default y
 
 endmenu
diff --git a/drivers/spi/imx_spi.c b/drivers/spi/imx_spi.c
index 1857d6c672..6dc41b92f5 100644
--- a/drivers/spi/imx_spi.c
+++ b/drivers/spi/imx_spi.c
@@ -373,13 +373,13 @@ static int imx_spi_probe(struct device_d *dev)
 		version = SPI_IMX_VER_0_0;
 #endif
 #ifdef CONFIG_DRIVER_SPI_IMX_2_3
-	if (cpu_is_mx51())
+	if (cpu_is_mx51() || cpu_is_mx53())
 		version = SPI_IMX_VER_2_3;
 #endif
 	imx->chipselect = spi_imx_devtype_data[version].chipselect;
 	imx->xchg_single = spi_imx_devtype_data[version].xchg_single;
 	imx->init = spi_imx_devtype_data[version].init;
-	imx->regs = (void __iomem *)dev->map_base;
+	imx->regs = dev_request_mem_region(dev, 0);
 
 	imx->init(imx);
 
diff --git a/drivers/usb/gadget/fsl_udc.c b/drivers/usb/gadget/fsl_udc.c
index 20a506489a..1e4d4b08f3 100644
--- a/drivers/usb/gadget/fsl_udc.c
+++ b/drivers/usb/gadget/fsl_udc.c
@@ -560,7 +560,7 @@ static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
 		if (j != req->dtd_count - 1) {
 			next_td = curr_td->next_td_virt;
 		}
-		dma_free_coherent(curr_td);
+		dma_free_coherent(curr_td, sizeof(struct ep_td_struct));
 	}
 
 	dma_inv_range((unsigned long)req->req.buf,
@@ -2239,7 +2239,7 @@ static int fsl_udc_probe(struct device_d *dev)
 	udc_controller = xzalloc(sizeof(*udc_controller));
 	udc_controller->stopped = 1;
 
-	dr_regs = (void *)dev->map_base;
+	dr_regs = dev_request_mem_region(dev, 0);
 
 	/* Read Device Controller Capability Parameters register */
 	dccparams = readl(&dr_regs->dccparams);
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 844dc1db2a..60fc1819eb 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -900,20 +900,22 @@ static int ehci_probe(struct device_d *dev)
 	host = &ehci->host;
 	dev->priv = ehci;
 
-	if (pdata) {
+	/* default to EHCI_HAS_TT to not change behaviour of boards
+	 * without platform_data
+	 */
+	if (pdata)
 		ehci->flags = pdata->flags;
-		ehci->hccr = (void *)(dev->map_base + pdata->hccr_offset);
-		ehci->hcor = (void *)(dev->map_base + pdata->hcor_offset);
-	}
-	else {
-		/* default to EHCI_HAS_TT to not change behaviour of boards
-		 * with platform_data
-		 */
+	else
 		ehci->flags = EHCI_HAS_TT;
-		ehci->hccr = (void *)(dev->map_base + 0x100);
-		ehci->hcor = (void *)(dev->map_base + 0x140);
+
+	if (dev->num_resources < 2) {
+		printf("echi: need 2 resources base and data");
+		return -ENODEV;
 	}
 
+	ehci->hccr = dev_request_mem_region(dev, 0);
+	ehci->hcor = dev_request_mem_region(dev, 1);
+
 	host->init = ehci_init;
 	host->submit_int_msg = submit_int_msg;
 	host->submit_control_msg = submit_control_msg;
diff --git a/drivers/video/fb.c b/drivers/video/fb.c
index 85db9044c8..0be465f892 100644
--- a/drivers/video/fb.c
+++ b/drivers/video/fb.c
@@ -84,9 +84,9 @@ static int fb_setup_mode(struct device_d *dev, struct param_d *param,
 	ret = info->fbops->fb_activate_var(info);
 
 	if (!ret) {
-		dev->map_base = (unsigned long)info->screen_base;
+		dev->resource[0].start = (resource_size_t)info->screen_base;
 		info->cdev.size = info->xres * info->yres * (info->bits_per_pixel >> 3);
-		dev->size = info->cdev.size;
+		dev->resource[0].size = info->cdev.size;
 		dev_param_set_generic(dev, param, val);
 	} else
 		info->cdev.size = 0;
@@ -107,15 +107,19 @@ int register_framebuffer(struct fb_info *info)
 	int id = get_free_deviceid("fb");
 	struct device_d *dev;
 
+	dev = &info->dev;
+
 	info->cdev.ops = &fb_ops;
 	info->cdev.name = asprintf("fb%d", id);
 	info->cdev.size = info->xres * info->yres * (info->bits_per_pixel >> 3);
-	info->cdev.dev = &info->dev;
+	info->cdev.dev = dev;
 	info->cdev.priv = info;
-	info->cdev.dev->map_base = (unsigned long)info->screen_base;
-	info->cdev.dev->size = info->cdev.size;
+	dev->resource = xzalloc(sizeof(struct resource));
+	dev->resource[0].start = (resource_size_t)info->screen_base;
+	dev->resource[0].size = info->cdev.size;
+	dev->resource[0].flags = IORESOURCE_MEM;
+	dev->num_resources = 1;
 
-	dev = &info->dev;
 	dev->priv = info;
 	dev->id = id;
 
diff --git a/drivers/video/imx-ipu-fb.c b/drivers/video/imx-ipu-fb.c
index d9e1e212cc..5ae8c4b389 100644
--- a/drivers/video/imx-ipu-fb.c
+++ b/drivers/video/imx-ipu-fb.c
@@ -858,7 +858,7 @@ static int imxfb_probe(struct device_d *dev)
 	fbi = xzalloc(sizeof(*fbi));
 	info = &fbi->info;
 
-	fbi->regs = (void *)dev->map_base;
+	fbi->regs = dev_request_mem_region(dev, 0);
 	fbi->dev = dev;
 	info->priv = fbi;
 	info->fbops = &imxfb_ops;
diff --git a/drivers/video/imx.c b/drivers/video/imx.c
index ac518588ca..c19e83e50f 100644
--- a/drivers/video/imx.c
+++ b/drivers/video/imx.c
@@ -547,7 +547,7 @@ static int imxfb_probe(struct device_d *dev)
 	info = &fbi->info;
 
 	fbi->mode = pdata->mode;
-	fbi->regs = (void *)dev->map_base;
+	fbi->regs = dev_request_mem_region(dev, 0);
 	fbi->pcr = pdata->mode->pcr;
 	fbi->pwmr = pdata->pwmr;
 	fbi->lscr1 = pdata->lscr1;
diff --git a/drivers/video/s3c.c b/drivers/video/s3c.c
index 3715499b79..d079fdea59 100644
--- a/drivers/video/s3c.c
+++ b/drivers/video/s3c.c
@@ -331,11 +331,12 @@ static int s3cfb_activate_var(struct fb_info *fb_info)
 static void s3cfb_info(struct device_d *hw_dev)
 {
 	uint32_t con1, addr1, addr2, addr3;
+	struct s3cfb_info *fbi = hw_dev->priv;
 
-	con1 = readl(hw_dev->map_base + LCDCON1);
-	addr1 = readl(hw_dev->map_base + LCDSADDR1);
-	addr2 = readl(hw_dev->map_base + LCDSADDR2);
-	addr3 = readl(hw_dev->map_base + LCDSADDR3);
+	con1 = readl(fbi->base + LCDCON1);
+	addr1 = readl(fbi->base + LCDSADDR1);
+	addr2 = readl(fbi->base + LCDSADDR2);
+	addr3 = readl(fbi->base + LCDSADDR3);
 
 	printf(" Video hardware info:\n");
 	printf("  Video clock is running at %u Hz\n", s3c24xx_get_hclk() / ((GET_CLKVAL(con1) + 1) * 2));
@@ -371,15 +372,16 @@ static int s3cfb_probe(struct device_d *hw_dev)
 	if (! pdata)
 		return -ENODEV;
 
-	writel(0, hw_dev->map_base + LCDCON1);
-	writel(0, hw_dev->map_base + LCDCON5); /* FIXME not 0 for some displays */
+	fbi.base = dev_request_mem_region(hw_dev, 0);
+	writel(0, fbi.base + LCDCON1);
+	writel(0, fbi.base + LCDCON5); /* FIXME not 0 for some displays */
 
 	/* just init */
 	fbi.info.priv = &fbi;
 
 	/* add runtime hardware info */
 	fbi.hw_dev = hw_dev;
-	fbi.base = (void*)hw_dev->map_base;
+	hw_dev->priv = &fbi;
 
 	/* add runtime video info */
 	fbi.info.mode_list = pdata->mode_list;
diff --git a/drivers/video/stm.c b/drivers/video/stm.c
index ee2f0268bd..78acad7372 100644
--- a/drivers/video/stm.c
+++ b/drivers/video/stm.c
@@ -488,7 +488,7 @@ static int stmfb_probe(struct device_d *hw_dev)
 
 	/* add runtime hardware info */
 	fbi.hw_dev = hw_dev;
-	fbi.base = (void *)hw_dev->map_base;
+	fbi.base = dev_request_mem_region(hw_dev, 0);
 	fbi.pdata = pdata;
 
 	/* add runtime video info */
diff --git a/fs/devfs.c b/fs/devfs.c
index 07ca16c553..66f7ca4162 100644
--- a/fs/devfs.c
+++ b/fs/devfs.c
@@ -161,7 +161,9 @@ static int devfs_ioctl(struct device_d *_dev, FILE *f, int request, void *buf)
 
 static int devfs_truncate(struct device_d *dev, FILE *f, ulong size)
 {
-	if (size > f->dev->size)
+	if (f->dev->num_resources < 1)
+		return -ENOSPC;
+	if (size > f->dev->resource[0].size)
 		return -ENOSPC;
 	return 0;
 }
diff --git a/fs/fs.c b/fs/fs.c
index e71d5a29af..7d65ec819b 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -1043,13 +1043,12 @@ ssize_t mem_read(struct cdev *cdev, void *buf, size_t count, ulong offset, ulong
 	ulong size;
 	struct device_d *dev;
 
-	if (!cdev->dev)
+	if (!cdev->dev || cdev->dev->num_resources < 1)
 		return -1;
 	dev = cdev->dev;
 
-	size = min((ulong)count, dev->size - offset);
-	debug("mem_read: dev->map_base: %p size: %d offset: %d\n",dev->map_base, size, offset);
-	memcpy_sz(buf, (void *)(dev->map_base + offset), size, flags & O_RWSIZE_MASK);
+	size = min((ulong)count, dev->resource[0].size - offset);
+	memcpy_sz(buf, dev_get_mem_region(dev, 0) + offset, size, flags & O_RWSIZE_MASK);
 	return size;
 }
 EXPORT_SYMBOL(mem_read);
@@ -1059,12 +1058,12 @@ ssize_t mem_write(struct cdev *cdev, const void *buf, size_t count, ulong offset
 	ulong size;
 	struct device_d *dev;
 
-	if (!cdev->dev)
+	if (!cdev->dev || cdev->dev->num_resources < 1)
 		return -1;
 	dev = cdev->dev;
 
-	size = min((ulong)count, dev->size - offset);
-	memcpy_sz((void *)(dev->map_base + offset), buf, size, flags & O_RWSIZE_MASK);
+	size = min((ulong)count, dev->resource[0].size - offset);
+	memcpy_sz(dev_get_mem_region(dev, 0) + offset, buf, size, flags & O_RWSIZE_MASK);
 	return size;
 }
 EXPORT_SYMBOL(mem_write);
diff --git a/include/asm-generic/barebox.lds.h b/include/asm-generic/barebox.lds.h
index 2d1dc411d7..8aee5d2ce4 100644
--- a/include/asm-generic/barebox.lds.h
+++ b/include/asm-generic/barebox.lds.h
@@ -1,5 +1,5 @@
 
-#if defined CONFIG_ARCH_IMX25 || defined CONFIG_ARCH_IMX35 || defined CONFIG_ARCH_IMX51 || defined CONFIG_X86
+#if defined CONFIG_ARCH_IMX25 || defined CONFIG_ARCH_IMX35 || defined CONFIG_ARCH_IMX51 || defined CONFIG_ARCH_IMX53 || defined CONFIG_X86
 #include <mach/barebox.lds.h>
 #endif
 
@@ -16,7 +16,10 @@
 	KEEP(*(.initcall.5))			\
 	KEEP(*(.initcall.6))			\
 	KEEP(*(.initcall.7))			\
-	KEEP(*(.initcall.8))
+	KEEP(*(.initcall.8))			\
+	KEEP(*(.initcall.9))			\
+	KEEP(*(.initcall.10))			\
+	KEEP(*(.initcall.11))
 
 #define BAREBOX_CMDS	KEEP(*(SORT_BY_NAME(.barebox_cmd*)))
 
diff --git a/include/common.h b/include/common.h
index f3353c8643..0ce4a70b56 100644
--- a/include/common.h
+++ b/include/common.h
@@ -221,6 +221,7 @@ int run_shell(void);
 #define ULLONG_MAX	(~0ULL)
 
 #define PAGE_SIZE	4096
+#define PAGE_SHIFT	12
 
 int memory_display(char *addr, ulong offs, ulong nbytes, int size);
 
diff --git a/include/debug_ll.h b/include/debug_ll.h
index e99ae7d207..6b1b174ad4 100644
--- a/include/debug_ll.h
+++ b/include/debug_ll.h
@@ -35,9 +35,22 @@
 			     ch = ((v >> (i*4)) & 0xf);\
 			     ch += (ch >= 10) ? 'a' - 10 : '0';\
 			     PUTC_LL (ch); }})
+
+static __inline__ void PUTS_LL(char * str)
+{
+	while (*str) {
+		if (*str == '\n') {
+			PUTC_LL('\r');
+		}
+		PUTC_LL(*str);
+		str++;
+	}
+}
+
 #else
 # define PUTC_LL(c) do {} while (0)
 # define PUTHEX_LL(v) do {} while (0)
+# define PUTS_LL(c) do {} while (0)
 
 #endif
 
diff --git a/include/dm9000.h b/include/dm9000.h
index b4a04b1e63..a9a4635d2a 100644
--- a/include/dm9000.h
+++ b/include/dm9000.h
@@ -2,14 +2,7 @@
 #ifndef __DM9000_H__
 #define __DM9000_H__
 
-#define DM9000_WIDTH_8		1
-#define DM9000_WIDTH_16		2
-#define DM9000_WIDTH_32		3
-
 struct dm9000_platform_data {
-	unsigned long iobase;
-	unsigned long iodata;
-	int buswidth;
 	int srom;
 };
 
diff --git a/include/driver.h b/include/driver.h
index 6a4d45e3ec..e9ac7279f4 100644
--- a/include/driver.h
+++ b/include/driver.h
@@ -24,9 +24,10 @@
 #define DRIVER_H
 
 #include <linux/list.h>
+#include <linux/ioport.h>
 
 #define MAX_DRIVER_NAME		32
-#define FORMAT_DRIVER_MANE_ID	"%s%d"
+#define FORMAT_DRIVER_NAME_ID	"%s%d"
 
 #include <param.h>
 
@@ -70,11 +71,8 @@ struct device_d {
 	 * something like eth0 or nor0. */
 	int id;
 
-	resource_size_t size;
-
-	/*! For devices which are directly mapped into memory, i.e. NOR
-	 * Flash or SDRAM. */
-	resource_size_t map_base;
+	struct resource *resource;
+	int num_resources;
 
 	void *platform_data; /*! board specific information about this device */
 
@@ -184,6 +182,81 @@ static inline const char *dev_name(const struct device_d *dev)
 	return dev_id(dev);
 }
 
+/*
+ * get register base 'num' for a device
+ */
+void __iomem *dev_get_mem_region(struct device_d *dev, int num);
+
+/*
+ * exlusively request register base 'num' for a device
+ */
+static inline void __iomem *dev_request_mem_region(struct device_d *dev, int num)
+{
+	/* no resource tracking yet */
+	return dev_get_mem_region(dev, num);
+}
+
+/*
+ * register a generic device
+ * with only one resource
+ */
+struct device_d *add_generic_device(const char* devname, int id, const char *resname,
+		resource_size_t start, resource_size_t size, unsigned int flags,
+		void *pdata);
+
+/*
+ * register a memory device
+ */
+static inline struct device_d *add_mem_device(const char *name, resource_size_t start,
+		resource_size_t size, unsigned int flags)
+{
+	return add_generic_device("mem", -1, name, start, size,
+				  IORESOURCE_MEM | flags, NULL);
+}
+
+static inline struct device_d *add_cfi_flash_device(int id, resource_size_t start,
+		resource_size_t size, unsigned int flags)
+{
+	return add_generic_device("cfi_flash", id, NULL, start, size,
+				  IORESOURCE_MEM | flags, NULL);
+}
+
+struct NS16550_plat;
+static inline struct device_d *add_ns16550_device(int id, resource_size_t start,
+		resource_size_t size, int flags, struct NS16550_plat *pdata)
+{
+	return add_generic_device("serial_ns16550", id, NULL, start, size,
+				  IORESOURCE_MEM | flags, pdata);
+}
+
+#ifdef CONFIG_DRIVER_NET_DM9000
+struct device_d *add_dm9000_device(int id, resource_size_t base,
+		resource_size_t data, int flags, void *pdata);
+#else
+static inline struct device_d *add_dm9000_device(int id, resource_size_t base,
+		resource_size_t data, int flags, void *pdata)
+{
+	return NULL;
+}
+#endif
+
+#ifdef CONFIG_USB_EHCI
+struct device_d *add_usb_ehci_device(int id, resource_size_t hccr,
+		resource_size_t hcor, void *pdata);
+#else
+static inline struct device_d *add_usb_ehci_device(int id, resource_size_t hccr,
+		resource_size_t hcor, void *pdata)
+{
+	return NULL;
+}
+#endif
+
+static inline struct device_d *add_generic_usb_ehci_device(int id,
+		resource_size_t base, void *pdata)
+{
+	return add_usb_ehci_device(id, base + 0x100, base + 0x140, pdata);
+}
+
 /* linear list over all available devices
  */
 extern struct list_head device_list;
@@ -326,16 +399,10 @@ int cdev_erase(struct cdev *cdev, size_t count, unsigned long offset);
 #define DEVFS_PARTITION_FIXED		(1 << 0)
 #define DEVFS_PARTITION_READONLY	(1 << 1)
 #define DEVFS_IS_PARTITION		(1 << 2)
-#define DEVFS_RDWR			(1 << 3)
 
 int devfs_add_partition(const char *devname, unsigned long offset, size_t size,
 		int flags, const char *name);
 int devfs_del_partition(const char *name);
 
-struct memory_platform_data {
-	char *name;
-	unsigned int flags;
-};
-
 #endif /* DRIVER_H */
 
diff --git a/include/init.h b/include/init.h
index 2f4fac164b..976f643af8 100644
--- a/include/init.h
+++ b/include/init.h
@@ -30,10 +30,13 @@ typedef int (*initcall_t)(void);
 #define postcore_initcall(fn)		__define_initcall("2",fn,2)
 #define console_initcall(fn)		__define_initcall("3",fn,3)
 #define postconsole_initcall(fn)	__define_initcall("4",fn,4)
-#define coredevice_initcall(fn)		__define_initcall("5",fn,5)
-#define fs_initcall(fn)			__define_initcall("6",fn,6)
-#define device_initcall(fn)		__define_initcall("7",fn,7)
-#define late_initcall(fn)		__define_initcall("8",fn,8)
+#define mem_initcall(fn)		__define_initcall("5",fn,5)
+#define mmu_initcall(fn)		__define_initcall("6",fn,6)
+#define postmmu_initcall(fn)		__define_initcall("7",fn,7)
+#define coredevice_initcall(fn)		__define_initcall("8",fn,8)
+#define fs_initcall(fn)			__define_initcall("9",fn,9)
+#define device_initcall(fn)		__define_initcall("10",fn,10)
+#define late_initcall(fn)		__define_initcall("11",fn,11)
 
 /* section for code used very early when
  * - we're not running from where we linked at
diff --git a/include/ioports.h b/include/ioports.h
deleted file mode 100644
index cfba667cab..0000000000
--- a/include/ioports.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * definitions for MPC8260 I/O Ports
- *
- * (in addition to those provided in <asm/immap_8260.h>)
- *
- * Murray.Jensen@cmst.csiro.au, 20-Oct-00
- */
-
-/*
- * this structure mirrors the layout of the five port registers in
- * the internal memory map - see iop8260_t in <asm/immap_8260.h>
- */
-typedef struct {
-    unsigned int pdir;		/* Port Data Direction Register (35-3) */
-    unsigned int ppar;		/* Port Pin Assignment Register (35-4) */
-    unsigned int psor;		/* Port Special Options Register (35-5) */
-    unsigned int podr;		/* Port Open Drain Register (35-2) */
-    unsigned int pdat;		/* Port Data Register (35-3) */
-} ioport_t;
-
-/*
- * this macro calculates the address within the internal
- * memory map (im) of the set of registers for a port (idx)
- *
- * the internal memory map aligns the above structure on
- * a 0x20 byte boundary
- */
-#ifdef CONFIG_MPC85xx
-#define ioport_addr(im, idx) (ioport_t *)((uint)&((im)->im_cpm.im_cpm_iop) + ((idx)*0x20))
-#else
-#define ioport_addr(im, idx) (ioport_t *)((uint)&(im)->im_ioport + ((idx)*0x20))
-#endif
-
-/*
- * this structure provides configuration
- * information for one port pin
- */
-typedef struct {
-    unsigned char conf:1;	/* if 1, configure this port */
-    unsigned char ppar:1;	/* Port Pin Assignment Register (35-4) */
-    unsigned char psor:1;	/* Port Special Options Register (35-2) */
-    unsigned char pdir:1;	/* Port Data Direction Register (35-3) */
-    unsigned char podr:1;	/* Port Open Drain Register (35-2) */
-    unsigned char pdat:1;	/* Port Data Register (35-2) */
-} iop_conf_t;
-
-/*
- * a table that contains configuration information for all 32 pins
- * of all four MPC8260 I/O ports.
- *
- * NOTE: in the second dimension of this table, index 0 refers to pin 31
- * and index 31 refers to pin 0. this made the code in the table look more
- * like the table in the 8260UM (and in the hymod manuals).
- */
-extern const iop_conf_t iop_conf_tab[4][32];
-
-typedef struct {
-	unsigned char	port;
-	unsigned char	pin;
-	int		dir;
-	int		open_drain;
-	int		assign;
-} qe_iop_conf_t;
-
-#define QE_IOP_TAB_END	(-1)
diff --git a/include/linux/ioport.h b/include/linux/ioport.h
new file mode 100644
index 0000000000..51431158d3
--- /dev/null
+++ b/include/linux/ioport.h
@@ -0,0 +1,115 @@
+/*
+ * ioport.h	Definitions of routines for detecting, reserving and
+ *		allocating system resources.
+ *
+ * Authors:	Linus Torvalds
+ */
+
+#ifndef _LINUX_IOPORT_H
+#define _LINUX_IOPORT_H
+
+#ifndef __ASSEMBLY__
+#include <linux/compiler.h>
+#include <linux/types.h>
+/*
+ * Resources are tree-like, allowing
+ * nesting etc..
+ */
+struct resource {
+	resource_size_t start;
+	resource_size_t size;
+	const char *name;
+	unsigned long flags;
+};
+
+/*
+ * IO resources have these defined flags.
+ */
+#define IORESOURCE_BITS		0x000000ff	/* Bus-specific bits */
+
+#define IORESOURCE_TYPE_BITS	0x00001f00	/* Resource type */
+#define IORESOURCE_IO		0x00000100
+#define IORESOURCE_MEM		0x00000200
+#define IORESOURCE_IRQ		0x00000400
+#define IORESOURCE_DMA		0x00000800
+#define IORESOURCE_BUS		0x00001000
+
+#define IORESOURCE_PREFETCH	0x00002000	/* No side effects */
+#define IORESOURCE_READONLY	0x00004000
+#define IORESOURCE_CACHEABLE	0x00008000
+#define IORESOURCE_RANGELENGTH	0x00010000
+#define IORESOURCE_SHADOWABLE	0x00020000
+
+#define IORESOURCE_SIZEALIGN	0x00040000	/* size indicates alignment */
+#define IORESOURCE_STARTALIGN	0x00080000	/* start field is alignment */
+
+#define IORESOURCE_MEM_64	0x00100000
+#define IORESOURCE_WINDOW	0x00200000	/* forwarded by bridge */
+#define IORESOURCE_MUXED	0x00400000	/* Resource is software muxed */
+
+#define IORESOURCE_EXCLUSIVE	0x08000000	/* Userland may not map this resource */
+#define IORESOURCE_DISABLED	0x10000000
+#define IORESOURCE_UNSET	0x20000000
+#define IORESOURCE_AUTO		0x40000000
+#define IORESOURCE_BUSY		0x80000000	/* Driver has marked this resource busy */
+
+/* PnP IRQ specific bits (IORESOURCE_BITS) */
+#define IORESOURCE_IRQ_HIGHEDGE		(1<<0)
+#define IORESOURCE_IRQ_LOWEDGE		(1<<1)
+#define IORESOURCE_IRQ_HIGHLEVEL	(1<<2)
+#define IORESOURCE_IRQ_LOWLEVEL		(1<<3)
+#define IORESOURCE_IRQ_SHAREABLE	(1<<4)
+#define IORESOURCE_IRQ_OPTIONAL		(1<<5)
+
+/* PnP DMA specific bits (IORESOURCE_BITS) */
+#define IORESOURCE_DMA_TYPE_MASK	(3<<0)
+#define IORESOURCE_DMA_8BIT		(0<<0)
+#define IORESOURCE_DMA_8AND16BIT	(1<<0)
+#define IORESOURCE_DMA_16BIT		(2<<0)
+
+#define IORESOURCE_DMA_MASTER		(1<<2)
+#define IORESOURCE_DMA_BYTE		(1<<3)
+#define IORESOURCE_DMA_WORD		(1<<4)
+
+#define IORESOURCE_DMA_SPEED_MASK	(3<<6)
+#define IORESOURCE_DMA_COMPATIBLE	(0<<6)
+#define IORESOURCE_DMA_TYPEA		(1<<6)
+#define IORESOURCE_DMA_TYPEB		(2<<6)
+#define IORESOURCE_DMA_TYPEF		(3<<6)
+
+/* PnP memory I/O specific bits (IORESOURCE_BITS) */
+#define IORESOURCE_MEM_WRITEABLE	(1<<0)	/* dup: IORESOURCE_READONLY */
+#define IORESOURCE_MEM_CACHEABLE	(1<<1)	/* dup: IORESOURCE_CACHEABLE */
+#define IORESOURCE_MEM_RANGELENGTH	(1<<2)	/* dup: IORESOURCE_RANGELENGTH */
+#define IORESOURCE_MEM_TYPE_MASK	(3<<3)
+#define IORESOURCE_MEM_8BIT		(0<<3)
+#define IORESOURCE_MEM_16BIT		(1<<3)
+#define IORESOURCE_MEM_8AND16BIT	(2<<3)
+#define IORESOURCE_MEM_32BIT		(3<<3)
+#define IORESOURCE_MEM_SHADOWABLE	(1<<5)	/* dup: IORESOURCE_SHADOWABLE */
+#define IORESOURCE_MEM_EXPANSIONROM	(1<<6)
+
+/* PnP I/O specific bits (IORESOURCE_BITS) */
+#define IORESOURCE_IO_16BIT_ADDR	(1<<0)
+#define IORESOURCE_IO_FIXED		(1<<1)
+
+/* PCI ROM control bits (IORESOURCE_BITS) */
+#define IORESOURCE_ROM_ENABLE		(1<<0)	/* ROM is enabled, same as PCI_ROM_ADDRESS_ENABLE */
+#define IORESOURCE_ROM_SHADOW		(1<<1)	/* ROM is copy at C000:0 */
+#define IORESOURCE_ROM_COPY		(1<<2)	/* ROM is alloc'd copy, resource field overlaid */
+#define IORESOURCE_ROM_BIOS_COPY	(1<<3)	/* ROM is BIOS copy, resource field overlaid */
+
+/* PCI control bits.  Shares IORESOURCE_BITS with above PCI ROM.  */
+#define IORESOURCE_PCI_FIXED		(1<<4)	/* Do not move resource */
+
+static inline resource_size_t resource_size(const struct resource *res)
+{
+	return res->size;
+}
+static inline unsigned long resource_type(const struct resource *res)
+{
+	return res->flags & IORESOURCE_TYPE_BITS;
+}
+
+#endif /* __ASSEMBLY__ */
+#endif	/* _LINUX_IOPORT_H */
diff --git a/include/net.h b/include/net.h
index 31bf6a23fc..1272f23c02 100644
--- a/include/net.h
+++ b/include/net.h
@@ -28,8 +28,6 @@
 struct device_d;
 
 struct eth_device {
-	int iobase;
-	int state;
 	int active;
 
 	int  (*init) (struct eth_device*);
@@ -57,6 +55,12 @@ int eth_send(void *packet, int length);	   /* Send a packet		*/
 int eth_rx(void);			/* Check for received packets	*/
 void eth_halt(void);			/* stop SCC			*/
 
+/* associate a MAC address to a ethernet device. Should be called by
+ * board code for boards which store their MAC address at some unusual
+ * place.
+ */
+void eth_register_ethaddr(int ethid, const char *ethaddr);
+
 /*
  *	Ethernet header
  */
diff --git a/include/ns16550.h b/include/ns16550.h
index b40d1fa5ae..5fd52fa744 100644
--- a/include/ns16550.h
+++ b/include/ns16550.h
@@ -50,6 +50,8 @@ struct NS16550_plat {
 	 */
 	void (*reg_write) (unsigned int val, unsigned long base,
 				    unsigned char reg_offset);
+
+	int shift;
 };
 
 #endif				/* __NS16650_PLATFORM_H_ */
diff --git a/lib/Makefile b/lib/Makefile
index 8b986d2a70..d96cfe7c67 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -5,8 +5,6 @@ obj-y			+= string.o
 obj-y			+= vsprintf.o
 obj-y			+= div64.o
 obj-y			+= misc.o
-obj-y			+= driver.o
-obj-y			+= bus.o
 obj-y			+= parameter.o
 obj-y			+= xfuncs.o
 obj-y			+= getopt.o
diff --git a/net/eth.c b/net/eth.c
index c5b346c28e..2a801f5ce4 100644
--- a/net/eth.c
+++ b/net/eth.c
@@ -34,6 +34,52 @@ static struct eth_device *eth_current;
 
 static LIST_HEAD(netdev_list);
 
+struct eth_ethaddr {
+	struct list_head list;
+	u8 ethaddr[6];
+	int ethid;
+};
+
+static LIST_HEAD(ethaddr_list);
+
+static int eth_get_registered_ethaddr(int ethid, void *buf)
+{
+	struct eth_ethaddr *addr;
+
+	list_for_each_entry(addr, &ethaddr_list, list) {
+		if (addr->ethid == ethid) {
+			memcpy(buf, addr->ethaddr, 6);
+			return 0;
+		}
+	}
+	return -EINVAL;
+}
+
+static void eth_drop_ethaddr(int ethid)
+{
+	struct eth_ethaddr *addr, *tmp;
+
+	list_for_each_entry_safe(addr, tmp, &ethaddr_list, list) {
+		if (addr->ethid == ethid) {
+			list_del(&addr->list);
+			free(addr);
+			return;
+		}
+	}
+}
+
+void eth_register_ethaddr(int ethid, const char *ethaddr)
+{
+	struct eth_ethaddr *addr;
+
+	eth_drop_ethaddr(ethid);
+
+	addr = xzalloc(sizeof(*addr));
+	addr->ethid = ethid;
+	memcpy(addr->ethaddr, ethaddr, 6);
+	list_add_tail(&addr->list, &ethaddr_list);
+}
+
 void eth_set_current(struct eth_device *eth)
 {
 	if (eth_current && eth_current->active) {
@@ -144,6 +190,7 @@ int eth_register(struct eth_device *edev)
         struct device_d *dev = &edev->dev;
 	unsigned char ethaddr_str[20];
 	unsigned char ethaddr[6];
+	int ret, found = 0;
 
 	if (!edev->get_ethaddr) {
 		dev_err(dev, "no get_mac_address found for current eth device\n");
@@ -165,7 +212,17 @@ int eth_register(struct eth_device *edev)
 
 	list_add_tail(&edev->list, &netdev_list);
 
-	if (edev->get_ethaddr(edev, ethaddr) == 0) {
+	ret = eth_get_registered_ethaddr(dev->id, ethaddr);
+	if (!ret)
+		found = 1;
+
+	if (!found) {
+		ret = edev->get_ethaddr(edev, ethaddr);
+		if (!ret)
+			found = 1;
+	}
+
+	if (found) {
 		ethaddr_to_string(ethaddr, ethaddr_str);
 		if (is_valid_ether_addr(ethaddr)) {
 			dev_info(dev, "got MAC address from EEPROM: %s\n", ethaddr_str);