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authorTeresa Gámez <t.gamez@phytec.de>2011-08-24 10:56:50 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2011-08-24 18:39:14 +0200
commitaa2859577032b57ae59344a0d394e24373b03935 (patch)
tree752526f31ff91a62108cfc017ffa7173423aab3b
parente064ad3628aa6807e282eae2dd6b70f805986cba (diff)
downloadbarebox-aa2859577032b57ae59344a0d394e24373b03935.tar.gz
barebox-aa2859577032b57ae59344a0d394e24373b03935.tar.xz
ARM pcm043: New NOR Flash CS0 values
Set new CS0 values for new NOR-Flashes (28F256P33BF). These values also work with older flashes (28F256P33B). Also removed unnecessary setup of CSO in the core_init call. Signed-off-by: Teresa Gámez <t.gamez@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--arch/arm/boards/pcm043/pcm043.c10
1 files changed, 3 insertions, 7 deletions
diff --git a/arch/arm/boards/pcm043/pcm043.c b/arch/arm/boards/pcm043/pcm043.c
index 966899a5b..fbe8cea12 100644
--- a/arch/arm/boards/pcm043/pcm043.c
+++ b/arch/arm/boards/pcm043/pcm043.c
@@ -124,9 +124,9 @@ static int imx35_devices_init(void)
uint32_t reg;
/* CS0: Nor Flash */
- writel(0x0000cf03, CSCR_U(0));
- writel(0x10000d03, CSCR_L(0));
- writel(0x00720900, CSCR_A(0));
+ writel(0x22C0CF00, CSCR_U(0));
+ writel(0x75000D01, CSCR_L(0));
+ writel(0x00000900, CSCR_A(0));
led_gpio_register(&led0);
@@ -277,10 +277,6 @@ static int pcm043_core_setup(void)
writel(0x0, IMX_MAX_BASE + 0xc00); /* for M4 */
writel(0x0, IMX_MAX_BASE + 0xd00); /* for M5 */
- writel(0x0000DCF6, CSCR_U(0)); /* CS0: NOR Flash */
- writel(0x444A4541, CSCR_L(0));
- writel(0x44443302, CSCR_A(0));
-
/*
* M3IF Control Register (M3IFCTL)
* MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000