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| author | Marc Kleine-Budde <mkl@pengutronix.de> | 2013-04-19 16:36:29 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2013-04-24 16:45:08 +0200 |
| commit | 8bafdc1c46caf86546ad11de815cff774526d033 (patch) | |
| tree | 94b2faad7a7773a7558bfb6e17ae55b670cd5a78 | |
| parent | 46d7027a6a41ef8855e5bd2b38896eae339d47b7 (diff) | |
| download | barebox-8bafdc1c46caf86546ad11de815cff774526d033.tar.gz barebox-8bafdc1c46caf86546ad11de815cff774526d033.tar.xz | |
ARM i.MX28: make chip reset via reset pin work again
Since commit:
2ccd451 ARM i.MX28: change default watchdog reset method
the external reset via the reset pin is broken. That commit overwrites the
HW_CLKCTRL_RESET register with only WDOG_POR_DISABLE set, which results in
disabling the external reset.
This patch uses read-modify-write to set the WDOG_POR_DISABLE, leaving the
WDOG_POR_DISABLE untouched.
Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| -rw-r--r-- | arch/arm/mach-mxs/soc-imx28.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm/mach-mxs/soc-imx28.c b/arch/arm/mach-mxs/soc-imx28.c index 8972a3d909..ed931afc32 100644 --- a/arch/arm/mach-mxs/soc-imx28.c +++ b/arch/arm/mach-mxs/soc-imx28.c @@ -39,12 +39,16 @@ EXPORT_SYMBOL(reset_cpu); static int imx28_init(void) { + u32 reg; + /* * The default setting for the WDT is to do a POR. If the SoC is only * powered via battery, then a WDT reset powers the chip down instead * of resetting it. Use a software reset only. */ - writel(HW_CLKCTRL_WDOG_POR_DISABLE, IMX_CCM_BASE + HW_CLKCTRL_RESET); + reg = readl(IMX_CCM_BASE + HW_CLKCTRL_RESET) | + HW_CLKCTRL_WDOG_POR_DISABLE; + writel(reg, IMX_CCM_BASE + HW_CLKCTRL_RESET); return 0; } |