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| author | Enrico Scholz <enrico.scholz@sigma-chemnitz.de> | 2013-05-14 15:14:56 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2013-05-23 09:29:47 +0200 |
| commit | 465950ee64f6fbeb0daf138c2d43ad71be159375 (patch) | |
| tree | 2b7255e7951d88d994283e462d3f3dfa2138dfec | |
| parent | 9dac54b56a679cd1b64d1e4110b9a0053dacef2d (diff) | |
| download | barebox-465950ee64f6fbeb0daf138c2d43ad71be159375.tar.gz barebox-465950ee64f6fbeb0daf138c2d43ad71be159375.tar.xz | |
ARM v7: added v7_mmu_cache_invalidate()
At least the iMX6 boot rom seems to jump into barebox with a non
invalidated d-cache which causes data corruption when
v7_mmu_cache_flush() executed by arm_early_mmu_cache_flush() overrides
stack or other valid data.
That's why the cache must be invalided for this processors explicitly
(e.g. in barebox_arm_reset_vector()). Operation differs from flush only
in one instruction so that patch modifies the existing
v7_mmu_cache_flush() function slightly by adding an optional argument.
Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| -rw-r--r-- | arch/arm/cpu/cache-armv7.S | 24 |
1 files changed, 19 insertions, 5 deletions
diff --git a/arch/arm/cpu/cache-armv7.S b/arch/arm/cpu/cache-armv7.S index 5595cf6994..c19618bde1 100644 --- a/arch/arm/cpu/cache-armv7.S +++ b/arch/arm/cpu/cache-armv7.S @@ -56,8 +56,18 @@ ENTRY(v7_mmu_cache_off) ldmfd sp!, {r4-r12, pc} ENDPROC(v7_mmu_cache_off) -.section .text.v7_mmu_cache_flush +.section .text.v7_mmu_cache_flush_invalidate +ENTRY(v7_mmu_cache_invalidate) + mov r0, #1 + b __v7_mmu_cache_flush_invalidate +ENDPROC(v7_mmu_cache_invalidate) + ENTRY(v7_mmu_cache_flush) + mov r0, #0 + b __v7_mmu_cache_flush_invalidate +ENDPROC(v7_mmu_cache_flush) + +ENTRY(__v7_mmu_cache_flush_invalidate) mrc p15, 0, r12, c0, c1, 5 @ read ID_MMFR1 tst r12, #0xf << 16 @ hierarchical cache (ARMv7) mov r12, #0 @@ -65,7 +75,8 @@ ENTRY(v7_mmu_cache_flush) mcr p15, 0, r12, c7, c14, 0 @ clean+invalidate D b iflush hierarchical: - stmfd sp!, {r4-r7, r9-r11} + stmfd sp!, {r4-r11} + mov r8, r0 mcr p15, 0, r12, c7, c10, 5 @ DMB mrc p15, 1, r0, c0, c0, 1 @ read clidr ands r3, r0, #0x7000000 @ extract loc from clidr @@ -97,7 +108,10 @@ THUMB( lsl r6, r9, r5 ) THUMB( orr r11, r12, r6 ) @ factor way and cache number into r11 THUMB( lsl r6, r7, r2 ) THUMB( orr r11, r11, r6 ) @ factor index number into r11 - mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way + cmp r8, #0 +THUMB( ite eq ) + mcreq p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way + mcrne p15, 0, r11, c7, c6, 2 @ invalidate by set/way subs r9, r9, #1 @ decrement the way bge loop3 subs r7, r7, #1 @ decrement the index @@ -107,7 +121,7 @@ skip: cmp r3, r12 bgt loop1 finished: - ldmfd sp!, {r4-r7, r9-r11} + ldmfd sp!, {r4-r11} mov r12, #0 @ switch back to cache level 0 mcr p15, 2, r12, c0, c0, 0 @ select current cache level in cssr iflush: @@ -116,7 +130,7 @@ iflush: mcr p15, 0, r12, c7, c10, 4 @ DSB mcr p15, 0, r12, c7, c5, 4 @ ISB mov pc, lr -ENDPROC(v7_mmu_cache_flush) +ENDPROC(__v7_mmu_cache_flush_invalidate) /* * cache_line_size - get the cache line size from the CSIDR register |