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| author | Enrico Scholz <enrico.scholz@sigma-chemnitz.de> | 2013-05-14 15:14:55 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2013-05-23 09:29:41 +0200 |
| commit | 9dac54b56a679cd1b64d1e4110b9a0053dacef2d (patch) | |
| tree | 31a757fe9ba13af708f72c0739169e2633e75a01 | |
| parent | 431d8a247dfa63f817cda137a81dbb2244d413dc (diff) | |
| download | barebox-9dac54b56a679cd1b64d1e4110b9a0053dacef2d.tar.gz barebox-9dac54b56a679cd1b64d1e4110b9a0053dacef2d.tar.xz | |
ARM v7: v7_mmu_cache_flush(): do not restore r0-r3 (minor optimization)
Registers 'r0' till 'r3' are scratch registers and do not need to be
restored.
Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| -rw-r--r-- | arch/arm/cpu/cache-armv7.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/cpu/cache-armv7.S b/arch/arm/cpu/cache-armv7.S index 5bdf7e4bd5..5595cf6994 100644 --- a/arch/arm/cpu/cache-armv7.S +++ b/arch/arm/cpu/cache-armv7.S @@ -65,7 +65,7 @@ ENTRY(v7_mmu_cache_flush) mcr p15, 0, r12, c7, c14, 0 @ clean+invalidate D b iflush hierarchical: - stmfd sp!, {r0-r7, r9-r11} + stmfd sp!, {r4-r7, r9-r11} mcr p15, 0, r12, c7, c10, 5 @ DMB mrc p15, 1, r0, c0, c0, 1 @ read clidr ands r3, r0, #0x7000000 @ extract loc from clidr @@ -107,7 +107,7 @@ skip: cmp r3, r12 bgt loop1 finished: - ldmfd sp!, {r0-r7, r9-r11} + ldmfd sp!, {r4-r7, r9-r11} mov r12, #0 @ switch back to cache level 0 mcr p15, 2, r12, c0, c0, 0 @ select current cache level in cssr iflush: |