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authorAndreas Pretzsch <apr@cn-eng.de>2013-05-06 23:21:28 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2013-05-07 08:36:21 +0200
commit73c6c6da8a6d88cf901126519d6c7397c7c46c83 (patch)
treef70d7936237810e0f965c120980dbb171a7d6c57
parent3c4c5eefab8537ebf69b87f8394202651ae989c6 (diff)
downloadbarebox-73c6c6da8a6d88cf901126519d6c7397c7c46c83.tar.gz
barebox-73c6c6da8a6d88cf901126519d6c7397c7c46c83.tar.xz
ARM i.MX31 pcm037: fix erroneous IOMUX GPR setup in pcm037_usb_init()
In commit ad09b59f8bb58c27e3872b41f41beb1b9eb1aeb1 "ARM i.MX31: give register base addresses a proper MX31_ prefix", the IOMUX GPR setup to enable USBH2 was replaced with an incorrect source register. Instead of reading the GPR register, USBOTG HWHOST is used as rmw source, which contains 0x10020001. Beside the intended GPR[11] setup ("Enable USBH2 signals on AudioPort 3 and AudioPort6"), this erroneously also sets GPR[28] enable USBOTG loopback GPR[17] override DSR_DCE1 with USBOTG_DATA4 GPR[0] select FIR DMA requests instead of UART2 DMA Beside breaking UART2, it probably also broke some UART1 and USB OTG setups. Fix this and replace the address with the appropriate defines. Signed-off-by: Andreas Pretzsch <apr@cn-eng.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--arch/arm/boards/pcm037/pcm037.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/boards/pcm037/pcm037.c b/arch/arm/boards/pcm037/pcm037.c
index 276f9cda41..9361a9d523 100644
--- a/arch/arm/boards/pcm037/pcm037.c
+++ b/arch/arm/boards/pcm037/pcm037.c
@@ -83,9 +83,9 @@ static void pcm037_usb_init(void)
ulpi_setup((void *)(MX31_USB_OTG_BASE_ADDR + 0x170), 1);
/* Host 2 */
- tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x8);
- tmp |= 1 << 11;
- writel(tmp, MX31_IOMUXC_BASE_ADDR + 0x8);
+ tmp = readl(MX31_IOMUXC_GPR);
+ tmp |= 1 << 11; /* IOMUX GPR: enable USBH2 signals */
+ writel(tmp, MX31_IOMUXC_GPR);
imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC));
imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC));