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authorSascha Hauer <s.hauer@pengutronix.de>2013-08-05 12:50:09 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2013-08-05 12:50:09 +0200
commita67ba6597dfb5e0127742064748227471e616e31 (patch)
treeced26371dcadd555a10d831b5e320fa9ce33d3df
parent8599b7aec2a6220e37c64f004342c23342e2eb25 (diff)
parent89cdacb0cbd0a5914d8e3e1fa00cfdf85f83ef1d (diff)
downloadbarebox-a67ba6597dfb5e0127742064748227471e616e31.tar.gz
barebox-a67ba6597dfb5e0127742064748227471e616e31.tar.xz
Merge branch 'for-next/ppc'
-rw-r--r--arch/ppc/boards/freescale-p2020rdb/config.h4
-rw-r--r--arch/ppc/boards/freescale-p2020rdb/p2020rdb.c4
-rw-r--r--arch/ppc/cpu-85xx/start.S1
-rw-r--r--arch/ppc/include/asm/fsl_lbc.h2
-rw-r--r--arch/ppc/mach-mpc85xx/Makefile1
-rw-r--r--arch/ppc/mach-mpc85xx/cpu_init.c5
-rw-r--r--arch/ppc/mach-mpc85xx/fsl_lbc.c17
7 files changed, 7 insertions, 27 deletions
diff --git a/arch/ppc/boards/freescale-p2020rdb/config.h b/arch/ppc/boards/freescale-p2020rdb/config.h
index 3b2bb5ed04..c6d32161cf 100644
--- a/arch/ppc/boards/freescale-p2020rdb/config.h
+++ b/arch/ppc/boards/freescale-p2020rdb/config.h
@@ -87,8 +87,4 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
/* Leave 256 bytes for global data */
#define CFG_INIT_SP_OFFSET (0x00004000 - 256)
-#define CFG_BR0_PRELIM (BR_PHYS_ADDR(CFG_FLASH_BASE_PHYS) | \
- BR_PS_16 | BR_V) /* NOR Base Address */
-#define CFG_OR0_PRELIM 0xff000ff7 /* NOR Options */
-
#endif /* __CONFIG_H */
diff --git a/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c b/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c
index 6426bd3c7e..537565da6b 100644
--- a/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c
+++ b/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c
@@ -235,6 +235,10 @@ static int board_init_r(void)
checkboard();
+ /* Map the whole boot flash */
+ fsl_set_lbc_br(0, BR_PHYS_ADDR(CFG_FLASH_BASE_PHYS) | BR_PS_16 | BR_V);
+ fsl_set_lbc_or(0, 0xff000ff7);
+
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
diff --git a/arch/ppc/cpu-85xx/start.S b/arch/ppc/cpu-85xx/start.S
index c0e5ec0cfc..5bcba5fcc9 100644
--- a/arch/ppc/cpu-85xx/start.S
+++ b/arch/ppc/cpu-85xx/start.S
@@ -300,7 +300,6 @@ _start_cont:
mtmsr r3
isync
- bl cpu_init_f
bl initdram
b relocate_code
isync
diff --git a/arch/ppc/include/asm/fsl_lbc.h b/arch/ppc/include/asm/fsl_lbc.h
index 47205e7ab9..58cd080e50 100644
--- a/arch/ppc/include/asm/fsl_lbc.h
+++ b/arch/ppc/include/asm/fsl_lbc.h
@@ -44,8 +44,6 @@
#ifndef __ASSEMBLY__
#include <asm/io.h>
-extern void fsl_init_early_memctl_regs(void);
-
/* LBC register offsets. */
#define FSL_LBC_BRX(x) ((x) * 8) /* bank register offsets. */
#define FSL_LBC_ORX(x) (4 + ((x) * 8)) /* option register offset. */
diff --git a/arch/ppc/mach-mpc85xx/Makefile b/arch/ppc/mach-mpc85xx/Makefile
index af9be29271..cc412c51da 100644
--- a/arch/ppc/mach-mpc85xx/Makefile
+++ b/arch/ppc/mach-mpc85xx/Makefile
@@ -1,7 +1,6 @@
obj-y += cpuid.o
obj-y += cpu.o
obj-y += cpu_init.o
-obj-y += fsl_lbc.o
obj-y += fsl_law.o
obj-y += speed.o
obj-y +=time.o
diff --git a/arch/ppc/mach-mpc85xx/cpu_init.c b/arch/ppc/mach-mpc85xx/cpu_init.c
index ec9763e322..8372b7f0bc 100644
--- a/arch/ppc/mach-mpc85xx/cpu_init.c
+++ b/arch/ppc/mach-mpc85xx/cpu_init.c
@@ -114,10 +114,11 @@ void cpu_init_early_f(void)
e500_init_tlbs();
}
-void cpu_init_f(void)
+static int cpu_init_r(void)
{
e500_disable_tlb(14);
e500_disable_tlb(15);
- fsl_init_early_memctl_regs();
+ return 0;
}
+core_initcall(cpu_init_r);
diff --git a/arch/ppc/mach-mpc85xx/fsl_lbc.c b/arch/ppc/mach-mpc85xx/fsl_lbc.c
deleted file mode 100644
index ac9ca7402b..0000000000
--- a/arch/ppc/mach-mpc85xx/fsl_lbc.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#include <common.h>
-#include <asm/fsl_lbc.h>
-#include <mach/immap_85xx.h>
-
-void fsl_init_early_memctl_regs(void)
-{
- fsl_set_lbc_br(0, CFG_BR0_PRELIM);
- fsl_set_lbc_or(0, CFG_OR0_PRELIM);
-}