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| author | Eric Bénard <eric@eukrea.com> | 2013-09-10 19:57:54 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2013-09-10 21:03:59 +0200 |
| commit | f0b68f0008f94606f6b927590d1fafb34b1abc55 (patch) | |
| tree | 3bc29b6a7f19bf0940db28c34ba5a0bf5dc823ad | |
| parent | bf04eedf69d8842f0ba1e88bebce214d84cd8c04 (diff) | |
| download | barebox-f0b68f0008f94606f6b927590d1fafb34b1abc55.tar.gz barebox-f0b68f0008f94606f6b927590d1fafb34b1abc55.tar.xz | |
usb-imx28: fix enable
we need to power on the PLL when enabling the USB clock.
Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| -rw-r--r-- | arch/arm/mach-mxs/usb-imx28.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm/mach-mxs/usb-imx28.c b/arch/arm/mach-mxs/usb-imx28.c index 61d59c3616..e5b63c30a0 100644 --- a/arch/arm/mach-mxs/usb-imx28.c +++ b/arch/arm/mach-mxs/usb-imx28.c @@ -46,6 +46,7 @@ #define CLK_PLL0CTRL0 (IMX_CCM_BASE + 0x0) #define CLK_PLL1CTRL0 (IMX_CCM_BASE + 0x20) #define PLLCTRL0_EN_USB_CLKS (1 << 18) +#define PLLCTRL0_POWER (1 << 17) #define DIGCTRL_CTRL (IMX_DIGCTL_BASE + 0x0) #define DIGCTL_CTRL_USB0_CLKGATE (1 << 2) @@ -77,7 +78,7 @@ int imx28_usb_phy0_enable(void) imx28_usb_phy_reset((void *)IMX_USBPHY0_BASE); /* Turn on the USB clocks */ - writel(PLLCTRL0_EN_USB_CLKS, CLK_PLL0CTRL0 + SET); + writel(PLLCTRL0_EN_USB_CLKS | PLLCTRL0_POWER, CLK_PLL0CTRL0 + SET); writel(DIGCTL_CTRL_USB0_CLKGATE, DIGCTRL_CTRL + CLR); @@ -91,7 +92,7 @@ int imx28_usb_phy1_enable(void) imx28_usb_phy_reset((void *)IMX_USBPHY1_BASE); /* Turn on the USB clocks */ - writel(PLLCTRL0_EN_USB_CLKS, CLK_PLL1CTRL0 + SET); + writel(PLLCTRL0_EN_USB_CLKS | PLLCTRL0_POWER, CLK_PLL1CTRL0 + SET); writel(DIGCTL_CTRL_USB1_CLKGATE, DIGCTRL_CTRL + CLR); |