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| author | Teresa Gámez <t.gamez@phytec.de> | 2013-08-29 14:54:15 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2013-09-05 10:15:49 +0200 |
| commit | f1cf4433bfc2d2e7bfdab8eacc401a0ccf2fe08d (patch) | |
| tree | f1ee5b4a67f3bf0715457a3662dbbf6aaef890e2 | |
| parent | 327e3e128bb19a3185ef9f255480bb40f6113a70 (diff) | |
| download | barebox-f1cf4433bfc2d2e7bfdab8eacc401a0ccf2fe08d.tar.gz barebox-f1cf4433bfc2d2e7bfdab8eacc401a0ccf2fe08d.tar.xz | |
PCM051: Fixup DDRPLL
The correct DDRPLL for PCM051 is 303MHz.
Signed-off-by: Teresa Gámez <t.gamez@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| -rw-r--r-- | arch/arm/boards/pcm051/lowlevel.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-omap/include/mach/am33xx-clock.h | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/boards/pcm051/lowlevel.c b/arch/arm/boards/pcm051/lowlevel.c index 078e83b033..48578cd46c 100644 --- a/arch/arm/boards/pcm051/lowlevel.c +++ b/arch/arm/boards/pcm051/lowlevel.c @@ -68,7 +68,7 @@ static int pcm051_board_init(void) if (running_in_sdram()) return 0; - pll_init(MPUPLL_M_600, 25, DDRPLL_M_266); + pll_init(MPUPLL_M_600, 25, DDRPLL_M_303); am335x_sdram_init(0x18B, &MT41J256M8HX15E_2x256M8_cmd, &MT41J256M8HX15E_2x256M8_regs, diff --git a/arch/arm/mach-omap/include/mach/am33xx-clock.h b/arch/arm/mach-omap/include/mach/am33xx-clock.h index b3c7519c0d..ecd90b2229 100644 --- a/arch/arm/mach-omap/include/mach/am33xx-clock.h +++ b/arch/arm/mach-omap/include/mach/am33xx-clock.h @@ -49,6 +49,7 @@ /* DDR Freq is 266 MHZ for now*/ /* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */ #define DDRPLL_M_266 266 +#define DDRPLL_M_303 303 #define DDRPLL_M_400 400 #define DDRPLL_N (OSC - 1) #define DDRPLL_M2 1 |