Merge branch 'for-next/tegra'

14 files changed, 256 insertions, 21 deletions

diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index 8ee1bb7a05..0d8c9cf4cf 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -85,7 +85,7 @@ obj-$(CONFIG_MACH_SOLIDRUN_HUMMINGBOARD)	+= solidrun-hummingboard/
 obj-$(CONFIG_MACH_TNY_A9260)			+= tny-a926x/
 obj-$(CONFIG_MACH_TNY_A9263)			+= tny-a926x/
 obj-$(CONFIG_MACH_TNY_A9G20)			+= tny-a926x/
-obj-$(CONFIG_MACH_TORADEX_COLIBRI_T20_IRIS)	+= toradex-colibri-t20-iris/
+obj-$(CONFIG_MACH_TORADEX_COLIBRI_T20)		+= toradex-colibri-t20/
 obj-$(CONFIG_MACH_TOSHIBA_AC100)		+= toshiba-ac100/
 obj-$(CONFIG_MACH_TQMA53)			+= tqma53/
 obj-$(CONFIG_MACH_TQMA6X)			+= tqma6x/
diff --git a/arch/arm/boards/toradex-colibri-t20-iris/Makefile b/arch/arm/boards/toradex-colibri-t20/Makefile
index 5be3dd0e7c..5be3dd0e7c 100644
--- a/arch/arm/boards/toradex-colibri-t20-iris/Makefile
+++ b/arch/arm/boards/toradex-colibri-t20/Makefile
diff --git a/arch/arm/boards/toradex-colibri-t20-iris/entry.c b/arch/arm/boards/toradex-colibri-t20/entry.c
index 886613f13d..886613f13d 100644
--- a/arch/arm/boards/toradex-colibri-t20-iris/entry.c
+++ b/arch/arm/boards/toradex-colibri-t20/entry.c
diff --git a/arch/arm/configs/tegra_v7_defconfig b/arch/arm/configs/tegra_v7_defconfig
index 831c13889f..f76b5017a8 100644
--- a/arch/arm/configs/tegra_v7_defconfig
+++ b/arch/arm/configs/tegra_v7_defconfig
@@ -1,5 +1,5 @@
 CONFIG_ARCH_TEGRA=y
-CONFIG_MACH_TORADEX_COLIBRI_T20_IRIS=y
+CONFIG_MACH_TORADEX_COLIBRI_T20=y
 CONFIG_MACH_TOSHIBA_AC100=y
 CONFIG_AEABI=y
 CONFIG_CMD_ARM_MMUINFO=y
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 1417093095..6bac3b908f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -47,7 +47,7 @@ pbl-$(CONFIG_MACH_PHYTEC_PFLA02) += imx6q-phytec-pbab01.dtb.o
 pbl-$(CONFIG_MACH_REALQ7) += imx6q-dmo-edmqmx6.dtb.o
 pbl-$(CONFIG_MACH_SOLIDRUN_CUBOX) += dove-cubox-bb.dtb.o
 pbl-$(CONFIG_MACH_GK802) += imx6q-gk802.dtb.o
-pbl-$(CONFIG_MACH_TORADEX_COLIBRI_T20_IRIS) += tegra20-colibri-iris.dtb.o
+pbl-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += tegra20-colibri-iris.dtb.o
 pbl-$(CONFIG_MACH_TOSHIBA_AC100) += tegra20-paz00.dtb.o
 pbl-$(CONFIG_MACH_TQMA53) += imx53-mba53.dtb.o
 pbl-$(CONFIG_MACH_TQMA6X) += imx6dl-mba6x.dtb.o imx6q-mba6x.dtb.o
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 3becb84d00..34e1c37f54 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -48,8 +48,8 @@ config ARCH_TEGRA_2x_SOC
 
 menu "select Tegra boards to be built"
 
-config MACH_TORADEX_COLIBRI_T20_IRIS
-	bool "Toradex Colibri T20 on Iris Carrier"
+config MACH_TORADEX_COLIBRI_T20
+	bool "Toradex Colibri T20"
 	select ARCH_TEGRA_2x_SOC
 
 config MACH_TOSHIBA_AC100
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 0fa843022b..791d5d45a7 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,5 +1,5 @@
-CFLAGS_tegra_avp_init.o := -mcpu=arm7tdmi -march=armv4t
-CFLAGS_pbl-tegra_avp_init.o := -mcpu=arm7tdmi -march=armv4t
+CFLAGS_tegra_avp_init.o := -mcpu=arm7tdmi -march=armv4t -fno-jump-tables
+CFLAGS_pbl-tegra_avp_init.o := -mcpu=arm7tdmi -march=armv4t -fno-jump-tables
 lwl-y += tegra_avp_init.o
 lwl-y += tegra_maincomplex_init.o
 obj-y += tegra20.o
diff --git a/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h b/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h
new file mode 100644
index 0000000000..f7f6328f65
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/lowlevel-dvc.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/compiler.h>
+#include "mach/tegra20-car.h"
+#include "mach/lowlevel.h"
+
+static __always_inline
+void tegra_dvc_init(void)
+{
+	int div;
+	u32 reg;
+
+	/* reset DVC controller and enable clock */
+	writel(CRC_RST_DEV_H_DVC, TEGRA_CLK_RESET_BASE + CRC_RST_DEV_H_SET);
+	reg = readl(TEGRA_CLK_RESET_BASE + CRC_CLK_OUT_ENB_H);
+	reg |= CRC_CLK_OUT_ENB_H_DVC;
+	writel(reg, TEGRA_CLK_RESET_BASE + CRC_CLK_OUT_ENB_H);
+
+	/* set DVC I2C clock source to CLK_M and aim for 100kHz I2C clock */
+	div = ((tegra_get_osc_clock() * 3) >> 22) - 1;
+	writel((div) | (3 << 30),
+	       TEGRA_CLK_RESET_BASE + CRC_CLK_SOURCE_DVC);
+
+	/* clear DVC reset */
+	tegra_ll_delay_usec(3);
+	writel(CRC_RST_DEV_H_DVC, TEGRA_CLK_RESET_BASE + CRC_RST_DEV_H_CLR);
+}
+
+#define TEGRA_I2C_CNFG		0x00
+#define TEGRA_I2C_CMD_ADDR0	0x04
+#define TEGRA_I2C_CMD_DATA1	0x0c
+#define TEGRA_I2C_SEND_2_BYTES	0x0a02
+
+static __always_inline
+void tegra_dvc_write_addr(u32 addr, u32 config)
+{
+	writel(addr, TEGRA_DVC_BASE + TEGRA_I2C_CMD_ADDR0);
+	writel(config, TEGRA_DVC_BASE + TEGRA_I2C_CNFG);
+}
+
+static __always_inline
+void tegra_dvc_write_data(u32 data, u32 config)
+{
+	writel(data, TEGRA_DVC_BASE + TEGRA_I2C_CMD_DATA1);
+	writel(config, TEGRA_DVC_BASE + TEGRA_I2C_CNFG);
+}
+
+static inline __attribute__((always_inline))
+void tegra30_tps65911_cpu_rail_enable(void)
+{
+	tegra_dvc_write_addr(0x5a, 2);
+	/* reg 28, 600mV + (35-3) * 12,5mV = 1,0V */
+	tegra_dvc_write_data(0x2328, TEGRA_I2C_SEND_2_BYTES);
+	tegra_ll_delay_usec(1000);
+	/* reg 27, VDDctrl enable */
+	tegra_dvc_write_data(0x0127, TEGRA_I2C_SEND_2_BYTES);
+	tegra_ll_delay_usec(10 * 1000);
+}
diff --git a/arch/arm/mach-tegra/include/mach/lowlevel.h b/arch/arm/mach-tegra/include/mach/lowlevel.h
index 472348acab..cc346a023d 100644
--- a/arch/arm/mach-tegra/include/mach/lowlevel.h
+++ b/arch/arm/mach-tegra/include/mach/lowlevel.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
+ * Copyright (C) 2013-2014 Lucas Stach <l.stach@pengutronix.de>
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -21,6 +21,10 @@
  * be used by both the main CPU complex (ARMv7) and the AVP (ARMv4).
  */
 
+#ifndef __TEGRA_LOWLEVEL_H
+#define __TEGRA_LOWLEVEL_H
+
+#include <linux/compiler.h>
 #include <sizes.h>
 #include <io.h>
 #include <mach/iomap.h>
@@ -40,7 +44,7 @@
 #define T20_ODMDATA_UARTID_SHIFT	15
 #define T20_ODMDATA_UARTID_MASK		(7 << T20_ODMDATA_UARTID_SHIFT)
 
-static inline __attribute__((always_inline))
+static __always_inline
 u32 tegra_get_odmdata(void)
 {
 	u32 bctsize, bctptr, odmdata;
@@ -61,9 +65,10 @@ u32 tegra_get_odmdata(void)
 enum tegra_chiptype {
 	TEGRA_UNK_REV = -1,
 	TEGRA20 = 0,
+	TEGRA30 = 1,
 };
 
-static inline __attribute__((always_inline))
+static __always_inline
 enum tegra_chiptype tegra_get_chiptype(void)
 {
 	u32 hidrev;
@@ -73,26 +78,28 @@ enum tegra_chiptype tegra_get_chiptype(void)
 	switch ((hidrev & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT) {
 	case 0x20:
 		return TEGRA20;
+	case 0x30:
+		return TEGRA30;
 	default:
 		return TEGRA_UNK_REV;
 	}
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 int tegra_get_num_cores(void)
 {
 	switch (tegra_get_chiptype()) {
 	case TEGRA20:
 		return 2;
-		break;
+	case TEGRA30:
+		return 4;
 	default:
 		return 0;
-		break;
 	}
 }
 
 /* Runtime data */
-static inline __attribute__((always_inline))
+static __always_inline
 int tegra_cpu_is_maincomplex(void)
 {
 	u32 tag0;
@@ -102,7 +109,7 @@ int tegra_cpu_is_maincomplex(void)
 	return (tag0 & 0xff) == 0x55;
 }
 
-static inline __attribute__((always_inline))
+static __always_inline
 uint32_t tegra20_get_ramsize(void)
 {
 	switch ((tegra_get_odmdata() & T20_ODMDATA_RAMSIZE_MASK) >>
@@ -125,7 +132,7 @@ static long uart_id_to_base[] = {
 	TEGRA_UARTE_BASE,
 };
 
-static inline __attribute__((always_inline))
+static __always_inline
 long tegra20_get_debuguart_base(void)
 {
 	u32 odmdata;
@@ -152,7 +159,7 @@ long tegra20_get_debuguart_base(void)
 #define CRC_OSC_CTRL_OSC_FREQ_SHIFT	30
 #define CRC_OSC_CTRL_OSC_FREQ_MASK	(0x3 << CRC_OSC_CTRL_OSC_FREQ_SHIFT)
 
-static inline unsigned __attribute__((always_inline))
+static __always_inline
 int tegra_get_osc_clock(void)
 {
 	u32 osc_ctrl = readl(TEGRA_CLK_RESET_BASE + CRC_OSC_CTRL);
@@ -172,7 +179,50 @@ int tegra_get_osc_clock(void)
 	}
 }
 
-static inline __attribute__((always_inline))
+#define TIMER_CNTR_1US	0x00
+#define TIMER_USEC_CFG	0x04
+
+static __always_inline
+void tegra_ll_delay_setup(void)
+{
+	u32 reg;
+
+	/*
+	 * calibrate timer to run at 1MHz
+	 * TIMERUS_USEC_CFG selects the scale down factor with bits [0:7]
+	 * representing the divisor and bits [8:15] representing the dividend
+	 * each in n+1 form.
+	 */
+	switch (tegra_get_osc_clock()) {
+	case 12000000:
+		reg = 0x000b;
+		break;
+	case 13000000:
+		reg = 0x000c;
+		break;
+	case 19200000:
+		reg = 0x045f;
+		break;
+	case 26000000:
+		reg = 0x0019;
+		break;
+	default:
+		reg = 0;
+		break;
+	}
+
+	writel(reg, TEGRA_TMRUS_BASE + TIMER_USEC_CFG);
+}
+
+static __always_inline
+void tegra_ll_delay_usec(int delay)
+{
+	int timeout = (int)readl(TEGRA_TMRUS_BASE + TIMER_CNTR_1US) + delay;
+
+	while ((int)readl(TEGRA_TMRUS_BASE + TIMER_CNTR_1US) - timeout < 0);
+}
+
+static __always_inline
 void tegra_cpu_lowlevel_setup(void)
 {
 	uint32_t r;
@@ -182,6 +232,7 @@ void tegra_cpu_lowlevel_setup(void)
 	r &= ~0x1f;
 	r |= 0xd3;
 	__asm__ __volatile__("msr cpsr, %0" : : "r"(r));
+	tegra_ll_delay_setup();
 }
 
 /* reset vector for the AVP, to be called from board reset vector */
@@ -189,3 +240,5 @@ void tegra_avp_reset_vector(uint32_t boarddata);
 
 /* reset vector for the main CPU complex */
 void tegra_maincomplex_entry(void);
+
+#endif /* __TEGRA_LOWLEVEL_H */
diff --git a/arch/arm/mach-tegra/include/mach/tegra20-car.h b/arch/arm/mach-tegra/include/mach/tegra20-car.h
index 64873d79b9..161e3d82a1 100644
--- a/arch/arm/mach-tegra/include/mach/tegra20-car.h
+++ b/arch/arm/mach-tegra/include/mach/tegra20-car.h
@@ -46,6 +46,9 @@
 #define CRC_CLK_OUT_ENB_L_AC97		(1 << 3)
 #define CRC_CLK_OUT_ENB_L_CPU		(1 << 0)
 
+#define CRC_CLK_OUT_ENB_H		0x014
+#define CRC_CLK_OUT_ENB_H_DVC		(1 << 15)
+
 #define CRC_CCLK_BURST_POLICY		0x020
 #define CRC_CCLK_BURST_POLICY_SYS_STATE_SHIFT	28
 #define CRC_CCLK_BURST_POLICY_SYS_STATE_FIQ	8
@@ -109,6 +112,10 @@
 #define CRC_SUPER_SDIV_DIVISOR_SHIFT	0
 #define CRC_SUPER_SDIV_DIVISOR_MASK	(0xff << CRC_SUPER_SDIV_DIVISOR_SHIFT)
 
+#define CRC_CLK_SYSTEM_RATE		0x030
+#define CRC_CLK_SYSTEM_RATE_AHB_SHIFT	4
+#define CRC_CLK_SYSTEM_RATE_APB_SHIFT	0
+
 #define CRC_CLK_CPU_CMPLX		0x04c
 #define CRC_CLK_CPU_CMPLX_CPU3_CLK_STP	(1 << 11)
 #define CRC_CLK_CPU_CMPLX_CPU2_CLK_STP	(1 << 10)
@@ -273,6 +280,11 @@
 
 #define CRC_RST_DEV_L_CLR		0x304
 
+#define CRC_RST_DEV_H_SET		0x308
+#define CRC_RST_DEV_H_DVC		(1 << 15)
+
+#define CRC_RST_DEV_H_CLR		0x30c
+
 #define CRC_RST_CPU_CMPLX_SET		0x340
 
 #define CRC_RST_CPU_CMPLX_CLR		0x344
diff --git a/arch/arm/mach-tegra/include/mach/tegra30-car.h b/arch/arm/mach-tegra/include/mach/tegra30-car.h
new file mode 100644
index 0000000000..ce110602fc
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra30-car.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Register definitions */
+#define CRC_CLK_OUT_ENB_V		0x360
+#define CRC_CLK_OUT_ENB_V_MSELECT	(1 << 3)
+
+#define CRC_CLK_SOURCE_MSEL		0x3b4
+#define CRC_CLK_SOURCE_MSEL_SRC_SHIFT	30
+#define CRC_CLK_SOURCE_MSEL_SRC_PLLP	0
+#define CRC_CLK_SOURCE_MSEL_SRC_PLLC	1
+#define CRC_CLK_SOURCE_MSEL_SRC_PLLM	2
+#define CRC_CLK_SOURCE_MSEL_SRC_CLKM	3
+
+#define CRC_RST_DEV_V_SET		0x430
+#define CRC_RST_DEV_V_MSELECT		(1 << 3)
+
+#define CRC_RST_DEV_V_CLR		0x434
diff --git a/arch/arm/mach-tegra/include/mach/tegra30-flow.h b/arch/arm/mach-tegra/include/mach/tegra30-flow.h
new file mode 100644
index 0000000000..50a3030e5e
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra30-flow.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define FLOW_HALT_CPU_EVENTS		0x000
+#define FLOW_MODE_NONE			0
+#define FLOW_MODE_STOP			2
+
+#define FLOW_CLUSTER_CONTROL		0x02c
+#define FLOW_CLUSTER_CONTROL_ACTIVE_G	(0 << 0)
+#define FLOW_CLUSTER_CONTROL_ACTIVE_LP	(1 << 0)
diff --git a/arch/arm/mach-tegra/tegra_avp_init.c b/arch/arm/mach-tegra/tegra_avp_init.c
index 2c2d6fc626..3314db4572 100644
--- a/arch/arm/mach-tegra/tegra_avp_init.c
+++ b/arch/arm/mach-tegra/tegra_avp_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
+ * Copyright (C) 2013-2014 Lucas Stach <l.stach@pengutronix.de>
  *
  * Partly based on code (C) Copyright 2010-2011
  * NVIDIA Corporation <www.nvidia.com>
@@ -23,6 +23,8 @@
 #include <mach/lowlevel.h>
 #include <mach/tegra20-car.h>
 #include <mach/tegra20-pmc.h>
+#include <mach/tegra30-car.h>
+#include <mach/tegra30-flow.h>
 
 /* instruct the PMIC to enable the CPU power rail */
 static void enable_maincomplex_powerrail(void)
@@ -84,6 +86,12 @@ static struct pll_config pllx_config_table[][4] = {
 		{1000, 12, 0, 12},	/* OSC 12.0 MHz */
 		{1000, 26, 0, 12},	/* OSC 26.0 MHz */
 	}, /* TEGRA 20 */
+	{
+		{862, 8,  0, 8},
+		{583, 8,  0, 4},
+		{700, 6,  0, 8},
+		{700, 13, 0, 8},
+	}, /* TEGRA 30 */
 };
 
 static void init_pllx(void)
@@ -149,6 +157,23 @@ static void start_cpu0_clocks(void)
 	       TEGRA_CLK_RESET_BASE + CRC_SCLK_BURST_POLICY);
 	writel(CRC_SUPER_SDIV_ENB, TEGRA_CLK_RESET_BASE + CRC_SUPER_SCLK_DIV);
 
+	writel(1 << CRC_CLK_SYSTEM_RATE_AHB_SHIFT,
+	       TEGRA_CLK_RESET_BASE + CRC_CLK_SYSTEM_RATE);
+
+	if (tegra_get_chiptype() >= TEGRA30) {
+		/* init MSELECT */
+		writel(CRC_RST_DEV_V_MSELECT,
+		       TEGRA_CLK_RESET_BASE + CRC_RST_DEV_V_SET);
+		writel((CRC_CLK_SOURCE_MSEL_SRC_PLLP <<
+		       CRC_CLK_SOURCE_MSEL_SRC_SHIFT) | 2,
+		       TEGRA_CLK_RESET_BASE + CRC_CLK_SOURCE_MSEL);
+		writel(CRC_CLK_OUT_ENB_V_MSELECT,
+		       TEGRA_CLK_RESET_BASE + CRC_CLK_OUT_ENB_V);
+		tegra_ll_delay_usec(3);
+		writel(CRC_RST_DEV_V_MSELECT,
+		       TEGRA_CLK_RESET_BASE + CRC_RST_DEV_V_CLR);
+	}
+
 	/* deassert clock stop for cpu 0 */
 	reg = readl(TEGRA_CLK_RESET_BASE + CRC_CLK_CPU_CMPLX);
 	reg &= ~CRC_CLK_CPU_CMPLX_CPU0_CLK_STP;
@@ -158,6 +183,9 @@ static void start_cpu0_clocks(void)
 	reg = readl(TEGRA_CLK_RESET_BASE + CRC_CLK_OUT_ENB_L);
 	reg |= CRC_CLK_OUT_ENB_L_CPU;
 	writel(reg, TEGRA_CLK_RESET_BASE + CRC_CLK_OUT_ENB_L);
+
+	/* give clocks some time to settle */
+	tegra_ll_delay_usec(300);
 }
 
 static void maincomplex_powerup(void)
@@ -175,12 +203,28 @@ static void maincomplex_powerup(void)
 		reg = readl(TEGRA_PMC_BASE + PMC_REMOVE_CLAMPING_CMD);
 		reg |= PMC_REMOVE_CLAMPING_CMD_CPU;
 		writel(reg, TEGRA_PMC_BASE + PMC_REMOVE_CLAMPING_CMD);
+
+		tegra_ll_delay_usec(1000);
 	}
 }
+
+static void tegra_cluster_switch_hp(void)
+{
+	u32 reg;
+
+	reg = readl(TEGRA_FLOW_CTRL_BASE + FLOW_CLUSTER_CONTROL);
+	reg &= ~FLOW_CLUSTER_CONTROL_ACTIVE_LP;
+	writel(reg, TEGRA_FLOW_CTRL_BASE + FLOW_CLUSTER_CONTROL);
+}
+
 void tegra_avp_reset_vector(uint32_t boarddata)
 {
 	int num_cores;
 
+	/* we want to bring up the high performance CPU complex */
+	if (tegra_get_chiptype() == TEGRA30)
+		tegra_cluster_switch_hp();
+
 	/* get the number of cores in the main CPU complex of the current SoC */
 	num_cores = tegra_get_num_cores();
 
diff --git a/images/Makefile.tegra b/images/Makefile.tegra
index 1cf1432c96..f03503e838 100644
--- a/images/Makefile.tegra
+++ b/images/Makefile.tegra
@@ -9,6 +9,6 @@ pblx-$(CONFIG_MACH_TOSHIBA_AC100) += start_toshiba_ac100
 FILE_barebox-tegra20-toshiba-ac100.img = start_toshiba_ac100.pblx
 image-$(CONFIG_MACH_TOSHIBA_AC100) += barebox-tegra20-toshiba-ac100.img
 
-pblx-$(CONFIG_MACH_TORADEX_COLIBRI_T20_IRIS) += start_toradex_colibri_t20_iris
+pblx-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += start_toradex_colibri_t20_iris
 FILE_barebox-tegra20-toradex-colibri-t20-iris.img = start_toradex_colibri_t20_iris.pblx
-image-$(CONFIG_MACH_TORADEX_COLIBRI_T20_IRIS) += barebox-tegra20-toradex-colibri-t20-iris.img
+image-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += barebox-tegra20-toradex-colibri-t20-iris.img