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authorgrodriguez <guille.rodriguez@gmail.com>2016-06-13 19:29:15 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2016-06-14 08:32:15 +0200
commita945a51b76fbbd19e912273952fb0b0401fcc564 (patch)
tree185c843dd9f9df4fd330831223bbbeb10de62a3e
parentad198abad5493433eaed8eb2adc564e50826171a (diff)
downloadbarebox-a945a51b76fbbd19e912273952fb0b0401fcc564.tar.gz
barebox-a945a51b76fbbd19e912273952fb0b0401fcc564.tar.xz
Fix genphy_restart_aneg() for Micrel's ksz9031.
Commit da89ee8f2e04 ("Center FLP timing at 16ms") breaks genphy_restart_aneg() for Micrel's ksz9031. According to the datasheet, the ksz9031 requires a wait of 1ms after clearing the PDOWN bit and before read/write access to any PHY registers. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--drivers/net/phy/phy.c9
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 73176fbc04..ed69d9b463 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -561,7 +561,7 @@ int phy_wait_aneg_done(struct phy_device *phydev)
*/
int genphy_restart_aneg(struct phy_device *phydev)
{
- int ctl;
+ int ctl, pdown;
ctl = phy_read(phydev, MII_BMCR);
@@ -574,6 +574,7 @@ int genphy_restart_aneg(struct phy_device *phydev)
ctl &= ~(BMCR_ISOLATE);
/* Clear powerdown bit which eventually is set on some phys */
+ pdown = ctl & BMCR_PDOWN;
ctl &= ~BMCR_PDOWN;
ctl = phy_write(phydev, MII_BMCR, ctl);
@@ -581,6 +582,12 @@ int genphy_restart_aneg(struct phy_device *phydev)
if (ctl < 0)
return ctl;
+ /* Micrel's ksz9031 (and perhaps others?): Changing the PDOWN bit
+ * from '1' to '0' generates an internal reset. Must wait a minimum
+ * of 1ms before read/write access to the PHY registers. */
+ if (pdown)
+ mdelay(1);
+
return 0;
}