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author | Sascha Hauer <s.hauer@pengutronix.de> | 2016-09-13 15:41:05 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2016-09-14 14:39:57 +0200 |
commit | 7dc3354ac8fa4312b2c309037ec1f138212c393a (patch) | |
tree | 858ce016aae98d11a41d96259b221f74bf3c1bf5 | |
parent | 47f72a3b78f775dfb71bb9c266998264653be5a9 (diff) | |
download | barebox-7dc3354ac8fa4312b2c309037ec1f138212c393a.tar.gz barebox-7dc3354ac8fa4312b2c309037ec1f138212c393a.tar.xz |
ARM: i.MX6: Enable parent propagation for clk_gate2
Enable parent rate propagation for clk_gate2 to allow the
clock consumers to adjust their rates.
One effect of this is that the i.MX6 NAND controller now can adjust
its rate. It already called a clk_set_rate(rate, 96000000), but this
had no effect, so the clock stayed at reset default 24MHz resulting
in a rather slow timing. This became a problem when commit
"1daa3bc mtd: nand_mxs: Setup timing" introduced EDO timing mode for
faster NAND chips. EDO mode can only work properly for cycle times
< 30ns (at least that's specified in the ONFI spec). 1daa3bc resulted
in sporadic NAND read errors on some boards.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Tested-by: Sam Ravnborg <sam@ravnborg.org>
-rw-r--r-- | arch/arm/mach-imx/clk-gate2.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/clk-gate2.c b/arch/arm/mach-imx/clk-gate2.c index 344c2fb1e6..faed6313fb 100644 --- a/arch/arm/mach-imx/clk-gate2.c +++ b/arch/arm/mach-imx/clk-gate2.c @@ -79,6 +79,8 @@ static int clk_gate2_is_enabled(struct clk *clk) } static struct clk_ops clk_gate2_ops = { + .set_rate = clk_parent_set_rate, + .round_rate = clk_parent_round_rate, .enable = clk_gate2_enable, .disable = clk_gate2_disable, .is_enabled = clk_gate2_is_enabled, @@ -96,6 +98,7 @@ struct clk *clk_gate2_alloc(const char *name, const char *parent, g->clk.name = name; g->clk.parent_names = &g->parent; g->clk.num_parents = 1; + g->clk.flags = CLK_SET_RATE_PARENT; return &g->clk; } |