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authorSascha Hauer <s.hauer@pengutronix.de>2017-01-12 09:57:15 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2017-01-19 15:22:45 +0100
commit0ada0c03af9389de862577b86987417d7b12dcc2 (patch)
tree016c07951c6d5458376e72775ff5e5a93ae60c3d
parentcf6b5087944d0f70e78ee3085c2b0b27ade74d3b (diff)
downloadbarebox-0ada0c03af9389de862577b86987417d7b12dcc2.tar.gz
clk: i.MX: pllv3: Add support for the i.MX7 enet pll
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--drivers/clk/imx/clk-pllv3.c23
-rw-r--r--drivers/clk/imx/clk.h1
2 files changed, 19 insertions, 5 deletions
diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index dd924a4..6d4399b 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -32,6 +32,7 @@
#define BM_PLL_ENABLE (0x1 << 13)
#define BM_PLL_BYPASS (0x1 << 16)
#define BM_PLL_LOCK (0x1 << 31)
+#define IMX7_ENET_PLL_POWER (0x1 << 5)
struct clk_pllv3 {
struct clk clk;
@@ -42,6 +43,8 @@ struct clk_pllv3 {
const char *parent;
void __iomem *lock_reg;
u32 lock_mask;
+ u32 ref_clock;
+ u32 power_bit;
};
#define to_clk_pllv3(_clk) container_of(_clk, struct clk_pllv3, clk)
@@ -55,9 +58,9 @@ static int clk_pllv3_enable(struct clk *clk)
val = readl(pll->base);
val &= ~BM_PLL_BYPASS;
if (pll->powerup_set)
- val |= BM_PLL_POWER;
+ val |= pll->power_bit;
else
- val &= ~BM_PLL_POWER;
+ val &= ~pll->power_bit;
writel(val, pll->base);
/* Wait for PLL to lock */
@@ -87,9 +90,9 @@ static void clk_pllv3_disable(struct clk *clk)
val |= BM_PLL_BYPASS;
if (pll->powerup_set)
- val &= ~BM_PLL_POWER;
+ val &= ~pll->power_bit;
else
- val |= BM_PLL_POWER;
+ val |= pll->power_bit;
writel(val, pll->base);
}
@@ -269,7 +272,9 @@ static const struct clk_ops clk_pllv3_av_ops = {
static unsigned long clk_pllv3_enet_recalc_rate(struct clk *clk,
unsigned long parent_rate)
{
- return 500000000;
+ struct clk_pllv3 *pll = to_clk_pllv3(clk);
+
+ return pll->ref_clock;
}
static const struct clk_ops clk_pllv3_enet_ops = {
@@ -375,6 +380,8 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
pll = xzalloc(sizeof(*pll));
+ pll->power_bit = BM_PLL_POWER;
+
switch (type) {
case IMX_PLLV3_SYS_VF610:
ops = &clk_pllv3_sys_vf610_ops;
@@ -391,7 +398,13 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
case IMX_PLLV3_AV:
ops = &clk_pllv3_av_ops;
break;
+ case IMX_PLLV3_ENET_IMX7:
+ pll->power_bit = IMX7_ENET_PLL_POWER;
+ pll->ref_clock = 1000000000;
+ ops = &clk_pllv3_enet_ops;
+ break;
case IMX_PLLV3_ENET:
+ pll->ref_clock = 500000000;
ops = &clk_pllv3_enet_ops;
break;
case IMX_PLLV3_MLB:
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 0b28fb2..1dbfbf7 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -83,6 +83,7 @@ enum imx_pllv3_type {
IMX_PLLV3_USB_VF610,
IMX_PLLV3_AV,
IMX_PLLV3_ENET,
+ IMX_PLLV3_ENET_IMX7,
IMX_PLLV3_MLB,
};