Merge branch 'for-next/mxs'

5 files changed, 76 insertions, 17 deletions

diff --git a/arch/arm/boards/freescale-mx28-evk/mx28-evk.c b/arch/arm/boards/freescale-mx28-evk/mx28-evk.c
index 5bcb24cf45..4311473e65 100644
--- a/arch/arm/boards/freescale-mx28-evk/mx28-evk.c
+++ b/arch/arm/boards/freescale-mx28-evk/mx28-evk.c
@@ -109,6 +109,23 @@ static const uint32_t mx28evk_pads[] = {
 	LCD_RESET_GPIO | VE_3_3V | GPIO_OUT | GPIO_VALUE(0),
 	/* backlight  */
 	PWM2_GPIO | VE_3_3V | STRENGTH(S4MA) | SE | VE,
+
+	/* GPMI-NAND (blocks mmc1 for now) */
+	GPMI_D0 | VE_3_3V,
+	GPMI_D1 | VE_3_3V,
+	GPMI_D2 | VE_3_3V,
+	GPMI_D3 | VE_3_3V,
+	GPMI_D4 | VE_3_3V,
+	GPMI_D5 | VE_3_3V,
+	GPMI_D6 | VE_3_3V,
+	GPMI_D7 | VE_3_3V,
+	GPMI_READY0 | VE_3_3V,	/* external PU */
+	GPMI_CE0N | VE_3_3V, 	/* external PU */
+	GPMI_RDN | VE_3_3V,
+	GPMI_WRN | VE_3_3V,
+	GPMI_ALE | VE_3_3V,
+	GPMI_CLE | VE_3_3V,
+	GPMI_RESETN,		/* act as WP, external PU */
 };
 
 static struct mxs_mci_platform_data mci_pdata = {
@@ -239,6 +256,9 @@ static int mx28_evk_devices_init(void)
 	add_generic_device("imx28-fec", 0, NULL, IMX_FEC0_BASE, 0x4000,
 			   IORESOURCE_MEM, &fec_info);
 
+	add_generic_device("mxs_nand", 0, NULL, MXS_GPMI_BASE, 0x2000,
+			   IORESOURCE_MEM, NULL);
+
 	return 0;
 }
 device_initcall(mx28_evk_devices_init);
diff --git a/arch/arm/configs/imx28evk_defconfig b/arch/arm/configs/imx28evk_defconfig
index 0cc269bdba..3b69d4d9a4 100644
--- a/arch/arm/configs/imx28evk_defconfig
+++ b/arch/arm/configs/imx28evk_defconfig
@@ -12,41 +12,41 @@ CONFIG_GLOB=y
 CONFIG_HUSH_FANCY_PROMPT=y
 CONFIG_CMDLINE_EDITING=y
 CONFIG_AUTO_COMPLETE=y
-CONFIG_PARTITION=y
 CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
 CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/freescale-mx28-evk/env"
 CONFIG_DEBUG_INFO=y
 CONFIG_CMD_EDIT=y
 CONFIG_CMD_SLEEP=y
 CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_LOADENV=y
 CONFIG_CMD_EXPORT=y
 CONFIG_CMD_PRINTENV=y
 CONFIG_CMD_READLINE=y
+CONFIG_CMD_TFTP=y
 CONFIG_CMD_ECHO_E=y
-CONFIG_CMD_MTEST=y
-CONFIG_CMD_MTEST_ALTERNATIVE=y
-CONFIG_CMD_BOOTM_ZLIB=y
-CONFIG_CMD_BOOTM_BZLIB=y
 CONFIG_CMD_BOOTM_SHOW_TYPE=y
 CONFIG_CMD_RESET=y
 CONFIG_CMD_GO=y
+CONFIG_CMD_MTEST=y
+CONFIG_CMD_MTEST_ALTERNATIVE=y
+CONFIG_CMD_SPLASH=y
 CONFIG_CMD_TIMEOUT=y
 CONFIG_CMD_PARTITION=y
-CONFIG_CMD_SPLASH=y
 CONFIG_CMD_GPIO=y
 CONFIG_NET=y
 CONFIG_NET_DHCP=y
 CONFIG_NET_PING=y
-CONFIG_CMD_TFTP=y
-CONFIG_FS_TFTP=y
 CONFIG_NET_RESOLV=y
 CONFIG_DRIVER_NET_FEC_IMX=y
 # CONFIG_SPI is not set
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_MXS=y
 CONFIG_VIDEO=y
 CONFIG_DRIVER_VIDEO_STM=y
 CONFIG_MCI=y
 CONFIG_MCI_STARTUP=y
 CONFIG_MCI_MXS=y
+CONFIG_MXS_APBH_DMA=y
+CONFIG_FS_TFTP=y
 CONFIG_FS_FAT=y
 CONFIG_FS_FAT_LFN=y
diff --git a/arch/arm/mach-mxs/common.c b/arch/arm/mach-mxs/common.c
index 3730633c71..122d88362b 100644
--- a/arch/arm/mach-mxs/common.c
+++ b/arch/arm/mach-mxs/common.c
@@ -1,8 +1,26 @@
+/*
+ * Freescale i.MXS common code
+ *
+ * Copyright (C) 2012 Wolfram Sang <w.sang@pengutronix.de>
+ *
+ * Based on code from LTIB:
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
 #include <common.h>
 #include <io.h>
+#include <errno.h>
+#include <clock.h>
 #include <mach/mxs.h>
 #include <mach/imx-regs.h>
 
+#define	MXS_IP_RESET_TIMEOUT	(10 * MSECOND)
+
 #define	MXS_BLOCK_SFTRST				(1 << 31)
 #define	MXS_BLOCK_CLKGATE				(1 << 30)
 
@@ -10,7 +28,9 @@ int mxs_reset_block(void __iomem *reg, int just_enable)
 {
 	/* Clear SFTRST */
 	writel(MXS_BLOCK_SFTRST, reg + BIT_CLR);
-	mdelay(1);
+
+	if (wait_on_timeout(MXS_IP_RESET_TIMEOUT, !(readl(reg) & MXS_BLOCK_SFTRST)))
+		goto timeout;
 
 	/* Clear CLKGATE */
 	writel(MXS_BLOCK_CLKGATE, reg + BIT_CLR);
@@ -18,16 +38,27 @@ int mxs_reset_block(void __iomem *reg, int just_enable)
 	if (!just_enable) {
 		/* Set SFTRST */
 		writel(MXS_BLOCK_SFTRST, reg + BIT_SET);
-		mdelay(1);
+
+		/* Wait for CLKGATE being set */
+		if (wait_on_timeout(MXS_IP_RESET_TIMEOUT, readl(reg) & MXS_BLOCK_CLKGATE))
+			goto timeout;
 	}
 
 	/* Clear SFTRST */
 	writel(MXS_BLOCK_SFTRST, reg + BIT_CLR);
-	mdelay(1);
+
+	if (wait_on_timeout(MXS_IP_RESET_TIMEOUT, !(readl(reg) & MXS_BLOCK_SFTRST)))
+		goto timeout;
 
 	/* Clear CLKGATE */
 	writel(MXS_BLOCK_CLKGATE, reg + BIT_CLR);
-	mdelay(1);
+
+	if (wait_on_timeout(MXS_IP_RESET_TIMEOUT, !(readl(reg) & MXS_BLOCK_CLKGATE)))
+		goto timeout;
 
 	return 0;
+
+timeout:
+	printf("MXS: Timeout resetting block via register 0x%p\n", reg);
+	return -ETIMEDOUT;
 }
diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c
index 363878fb22..d30b8fb193 100644
--- a/drivers/dma/apbh_dma.c
+++ b/drivers/dma/apbh_dma.c
@@ -555,7 +555,9 @@ int mxs_dma_init(void)
 	int ret, channel;
 	u32 val, reg;
 
-	mxs_reset_block(apbh_regs, 0);
+	ret = mxs_reset_block(apbh_regs, 0);
+	if (ret)
+		return ret;
 
 	/* HACK: Get CPUID and determine APBH version */
 	val = readl(0x8001c310) >> 16;
diff --git a/drivers/mtd/nand/nand_mxs.c b/drivers/mtd/nand/nand_mxs.c
index d71983a6c2..975a44f569 100644
--- a/drivers/mtd/nand/nand_mxs.c
+++ b/drivers/mtd/nand/nand_mxs.c
@@ -1039,9 +1039,13 @@ static int mxs_nand_scan_bbt(struct mtd_info *mtd)
 	struct mxs_nand_info *nand_info = nand->priv;
 	void __iomem *bch_regs = (void __iomem *)MXS_BCH_BASE;
 	uint32_t tmp;
+	int ret;
 
 	/* Reset BCH. Don't use SFTRST on MX23 due to Errata #2847 */
-	mxs_reset_block(bch_regs + BCH_CTRL, nand_info->version == GPMI_VERSION_TYPE_MX23);
+	ret = mxs_reset_block(bch_regs + BCH_CTRL,
+				nand_info->version == GPMI_VERSION_TYPE_MX23);
+	if (ret)
+		return ret;
 
 	/* Configure layout 0 */
 	tmp = (mxs_nand_ecc_chunk_cnt(mtd->writesize) - 1)
@@ -1124,7 +1128,7 @@ int mxs_nand_alloc_buffers(struct mxs_nand_info *nand_info)
 int mxs_nand_hw_init(struct mxs_nand_info *info)
 {
 	void __iomem *gpmi_regs = (void *)MXS_GPMI_BASE;
-	int i = 0;
+	int i = 0, ret;
 	u32 val;
 
 	info->desc = malloc(sizeof(struct mxs_dma_desc *) *
@@ -1145,7 +1149,9 @@ int mxs_nand_hw_init(struct mxs_nand_info *info)
 	imx_enable_nandclk();
 
 	/* Reset the GPMI block. */
-	mxs_reset_block(gpmi_regs + GPMI_CTRL0, 0);
+	ret = mxs_reset_block(gpmi_regs + GPMI_CTRL0, 0);
+	if (ret)
+		return ret;
 
 	/*
 	 * Choose NAND mode, set IRQ polarity, disable write protection and