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authorSascha Hauer <s.hauer@pengutronix.de>2012-06-06 14:11:57 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2012-06-06 14:11:57 +0200
commit497d1c49f4b75a6827bb400513d53a39dc8bb57c (patch)
tree3227133463cb942c4d5be45108aab82e79daa98c
parent94418c2d0d3d7dbaa6995fb53f00a5d5fc9f4028 (diff)
parent4024d9ca11295b63dd2b9b795a8f1019b9bba64a (diff)
downloadbarebox-497d1c49f4b75a6827bb400513d53a39dc8bb57c.tar.gz
barebox-497d1c49f4b75a6827bb400513d53a39dc8bb57c.tar.xz
Merge branch 'next'
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-rw-r--r--arch/arm/configs/freescale_mx51_babbage_defconfig16
-rw-r--r--arch/arm/configs/mini2440_defconfig2
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-rw-r--r--arch/arm/configs/toshiba_ac100_defconfig39
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-rw-r--r--arch/arm/mach-samsung/lowlevel-s3c24x0.S (renamed from arch/arm/mach-samsung/lowlevel-init.S)12
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-rw-r--r--arch/blackfin/boards/ipe337/ipe337.c4
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-rw-r--r--arch/mips/boards/rzx50/serial.c66
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-rw-r--r--arch/mips/mach-xburst/include/mach/debug_ll.h30
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-rw-r--r--arch/ppc/configs/p2020rdb_defconfig23
-rw-r--r--arch/ppc/cpu-85xx/Makefile4
-rw-r--r--arch/ppc/cpu-85xx/fixed_ivor.S61
-rw-r--r--arch/ppc/cpu-85xx/resetvec.S2
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-rw-r--r--arch/ppc/mach-mpc85xx/include/mach/immap_85xx.h132
-rw-r--r--arch/ppc/mach-mpc85xx/include/mach/mmu.h47
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-rw-r--r--commands/Kconfig20
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-rw-r--r--drivers/base/resource.c2
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-rw-r--r--drivers/nor/cfi_flash.h10
-rw-r--r--drivers/serial/Kconfig2
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-rw-r--r--drivers/spi/imx_spi.c4
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-rw-r--r--fs/Kconfig4
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-rwxr-xr-xscripts/genenv2
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323 files changed, 10671 insertions, 1073 deletions
diff --git a/.gitignore b/.gitignore
index 8a5c58357d..df0ed2c351 100644
--- a/.gitignore
+++ b/.gitignore
@@ -33,10 +33,11 @@ barebox.S
barebox.bin
barebox.srec
barebox.netx
+barebox.s5p
barebox.map
System.map
Module.symvers
-barebox_default_env
+barebox_default_env*
#
# Generated include files
@@ -63,3 +64,4 @@ cscope.*
# patches
*.patch
scripts/gen_netx_image
+scripts/s5p_cksum
diff --git a/Documentation/boards.dox b/Documentation/boards.dox
index ba332a76f4..5241f5b442 100644
--- a/Documentation/boards.dox
+++ b/Documentation/boards.dox
@@ -37,6 +37,7 @@ ARM type:
@li @subpage edb9315a
@li @subpage board_cupid
@li @subpage phycard-a-l1
+@li @subpage toshiba-ac100
Blackfin type:
@@ -51,6 +52,7 @@ MIPS type:
@li @subpage dlink_dir_320
@li @subpage qemu_malta
+@li @subpage rzx50
*/
diff --git a/Makefile b/Makefile
index 0518d8352e..9294049204 100644
--- a/Makefile
+++ b/Makefile
@@ -1003,7 +1003,7 @@ CLEAN_DIRS += $(MODVERDIR)
CLEAN_FILES += barebox System.map include/generated/barebox_default_env.h \
.tmp_version .tmp_barebox* barebox.bin barebox.map barebox.S \
.tmp_kallsyms* barebox_default_env* barebox.ldr \
- Doxyfile.version barebox.srec
+ Doxyfile.version barebox.srec barebox.s5p
# Directories & files removed with 'make mrproper'
MRPROPER_DIRS += include/config include2 usr/include
diff --git a/README b/README
index c875b7d3ca..cec9ccbaf5 100644
--- a/README
+++ b/README
@@ -110,7 +110,7 @@ Barebox usually needs an environment for storing the configuration data.
You can generate an environment using the example environment contained
in board/sandbox/env:
- # ./scripts/bareboxenv -s -p 0x10000 board/sandbox/env/ env.bin
+ # ./scripts/bareboxenv -s -p 0x10000 arch/sandbox/board/env env.bin
To get some files to play with you can generate a cramfs image:
# mkcramfs somedir/ cramfs.bin
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8a4e1a2b41..3eada5b80f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -73,10 +73,21 @@ config ARCH_S3C24xx
select CPU_ARM920T
select GENERIC_GPIO
+config ARCH_S5PCxx
+ bool "Samsung S5PC110, S5PV210"
+ select ARCH_SAMSUNG
+ select CPU_V7
+ select GENERIC_GPIO
+
config ARCH_VERSATILE
bool "ARM Versatile boards (ARM926EJ-S)"
select CPU_ARM926T
+config ARCH_TEGRA
+ bool "Nvidia Tegra-based boards"
+ select CPU_ARM926T
+ select HAS_DEBUG_LL
+
endchoice
source arch/arm/cpu/Kconfig
@@ -90,6 +101,7 @@ source arch/arm/mach-omap/Kconfig
source arch/arm/mach-pxa/Kconfig
source arch/arm/mach-samsung/Kconfig
source arch/arm/mach-versatile/Kconfig
+source arch/arm/mach-tegra/Kconfig
config ARM_ASM_UNIFIED
bool
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 2e6402b031..bd684dc23a 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -61,6 +61,7 @@ machine-$(CONFIG_ARCH_OMAP) := omap
machine-$(CONFIG_ARCH_PXA) := pxa
machine-$(CONFIG_ARCH_SAMSUNG) := samsung
machine-$(CONFIG_ARCH_VERSATILE) := versatile
+machine-$(CONFIG_ARCH_TEGRA) := tegra
# Board directory name. This list is sorted alphanumerically
# by CONFIG_* macro name.
@@ -134,6 +135,7 @@ board-$(CONFIG_MACH_TX25) := karo-tx25
board-$(CONFIG_MACH_TQMA53) := tqma53
board-$(CONFIG_MACH_TX51) := karo-tx51
board-$(CONFIG_MACH_MX6Q_ARM2) := freescale-mx6-arm2
+board-$(CONFIG_MACH_TOSHIBA_AC100) := toshiba-ac100
machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
@@ -165,6 +167,13 @@ ifeq ($(machine-y),netx)
KBUILD_IMAGE := barebox.netx
endif
+barebox.s5p: barebox.bin
+ $(Q)scripts/s5p_cksum barebox.bin barebox.s5p
+
+ifeq ($(CONFIG_ARCH_S5PCxx),y)
+KBUILD_IMAGE := barebox.s5p
+endif
+
MLO: barebox.bin
@echo " IFT " $@
$(Q)scripts/omap_signGP barebox.bin $(TEXT_BASE) 1
diff --git a/arch/arm/boards/a9m2410/a9m2410.c b/arch/arm/boards/a9m2410/a9m2410.c
index 1a3181ebfb..eaafdbdd71 100644
--- a/arch/arm/boards/a9m2410/a9m2410.c
+++ b/arch/arm/boards/a9m2410/a9m2410.c
@@ -121,10 +121,10 @@ static int a9m2410_devices_init(void)
#ifdef CONFIG_NAND
/* ----------- add some vital partitions -------- */
- devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
+ devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
- devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
+ devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
#endif
@@ -136,7 +136,7 @@ static int a9m2410_devices_init(void)
device_initcall(a9m2410_devices_init);
-#ifdef CONFIG_S3C24XX_NAND_BOOT
+#ifdef CONFIG_S3C_NAND_BOOT
void __bare_init nand_boot(void)
{
s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0);
diff --git a/arch/arm/boards/a9m2410/config.h b/arch/arm/boards/a9m2410/config.h
index 87b05fc55d..4b8a9a296a 100644
--- a/arch/arm/boards/a9m2410/config.h
+++ b/arch/arm/boards/a9m2410/config.h
@@ -115,7 +115,7 @@
#define A9M2410_TWRPH1 1
/* needed in the generic NAND boot code only */
-#ifdef CONFIG_S3C24XX_NAND_BOOT
+#ifdef CONFIG_S3C_NAND_BOOT
# define BOARD_DEFAULT_NAND_TIMING CALC_NFCONF_TIMING(A9M2410_TACLS, A9M2410_TWRPH0, A9M2410_TWRPH1)
#endif
diff --git a/arch/arm/boards/a9m2410/lowlevel_init.S b/arch/arm/boards/a9m2410/lowlevel_init.S
index a106d53a1d..0463b260be 100644
--- a/arch/arm/boards/a9m2410/lowlevel_init.S
+++ b/arch/arm/boards/a9m2410/lowlevel_init.S
@@ -28,7 +28,7 @@ board_init_lowlevel:
bl s3c24x0_sdram_init
-#ifdef CONFIG_S3C24XX_NAND_BOOT
+#ifdef CONFIG_S3C_NAND_BOOT
mov lr, r10 /* restore the link register */
/* up to here we are running from the internal SRAM area */
b s3c24x0_nand_boot /* does return directly to our caller into SDRAM */
diff --git a/arch/arm/boards/a9m2440/a9m2440.c b/arch/arm/boards/a9m2440/a9m2440.c
index 4094e31cd7..1d202483e5 100644
--- a/arch/arm/boards/a9m2440/a9m2440.c
+++ b/arch/arm/boards/a9m2440/a9m2440.c
@@ -141,10 +141,10 @@ static int a9m2440_devices_init(void)
#ifdef CONFIG_NAND
/* ----------- add some vital partitions -------- */
- devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
+ devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
- devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
+ devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
#endif
armlinux_set_bootparams((void*)S3C_SDRAM_BASE + 0x100);
@@ -155,7 +155,7 @@ static int a9m2440_devices_init(void)
device_initcall(a9m2440_devices_init);
-#ifdef CONFIG_S3C24XX_NAND_BOOT
+#ifdef CONFIG_S3C_NAND_BOOT
void __bare_init nand_boot(void)
{
s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0);
diff --git a/arch/arm/boards/a9m2440/config.h b/arch/arm/boards/a9m2440/config.h
index 43cb6ab934..09ad94906f 100644
--- a/arch/arm/boards/a9m2440/config.h
+++ b/arch/arm/boards/a9m2440/config.h
@@ -66,7 +66,7 @@
#define A9M2440_TWRPH1 1
/* needed in the generic NAND boot code only */
-#ifdef CONFIG_S3C24XX_NAND_BOOT
+#ifdef CONFIG_S3C_NAND_BOOT
# define BOARD_DEFAULT_NAND_TIMING CALC_NFCONF_TIMING(A9M2440_TACLS, A9M2440_TWRPH0, A9M2440_TWRPH1)
#endif
diff --git a/arch/arm/boards/a9m2440/lowlevel_init.S b/arch/arm/boards/a9m2440/lowlevel_init.S
index e915a1649c..305014cd51 100644
--- a/arch/arm/boards/a9m2440/lowlevel_init.S
+++ b/arch/arm/boards/a9m2440/lowlevel_init.S
@@ -232,7 +232,7 @@ board_init_lowlevel:
bl sdram_init
-#ifdef CONFIG_S3C24XX_NAND_BOOT
+#ifdef CONFIG_S3C_NAND_BOOT
mov lr, r10 /* restore the link register */
/* up to here we are running from the internal SRAM area */
b s3c24x0_nand_boot /* does return directly to our caller into SDRAM */
diff --git a/arch/arm/boards/at91rm9200ek/init.c b/arch/arm/boards/at91rm9200ek/init.c
index 3875f4ab4d..17fb8e1678 100644
--- a/arch/arm/boards/at91rm9200ek/init.c
+++ b/arch/arm/boards/at91rm9200ek/init.c
@@ -124,8 +124,8 @@ static int at91rm9200ek_devices_init(void)
ek_add_device_udc();
#if defined(CONFIG_DRIVER_CFI) || defined(CONFIG_DRIVER_CFI_OLD)
- devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self");
- devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
+ devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self");
+ devfs_add_partition("nor0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0");
#endif
armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100));
diff --git a/arch/arm/boards/at91sam9260ek/init.c b/arch/arm/boards/at91sam9260ek/init.c
index a1d37507af..daadf9489f 100644
--- a/arch/arm/boards/at91sam9260ek/init.c
+++ b/arch/arm/boards/at91sam9260ek/init.c
@@ -264,13 +264,13 @@ static int at91sam9260ek_devices_init(void)
armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100));
ek_set_board_type();
- devfs_add_partition("nand0", 0x00000, SZ_128K, PARTITION_FIXED, "at91bootstrap_raw");
+ devfs_add_partition("nand0", 0x00000, SZ_128K, DEVFS_PARTITION_FIXED, "at91bootstrap_raw");
dev_add_bb_dev("at91bootstrap_raw", "at91bootstrap");
- devfs_add_partition("nand0", SZ_128K, SZ_256K, PARTITION_FIXED, "self_raw");
+ devfs_add_partition("nand0", SZ_128K, SZ_256K, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
- devfs_add_partition("nand0", SZ_256K + SZ_128K, SZ_128K, PARTITION_FIXED, "env_raw");
+ devfs_add_partition("nand0", SZ_256K + SZ_128K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
- devfs_add_partition("nand0", SZ_512K, SZ_128K, PARTITION_FIXED, "env_raw1");
+ devfs_add_partition("nand0", SZ_512K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw1");
dev_add_bb_dev("env_raw1", "env1");
return 0;
diff --git a/arch/arm/boards/at91sam9261ek/init.c b/arch/arm/boards/at91sam9261ek/init.c
index acc71f4f58..b0cab5b0e6 100644
--- a/arch/arm/boards/at91sam9261ek/init.c
+++ b/arch/arm/boards/at91sam9261ek/init.c
@@ -251,12 +251,12 @@ static int at91sam9261ek_devices_init(void)
ek_add_device_buttons();
ek_device_add_leds();
- devfs_add_partition("nand0", 0x00000, SZ_128K, PARTITION_FIXED, "at91bootstrap_raw");
- devfs_add_partition("nand0", SZ_128K, SZ_256K, PARTITION_FIXED, "self_raw");
+ devfs_add_partition("nand0", 0x00000, SZ_128K, DEVFS_PARTITION_FIXED, "at91bootstrap_raw");
+ devfs_add_partition("nand0", SZ_128K, SZ_256K, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
- devfs_add_partition("nand0", SZ_256K + SZ_128K, SZ_128K, PARTITION_FIXED, "env_raw");
+ devfs_add_partition("nand0", SZ_256K + SZ_128K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
- devfs_add_partition("nand0", SZ_512K, SZ_128K, PARTITION_FIXED, "env_raw1");
+ devfs_add_partition("nand0", SZ_512K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw1");
dev_add_bb_dev("env_raw1", "env1");
armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100));
diff --git a/arch/arm/boards/at91sam9263ek/init.c b/arch/arm/boards/at91sam9263ek/init.c
index 33b7955edb..68f4bfc3f1 100644
--- a/arch/arm/boards/at91sam9263ek/init.c
+++ b/arch/arm/boards/at91sam9263ek/init.c
@@ -191,16 +191,16 @@ static int at91sam9263ek_devices_init(void)
ek_add_device_buttons();
if (IS_ENABLED(CONFIG_DRIVER_CFI) && cdev_by_name("nor0")) {
- devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self");
- devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
+ devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self");
+ devfs_add_partition("nor0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0");
} else if (IS_ENABLED(CONFIG_NAND_ATMEL)) {
- devfs_add_partition("nand0", 0x00000, SZ_128K, PARTITION_FIXED, "at91bootstrap_raw");
+ devfs_add_partition("nand0", 0x00000, SZ_128K, DEVFS_PARTITION_FIXED, "at91bootstrap_raw");
dev_add_bb_dev("at91bootstrap_raw", "at91bootstrap");
- devfs_add_partition("nand0", SZ_128K, SZ_256K, PARTITION_FIXED, "self_raw");
+ devfs_add_partition("nand0", SZ_128K, SZ_256K, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
- devfs_add_partition("nand0", SZ_256K + SZ_128K, SZ_128K, PARTITION_FIXED, "env_raw");
+ devfs_add_partition("nand0", SZ_256K + SZ_128K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
- devfs_add_partition("nand0", SZ_512K, SZ_128K, PARTITION_FIXED, "env_raw1");
+ devfs_add_partition("nand0", SZ_512K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw1");
dev_add_bb_dev("env_raw1", "env1");
}
diff --git a/arch/arm/boards/at91sam9m10g45ek/init.c b/arch/arm/boards/at91sam9m10g45ek/init.c
index c4b1a97f8e..d4209a076f 100644
--- a/arch/arm/boards/at91sam9m10g45ek/init.c
+++ b/arch/arm/boards/at91sam9m10g45ek/init.c
@@ -230,13 +230,13 @@ static int at91sam9m10g45ek_devices_init(void)
ek_device_add_leds();
ek_device_add_keyboard();
- devfs_add_partition("nand0", 0x00000, SZ_128K, PARTITION_FIXED, "at91bootstrap_raw");
+ devfs_add_partition("nand0", 0x00000, SZ_128K, DEVFS_PARTITION_FIXED, "at91bootstrap_raw");
dev_add_bb_dev("at91bootstrap_raw", "at91bootstrap");
- devfs_add_partition("nand0", SZ_128K, SZ_256K, PARTITION_FIXED, "self_raw");
+ devfs_add_partition("nand0", SZ_128K, SZ_256K, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
- devfs_add_partition("nand0", SZ_256K + SZ_128K, SZ_128K, PARTITION_FIXED, "env_raw");
+ devfs_add_partition("nand0", SZ_256K + SZ_128K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
- devfs_add_partition("nand0", SZ_512K, SZ_128K, PARTITION_FIXED, "env_raw1");
+ devfs_add_partition("nand0", SZ_512K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw1");
dev_add_bb_dev("env_raw1", "env1");
armlinux_set_bootparams((void *)(AT91_CHIPSELECT_6 + 0x100));
diff --git a/arch/arm/boards/at91sam9x5ek/init.c b/arch/arm/boards/at91sam9x5ek/init.c
index 1839dd6642..ee0343ae17 100644
--- a/arch/arm/boards/at91sam9x5ek/init.c
+++ b/arch/arm/boards/at91sam9x5ek/init.c
@@ -144,13 +144,13 @@ static int at91sam9x5ek_devices_init(void)
armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100));
armlinux_set_architecture(CONFIG_MACH_AT91SAM9X5EK);
- devfs_add_partition("nand0", 0x00000, SZ_256K, PARTITION_FIXED, "at91bootstrap_raw");
+ devfs_add_partition("nand0", 0x00000, SZ_256K, DEVFS_PARTITION_FIXED, "at91bootstrap_raw");
dev_add_bb_dev("at91bootstrap_raw", "at91bootstrap");
- devfs_add_partition("nand0", SZ_256K, SZ_256K + SZ_128K, PARTITION_FIXED, "self_raw");
+ devfs_add_partition("nand0", SZ_256K, SZ_256K + SZ_128K, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
- devfs_add_partition("nand0", SZ_512K + SZ_128K, SZ_128K, PARTITION_FIXED, "env_raw");
+ devfs_add_partition("nand0", SZ_512K + SZ_128K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
- devfs_add_partition("nand0", SZ_512K + SZ_256K, SZ_128K, PARTITION_FIXED, "env_raw1");
+ devfs_add_partition("nand0", SZ_512K + SZ_256K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw1");
dev_add_bb_dev("env_raw1", "env1");
return 0;
diff --git a/arch/arm/boards/dss11/init.c b/arch/arm/boards/dss11/init.c
index 950cf763e9..aacef3342f 100644
--- a/arch/arm/boards/dss11/init.c
+++ b/arch/arm/boards/dss11/init.c
@@ -138,11 +138,11 @@ static int dss11_devices_init(void)
armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100));
armlinux_set_architecture(MACH_TYPE_DSS11);
- devfs_add_partition("nand0", 0x00000, 0x20000, PARTITION_FIXED, "bootstrap");
+ devfs_add_partition("nand0", 0x00000, 0x20000, DEVFS_PARTITION_FIXED, "bootstrap");
dev_add_bb_dev("bootstrap", "bootstrap.bb");
- devfs_add_partition("nand0", 0x20000, 0x40000, PARTITION_FIXED, "barebox");
+ devfs_add_partition("nand0", 0x20000, 0x40000, DEVFS_PARTITION_FIXED, "barebox");
dev_add_bb_dev("barebox", "barebox.bb");
- devfs_add_partition("nand0", 0x60000, 0x40000, PARTITION_FIXED, "barebox-env");
+ devfs_add_partition("nand0", 0x60000, 0x40000, DEVFS_PARTITION_FIXED, "barebox-env");
dev_add_bb_dev("barebox-env", "env0");
return 0;
diff --git a/arch/arm/boards/edb93xx/edb93xx.c b/arch/arm/boards/edb93xx/edb93xx.c
index e1e8adcddb..d32daf4923 100644
--- a/arch/arm/boards/edb93xx/edb93xx.c
+++ b/arch/arm/boards/edb93xx/edb93xx.c
@@ -63,8 +63,8 @@ static int ep93xx_devices_init(void)
* Create partitions that should be
* not touched by any regular user
*/
- devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
- devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
+ devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0");
+ devfs_add_partition("nor0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
diff --git a/arch/arm/boards/eukrea_cpuimx25/env/bin/init_board b/arch/arm/boards/eukrea_cpuimx25/env/bin/init_board
index 2199b88904..ff3365d089 100644
--- a/arch/arm/boards/eukrea_cpuimx25/env/bin/init_board
+++ b/arch/arm/boards/eukrea_cpuimx25/env/bin/init_board
@@ -9,6 +9,27 @@ elif [ -f /env/logo.bmp.lzo ]; then
fb0.enable=1
fi
+gpio_get_value 82
+if [ $? -eq 0 ]; then
+ gpio_set_value 83 0
+ usbserial
+ timeout -s -a 2
+ gpio_get_value 82
+ if [ $? -eq 0 ]; then
+ usbserial -d
+ dfu -V 0x1234 -P 0x1234 /dev/nand0.barebox.bb(barebox)sr,/dev/nand0.kernel.bb(kernel)r,/dev/nand0.root.bb(root)r
+ gpio_get_value 82
+ if [ $? -eq 0 ]; then
+ usbserial
+ autoboot_timeout=60
+ else
+ reset
+ fi
+ else
+ autoboot_timeout=28
+ fi
+fi
+
if [ -z $eth0.ethaddr ]; then
while [ -z $eth0.ethaddr ]; do
readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr
diff --git a/arch/arm/boards/eukrea_cpuimx25/env/config b/arch/arm/boards/eukrea_cpuimx25/env/config
index 9d9ff9aef1..b6bf93f58f 100644
--- a/arch/arm/boards/eukrea_cpuimx25/env/config
+++ b/arch/arm/boards/eukrea_cpuimx25/env/config
@@ -2,6 +2,8 @@
# otg port mode : can be 'host' or 'device'
otg_mode="device"
+# video : can be CMO-QVGA, URT-WVGA, DVI-VGA or DVI-SVGA
+video="CMO-QVGA"
hostname=eukrea-cpuimx25
@@ -35,7 +37,7 @@ nfsroot="$eth0.serverip:/srv/nfs/$hostname"
autoboot_timeout=1
-bootargs="console=ttymxc0,115200 otg_mode=$otg_mode"
+bootargs="console=ttymxc0,115200 otg_mode=$otg_mode video=imxfb:$video"
nand_parts="256k(barebox)ro,128k(bareboxenv),3M(kernel),-(root)"
rootfs_mtdblock_nand=3
diff --git a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
index c717f0b0a2..1b8f618138 100644
--- a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
+++ b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
@@ -87,7 +87,7 @@ unsigned long __image_len_section barebox_len = DCD_BAREBOX_SIZE;
static struct fec_platform_data fec_info = {
.xcv_type = RMII,
- .phy_addr = 1,
+ .phy_addr = 0,
};
struct imx_nand_platform_data nand_info = {
@@ -216,6 +216,8 @@ static iomux_v3_cfg_t eukrea_cpuimx25_pads[] = {
MX25_PAD_SD1_DATA3__SD1_DATA3,
/* LED */
MX25_PAD_POWER_FAIL__GPIO_3_19,
+ /* SWITCH */
+ MX25_PAD_VSTBY_ACK__GPIO_3_18,
};
static int eukrea_cpuimx25_devices_init(void)
@@ -232,11 +234,11 @@ static int eukrea_cpuimx25_devices_init(void)
imx25_add_nand(&nand_info);
devfs_add_partition("nand0", 0x00000, 0x40000,
- PARTITION_FIXED, "self_raw");
+ DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", 0x40000, 0x20000,
- PARTITION_FIXED, "env_raw");
+ DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
/* enable LCD */
@@ -246,6 +248,9 @@ static int eukrea_cpuimx25_devices_init(void)
/* LED : default OFF */
gpio_direction_output(2 * 32 + 19, 1);
+ /* Switch : input */
+ gpio_direction_input(2 * 32 + 18);
+
imx25_add_fb(&eukrea_cpuimx25_fb_data);
imx25_add_i2c0(NULL);
@@ -255,8 +260,12 @@ static int eukrea_cpuimx25_devices_init(void)
imx25_usb_init();
add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE + 0x400, NULL);
#endif
+#ifdef CONFIG_USB_GADGET
+ /* Workaround ENGcm09152 */
+ writel(readl(IMX_OTG_BASE + 0x608) | (1 << 23), IMX_OTG_BASE + 0x608);
add_generic_device("fsl-udc", DEVICE_ID_DYNAMIC, NULL, IMX_OTG_BASE, 0x200,
IORESOURCE_MEM, &usb_pdata);
+#endif
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_EUKREA_CPUIMX25SD);
diff --git a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
index 45ba4f00d1..63e87c9551 100644
--- a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
+++ b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
@@ -200,8 +200,8 @@ static int eukrea_cpuimx27_devices_init(void)
i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
imx27_add_i2c0(NULL);
- devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
- devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
+ devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0");
+ devfs_add_partition("nor0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
envdev = "NOR";
diff --git a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S
index 5295a8a227..e31854606d 100644
--- a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S
+++ b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S
@@ -124,7 +124,7 @@ board_init_lowlevel:
copy_loop:
ldmia r0!, {r3-r9} /* copy from source address [r0] */
stmia r1!, {r3-r9} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
+ cmp r0, r2 /* until source end address [r2] */
ble copy_loop
ldr pc, =1f /* Jump to SDRAM */
diff --git a/arch/arm/boards/eukrea_cpuimx35/env/bin/init_board b/arch/arm/boards/eukrea_cpuimx35/env/bin/init_board
index cb624e57aa..89fd9a90db 100644
--- a/arch/arm/boards/eukrea_cpuimx35/env/bin/init_board
+++ b/arch/arm/boards/eukrea_cpuimx35/env/bin/init_board
@@ -11,6 +11,27 @@ elif [ -f /env/logo.bmp.lzo ]; then
gpio_set_value 1 1
fi
+gpio_get_value 89
+if [ $? -eq 0 ]; then
+ gpio_set_value 93 0
+ usbserial
+ timeout -s -a 2
+ gpio_get_value 89
+ if [ $? -eq 0 ]; then
+ usbserial -d
+ dfu -V 0x1234 -P 0x1234 /dev/nand0.barebox.bb(barebox)sr,/dev/nand0.kernel.bb(kernel)r,/dev/nand0.root.bb(root)r
+ gpio_get_value 89
+ if [ $? -eq 0 ]; then
+ usbserial
+ autoboot_timeout=60
+ else
+ reset
+ fi
+ else
+ autoboot_timeout=28
+ fi
+fi
+
if [ -z $eth0.ethaddr ]; then
while [ -z $eth0.ethaddr ]; do
readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr
diff --git a/arch/arm/boards/eukrea_cpuimx35/env/config b/arch/arm/boards/eukrea_cpuimx35/env/config
index 1b19bd232e..01cbfe9b06 100644
--- a/arch/arm/boards/eukrea_cpuimx35/env/config
+++ b/arch/arm/boards/eukrea_cpuimx35/env/config
@@ -2,6 +2,8 @@
# otg port mode : can be 'host' or 'device'
otg_mode="device"
+# video : can be CMO-QVGA, URT-WVGA, DVI-VGA or DVI-SVGA
+video="CMO-QVGA"
hostname=eukrea-cpuimx35
@@ -35,7 +37,7 @@ nfsroot="$eth0.serverip:/srv/nfs/$hostname"
autoboot_timeout=1
-bootargs="console=ttymxc0,115200 otg_mode=$otg_mode"
+bootargs="console=ttymxc0,115200 otg_mode=$otg_mode video=mx3fb:$video"
nand_parts="256k(barebox)ro,128k(bareboxenv),3M(kernel),-(root)"
rootfs_mtdblock_nand=3
diff --git a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
index 37c32ad0db..93d5ac97fd 100644
--- a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
+++ b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
@@ -57,7 +57,7 @@
static struct fec_platform_data fec_info = {
.xcv_type = MII100,
- .phy_addr = 0x1F,
+ .phy_addr = 0,
};
struct imx_nand_platform_data nand_info = {
@@ -142,43 +142,6 @@ static int eukrea_cpuimx35_mmu_init(void)
}
postmmu_initcall(eukrea_cpuimx35_mmu_init);
-static int eukrea_cpuimx35_devices_init(void)
-{
-#ifdef CONFIG_USB_GADGET
- unsigned int tmp;
-#endif
- imx35_add_nand(&nand_info);
-
- devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
- dev_add_bb_dev("self_raw", "self0");
- devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
- dev_add_bb_dev("env_raw", "env0");
-
- imx35_add_fec(&fec_info);
- imx35_add_fb(&ipu_fb_data);
-
- imx35_add_i2c0(NULL);
- imx35_add_mmc0(NULL);
-
-#ifdef CONFIG_USB
- imx35_usb_init();
- add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE + 0x400, NULL);
-#endif
-#ifdef CONFIG_USB_GADGET
- /* Workaround ENGcm09152 */
- tmp = readl(IMX_OTG_BASE + 0x608);
- writel(tmp | (1 << 23), IMX_OTG_BASE + 0x608);
- add_generic_device("fsl-udc", DEVICE_ID_DYNAMIC, NULL, IMX_OTG_BASE, 0x200,
- IORESOURCE_MEM, &usb_pdata);
-#endif
- armlinux_set_bootparams((void *)0x80000100);
- armlinux_set_architecture(MACH_TYPE_EUKREA_CPUIMX35SD);
-
- return 0;
-}
-
-device_initcall(eukrea_cpuimx35_devices_init);
-
static iomux_v3_cfg_t eukrea_cpuimx35_pads[] = {
MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
@@ -219,20 +182,63 @@ static iomux_v3_cfg_t eukrea_cpuimx35_pads[] = {
MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
+
+ MX35_PAD_LD19__GPIO3_25,
};
-static int eukrea_cpuimx35_console_init(void)
+static int eukrea_cpuimx35_devices_init(void)
{
+#ifdef CONFIG_USB_GADGET
+ unsigned int tmp;
+#endif
mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads,
ARRAY_SIZE(eukrea_cpuimx35_pads));
+ imx35_add_nand(&nand_info);
+
+ devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
+ dev_add_bb_dev("self_raw", "self0");
+ devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw");
+ dev_add_bb_dev("env_raw", "env0");
+
+ imx35_add_fec(&fec_info);
+ imx35_add_fb(&ipu_fb_data);
+
+ imx35_add_i2c0(NULL);
+ imx35_add_mmc0(NULL);
+
+ /* led default off */
+ gpio_direction_output(32 * 2 + 29, 1);
+
+ /* Switch : input */
+ gpio_direction_input(32 * 2 + 25);
+
/* screen default on to prevent flicker */
gpio_direction_output(4, 0);
/* backlight default off */
gpio_direction_output(1, 0);
- /* led default off */
- gpio_direction_output(32 * 2 + 29, 1);
+#ifdef CONFIG_USB
+ imx35_usb_init();
+ add_generic_usb_ehci_device(-1, IMX_OTG_BASE + 0x400, NULL);
+#endif
+#ifdef CONFIG_USB_GADGET
+ /* Workaround ENGcm09152 */
+ tmp = readl(IMX_OTG_BASE + 0x608);
+ writel(tmp | (1 << 23), IMX_OTG_BASE + 0x608);
+ add_generic_device("fsl-udc", -1, NULL, IMX_OTG_BASE, 0x200,
+ IORESOURCE_MEM, &usb_pdata);
+#endif
+ armlinux_set_bootparams((void *)0x80000100);
+ armlinux_set_architecture(MACH_TYPE_EUKREA_CPUIMX35SD);
+
+ return 0;
+}
+
+device_initcall(eukrea_cpuimx35_devices_init);
+
+static int eukrea_cpuimx35_console_init(void)
+{
imx35_add_uart0();
return 0;
}
diff --git a/arch/arm/boards/eukrea_cpuimx51/env/config b/arch/arm/boards/eukrea_cpuimx51/env/config
index 531fa4329a..163d026158 100644
--- a/arch/arm/boards/eukrea_cpuimx51/env/config
+++ b/arch/arm/boards/eukrea_cpuimx51/env/config
@@ -2,9 +2,11 @@
# otg port mode : can be 'host' or 'device'
otg_mode="device"
-# video mode : can be 'CMO-QVGA' or any modefb mode
+# video mode : can be 'CMO-QVGA' or 'URT-WVGA' or any modefb mode
# ex : 640x480M-16@60 800x600M-24@60 1024x768M-16@60
video="CMO-QVGA"
+# screen type : can be 'tft' or 'dvi'
+screen_type="tft"
hostname=eukrea-cpuimx51
@@ -38,12 +40,6 @@ nfsroot="$eth0.serverip:/srv/nfs/$hostname"
autoboot_timeout=1
-if [ x$video = xCMO-QVGA ]; then
- screen_type="tft"
-else
- screen_type="dvi"
-fi
-
bootargs="console=ttymxc0,115200 otg_mode=$otg_mode video=$video screen_type=$screen_type"
nand_parts="256k(barebox)ro,128k(bareboxenv),3M(kernel),-(root)"
diff --git a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c
index 2bda9743df..3cc7a72252 100644
--- a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c
+++ b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c
@@ -118,9 +118,9 @@ static int eukrea_cpuimx51_devices_init(void)
#endif
imx51_add_nand(&nand_info);
- devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
+ devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
- devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
+ devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
gpio_direction_output(GPIO_LAN8700_RESET, 0);
diff --git a/arch/arm/boards/freescale-mx25-3-stack/3stack.c b/arch/arm/boards/freescale-mx25-3-stack/3stack.c
index ac781fd134..323cd1107f 100644
--- a/arch/arm/boards/freescale-mx25-3-stack/3stack.c
+++ b/arch/arm/boards/freescale-mx25-3-stack/3stack.c
@@ -225,10 +225,10 @@ static int imx25_devices_init(void)
imx25_add_nand(&nand_info);
- devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
+ devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
- devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
+ devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
diff --git a/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S b/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S
index 73bb14723e..7b75233ebb 100644
--- a/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S
+++ b/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S
@@ -117,7 +117,7 @@ board_init_lowlevel:
copy_loop:
ldmia r0!, {r3-r9} /* copy from source address [r0] */
stmia r1!, {r3-r9} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
+ cmp r0, r2 /* until source end address [r2] */
ble copy_loop
ldr pc, =1f /* Jump to SDRAM */
diff --git a/arch/arm/boards/freescale-mx35-3-stack/3stack.c b/arch/arm/boards/freescale-mx35-3-stack/3stack.c
index ca8680a82c..cb1280d377 100644
--- a/arch/arm/boards/freescale-mx35-3-stack/3stack.c
+++ b/arch/arm/boards/freescale-mx35-3-stack/3stack.c
@@ -162,15 +162,15 @@ static int f3s_devices_init(void)
switch ((reg >> 25) & 0x3) {
case 0x01: /* NAND is the source */
- devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
+ devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
- devfs_add_partition("nand0", 0x40000, 0x80000, PARTITION_FIXED, "env_raw");
+ devfs_add_partition("nand0", 0x40000, 0x80000, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
break;
case 0x00: /* NOR is the source */
- devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
- devfs_add_partition("nor0", 0x40000, 0x80000, PARTITION_FIXED, "env0");
+ devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0");
+ devfs_add_partition("nor0", 0x40000, 0x80000, DEVFS_PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
break;
}
diff --git a/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S b/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S
index 413e04a63f..30dbcc035a 100644
--- a/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S
+++ b/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S
@@ -173,7 +173,7 @@ board_init_lowlevel:
copy_loop:
ldmia r0!, {r3-r9} /* copy from source address [r0] */
stmia r1!, {r3-r9} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
+ cmp r0, r2 /* until source end address [r2] */
ble copy_loop
ldr pc, =1f /* Jump to SDRAM */
diff --git a/arch/arm/boards/freescale-mx51-pdk/board.c b/arch/arm/boards/freescale-mx51-pdk/board.c
index 00133fc22f..0bb2ffed29 100644
--- a/arch/arm/boards/freescale-mx51-pdk/board.c
+++ b/arch/arm/boards/freescale-mx51-pdk/board.c
@@ -257,8 +257,8 @@ device_initcall(f3s_devices_init);
static int f3s_part_init(void)
{
- devfs_add_partition("disk0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
- devfs_add_partition("disk0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
+ devfs_add_partition("disk0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0");
+ devfs_add_partition("disk0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0");
return 0;
}
diff --git a/arch/arm/boards/freescale-mx51-pdk/env/config b/arch/arm/boards/freescale-mx51-pdk/env/config
deleted file mode 100644
index 7a2841e606..0000000000
--- a/arch/arm/boards/freescale-mx51-pdk/env/config
+++ /dev/null
@@ -1,47 +0,0 @@
-#!/bin/sh
-
-hostname=babbage
-eth0.serverip=
-user=
-
-# use 'dhcp' to do dhcp in barebox and in kernel
-# use 'none' if you want to skip kernel ip autoconfiguration
-ip=dhcp
-
-# or set your networking parameters here
-#eth0.ipaddr=a.b.c.d
-#eth0.netmask=a.b.c.d
-#eth0.gateway=a.b.c.d
-#eth0.serverip=a.b.c.d
-
-# can be either 'nfs', 'tftp', 'nor' or 'nand'
-kernel_loc=tftp
-# can be either 'net', 'nor', 'nand' or 'initrd'
-rootfs_loc=net
-
-# can be either 'jffs2' or 'ubifs'
-rootfs_type=ubifs
-rootfsimage=root-$hostname.$rootfs_type
-
-kernelimage=zImage-$hostname
-#kernelimage=uImage-$hostname
-#kernelimage=Image-$hostname
-#kernelimage=Image-$hostname.lzo
-
-if [ -n $user ]; then
- kernelimage="$user"-"$kernelimage"
- nfsroot="$eth0.serverip:/home/$user/nfsroot/$hostname"
- rootfsimage="$user"-"$rootfsimage"
-else
- nfsroot="$eth0.serverip:/path/to/nfs/root"
-fi
-
-autoboot_timeout=3
-
-bootargs="console=ttymxc0,115200"
-
-disk_parts="256k(barebox)ro,128k(bareboxenv),4M(kernel),-(root)"
-
-# set a fancy prompt (if support is compiled in)
-PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "
-
diff --git a/arch/arm/boards/freescale-mx51-pdk/env/init/bootargs-base b/arch/arm/boards/freescale-mx51-pdk/env/init/bootargs-base
new file mode 100644
index 0000000000..d86975406e
--- /dev/null
+++ b/arch/arm/boards/freescale-mx51-pdk/env/init/bootargs-base
@@ -0,0 +1,8 @@
+#!/bin/sh
+
+if [ "$1" = menu ]; then
+ init-menu-add-entry "$0" "Base bootargs"
+ exit
+fi
+
+global.linux.bootargs.base="console=ttymxc0,115200"
diff --git a/arch/arm/boards/freescale-mx51-pdk/env/init/hostname b/arch/arm/boards/freescale-mx51-pdk/env/init/hostname
new file mode 100644
index 0000000000..4c78902a17
--- /dev/null
+++ b/arch/arm/boards/freescale-mx51-pdk/env/init/hostname
@@ -0,0 +1,8 @@
+#!/bin/sh
+
+if [ "$1" = menu ]; then
+ init-menu-add-entry "$0" "hostname"
+ exit
+fi
+
+global.hostname=babbage
diff --git a/arch/arm/boards/freescale-mx53-loco/board.c b/arch/arm/boards/freescale-mx53-loco/board.c
index ac3323b4ed..0d715559dc 100644
--- a/arch/arm/boards/freescale-mx53-loco/board.c
+++ b/arch/arm/boards/freescale-mx53-loco/board.c
@@ -203,8 +203,8 @@ device_initcall(loco_devices_init);
static int loco_part_init(void)
{
- devfs_add_partition("disk0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
- devfs_add_partition("disk0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
+ devfs_add_partition("disk0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0");
+ devfs_add_partition("disk0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0");
return 0;
}
diff --git a/arch/arm/boards/freescale-mx53-smd/board.c b/arch/arm/boards/freescale-mx53-smd/board.c
index b6632555af..04831030a8 100644
--- a/arch/arm/boards/freescale-mx53-smd/board.c
+++ b/arch/arm/boards/freescale-mx53-smd/board.c
@@ -149,8 +149,8 @@ device_initcall(smd_devices_init);
static int smd_part_init(void)
{
- devfs_add_partition("disk0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
- devfs_add_partition("disk0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
+ devfs_add_partition("disk0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0");
+ devfs_add_partition("disk0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0");
return 0;
}
diff --git a/arch/arm/boards/freescale-mx6-arm2/board.c b/arch/arm/boards/freescale-mx6-arm2/board.c
index 14224727a2..e4a9a49b55 100644
--- a/arch/arm/boards/freescale-mx6-arm2/board.c
+++ b/arch/arm/boards/freescale-mx6-arm2/board.c
@@ -152,8 +152,8 @@ static int arm2_devices_init(void)
armlinux_set_bootparams((void *)0x10000100);
armlinux_set_architecture(3837);
- devfs_add_partition("disk0", 0, SZ_1M, PARTITION_FIXED, "self0");
- devfs_add_partition("disk0", SZ_1M + SZ_1M, SZ_512K, PARTITION_FIXED, "env0");
+ devfs_add_partition("disk0", 0, SZ_1M, DEVFS_PARTITION_FIXED, "self0");
+ devfs_add_partition("disk0", SZ_1M + SZ_1M, SZ_512K, DEVFS_PARTITION_FIXED, "env0");
return 0;
}
diff --git a/arch/arm/boards/guf-cupid/board.c b/arch/arm/boards/guf-cupid/board.c
index 653d4408f9..fb3c56061e 100644
--- a/arch/arm/boards/guf-cupid/board.c
+++ b/arch/arm/boards/guf-cupid/board.c
@@ -130,9 +130,9 @@ static int cupid_devices_init(void)
imx35_add_fec(&fec_info);
imx35_add_nand(&nand_info);
- devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
+ devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
- devfs_add_partition("nand0", 0x40000, 0x80000, PARTITION_FIXED, "env_raw");
+ devfs_add_partition("nand0", 0x40000, 0x80000, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
imx35_add_fb(&ipu_fb_data);
diff --git a/arch/arm/boards/guf-neso/board.c b/arch/arm/boards/guf-neso/board.c
index 84ef2253b3..fbb20c10e0 100644
--- a/arch/arm/boards/guf-neso/board.c
+++ b/arch/arm/boards/guf-neso/board.c
@@ -285,10 +285,10 @@ static int neso_devices_init(void)
imx27_add_fec(&fec_info);
- devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
+ devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
- devfs_add_partition("nand0", 0x40000, 0x80000, PARTITION_FIXED, "env_raw");
+ devfs_add_partition("nand0", 0x40000, 0x80000, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
armlinux_set_bootparams((void *)0xa0000100);
diff --git a/arch/arm/boards/imx21ads/lowlevel_init.S b/arch/arm/boards/imx21ads/lowlevel_init.S
index 607da27476..7926e281c6 100644
--- a/arch/arm/boards/imx21ads/lowlevel_init.S
+++ b/arch/arm/boards/imx21ads/lowlevel_init.S
@@ -138,7 +138,7 @@ board_init_lowlevel:
copy_loop:
ldmia r0!, {r3-r9} /* copy from source address [r0] */
stmia r1!, {r3-r9} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
+ cmp r0, r2 /* until source end address [r2] */
ble copy_loop
ldr pc, =1f /* Jump to SDRAM */
diff --git a/arch/arm/boards/imx27ads/imx27ads.c b/arch/arm/boards/imx27ads/imx27ads.c
index 7ffaeab2f8..ff002249de 100644
--- a/arch/arm/boards/imx27ads/imx27ads.c
+++ b/arch/arm/boards/imx27ads/imx27ads.c
@@ -111,8 +111,8 @@ static int mx27ads_devices_init(void)
add_cfi_flash_device(-1, 0xC0000000, 32 * 1024 * 1024, 0);
imx27_add_fec(&fec_info);
- devfs_add_partition("nor0", 0x00000, 0x20000, PARTITION_FIXED, "self0");
- devfs_add_partition("nor0", 0x20000, 0x20000, PARTITION_FIXED, "env0");
+ devfs_add_partition("nor0", 0x00000, 0x20000, DEVFS_PARTITION_FIXED, "self0");
+ devfs_add_partition("nor0", 0x20000, 0x20000, DEVFS_PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
armlinux_set_bootparams((void *)0xa0000100);
diff --git a/arch/arm/boards/karo-tx25/board.c b/arch/arm/boards/karo-tx25/board.c
index 7df2e4c6ec..040c75bda6 100644
--- a/arch/arm/boards/karo-tx25/board.c
+++ b/arch/arm/boards/karo-tx25/board.c
@@ -116,10 +116,10 @@ static int tx25_devices_init(void)
imx25_add_nand(&nand_info);
- devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
+ devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
- devfs_add_partition("nand0", 0x40000, 0x80000, PARTITION_FIXED, "env_raw");
+ devfs_add_partition("nand0", 0x40000, 0x80000, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
armlinux_set_bootparams((void *)0x80000100);
diff --git a/arch/arm/boards/karo-tx51/tx51.c b/arch/arm/boards/karo-tx51/tx51.c
index b0b4278dd3..096683a1ad 100644
--- a/arch/arm/boards/karo-tx51/tx51.c
+++ b/arch/arm/boards/karo-tx51/tx51.c
@@ -271,9 +271,9 @@ device_initcall(tx51_devices_init);
static int tx51_part_init(void)
{
- devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
+ devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
- devfs_add_partition("nand0", 0x40000, 0x80000, PARTITION_FIXED, "env_raw");
+ devfs_add_partition("nand0", 0x40000, 0x80000, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
return 0;
diff --git a/arch/arm/boards/mini2440/config.h b/arch/arm/boards/mini2440/config.h
index 8d36193c1d..674d9743f9 100644
--- a/arch/arm/boards/mini2440/config.h
+++ b/arch/arm/boards/mini2440/config.h
@@ -66,7 +66,7 @@
#define MINI2440_TWRPH1 1
/* needed in the generic NAND boot code only */
-#ifdef CONFIG_S3C24XX_NAND_BOOT
+#ifdef CONFIG_S3C_NAND_BOOT
# define BOARD_DEFAULT_NAND_TIMING \
CALC_NFCONF_TIMING(MINI2440_TACLS, MINI2440_TWRPH0, MINI2440_TWRPH1)
#endif
diff --git a/arch/arm/boards/mini2440/lowlevel_init.S b/arch/arm/boards/mini2440/lowlevel_init.S
index 1c8860a631..827cf0016b 100644
--- a/arch/arm/boards/mini2440/lowlevel_init.S
+++ b/arch/arm/boards/mini2440/lowlevel_init.S
@@ -30,7 +30,7 @@ board_init_lowlevel:
bl s3c24x0_sdram_init
-#ifdef CONFIG_S3C24XX_NAND_BOOT
+#ifdef CONFIG_S3C_NAND_BOOT
mov lr, r10 /* restore the link register */
/* up to here we are running from the internal SRAM area */
b s3c24x0_nand_boot /* does return directly to our caller into SDRAM */
diff --git a/arch/arm/boards/mini2440/mini2440.c b/arch/arm/boards/mini2440/mini2440.c
index 361a3e294f..3d3b820f20 100644
--- a/arch/arm/boards/mini2440/mini2440.c
+++ b/arch/arm/boards/mini2440/mini2440.c
@@ -305,11 +305,11 @@ static int mini2440_devices_init(void)
#ifdef CONFIG_NAND
/* ----------- add some vital partitions -------- */
devfs_del_partition("self_raw");
- devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
+ devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_del_partition("env_raw");
- devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
+ devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
#endif
add_generic_device("s3c_mci", 0, NULL, S3C2410_SDI_BASE, 0,
@@ -326,7 +326,7 @@ static int mini2440_devices_init(void)
device_initcall(mini2440_devices_init);
-#ifdef CONFIG_S3C24XX_NAND_BOOT
+#ifdef CONFIG_S3C_NAND_BOOT
void __bare_init nand_boot(void)
{
s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0);
diff --git a/arch/arm/boards/mioa701/board.c b/arch/arm/boards/mioa701/board.c
index 14c81104ff..ab5a493e76 100644
--- a/arch/arm/boards/mioa701/board.c
+++ b/arch/arm/boards/mioa701/board.c
@@ -261,8 +261,17 @@ static int mioa701_coredevice_init(void)
/* route pins */
pxa2xx_mfp_config(ARRAY_AND_SIZE(mioa701_pin_config));
- CCCR = CCCR_A | 0x20110;
- cclk = 0x02;
+ /*
+ * Put the board in superspeed (520 MHz) to speed-up logo/OS loading.
+ * This requires to command the Maxim 1586 to upgrade core voltage to
+ * 1.475 V, on the power I2C bus (device 0x14).
+ */
+ CCCR = CCCR_A | 0x20290;
+ PCFR = PCFR_GPR_EN | PCFR_FVC | PCFR_DC_EN | PCFR_PI2C_EN | PCFR_OPDE;
+ PCMD(0) = PCMD_LC | 0x1f;
+ PVCR = 0x14;
+
+ cclk = 0x0b;
asm volatile("mcr p14, 0, %0, c6, c0, 0 @ set CCLK"
: : "r" (cclk) : "cc");
diff --git a/arch/arm/boards/mioa701/env/bin/barebox_update b/arch/arm/boards/mioa701/env/bin/barebox_update
index 564549bb75..b544563bef 100644
--- a/arch/arm/boards/mioa701/env/bin/barebox_update
+++ b/arch/arm/boards/mioa701/env/bin/barebox_update
@@ -3,3 +3,8 @@
# Page+OOB specific partitions
addpart /dev/mtdraw0 1081344@3649536(msipl)
addpart /dev/mtdraw0 270336@3649536(barebox)
+
+if [ -r /barebox.BIP0 ]; then
+ erase /dev/mtdraw0.barebox
+ cp -v /barebox.BIP0 /dev/mtdraw0.barebox
+fi
diff --git a/arch/arm/boards/mioa701/env/bin/dps1_unlock b/arch/arm/boards/mioa701/env/bin/dps1_unlock
new file mode 100644
index 0000000000..2d7dab8c58
--- /dev/null
+++ b/arch/arm/boards/mioa701/env/bin/dps1_unlock
@@ -0,0 +1,12 @@
+#!/bin/sh
+#
+# Shell to unlock the DPS1 with "12345678" key.
+
+mw -b 0x105e 0x31
+mw -b 0x105e 0x32
+mw -b 0x105e 0x33
+mw -b 0x105e 0x34
+mw -b 0x105e 0x35
+mw -b 0x105e 0x36
+mw -b 0x105e 0x37
+mw -b 0x105e 0x38
diff --git a/arch/arm/boards/mioa701/env/bin/dps1_update b/arch/arm/boards/mioa701/env/bin/dps1_update
new file mode 100644
index 0000000000..a9d72da891
--- /dev/null
+++ b/arch/arm/boards/mioa701/env/bin/dps1_update
@@ -0,0 +1,12 @@
+#!/bin/sh
+
+# Page+OOB specific partitions
+addpart /dev/mtdraw0 67584@202752(dps1)
+uncompress /env/data/dps1.raw.gz /dps1.raw
+
+if [ -r /dps1.raw ]; then
+ dps1_unlock
+ erase /dev/mtdraw0.dps1
+ cp -v /dps1.raw /dev/mtdraw0.dps1
+ dps1_unlock
+fi
diff --git a/arch/arm/boards/mioa701/env/bin/init b/arch/arm/boards/mioa701/env/bin/init
index 8a54da0c10..494d0674aa 100644
--- a/arch/arm/boards/mioa701/env/bin/init
+++ b/arch/arm/boards/mioa701/env/bin/init
@@ -22,14 +22,19 @@ if [ $? = 0 ]; then
fi
echo "No custom environment found"
-echo -n "Hit any key to stop autoboot: "
-timeout -a $autoboot_timeout
-if [ $? != 0 ]; then
- echo
- echo "Welcome to barebox console"
- exit
+
+gpio_get_value 22
+is_usb_connected=$?
+if [ $is_usb_connected != 0 ]; then
+ echo -n "Hit any key to stop autoboot: "
+ timeout -a $autoboot_timeout
+ if [ $? != 0 ]; then
+ echo
+ echo "Welcome to barebox console"
+ exit
+ fi
fi
echo "Booting linux kernel on docg3 chip ..."
-bootargs="$bootargs mtdparts=mtd0:$mtdparts root=/dev/mtd4"
+bootargs="$bootargs mtdparts=docg3.0:$mtdparts ubi.mtd=4 rootfstype=ubifs root=ubi0:linux_root ro"
bootm /dev/mtd0.kernel
diff --git a/arch/arm/boards/mioa701/env/data/dps1.raw.gz b/arch/arm/boards/mioa701/env/data/dps1.raw.gz
new file mode 100644
index 0000000000..93112bfca1
--- /dev/null
+++ b/arch/arm/boards/mioa701/env/data/dps1.raw.gz
Binary files differ
diff --git a/arch/arm/boards/mmccpu/init.c b/arch/arm/boards/mmccpu/init.c
index 9d4d496521..a7120400fa 100644
--- a/arch/arm/boards/mmccpu/init.c
+++ b/arch/arm/boards/mmccpu/init.c
@@ -63,8 +63,8 @@ static int mmccpu_devices_init(void)
at91_add_device_eth(0, &macb_pdata);
add_cfi_flash_device(0, AT91_CHIPSELECT_0, 0, 0);
- devfs_add_partition("nor0", 0x00000, 256 * 1024, PARTITION_FIXED, "self0");
- devfs_add_partition("nor0", 0x40000, 128 * 1024, PARTITION_FIXED, "env0");
+ devfs_add_partition("nor0", 0x00000, 256 * 1024, DEVFS_PARTITION_FIXED, "self0");
+ devfs_add_partition("nor0", 0x40000, 128 * 1024, DEVFS_PARTITION_FIXED, "env0");
armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100));
armlinux_set_architecture(MACH_TYPE_MMCCPU);
diff --git a/arch/arm/boards/netx/netx.c b/arch/arm/boards/netx/netx.c
index 7873d32fbf..c4a8733aad 100644
--- a/arch/arm/boards/netx/netx.c
+++ b/arch/arm/boards/netx/netx.c
@@ -54,10 +54,10 @@ static int netx_devices_init(void) {
add_generic_device("netx-eth", DEVICE_ID_DYNAMIC, NULL, 0, 0, IORESOURCE_MEM,
&eth1_data);
- devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
+ devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0");
/* Do not overwrite primary env for now */
- devfs_add_partition("nor0", 0xc0000, 0x80000, PARTITION_FIXED, "env0");
+ devfs_add_partition("nor0", 0xc0000, 0x80000, DEVFS_PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
diff --git a/arch/arm/boards/nhk8815/setup.c b/arch/arm/boards/nhk8815/setup.c
index ae76124c7f..173892acd8 100644
--- a/arch/arm/boards/nhk8815/setup.c
+++ b/arch/arm/boards/nhk8815/setup.c
@@ -103,11 +103,11 @@ static int nhk8815_devices_init(void)
armlinux_set_architecture(MACH_TYPE_NOMADIK);
armlinux_set_bootparams((void *)(0x00000100));
- devfs_add_partition("nand0", 0x0000000, 0x040000, PARTITION_FIXED, "xloader_raw");
- devfs_add_partition("nand0", 0x0040000, 0x080000, PARTITION_FIXED, "meminit_raw");
- devfs_add_partition("nand0", 0x0080000, 0x200000, PARTITION_FIXED, "self_raw");
+ devfs_add_partition("nand0", 0x0000000, 0x040000, DEVFS_PARTITION_FIXED, "xloader_raw");
+ devfs_add_partition("nand0", 0x0040000, 0x080000, DEVFS_PARTITION_FIXED, "meminit_raw");
+ devfs_add_partition("nand0", 0x0080000, 0x200000, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
- devfs_add_partition("nand0", 0x7FE0000, 0x020000, PARTITION_FIXED, "env_raw");
+ devfs_add_partition("nand0", 0x7FE0000, 0x020000, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
return 0;
diff --git a/arch/arm/boards/panda/board.c b/arch/arm/boards/panda/board.c
index 26d365c370..84b4ecd77e 100644
--- a/arch/arm/boards/panda/board.c
+++ b/arch/arm/boards/panda/board.c
@@ -20,6 +20,9 @@
#include <mach/gpio.h>
#include <environment.h>
#include <mach/xload.h>
+#include <i2c/i2c.h>
+#include <gpio.h>
+#include <led.h>
static int board_revision;
@@ -106,6 +109,28 @@ static void __init panda_boardrev_init(void)
pr_info("PandaBoard Revision: %03d\n", board_revision);
}
+static struct i2c_board_info i2c_devices[] = {
+ {
+ I2C_BOARD_INFO("twl6030", 0x48),
+ },
+};
+
+struct gpio_led panda_leds[] = {
+ {
+ .gpio = 7,
+ .led = {
+ .name = "heartbeat",
+ },
+ },
+};
+
+static void panda_led_init(void)
+{
+ gpio_direction_output(7, 0);
+ led_gpio_register(&panda_leds[0]);
+ led_set_trigger(LED_TRIGGER_HEARTBEAT, &panda_leds[0].led);
+}
+
static int panda_devices_init(void)
{
panda_boardrev_init();
@@ -134,10 +159,17 @@ static int panda_devices_init(void)
sr32(OMAP44XX_SCRM_ALTCLKSRC, 2, 2, 0x3);
}
+ i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
+ add_generic_device("i2c-omap", DEVICE_ID_DYNAMIC,
+ NULL, 0x48070000, 0x1000,
+ IORESOURCE_MEM, NULL);
+
+
add_generic_device("omap-hsmmc", DEVICE_ID_DYNAMIC, NULL, 0x4809C100, SZ_4K,
IORESOURCE_MEM, NULL);
panda_ehci_init();
+ panda_led_init();
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_OMAP4_PANDA);
diff --git a/arch/arm/boards/pcm027/board.c b/arch/arm/boards/pcm027/board.c
index ab55c345c8..2801967dd2 100644
--- a/arch/arm/boards/pcm027/board.c
+++ b/arch/arm/boards/pcm027/board.c
@@ -165,8 +165,8 @@ static int pcm027_devices_init(void)
armlinux_set_bootparams((void *)0xa0000100);
armlinux_set_architecture(MACH_TYPE_PCM027);
- devfs_add_partition("nor0", 0x00000, SZ_512K, PARTITION_FIXED, "self0");
- devfs_add_partition("nor0", SZ_512K, SZ_256K, PARTITION_FIXED, "env0");
+ devfs_add_partition("nor0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self0");
+ devfs_add_partition("nor0", SZ_512K, SZ_256K, DEVFS_PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
return 0;
diff --git a/arch/arm/boards/pcm037/lowlevel_init.S b/arch/arm/boards/pcm037/lowlevel_init.S
index 8988db23a2..cc4674d2e2 100644
--- a/arch/arm/boards/pcm037/lowlevel_init.S
+++ b/arch/arm/boards/pcm037/lowlevel_init.S
@@ -151,7 +151,7 @@ clear_iomux:
copy_loop:
ldmia r0!, {r3-r9} /* copy from source address [r0] */
stmia r1!, {r3-r9} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
+ cmp r0, r2 /* until source end address [r2] */
ble copy_loop
ldr pc, =1f /* Jump to SDRAM */
diff --git a/arch/arm/boards/pcm037/pcm037.c b/arch/arm/boards/pcm037/pcm037.c
index 660c9ab428..d789b28e01 100644
--- a/arch/arm/boards/pcm037/pcm037.c
+++ b/arch/arm/boards/pcm037/pcm037.c
@@ -194,8 +194,8 @@ static int imx31_devices_init(void)
* Create partitions that should be
* not touched by any regular user
*/
- devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0"); /* ourself */
- devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0"); /* environment */
+ devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0"); /* ourself */
+ devfs_add_partition("nor0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0"); /* environment */
protect_file("/dev/env0", 1);
diff --git a/arch/arm/boards/pcm038/Makefile b/arch/arm/boards/pcm038/Makefile
index 970804e280..6cd3a5b6c6 100644
--- a/arch/arm/boards/pcm038/Makefile
+++ b/arch/arm/boards/pcm038/Makefile
@@ -1,3 +1,2 @@
-
-obj-y += lowlevel.o
-obj-y += pcm038.o
+obj-y += lowlevel.o pcm038.o
+obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970.o
diff --git a/arch/arm/boards/pcm038/env/boot/nand-ubi b/arch/arm/boards/pcm038/env/boot/nand-ubi
new file mode 100644
index 0000000000..a3f748e746
--- /dev/null
+++ b/arch/arm/boards/pcm038/env/boot/nand-ubi
@@ -0,0 +1,10 @@
+#!/bin/sh
+
+if [ "$1" = menu ]; then
+ boot-menu-add-entry "$0" "nand (UBI)"
+ exit
+fi
+
+global.bootm.image="/dev/nand0.kernel.bb"
+#global.bootm.oftree="/env/oftree"
+bootargs-root-ubi -r root -m nand0.root
diff --git a/arch/arm/boards/pcm038/env/config b/arch/arm/boards/pcm038/env/config
deleted file mode 100644
index 32be5ec419..0000000000
--- a/arch/arm/boards/pcm038/env/config
+++ /dev/null
@@ -1,52 +0,0 @@
-#!/bin/sh
-
-hostname=pcm038
-eth0.serverip=
-user=
-
-# use 'dhcp' to do dhcp in barebox and in kernel
-# use 'none' if you want to skip kernel ip autoconfiguration
-ip=dhcp
-
-# or set your networking parameters here
-#eth0.ipaddr=a.b.c.d
-#eth0.netmask=a.b.c.d
-#eth0.gateway=a.b.c.d
-#eth0.serverip=a.b.c.d
-
-# can be either 'nfs', 'tftp', 'nor' or 'nand'
-kernel_loc=tftp
-# can be either 'net', 'nor', 'nand' or 'initrd'
-rootfs_loc=net
-
-# can be either 'jffs2' or 'ubifs'
-rootfs_type=ubifs
-rootfsimage=root-$hostname.$rootfs_type
-
-kernelimage=zImage-$hostname
-#kernelimage=uImage-$hostname
-#kernelimage=Image-$hostname
-#kernelimage=Image-$hostname.lzo
-
-if [ -n $user ]; then
- kernelimage="$user"-"$kernelimage"
- nfsroot="$eth0.serverip:/home/$user/nfsroot/$hostname"
- rootfsimage="$user"-"$rootfsimage"
-else
- nfsroot="$eth0.serverip:/path/to/nfs/root"
-fi
-
-autoboot_timeout=3
-
-bootargs="console=ttymxc0,115200"
-
-nor_parts="512k(barebox)ro,128k(bareboxenv),2M(kernel),-(root)"
-rootfs_mtdblock_nor=3
-
-nand_parts="512k(barebox)ro,128k(bareboxenv),2M(kernel),-(root)"
-rootfs_mtdblock_nand=7
-nand_device="mxc_nand"
-
-# set a fancy prompt (if support is compiled in)
-PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "
-
diff --git a/arch/arm/boards/pcm038/env/init/bootargs-base b/arch/arm/boards/pcm038/env/init/bootargs-base
new file mode 100644
index 0000000000..d86975406e
--- /dev/null
+++ b/arch/arm/boards/pcm038/env/init/bootargs-base
@@ -0,0 +1,8 @@
+#!/bin/sh
+
+if [ "$1" = menu ]; then
+ init-menu-add-entry "$0" "Base bootargs"
+ exit
+fi
+
+global.linux.bootargs.base="console=ttymxc0,115200"
diff --git a/arch/arm/boards/pcm038/env/init/hostname b/arch/arm/boards/pcm038/env/init/hostname
new file mode 100644
index 0000000000..09c2f08c38
--- /dev/null
+++ b/arch/arm/boards/pcm038/env/init/hostname
@@ -0,0 +1,8 @@
+#!/bin/sh
+
+if [ "$1" = menu ]; then
+ init-menu-add-entry "$0" "hostname"
+ exit
+fi
+
+global.hostname=pcm038
diff --git a/arch/arm/boards/pcm038/env/init/mtdparts-nand b/arch/arm/boards/pcm038/env/init/mtdparts-nand
new file mode 100644
index 0000000000..84220b77b3
--- /dev/null
+++ b/arch/arm/boards/pcm038/env/init/mtdparts-nand
@@ -0,0 +1,11 @@
+#!/bin/sh
+
+if [ "$1" = menu ]; then
+ init-menu-add-entry "$0" "NAND partitions"
+ exit
+fi
+
+mtdparts="512k(nand0.barebox)ro,128k(nand0.bareboxenv),4M(nand0.kernel),-(nand0.root)"
+kernelname="mxc_nand"
+
+mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts}
diff --git a/arch/arm/boards/pcm038/env/init/mtdparts-nor b/arch/arm/boards/pcm038/env/init/mtdparts-nor
new file mode 100644
index 0000000000..c2c40655f3
--- /dev/null
+++ b/arch/arm/boards/pcm038/env/init/mtdparts-nor
@@ -0,0 +1,11 @@
+#!/bin/sh
+
+if [ "$1" = menu ]; then
+ init-menu-add-entry "$0" "NOR partitions"
+ exit
+fi
+
+mtdparts="512k(nor0.barebox)ro,128k(nor0.bareboxenv),4M(nor0.kernel),-(nor0.root)"
+kernelname="physmap-flash.0"
+
+mtdparts-add -d nor0 -k ${kernelname} -p ${mtdparts}
diff --git a/arch/arm/boards/pcm038/pcm038.c b/arch/arm/boards/pcm038/pcm038.c
index d481bdc576..badc978a24 100644
--- a/arch/arm/boards/pcm038/pcm038.c
+++ b/arch/arm/boards/pcm038/pcm038.c
@@ -30,17 +30,13 @@
#include <generated/mach-types.h>
#include <partition.h>
#include <fs.h>
-#include <fcntl.h>
#include <nand.h>
-#include <command.h>
#include <spi/spi.h>
#include <io.h>
#include <mach/imx-nand.h>
#include <mach/imx-pll.h>
#include <mach/imxfb.h>
-#include <asm/mmu.h>
#include <i2c/i2c.h>
-#include <usb/ulpi.h>
#include <mach/spi.h>
#include <mach/iomux-mx27.h>
#include <mach/devices-imx27.h>
@@ -110,27 +106,67 @@ static struct imx_fb_platform_data pcm038_fb_data = {
.dmacr = 0x00020010,
};
-#ifdef CONFIG_USB
-static void pcm038_usbh_init(void)
+/**
+ * The spctl0 register is a beast: Seems you can read it
+ * only one times without writing it again.
+ */
+static inline uint32_t get_pll_spctl10(void)
{
- uint32_t temp;
+ uint32_t reg;
- temp = readl(IMX_OTG_BASE + 0x600);
- temp &= ~((3 << 21) | 1);
- temp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 20);
- writel(temp, IMX_OTG_BASE + 0x600);
+ reg = SPCTL0;
+ SPCTL0 = reg;
+
+ return reg;
+}
- temp = readl(IMX_OTG_BASE + 0x584);
- temp &= ~(3 << 30);
- temp |= 2 << 30;
- writel(temp, IMX_OTG_BASE + 0x584);
+/**
+ * If the PLL settings are in place switch the CPU core frequency to the max. value
+ */
+static int pcm038_power_init(void)
+{
+#ifdef CONFIG_MFD_MC13XXX
+ uint32_t spctl0 = get_pll_spctl10();
+ struct mc13xxx *mc13xxx = mc13xxx_get();
- mdelay(10);
+ /* PLL registers already set to their final values? */
+ if (spctl0 == SPCTL0_VAL && MPCTL0 == MPCTL0_VAL) {
+ console_flush();
+ if (mc13xxx) {
+ mc13xxx_reg_write(mc13xxx, MC13783_REG_SWITCHERS(0),
+ MC13783_SWX_VOLTAGE(MC13783_SWX_VOLTAGE_1_450) |
+ MC13783_SWX_VOLTAGE_DVS(MC13783_SWX_VOLTAGE_1_450) |
+ MC13783_SWX_VOLTAGE_STANDBY(MC13783_SWX_VOLTAGE_1_450));
+
+ mc13xxx_reg_write(mc13xxx, MC13783_REG_SWITCHERS(4),
+ MC13783_SW1A_MODE(MC13783_SWX_MODE_NO_PULSE_SKIP) |
+ MC13783_SW1A_MODE_STANDBY(MC13783_SWX_MODE_NO_PULSE_SKIP) |
+ MC13783_SW1A_SOFTSTART |
+ MC13783_SW1B_MODE(MC13783_SWX_MODE_NO_PULSE_SKIP) |
+ MC13783_SW1B_MODE_STANDBY(MC13783_SWX_MODE_NO_PULSE_SKIP) |
+ MC13783_SW1B_SOFTSTART |
+ MC13783_SW_PLL_FACTOR(32));
- ulpi_setup((void *)(IMX_OTG_BASE + 0x570), 1);
-}
+ /* wait for required power level to run the CPU at 400 MHz */
+ udelay(100000);
+ CSCR = CSCR_VAL_FINAL;
+ PCDR0 = 0x130410c3;
+ PCDR1 = 0x09030911;
+
+ /* Clocks have changed. Notify clients */
+ clock_notifier_call_chain();
+ } else {
+ printf("Failed to initialize PMIC. Will continue with low CPU speed\n");
+ }
+ }
#endif
+ /* clock gating enable */
+ GPCR = 0x00050f08;
+
+ return 0;
+}
+
static int pcm038_mem_init(void)
{
arm_add_mem_device("ram0", 0xa0000000, 128 * 1024 * 1024);
@@ -202,19 +238,6 @@ static int pcm038_devices_init(void)
PA29_PF_VSYNC,
PA30_PF_CONTRAST,
PA31_PF_OE_ACD,
- /* USB host 2 */
- PA0_PF_USBH2_CLK,
- PA1_PF_USBH2_DIR,
- PA2_PF_USBH2_DATA7,
- PA3_PF_USBH2_NXT,
- PA4_PF_USBH2_STP,
- PD19_AF_USBH2_DATA4,
- PD20_AF_USBH2_DATA3,
- PD21_AF_USBH2_DATA6,
- PD22_AF_USBH2_DATA0,
- PD23_AF_USBH2_DATA2,
- PD24_AF_USBH2_DATA1,
- PD26_AF_USBH2_DATA5,
/* I2C1 */
PD17_PF_I2C_DATA | GPIO_PUEN,
PD18_PF_I2C_CLK,
@@ -229,9 +252,6 @@ static int pcm038_devices_init(void)
/* configure SRAM on cs1 */
imx27_setup_weimcs(1, 0x0000d843, 0x22252521, 0x22220a00);
- /* configure SJA1000 on cs4 */
- imx27_setup_weimcs(4, 0x0000DCF6, 0x444A0301, 0x44443302);
-
/* initizalize gpios */
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
@@ -239,12 +259,11 @@ static int pcm038_devices_init(void)
PCCR0 |= PCCR0_CSPI1_EN;
PCCR1 |= PCCR1_PERCLK2_EN;
- gpio_direction_output(GPIO_PORTD | 28, 0);
- gpio_set_value(GPIO_PORTD | 28, 0);
-
spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info));
imx27_add_spi0(&pcm038_spi_0_data);
+ pcm038_power_init();
+
add_cfi_flash_device(-1, 0xC0000000, 32 * 1024 * 1024, 0);
imx27_add_nand(&nand_info);
imx27_add_fb(&pcm038_fb_data);
@@ -253,11 +272,6 @@ static int pcm038_devices_init(void)
imx27_add_i2c0(NULL);
imx27_add_i2c1(NULL);
-#ifdef CONFIG_USB
- pcm038_usbh_init();
- add_generic_usb_ehci_device(-1, IMX_OTG_BASE + 0x400, NULL);
-#endif
-
/* Register the fec device after the PLL re-initialisation
* as the fec depends on the (now higher) ipg clock
*/
@@ -269,19 +283,19 @@ static int pcm038_devices_init(void)
case GPCR_BOOT_16BIT_NAND_512:
case GPCR_BOOT_8BIT_NAND_512:
devfs_add_partition("nand0", 0x00000, 0x80000,
- PARTITION_FIXED, "self_raw");
+ DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", 0x80000, 0x100000,
- PARTITION_FIXED, "env_raw");
+ DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
envdev = "NAND";
break;
default:
devfs_add_partition("nor0", 0x00000, 0x80000,
- PARTITION_FIXED, "self0");
+ DEVFS_PARTITION_FIXED, "self0");
devfs_add_partition("nor0", 0x80000, 0x100000,
- PARTITION_FIXED, "env0");
+ DEVFS_PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
envdev = "NOR";
@@ -305,80 +319,3 @@ static int pcm038_console_init(void)
}
console_initcall(pcm038_console_init);
-
-#ifdef CONFIG_MFD_MC13XXX
-static int pmic_power(void)
-{
- struct mc13xxx *mc13xxx;
-
- mc13xxx = mc13xxx_get();
- if (!mc13xxx)
- return -ENODEV;
-
- mc13xxx_reg_write(mc13xxx, MC13783_REG_SWITCHERS(0),
- MC13783_SWX_VOLTAGE(MC13783_SWX_VOLTAGE_1_450) |
- MC13783_SWX_VOLTAGE_DVS(MC13783_SWX_VOLTAGE_1_450) |
- MC13783_SWX_VOLTAGE_STANDBY(MC13783_SWX_VOLTAGE_1_450));
-
- mc13xxx_reg_write(mc13xxx, MC13783_REG_SWITCHERS(4),
- MC13783_SW1A_MODE(MC13783_SWX_MODE_NO_PULSE_SKIP) |
- MC13783_SW1A_MODE_STANDBY(MC13783_SWX_MODE_NO_PULSE_SKIP) |
- MC13783_SW1A_SOFTSTART |
- MC13783_SW1B_MODE(MC13783_SWX_MODE_NO_PULSE_SKIP) |
- MC13783_SW1B_MODE_STANDBY(MC13783_SWX_MODE_NO_PULSE_SKIP) |
- MC13783_SW1B_SOFTSTART |
- MC13783_SW_PLL_FACTOR(32));
-
- return 0;
-}
-#else
-# define pmic_power() (1)
-#endif
-
-/**
- * The spctl0 register is a beast: Seems you can read it
- * only one times without writing it again.
- */
-static inline uint32_t get_pll_spctl10(void)
-{
- uint32_t reg;
-
- reg = SPCTL0;
- SPCTL0 = reg;
-
- return reg;
-}
-
-/**
- * If the PLL settings are in place switch the CPU core frequency to the max. value
- */
-static int pcm038_power_init(void)
-{
- uint32_t spctl0;
-
- spctl0 = get_pll_spctl10();
-
- /* PLL registers already set to their final values? */
- if (spctl0 == SPCTL0_VAL && MPCTL0 == MPCTL0_VAL) {
- console_flush();
- if (!pmic_power()) {
- /* wait for required power level to run the CPU at 400 MHz */
- udelay(100000);
- CSCR = CSCR_VAL_FINAL;
- PCDR0 = 0x130410c3;
- PCDR1 = 0x09030911;
- /* Clocks have changed. Notify clients */
- clock_notifier_call_chain();
- } else {
- printf("Failed to initialize PMIC. Will continue with low CPU speed\n");
- }
- }
-
- /* clock gating enable */
- GPCR = 0x00050f08;
-
- return 0;
-}
-
-late_initcall(pcm038_power_init);
-
diff --git a/arch/arm/boards/pcm038/pcm038.dox b/arch/arm/boards/pcm038/pcm038.dox
index 9b17674a21..85177d2eb1 100644
--- a/arch/arm/boards/pcm038/pcm038.dox
+++ b/arch/arm/boards/pcm038/pcm038.dox
@@ -2,7 +2,8 @@
This CPU card is based on a Freescale i.MX27 CPU. The card is shipped with:
-- up to 32MiB NOR type Flash Memory
-- 32MiB synchronous dynamic RAM
+- up to 64MB NOR Flash Memory
+- up to 1GB NAND Flash Memory
+- up to 256MB DRAM
*/
diff --git a/arch/arm/boards/pcm038/pcm970.c b/arch/arm/boards/pcm038/pcm970.c
new file mode 100644
index 0000000000..ca10afb8ca
--- /dev/null
+++ b/arch/arm/boards/pcm038/pcm970.c
@@ -0,0 +1,187 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <io.h>
+#include <init.h>
+#include <sizes.h>
+#include <platform_ide.h>
+#include <mach/imx-regs.h>
+#include <mach/iomux-mx27.h>
+#include <mach/gpio.h>
+#include <usb/ulpi.h>
+
+#define GPIO_IDE_POWER (GPIO_PORTE + 18)
+#define GPIO_IDE_PCOE (GPIO_PORTF + 7)
+#define GPIO_IDE_RESET (GPIO_PORTF + 10)
+
+#ifdef CONFIG_USB
+static void pcm970_usbh2_init(void)
+{
+ uint32_t temp;
+
+ temp = readl(IMX_OTG_BASE + 0x600);
+ temp &= ~((3 << 21) | 1);
+ temp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 20);
+ writel(temp, IMX_OTG_BASE + 0x600);
+
+ temp = readl(IMX_OTG_BASE + 0x584);
+ temp &= ~(3 << 30);
+ temp |= 2 << 30;
+ writel(temp, IMX_OTG_BASE + 0x584);
+
+ mdelay(10);
+
+ if (!ulpi_setup((void *)(IMX_OTG_BASE + 0x570), 1))
+ add_generic_usb_ehci_device(-1, IMX_OTG_BASE + 0x400, NULL);
+}
+#endif
+
+#ifdef CONFIG_DISK_INTF_PLATFORM_IDE
+static struct resource pcm970_ide_resources[] = {
+ {
+ .start = IMX_PCMCIA_MEM_BASE,
+ .size = SZ_1K,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static void pcm970_ide_reset(int state)
+{
+ /* Switch reset line to low/high state */
+ gpio_set_value(GPIO_IDE_RESET, !!state);
+}
+
+static struct ide_port_info pcm970_ide_pdata = {
+ .ioport_shift = 0,
+ .reset = &pcm970_ide_reset,
+};
+
+static struct device_d pcm970_ide_device = {
+ .id = -1,
+ .name = "ide_intf",
+ .num_resources = ARRAY_SIZE(pcm970_ide_resources),
+ .resource = pcm970_ide_resources,
+ .platform_data = &pcm970_ide_pdata,
+};
+
+static void pcm970_ide_init(void)
+{
+ uint32_t i;
+ unsigned int mode[] = {
+ /* PCMCIA */
+ PF20_PF_PC_CD1,
+ PF19_PF_PC_CD2,
+ PF18_PF_PC_WAIT,
+ PF17_PF_PC_READY,
+ PF16_PF_PC_PWRON,
+ PF14_PF_PC_VS1,
+ PF13_PF_PC_VS2,
+ PF12_PF_PC_BVD1,
+ PF11_PF_PC_BVD2,
+ PF9_PF_PC_IOIS16,
+ PF8_PF_PC_RW,
+ GPIO_IDE_PCOE | GPIO_GPIO | GPIO_OUT, /* PCOE */
+ GPIO_IDE_RESET | GPIO_GPIO | GPIO_OUT, /* Reset */
+ GPIO_IDE_POWER | GPIO_GPIO | GPIO_OUT, /* Power */
+ };
+
+ for (i = 0; i < ARRAY_SIZE(mode); i++)
+ imx_gpio_mode(mode[i] | GPIO_PUEN);
+
+ /* Always set PCOE signal to low */
+ gpio_set_value(GPIO_IDE_PCOE, 0);
+
+ /* Assert RESET line */
+ gpio_set_value(GPIO_IDE_RESET, 0);
+
+ /* Power up CF-card (Also switched on User-LED) */
+ gpio_set_value(GPIO_IDE_POWER, 1);
+ mdelay(10);
+
+ /* Reset PCMCIA Status Change Register */
+ writel(0x00000fff, PCMCIA_PSCR);
+ mdelay(10);
+
+ /* Check PCMCIA Input Pins Register for Card Detect & Power */
+ if ((readl(PCMCIA_PIPR) & ((1 << 8) | (3 << 3))) != (1 << 8)) {
+ printf("CompactFlash card not found. Driver not enabled.\n");
+ return;
+ }
+
+ /* Disable all interrupts */
+ writel(0, PCMCIA_PER);
+
+ /* Disable all PCMCIA banks */
+ for (i = 0; i < 5; i++)
+ writel(0, PCMCIA_POR(i));
+
+ /* Not use internal PCOE */
+ writel(0, PCMCIA_PGCR);
+
+ /* Setup PCMCIA bank0 for Common memory mode */
+ writel(0, PCMCIA_PBR(0));
+ writel(0, PCMCIA_POFR(0));
+ writel((0 << 25) | (17 << 17) | (4 << 11) | (3 << 5) | 0xf, PCMCIA_POR(0));
+
+ /* Clear PCMCIA General Status Register */
+ writel(0x0000001f, PCMCIA_PGSR);
+
+ /* Make PCMCIA bank0 valid */
+ writel(readl(PCMCIA_POR(0)) | (1 << 29), PCMCIA_POR(0));
+
+ register_device(&pcm970_ide_device);
+}
+#endif
+
+static int pcm970_init(void)
+{
+ int i;
+ unsigned int mode[] = {
+ /* USB Host 2 */
+ PA0_PF_USBH2_CLK,
+ PA1_PF_USBH2_DIR,
+ PA2_PF_USBH2_DATA7,
+ PA3_PF_USBH2_NXT,
+ PA4_PF_USBH2_STP,
+ PD19_AF_USBH2_DATA4,
+ PD20_AF_USBH2_DATA3,
+ PD21_AF_USBH2_DATA6,
+ PD22_AF_USBH2_DATA0,
+ PD23_AF_USBH2_DATA2,
+ PD24_AF_USBH2_DATA1,
+ PD26_AF_USBH2_DATA5,
+ };
+
+ for (i = 0; i < ARRAY_SIZE(mode); i++)
+ imx_gpio_mode(mode[i]);
+
+ /* Configure SJA1000 on cs4 */
+ imx27_setup_weimcs(4, 0x0000DCF6, 0x444A0301, 0x44443302);
+
+#ifdef CONFIG_USB
+ pcm970_usbh2_init();
+#endif
+
+#ifdef CONFIG_DISK_INTF_PLATFORM_IDE
+ pcm970_ide_init();
+#endif
+
+ return 0;
+}
+
+late_initcall(pcm970_init);
diff --git a/arch/arm/boards/pcm043/pcm043.c b/arch/arm/boards/pcm043/pcm043.c
index 6da5dd45fb..152b47ce65 100644
--- a/arch/arm/boards/pcm043/pcm043.c
+++ b/arch/arm/boards/pcm043/pcm043.c
@@ -153,15 +153,15 @@ static int imx35_devices_init(void)
if ((reg & 0xc00) == 0x800) { /* reset mode: external boot */
switch ( (reg >> 25) & 0x3) {
case 0x01: /* NAND is the source */
- devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
+ devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
- devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
+ devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
break;
case 0x00: /* NOR is the source */
- devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0"); /* ourself */
- devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0"); /* environment */
+ devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0"); /* ourself */
+ devfs_add_partition("nor0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0"); /* environment */
protect_file("/dev/env0", 1);
break;
}
diff --git a/arch/arm/boards/pcm049/board.c b/arch/arm/boards/pcm049/board.c
index e4043edca1..5b7854a5e3 100644
--- a/arch/arm/boards/pcm049/board.c
+++ b/arch/arm/boards/pcm049/board.c
@@ -111,11 +111,11 @@ static int pcm049_devices_init(void)
OMAP_ECC_BCH8_CODE_HW, &omap4_nand_cfg);
#ifdef CONFIG_PARTITION
- devfs_add_partition("nand0", 0x00000, SZ_128K, PARTITION_FIXED, "xload_raw");
+ devfs_add_partition("nand0", 0x00000, SZ_128K, DEVFS_PARTITION_FIXED, "xload_raw");
dev_add_bb_dev("xload_raw", "xload");
- devfs_add_partition("nand0", SZ_128K, SZ_256K, PARTITION_FIXED, "self_raw");
+ devfs_add_partition("nand0", SZ_128K, SZ_256K, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
- devfs_add_partition("nand0", SZ_128K + SZ_256K, SZ_128K, PARTITION_FIXED, "env_raw");
+ devfs_add_partition("nand0", SZ_128K + SZ_256K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
#endif
diff --git a/arch/arm/boards/phycard-a-l1/pca-a-l1.c b/arch/arm/boards/phycard-a-l1/pca-a-l1.c
index c8e93641c4..1cc2815df9 100644
--- a/arch/arm/boards/phycard-a-l1/pca-a-l1.c
+++ b/arch/arm/boards/phycard-a-l1/pca-a-l1.c
@@ -336,13 +336,13 @@ static int pcaal1_late_init(void)
nand = get_device_by_name("nand0");
- devfs_add_partition("nand0", 0x00000, 0x80000, PARTITION_FIXED, "x-loader");
+ devfs_add_partition("nand0", 0x00000, 0x80000, DEVFS_PARTITION_FIXED, "x-loader");
dev_add_bb_dev("self_raw", "x_loader0");
- devfs_add_partition("nand0", 0x80000, 0x1e0000, PARTITION_FIXED, "self_raw");
+ devfs_add_partition("nand0", 0x80000, 0x1e0000, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
- devfs_add_partition("nand0", 0x260000, 0x20000, PARTITION_FIXED, "env_raw");
+ devfs_add_partition("nand0", 0x260000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
return 0;
diff --git a/arch/arm/boards/phycard-a-xl2/pca-a-xl2.c b/arch/arm/boards/phycard-a-xl2/pca-a-xl2.c
index 7358fe0606..128cb8fd28 100644
--- a/arch/arm/boards/phycard-a-xl2/pca-a-xl2.c
+++ b/arch/arm/boards/phycard-a-xl2/pca-a-xl2.c
@@ -129,13 +129,13 @@ static int pcaaxl2_devices_init(void)
#ifdef CONFIG_PARTITION
devfs_add_partition("nand0", 0x00000, SZ_128K,
- PARTITION_FIXED, "xload_raw");
+ DEVFS_PARTITION_FIXED, "xload_raw");
dev_add_bb_dev("xload_raw", "xload");
devfs_add_partition("nand0", SZ_128K, SZ_256K,
- PARTITION_FIXED, "self_raw");
+ DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", SZ_128K + SZ_256K, SZ_128K,
- PARTITION_FIXED, "env_raw");
+ DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
#endif
diff --git a/arch/arm/boards/phycard-i.MX27/lowlevel_init.S b/arch/arm/boards/phycard-i.MX27/lowlevel_init.S
index 9349581165..3ef2c543e6 100644
--- a/arch/arm/boards/phycard-i.MX27/lowlevel_init.S
+++ b/arch/arm/boards/phycard-i.MX27/lowlevel_init.S
@@ -111,7 +111,7 @@ board_init_lowlevel:
copy_loop:
ldmia r0!, {r3-r9} /* copy from source address [r0] */
stmia r1!, {r3-r9} /* copy to target address [r1] */
- cmp r0, r2 /* until source end addreee [r2] */
+ cmp r0, r2 /* until source end address [r2] */
ble copy_loop
ldr pc, =1f /* Jump to SDRAM */
diff --git a/arch/arm/boards/phycard-i.MX27/pca100.c b/arch/arm/boards/phycard-i.MX27/pca100.c
index a0a9911a88..6fdcf6ea62 100644
--- a/arch/arm/boards/phycard-i.MX27/pca100.c
+++ b/arch/arm/boards/phycard-i.MX27/pca100.c
@@ -303,10 +303,10 @@ static int pca100_devices_init(void)
#endif
nand = get_device_by_name("nand0");
- devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
+ devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
- devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
+ devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
armlinux_set_bootparams((void *)0xa0000100);
diff --git a/arch/arm/boards/pm9261/init.c b/arch/arm/boards/pm9261/init.c
index f7f2928c44..7f22f9bcda 100644
--- a/arch/arm/boards/pm9261/init.c
+++ b/arch/arm/boards/pm9261/init.c
@@ -140,8 +140,8 @@ static int pm9261_devices_init(void)
pm_add_device_dm9000();
add_cfi_flash_device(0, AT91_CHIPSELECT_0, 4 * 1024 * 1024, 0);
- devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self");
- devfs_add_partition("nor0", 0x40000, 0x10000, PARTITION_FIXED, "env0");
+ devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self");
+ devfs_add_partition("nor0", 0x40000, 0x10000, DEVFS_PARTITION_FIXED, "env0");
armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100));
armlinux_set_architecture(MACH_TYPE_PM9261);
diff --git a/arch/arm/boards/pm9263/init.c b/arch/arm/boards/pm9263/init.c
index 499ee466e4..28e1b1c5f6 100644
--- a/arch/arm/boards/pm9263/init.c
+++ b/arch/arm/boards/pm9263/init.c
@@ -111,8 +111,8 @@ static int pm9263_devices_init(void)
at91_add_device_eth(0, &macb_pdata);
add_cfi_flash_device(0, AT91_CHIPSELECT_0, 4 * 1024 * 1024, 0);
- devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
- devfs_add_partition("nor0", 0x40000, 0x10000, PARTITION_FIXED, "env0");
+ devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0");
+ devfs_add_partition("nor0", 0x40000, 0x10000, DEVFS_PARTITION_FIXED, "env0");
armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100));
armlinux_set_architecture(MACH_TYPE_PM9263);
diff --git a/arch/arm/boards/pm9g45/init.c b/arch/arm/boards/pm9g45/init.c
index 9b2227647a..6ef31b600a 100644
--- a/arch/arm/boards/pm9g45/init.c
+++ b/arch/arm/boards/pm9g45/init.c
@@ -141,9 +141,9 @@ static int pm9g45_devices_init(void)
at91_add_device_eth(0, &macb_pdata);
pm9g45_add_device_usbh();
- devfs_add_partition("nand0", 0x00000, 0x80000, PARTITION_FIXED, "self_raw");
+ devfs_add_partition("nand0", 0x00000, 0x80000, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
- devfs_add_partition("nand0", 0x40000, 0x40000, PARTITION_FIXED, "env_raw");
+ devfs_add_partition("nand0", 0x40000, 0x40000, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
armlinux_set_bootparams((void *)(AT91_CHIPSELECT_6 + 0x100));
diff --git a/arch/arm/boards/scb9328/scb9328.c b/arch/arm/boards/scb9328/scb9328.c
index 906a17e07e..9a342a8170 100644
--- a/arch/arm/boards/scb9328/scb9328.c
+++ b/arch/arm/boards/scb9328/scb9328.c
@@ -92,8 +92,8 @@ static int scb9328_devices_init(void)
add_dm9000_device(-1, 0x16000000, 0x16000004,
IORESOURCE_MEM_16BIT, &dm9000_data);
- devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
- devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
+ devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0");
+ devfs_add_partition("nor0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
armlinux_set_bootparams((void *)0x08000100);
diff --git a/arch/arm/boards/tny-a926x/init.c b/arch/arm/boards/tny-a926x/init.c
index eeaca7626f..2cb7da7cff 100644
--- a/arch/arm/boards/tny-a926x/init.c
+++ b/arch/arm/boards/tny-a926x/init.c
@@ -192,13 +192,13 @@ static int tny_a9260_devices_init(void)
at91_add_device_spi(0, &spi_pdata);
}
- devfs_add_partition("nand0", 0x00000, SZ_128K, PARTITION_FIXED, "at91bootstrap_raw");
+ devfs_add_partition("nand0", 0x00000, SZ_128K, DEVFS_PARTITION_FIXED, "at91bootstrap_raw");
dev_add_bb_dev("at91bootstrap_raw", "at91bootstrap");
- devfs_add_partition("nand0", SZ_128K, SZ_256K, PARTITION_FIXED, "self_raw");
+ devfs_add_partition("nand0", SZ_128K, SZ_256K, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
- devfs_add_partition("nand0", SZ_256K + SZ_128K, SZ_128K, PARTITION_FIXED, "env_raw");
+ devfs_add_partition("nand0", SZ_256K + SZ_128K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
- devfs_add_partition("nand0", SZ_512K, SZ_128K, PARTITION_FIXED, "env_raw1");
+ devfs_add_partition("nand0", SZ_512K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw1");
dev_add_bb_dev("env_raw1", "env1");
return 0;
diff --git a/arch/arm/boards/toshiba-ac100/Kconfig b/arch/arm/boards/toshiba-ac100/Kconfig
new file mode 100644
index 0000000000..abba2cc582
--- /dev/null
+++ b/arch/arm/boards/toshiba-ac100/Kconfig
@@ -0,0 +1,9 @@
+if MACH_TOSHIBA_AC100
+
+config ARCH_TEXT_BASE
+ hex
+ default 0x01000000
+
+config BOARDINFO
+ default "Toshiba AC100 (Tegra2)"
+endif
diff --git a/arch/arm/boards/toshiba-ac100/Makefile b/arch/arm/boards/toshiba-ac100/Makefile
new file mode 100644
index 0000000000..9e14763111
--- /dev/null
+++ b/arch/arm/boards/toshiba-ac100/Makefile
@@ -0,0 +1,2 @@
+obj-y += board.o
+obj-$(CONFIG_DRIVER_SERIAL_NS16550) += serial.o
diff --git a/arch/arm/boards/toshiba-ac100/board.c b/arch/arm/boards/toshiba-ac100/board.c
new file mode 100644
index 0000000000..b54f99fd57
--- /dev/null
+++ b/arch/arm/boards/toshiba-ac100/board.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2011 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <types.h>
+#include <driver.h>
+#include <init.h>
+#include <asm/armlinux.h>
+#include <sizes.h>
+#include <usb/ehci.h>
+#include <mach/iomap.h>
+
+static int ac100_mem_init(void)
+{
+ arm_add_mem_device("ram0", 0x0, SZ_512M);
+
+ return 0;
+}
+mem_initcall(ac100_mem_init);
+
+static struct ehci_platform_data ehci_pdata = {
+ .flags = EHCI_HAS_TT,
+};
+
+static int ac100_devices_init(void)
+{
+ add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, TEGRA_USB3_BASE,
+ &ehci_pdata);
+
+ return 0;
+}
+device_initcall(ac100_devices_init);
diff --git a/arch/arm/boards/toshiba-ac100/config.h b/arch/arm/boards/toshiba-ac100/config.h
new file mode 100644
index 0000000000..25bb18f787
--- /dev/null
+++ b/arch/arm/boards/toshiba-ac100/config.h
@@ -0,0 +1,5 @@
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#endif /* __CONFIG_H */
diff --git a/arch/arm/boards/toshiba-ac100/serial.c b/arch/arm/boards/toshiba-ac100/serial.c
new file mode 100644
index 0000000000..2ed0e3901c
--- /dev/null
+++ b/arch/arm/boards/toshiba-ac100/serial.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2011 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <types.h>
+#include <driver.h>
+#include <init.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <asm/common.h>
+#include <mach/iomap.h>
+
+static struct NS16550_plat serial_plat = {
+ .clock = 0x75 * 115200 * 16 /* MODE_X_DIV */,
+ .shift = 2,
+};
+
+static int ac100_serial_console_init(void)
+{
+ /* Register the serial port */
+ add_ns16550_device(-1, TEGRA_UARTA_BASE, 8 << serial_plat.shift,
+ IORESOURCE_MEM_8BIT, &serial_plat);
+
+ return 0;
+}
+console_initcall(ac100_serial_console_init);
diff --git a/arch/arm/boards/toshiba-ac100/toshiba-ac100.dox b/arch/arm/boards/toshiba-ac100/toshiba-ac100.dox
new file mode 100644
index 0000000000..7c50f3c1d9
--- /dev/null
+++ b/arch/arm/boards/toshiba-ac100/toshiba-ac100.dox
@@ -0,0 +1,37 @@
+/** @page toshiba-ac100 Toshiba AC100
+
+Toshiba AC100 is a Tegra2-based netbook.
+
+The netbook has
+@li NVidia Tegra 250 SoC;
+@li 512 MiB DDR2 RAM;
+@li 8 GiB internal e-MMC Flash Memory (some models have 32 GiB);
+@li RS232 serial interface (LV-TTL levels on the board!);
+@li SD card slot;
+@li 2xUSB interface (miniUSB-B and USB-A connectors);
+@li 10" LCD display (1024x600);
+@li HDMI-interface;
+@li touchpad and keyboard connected via I2C; the ENE KB926QF keyboard controller is used;
+@li web camera;
+@li some models have 3G-modem.
+
+U-Boot master branch is working on AC100, but there's no support for the keyboard or the display.
+
+barebox-toshiba-ac100 mini-howto:
+
+1. Connect to the netbook's UART (see http://pecourt.ovh.org/wiki-tegra/doku.php?id=hardware);
+
+2. Start U-Boot loader. See http://ac100.grandou.net/uboot and http://ac100.grandou.net/swarren_brain_dump for details.
+
+3. If you use U-Boot with turned on display support, then switch to serial console:
+@verbatim
+ Tegra2 (ac100) # setenv stdout serial
+@endverbatim
+
+4. Upload barebox.bin via Ymodem and start it:
+@verbatim
+ Tegra2 (ac100) # loady 0x01f00000
+ Tegra2 (ac100) # go 0x01f00000
+@endverbatim
+
+*/
diff --git a/arch/arm/boards/tqma53/board.c b/arch/arm/boards/tqma53/board.c
index 947c3f107a..8c3d855608 100644
--- a/arch/arm/boards/tqma53/board.c
+++ b/arch/arm/boards/tqma53/board.c
@@ -254,8 +254,8 @@ device_initcall(tqma53_devices_init);
static int tqma53_part_init(void)
{
- devfs_add_partition("disk0", 0x00000, SZ_1M, PARTITION_FIXED, "self0");
- devfs_add_partition("disk0", SZ_1M, SZ_1M, PARTITION_FIXED, "env0");
+ devfs_add_partition("disk0", 0x00000, SZ_1M, DEVFS_PARTITION_FIXED, "self0");
+ devfs_add_partition("disk0", SZ_1M, SZ_1M, DEVFS_PARTITION_FIXED, "env0");
return 0;
}
diff --git a/arch/arm/boards/usb-a926x/init.c b/arch/arm/boards/usb-a926x/init.c
index 57609b1818..824a38a94d 100644
--- a/arch/arm/boards/usb-a926x/init.c
+++ b/arch/arm/boards/usb-a926x/init.c
@@ -331,13 +331,13 @@ static int usb_a9260_devices_init(void)
armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100));
usb_a9260_set_board_type();
- devfs_add_partition("nand0", 0x00000, SZ_128K, PARTITION_FIXED, "at91bootstrap_raw");
+ devfs_add_partition("nand0", 0x00000, SZ_128K, DEVFS_PARTITION_FIXED, "at91bootstrap_raw");
dev_add_bb_dev("at91bootstrap_raw", "at91bootstrap");
- devfs_add_partition("nand0", SZ_128K, SZ_256K, PARTITION_FIXED, "self_raw");
+ devfs_add_partition("nand0", SZ_128K, SZ_256K, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
- devfs_add_partition("nand0", SZ_256K + SZ_128K, SZ_128K, PARTITION_FIXED, "env_raw");
+ devfs_add_partition("nand0", SZ_256K + SZ_128K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
- devfs_add_partition("nand0", SZ_512K, SZ_128K, PARTITION_FIXED, "env_raw1");
+ devfs_add_partition("nand0", SZ_512K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw1");
dev_add_bb_dev("env_raw1", "env1");
return 0;
diff --git a/arch/arm/boards/versatile/versatilepb.c b/arch/arm/boards/versatile/versatilepb.c
index 436f42177c..b95e605ab2 100644
--- a/arch/arm/boards/versatile/versatilepb.c
+++ b/arch/arm/boards/versatile/versatilepb.c
@@ -51,8 +51,8 @@ mem_initcall(vpb_mem_init);
static int vpb_devices_init(void)
{
add_cfi_flash_device(-1, VERSATILE_FLASH_BASE, VERSATILE_FLASH_SIZE, 0);
- devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self");
- devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
+ devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self");
+ devfs_add_partition("nor0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0");
add_generic_device("smc91c111", DEVICE_ID_DYNAMIC, NULL, VERSATILE_ETH_BASE,
64 * 1024, IORESOURCE_MEM, NULL);
diff --git a/arch/arm/configs/a9m2410_defconfig b/arch/arm/configs/a9m2410_defconfig
index 57e73c7f44..19550232a1 100644
--- a/arch/arm/configs/a9m2410_defconfig
+++ b/arch/arm/configs/a9m2410_defconfig
@@ -1,5 +1,5 @@
CONFIG_ARCH_S3C24xx=y
-CONFIG_S3C24XX_NAND_BOOT=y
+CONFIG_S3C_NAND_BOOT=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_BROKEN=y
CONFIG_EXPERIMENTAL=y
diff --git a/arch/arm/configs/a9m2440_defconfig b/arch/arm/configs/a9m2440_defconfig
index ae7f5238c3..ebdf64f864 100644
--- a/arch/arm/configs/a9m2440_defconfig
+++ b/arch/arm/configs/a9m2440_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARCH_S3C24xx=y
CONFIG_MACH_A9M2440=y
-CONFIG_S3C24XX_SDRAM_INIT=y
-CONFIG_S3C24XX_NAND_BOOT=y
+CONFIG_S3C_SDRAM_INIT=y
+CONFIG_S3C_NAND_BOOT=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_BROKEN=y
CONFIG_EXPERIMENTAL=y
diff --git a/arch/arm/configs/eukrea_cpuimx25_defconfig b/arch/arm/configs/eukrea_cpuimx25_defconfig
index 52fef5596d..94ae6700e3 100644
--- a/arch/arm/configs/eukrea_cpuimx25_defconfig
+++ b/arch/arm/configs/eukrea_cpuimx25_defconfig
@@ -5,7 +5,9 @@ CONFIG_IMX_IIM_FUSE_BLOW=y
CONFIG_AEABI=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
CONFIG_MALLOC_SIZE=0x800000
+CONFIG_EXPERIMENTAL=y
CONFIG_LONGHELP=y
CONFIG_GLOB=y
CONFIG_HUSH_FANCY_PROMPT=y
@@ -18,10 +20,10 @@ CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/eukrea_cpuimx25/env"
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_LOADENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
+CONFIG_CMD_AUTOMOUNT=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_LOADB=y
CONFIG_CMD_MEMINFO=y
@@ -29,7 +31,10 @@ CONFIG_CMD_IOMEM=y
CONFIG_CMD_MTEST=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
-CONFIG_CMD_IMINFO=y
+CONFIG_CMD_BOOTM_VERBOSE=y
+CONFIG_CMD_BOOTM_INITRD=y
+CONFIG_CMD_BOOTM_OFTREE=y
+CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_OFTREE=y
@@ -45,19 +50,25 @@ CONFIG_CMD_LED=y
CONFIG_CMD_LED_TRIGGER=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
+CONFIG_NET_NFS=y
CONFIG_NET_PING=y
CONFIG_NET_TFTP=y
CONFIG_NET_TFTP_PUSH=y
+CONFIG_NET_NETCONSOLE=y
CONFIG_DRIVER_NET_FEC_IMX=y
# CONFIG_SPI is not set
CONFIG_I2C=y
CONFIG_I2C_IMX=y
CONFIG_MTD=y
+CONFIG_MTD_RAW_DEVICE=y
CONFIG_NAND=y
CONFIG_NAND_IMX=y
CONFIG_USB=y
CONFIG_USB_EHCI=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DFU=y
+CONFIG_USB_GADGET_SERIAL=y
CONFIG_VIDEO=y
CONFIG_DRIVER_VIDEO_IMX=y
CONFIG_MCI=y
@@ -65,9 +76,7 @@ CONFIG_MCI_IMX_ESDHC=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_LED_TRIGGERS=y
-CONFIG_FS_CRAMFS=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_WRITE=y
CONFIG_FS_FAT_LFN=y
-CONFIG_BZLIB=y
CONFIG_LZO_DECOMPRESS=y
diff --git a/arch/arm/configs/eukrea_cpuimx35_defconfig b/arch/arm/configs/eukrea_cpuimx35_defconfig
index b741b4f74c..a888765d99 100644
--- a/arch/arm/configs/eukrea_cpuimx35_defconfig
+++ b/arch/arm/configs/eukrea_cpuimx35_defconfig
@@ -6,7 +6,9 @@ CONFIG_IMX_IIM_FUSE_BLOW=y
CONFIG_AEABI=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
CONFIG_MALLOC_SIZE=0x800000
+CONFIG_EXPERIMENTAL=y
CONFIG_LONGHELP=y
CONFIG_GLOB=y
CONFIG_HUSH_FANCY_PROMPT=y
@@ -19,10 +21,10 @@ CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/eukrea_cpuimx35/env"
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_LOADENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
+CONFIG_CMD_AUTOMOUNT=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_LOADB=y
CONFIG_CMD_MEMINFO=y
@@ -30,7 +32,10 @@ CONFIG_CMD_IOMEM=y
CONFIG_CMD_MTEST=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
-CONFIG_CMD_IMINFO=y
+CONFIG_CMD_BOOTM_VERBOSE=y
+CONFIG_CMD_BOOTM_INITRD=y
+CONFIG_CMD_BOOTM_OFTREE=y
+CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_OFTREE=y
@@ -42,21 +47,29 @@ CONFIG_CMD_BMP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_CMD_I2C=y
+CONFIG_CMD_LED=y
+CONFIG_CMD_LED_TRIGGER=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
+CONFIG_NET_NFS=y
CONFIG_NET_PING=y
CONFIG_NET_TFTP=y
CONFIG_NET_TFTP_PUSH=y
+CONFIG_NET_NETCONSOLE=y
CONFIG_DRIVER_NET_FEC_IMX=y
# CONFIG_SPI is not set
CONFIG_I2C=y
CONFIG_I2C_IMX=y
CONFIG_MTD=y
+CONFIG_MTD_RAW_DEVICE=y
CONFIG_NAND=y
CONFIG_NAND_IMX=y
CONFIG_USB=y
CONFIG_USB_EHCI=y
CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DFU=y
+CONFIG_USB_GADGET_SERIAL=y
CONFIG_VIDEO=y
CONFIG_DRIVER_VIDEO_IMX_IPU=y
CONFIG_MCI=y
@@ -64,9 +77,7 @@ CONFIG_MCI_IMX_ESDHC=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_LED_TRIGGERS=y
-CONFIG_FS_CRAMFS=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_WRITE=y
CONFIG_FS_FAT_LFN=y
-CONFIG_BZLIB=y
CONFIG_LZO_DECOMPRESS=y
diff --git a/arch/arm/configs/eukrea_cpuimx51_defconfig b/arch/arm/configs/eukrea_cpuimx51_defconfig
index 76119cf5a5..f6fd7bcb37 100644
--- a/arch/arm/configs/eukrea_cpuimx51_defconfig
+++ b/arch/arm/configs/eukrea_cpuimx51_defconfig
@@ -4,7 +4,9 @@ CONFIG_MACH_EUKREA_CPUIMX51SD=y
CONFIG_AEABI=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_MMU=y
+CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
CONFIG_MALLOC_SIZE=0x2000000
+CONFIG_EXPERIMENTAL=y
CONFIG_LONGHELP=y
CONFIG_GLOB=y
CONFIG_HUSH_FANCY_PROMPT=y
@@ -15,7 +17,6 @@ CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/eukrea_cpuimx51/env"
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_LOADENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
@@ -23,10 +24,14 @@ CONFIG_CMD_ECHO_E=y
CONFIG_CMD_LOADB=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_IOMEM=y
+CONFIG_CMD_MD5SUM=y
CONFIG_CMD_MTEST=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
-CONFIG_CMD_IMINFO=y
+CONFIG_CMD_BOOTM_VERBOSE=y
+CONFIG_CMD_BOOTM_INITRD=y
+CONFIG_CMD_BOOTM_OFTREE=y
+CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_OFTREE=y
@@ -36,10 +41,17 @@ CONFIG_CMD_MAGICVAR=y
CONFIG_CMD_MAGICVAR_HELP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNCOMPRESS=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_LED=y
+CONFIG_CMD_LED_TRIGGER=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
+CONFIG_NET_NFS=y
CONFIG_NET_PING=y
CONFIG_NET_TFTP=y
+CONFIG_NET_TFTP_PUSH=y
+CONFIG_NET_NETCONSOLE=y
+CONFIG_NET_RESOLV=y
CONFIG_DRIVER_NET_FEC_IMX=y
# CONFIG_SPI is not set
CONFIG_I2C=y
@@ -53,9 +65,8 @@ CONFIG_MCI_IMX_ESDHC=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_LED_TRIGGERS=y
+CONFIG_FS_TFTP=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_WRITE=y
CONFIG_FS_FAT_LFN=y
-CONFIG_ZLIB=y
-CONFIG_BZLIB=y
CONFIG_LZO_DECOMPRESS=y
diff --git a/arch/arm/configs/freescale_mx51_babbage_defconfig b/arch/arm/configs/freescale_mx51_babbage_defconfig
index c4f7aeff78..22ef163a4b 100644
--- a/arch/arm/configs/freescale_mx51_babbage_defconfig
+++ b/arch/arm/configs/freescale_mx51_babbage_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_IMX51=y
CONFIG_IMX_IIM=y
CONFIG_IMX_IIM_FUSE_BLOW=y
CONFIG_AEABI=y
+CONFIG_THUMB2_BAREBOX=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ARM_UNWIND=y
CONFIG_MMU=y
@@ -11,23 +12,26 @@ CONFIG_MALLOC_SIZE=0x2000000
CONFIG_MALLOC_TLSF=y
CONFIG_KALLSYMS=y
CONFIG_LONGHELP=y
-CONFIG_GLOB=y
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
-CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
+CONFIG_MENU=y
+CONFIG_DEFAULT_ENVIRONMENT_COMPRESSED_LZO=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/freescale-mx51-pdk/env/"
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_LOADENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
+CONFIG_CMD_MENU=y
+CONFIG_CMD_MENU_MANAGEMENT=y
CONFIG_CMD_TIME=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_IOMEM=y
+CONFIG_CMD_CRC=y
+CONFIG_CMD_CRC_CMP=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
CONFIG_CMD_BOOTM_VERBOSE=y
@@ -47,10 +51,8 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
-CONFIG_NET_NFS=y
CONFIG_NET_PING=y
-CONFIG_NET_TFTP=y
-CONFIG_NET_TFTP_PUSH=y
+CONFIG_NET_RESOLV=y
CONFIG_DRIVER_NET_FEC_IMX=y
CONFIG_DRIVER_SPI_IMX=y
CONFIG_DRIVER_CFI=y
@@ -59,6 +61,8 @@ CONFIG_MCI=y
CONFIG_MCI_STARTUP=y
CONFIG_MCI_IMX_ESDHC=y
CONFIG_MFD_MC13XXX=y
+CONFIG_FS_TFTP=y
+CONFIG_FS_NFS=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_WRITE=y
CONFIG_FS_FAT_LFN=y
diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig
index 9b35dd5f65..efe76e42dd 100644
--- a/arch/arm/configs/mini2440_defconfig
+++ b/arch/arm/configs/mini2440_defconfig
@@ -1,7 +1,7 @@
CONFIG_ARCH_S3C24xx=y
CONFIG_MACH_MINI2440=y
CONFIG_MINI2440_VIDEO_N35=y
-CONFIG_S3C24XX_NAND_BOOT=y
+CONFIG_S3C_NAND_BOOT=y
CONFIG_AEABI=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_TEXT_BASE=0x33e00000
diff --git a/arch/arm/configs/panda_defconfig b/arch/arm/configs/panda_defconfig
index 68cc11eb2f..0b2d42334b 100644
--- a/arch/arm/configs/panda_defconfig
+++ b/arch/arm/configs/panda_defconfig
@@ -19,7 +19,6 @@ CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/panda/env"
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_LOADENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
@@ -43,6 +42,8 @@ CONFIG_CMD_MAGICVAR=y
CONFIG_CMD_MAGICVAR_HELP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNCOMPRESS=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_LED=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_NFS=y
@@ -54,11 +55,16 @@ CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
CONFIG_NET_USB=y
CONFIG_NET_USB_SMSC95XX=y
# CONFIG_SPI is not set
+CONFIG_I2C=y
+CONFIG_I2C_OMAP=y
CONFIG_USB=y
CONFIG_USB_EHCI=y
CONFIG_MCI=y
CONFIG_MCI_STARTUP=y
CONFIG_MCI_OMAP_HSMMC=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_LED_TRIGGERS=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_WRITE=y
CONFIG_FS_FAT_LFN=y
diff --git a/arch/arm/configs/pcm038_defconfig b/arch/arm/configs/pcm038_defconfig
index 4cb83e5059..5ce4f7abcc 100644
--- a/arch/arm/configs/pcm038_defconfig
+++ b/arch/arm/configs/pcm038_defconfig
@@ -12,21 +12,22 @@ CONFIG_MALLOC_SIZE=0x1000000
CONFIG_MALLOC_TLSF=y
CONFIG_KALLSYMS=y
CONFIG_LONGHELP=y
-CONFIG_GLOB=y
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
+CONFIG_MENU=y
CONFIG_PARTITION=y
CONFIG_PARTITION_DISK=y
-CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/pcm038/env"
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_LOADENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
+CONFIG_CMD_MENU=y
+CONFIG_CMD_MENU_MANAGEMENT=y
CONFIG_CMD_TIME=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_MEMINFO=y
@@ -54,9 +55,8 @@ CONFIG_CMD_UNCOMPRESS=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_PING=y
-CONFIG_NET_TFTP=y
-CONFIG_NET_TFTP_PUSH=y
CONFIG_NET_NETCONSOLE=y
+CONFIG_NET_RESOLV=y
CONFIG_DRIVER_NET_FEC_IMX=y
CONFIG_NET_USB=y
CONFIG_NET_USB_ASIX=y
@@ -67,13 +67,13 @@ CONFIG_NAND=y
# CONFIG_NAND_ECC_SOFT is not set
# CONFIG_NAND_ECC_HW_SYNDROME is not set
CONFIG_NAND_IMX=y
-CONFIG_UBI=y
CONFIG_USB=y
CONFIG_USB_EHCI=y
CONFIG_USB_ULPI=y
CONFIG_VIDEO=y
CONFIG_DRIVER_VIDEO_IMX=y
CONFIG_IMXFB_DRIVER_VIDEO_IMX_OVERLAY=y
+CONFIG_FS_TFTP=y
+CONFIG_FS_NFS=y
CONFIG_ZLIB=y
CONFIG_LZO_DECOMPRESS=y
-CONFIG_MFD_MC13XXX=y
diff --git a/arch/arm/configs/toshiba_ac100_defconfig b/arch/arm/configs/toshiba_ac100_defconfig
new file mode 100644
index 0000000000..053f53a457
--- /dev/null
+++ b/arch/arm/configs/toshiba_ac100_defconfig
@@ -0,0 +1,39 @@
+CONFIG_ARCH_TEGRA=y
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_TEXT_BASE=0x01000000
+CONFIG_BROKEN=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_PROMPT="toshiba ac100> "
+CONFIG_LONGHELP=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+# CONFIG_ERRNO_MESSAGES is not set
+# CONFIG_DEFAULT_ENVIRONMENT is not set
+CONFIG_POLLER=y
+CONFIG_ENABLE_DEVICE_NOISE=y
+CONFIG_CMD_SLEEP=y
+# CONFIG_CMD_TRUE is not set
+# CONFIG_CMD_FALSE is not set
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_LOADY=y
+CONFIG_CMD_LOADS=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_CMD_BOOTM_SHOW_TYPE=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_GO=y
+CONFIG_NET=y
+CONFIG_NET_DHCP=y
+CONFIG_NET_PING=y
+CONFIG_NET_TFTP=y
+CONFIG_NET_TFTP_PUSH=y
+CONFIG_NET_NETCONSOLE=y
+CONFIG_DRIVER_SERIAL_NS16550=y
+CONFIG_NET_USB=y
+CONFIG_NET_USB_ASIX=y
+# CONFIG_SPI is not set
+CONFIG_USB=y
+CONFIG_USB_EHCI=y
+CONFIG_USB_STORAGE=y
+CONFIG_FS_FAT=y
diff --git a/arch/arm/cpu/cache-armv4.S b/arch/arm/cpu/cache-armv4.S
index fc53653c34..6d03565c58 100644
--- a/arch/arm/cpu/cache-armv4.S
+++ b/arch/arm/cpu/cache-armv4.S
@@ -42,7 +42,6 @@ ENTRY(__mmu_cache_off)
mov pc, lr
ENDPROC(__mmu_cache_off)
-__BARE_INIT
ENTRY(__mmu_cache_flush)
mrc p15, 0, r6, c0, c0 @ get processor ID
mov r2, #64*1024 @ default: 32K dcache size (*2)
diff --git a/arch/arm/cpu/cache-armv5.S b/arch/arm/cpu/cache-armv5.S
index d870e6b80f..a1193a6a66 100644
--- a/arch/arm/cpu/cache-armv5.S
+++ b/arch/arm/cpu/cache-armv5.S
@@ -42,7 +42,6 @@ ENTRY(__mmu_cache_off)
mov pc, lr
ENDPROC(__mmu_cache_off)
-__BARE_INIT
ENTRY(__mmu_cache_flush)
1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
bne 1b
diff --git a/arch/arm/cpu/cache-armv6.S b/arch/arm/cpu/cache-armv6.S
index 9de76da452..335bac2a45 100644
--- a/arch/arm/cpu/cache-armv6.S
+++ b/arch/arm/cpu/cache-armv6.S
@@ -44,7 +44,6 @@ ENTRY(__mmu_cache_off)
#endif
mov pc, lr
-__BARE_INIT
ENTRY(__mmu_cache_flush)
mov r1, #0
mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
diff --git a/arch/arm/cpu/cache-armv7.S b/arch/arm/cpu/cache-armv7.S
index 416498d329..28a6315522 100644
--- a/arch/arm/cpu/cache-armv7.S
+++ b/arch/arm/cpu/cache-armv7.S
@@ -50,7 +50,6 @@ ENTRY(__mmu_cache_off)
mov pc, r12
ENDPROC(__mmu_cache_off)
-__BARE_INIT
ENTRY(__mmu_cache_flush)
mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c
index ede8fd1f09..3c282ee791 100644
--- a/arch/arm/cpu/start.c
+++ b/arch/arm/cpu/start.c
@@ -75,12 +75,6 @@ void __naked __bare_init reset(void)
#ifdef CONFIG_ARCH_HAS_LOWLEVEL_INIT
arch_init_lowlevel();
#endif
- __asm__ __volatile__ (
- "bl __mmu_cache_flush;"
- :
- :
- : "r0", "r1", "r2", "r3", "r6", "r10", "r12", "lr", "cc", "memory"
- );
/* disable MMU stuff and caches */
r = get_cr();
@@ -108,7 +102,7 @@ void __naked __bare_init reset(void)
/*
* Board code can jump here by either returning from board_init_lowlevel
- * or by calling this funtion directly.
+ * or by calling this function directly.
*/
void __naked __section(.text_ll_return) board_init_lowlevel_return(void)
{
@@ -135,6 +129,9 @@ void __naked __section(.text_ll_return) board_init_lowlevel_return(void)
/* clear bss */
memset(__bss_start, 0, __bss_stop - __bss_start);
+ /* flush I-cache before jumping to the copied binary */
+ __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
+
/* call start_barebox with its absolute address */
r = (unsigned int)&start_barebox;
__asm__ __volatile__("mov pc, %0" : : "r"(r));
diff --git a/arch/arm/include/asm/barebox-arm-head.h b/arch/arm/include/asm/barebox-arm-head.h
index 0dc3074a27..2c250e948e 100644
--- a/arch/arm/include/asm/barebox-arm-head.h
+++ b/arch/arm/include/asm/barebox-arm-head.h
@@ -24,8 +24,7 @@ static inline void barebox_arm_head(void)
"1: b 1b\n"
"1: b 1b\n"
#endif
- ".word 0x65726162\n" /* 'bare' */
- ".word 0x00786f62\n" /* 'box' */
+ ".asciz \"barebox\"\n"
".word _text\n" /* text base. If copied there,
* barebox can skip relocation
*/
diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h
index 89df4dc708..6ce35fb8d3 100644
--- a/arch/arm/include/asm/setup.h
+++ b/arch/arm/include/asm/setup.h
@@ -1,6 +1,4 @@
/*
- * linux/include/asm/setup.h
- *
* Copyright (C) 1997-1999 Russell King
*
* This program is free software; you can redistribute it and/or modify
@@ -10,13 +8,6 @@
* Structure passed to kernel to tell it about the
* hardware it's running on. See linux/Documentation/arm/Setup
* for more info.
- *
- * NOTE:
- * This file contains two ways to pass information from the boot
- * loader to the kernel. The old struct param_struct is deprecated,
- * but it will be kept in the kernel for 5 years from now
- * (2001). This will allow boot loaders to convert to the new struct
- * tag way.
*/
#ifndef __ASMARM_SETUP_H
#define __ASMARM_SETUP_H
@@ -32,50 +23,6 @@
*/
#define COMMAND_LINE_SIZE 1024
-/* This is the old deprecated way to pass parameters to the kernel */
-struct param_struct {
- union {
- struct {
- unsigned long page_size; /* 0 */
- unsigned long nr_pages; /* 4 */
- unsigned long ramdisk_size; /* 8 */
- unsigned long flags; /* 12 */
-#define FLAG_READONLY 1
-#define FLAG_RDLOAD 4
-#define FLAG_RDPROMPT 8
- unsigned long rootdev; /* 16 */
- unsigned long video_num_cols; /* 20 */
- unsigned long video_num_rows; /* 24 */
- unsigned long video_x; /* 28 */
- unsigned long video_y; /* 32 */
- unsigned long memc_control_reg; /* 36 */
- unsigned char sounddefault; /* 40 */
- unsigned char adfsdrives; /* 41 */
- unsigned char bytes_per_char_h; /* 42 */
- unsigned char bytes_per_char_v; /* 43 */
- unsigned long pages_in_bank[4]; /* 44 */
- unsigned long pages_in_vram; /* 60 */
- unsigned long initrd_start; /* 64 */
- unsigned long initrd_size; /* 68 */
- unsigned long rd_start; /* 72 */
- unsigned long system_rev; /* 76 */
- unsigned long system_serial_low; /* 80 */
- unsigned long system_serial_high; /* 84 */
- unsigned long mem_fclk_21285; /* 88 */
- } s;
- char unused[256];
- } u1;
- union {
- char paths[8][128];
- struct {
- unsigned long magic;
- char n[1024 - sizeof(unsigned long)];
- } s;
- } u2;
- char commandline[COMMAND_LINE_SIZE];
-};
-
-
/*
* The new way of passing information: a list of tagged entries
*/
diff --git a/arch/arm/lib/armlinux.c b/arch/arm/lib/armlinux.c
index a167036db5..9f9dea8754 100644
--- a/arch/arm/lib/armlinux.c
+++ b/arch/arm/lib/armlinux.c
@@ -227,7 +227,7 @@ static void setup_end_tag (void)
static void setup_tags(unsigned long initrd_address,
unsigned long initrd_size, int swap)
{
- const char *commandline = getenv("bootargs");
+ const char *commandline = linux_bootargs_get();
setup_start_tag();
setup_memory_tags();
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index c4a50c301c..033e2eb15b 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -394,7 +394,7 @@ static int do_bootm_aimage(struct image_data *data)
}
if (!getenv("aimage_noverwrite_bootargs"))
- setenv("bootargs", header->cmdline);
+ linux_bootargs_overwrite(header->cmdline);
if (!getenv("aimage_noverwrite_tags"))
armlinux_set_bootparams((void*)header->tags_addr);
@@ -432,6 +432,7 @@ static int do_bootm_aimage(struct image_data *data)
return __do_bootm_linux(data, 0);
err_out:
+ linux_bootargs_overwrite(NULL);
close(fd);
return ret;
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 32367627d4..564e2fe92d 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -290,10 +290,19 @@ config MACH_PCM038
select SPI
select DRIVER_SPI_IMX
select MFD_MC13XXX
+ select HAVE_DEFAULT_ENVIRONMENT_NEW
help
Say Y here if you are using Phytec's phyCORE-i.MX27 (pcm038) equipped
with a Freescale i.MX27 Processor
+config MACH_PCM970_BASEBOARD
+ bool "PHYTEC PCM970 development board"
+ depends on MACH_PCM038
+ default y
+ help
+ This adds board specific devices that can be found on Phytec's
+ PCM970 evaluation board.
+
config MACH_NESO
bool "Garz+Fricke Neso"
select MACH_HAS_LOWLEVEL_INIT
@@ -382,6 +391,7 @@ choice
prompt "i.MX51 Board Type"
config MACH_FREESCALE_MX51_PDK
+ select DEFAULT_ENVIRONMENT_GENERIC_NEW
bool "Freescale i.MX51 PDK"
config MACH_EUKREA_CPUIMX51SD
diff --git a/arch/arm/mach-imx/imx51.c b/arch/arm/mach-imx/imx51.c
index 25cc6dae5d..53205a9215 100644
--- a/arch/arm/mach-imx/imx51.c
+++ b/arch/arm/mach-imx/imx51.c
@@ -269,7 +269,7 @@ void imx51_init_lowlevel(unsigned int cpufreq_mhz)
writel(0xffffffff, ccm + MX5_CCM_CCGR6);
/* Use PLL 2 for UART's, get 66.5MHz from it */
- writel(0xA5A2A020, ccm + MX5_CCM_CSCMR1);
+ writel(0xA591A020, ccm + MX5_CCM_CSCMR1);
writel(0x00C30321, ccm + MX5_CCM_CSCDR1);
/* make sure divider effective */
diff --git a/arch/arm/mach-imx/include/mach/devices-imx51.h b/arch/arm/mach-imx/include/mach/devices-imx51.h
index 9ad6476aa0..5de0fa776c 100644
--- a/arch/arm/mach-imx/include/mach/devices-imx51.h
+++ b/arch/arm/mach-imx/include/mach/devices-imx51.h
@@ -4,17 +4,17 @@
static inline struct device_d *imx51_add_spi0(struct spi_imx_master *pdata)
{
- return imx_add_spi((void *)MX51_CSPI1_BASE_ADDR, 0, pdata);
+ return imx_add_spi((void *)MX51_ECSPI1_BASE_ADDR, 0, pdata);
}
static inline struct device_d *imx51_add_spi1(struct spi_imx_master *pdata)
{
- return imx_add_spi((void *)MX51_CSPI2_BASE_ADDR, 1, pdata);
+ return imx_add_spi((void *)MX51_ECSPI2_BASE_ADDR, 1, pdata);
}
-static inline struct device_d *imx51_add_spi2(struct spi_imx_master *pdata)
+static inline struct device_d *imx51_add_cspi(struct spi_imx_master *pdata)
{
- return imx_add_spi((void *)MX51_CSPI3_BASE_ADDR, 2, pdata);
+ return imx_add_spi((void *)MX51_CSPI_BASE_ADDR, 2, pdata);
}
static inline struct device_d *imx51_add_i2c0(struct i2c_platform_data *pdata)
@@ -57,6 +57,11 @@ static inline struct device_d *imx51_add_mmc1(struct esdhc_platform_data *pdata)
return imx_add_esdhc((void *)MX51_MMC_SDHC2_BASE_ADDR, 1, pdata);
}
+static inline struct device_d *imx51_add_mmc2(struct esdhc_platform_data *pdata)
+{
+ return imx_add_esdhc((void *)MX51_MMC_SDHC3_BASE_ADDR, 2, pdata);
+}
+
static inline struct device_d *imx51_add_nand(struct imx_nand_platform_data *pdata)
{
struct resource res[] = {
diff --git a/arch/arm/mach-imx/include/mach/imx27-regs.h b/arch/arm/mach-imx/include/mach/imx27-regs.h
index 437cc7d302..19dcad9e9b 100644
--- a/arch/arm/mach-imx/include/mach/imx27-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx27-regs.h
@@ -41,6 +41,17 @@
#define IMX_NFC_BASE (0xd8000000)
#define IMX_ESD_BASE (0xd8001000)
#define IMX_WEIM_BASE (0xd8002000)
+#define IMX_M3IF_BASE (0xd8003000)
+#define IMX_PCMCIA_CTL_BASE (0xd8004000)
+
+#define PCMCIA_PIPR (IMX_PCMCIA_CTL_BASE + 0x00)
+#define PCMCIA_PSCR (IMX_PCMCIA_CTL_BASE + 0x04)
+#define PCMCIA_PER (IMX_PCMCIA_CTL_BASE + 0x08)
+#define PCMCIA_PBR(x) (IMX_PCMCIA_CTL_BASE + 0x0c + ((x) << 2))
+#define PCMCIA_POR(x) (IMX_PCMCIA_CTL_BASE + 0x28 + ((x) << 2))
+#define PCMCIA_POFR(x) (IMX_PCMCIA_CTL_BASE + 0x44 + ((x) << 2))
+#define PCMCIA_PGCR (IMX_PCMCIA_CTL_BASE + 0x60)
+#define PCMCIA_PGSR (IMX_PCMCIA_CTL_BASE + 0x64)
/* AIPI */
#define AIPI1_PSR0 __REG(IMX_AIPI1_BASE + 0x00)
@@ -240,6 +251,8 @@
#define IMX_CS4_BASE 0xD4000000
#define IMX_CS5_BASE 0xD6000000
+#define IMX_PCMCIA_MEM_BASE (0xdc000000)
+
#ifndef __ASSEMBLY__
static inline void imx27_setup_weimcs(size_t cs, unsigned upper, unsigned lower, unsigned addional)
{
diff --git a/arch/arm/mach-imx/include/mach/imx51-regs.h b/arch/arm/mach-imx/include/mach/imx51-regs.h
index 3eb0a1f894..b51aa67c6f 100644
--- a/arch/arm/mach-imx/include/mach/imx51-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx51-regs.h
@@ -76,12 +76,12 @@
#define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A0000)
#define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A4000)
#define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A8000)
-#define MX51_CSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000AC000)
+#define MX51_ECSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000AC000)
#define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B0000)
#define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B4000)
#define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B8000)
#define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000BC000)
-#define MX51_CSPI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C0000)
+#define MX51_CSPI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C0000)
#define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C4000)
#define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C8000)
#define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000CC000)
@@ -104,7 +104,7 @@
#define MX51_MMC_SDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00004000)
#define MX51_MMC_SDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00008000)
#define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0000C000)
-#define MX51_CSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00010000)
+#define MX51_ECSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00010000)
#define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00014000)
#define MX51_MMC_SDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00020000)
#define MX51_MMC_SDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00024000)
diff --git a/arch/arm/mach-imx/speed-imx51.c b/arch/arm/mach-imx/speed-imx51.c
index 5a845a64f5..8d1ecf3e40 100644
--- a/arch/arm/mach-imx/speed-imx51.c
+++ b/arch/arm/mach-imx/speed-imx51.c
@@ -24,6 +24,14 @@ static unsigned long fpm_get_rate(void)
return ckil_get_rate() * 512;
}
+static unsigned long lp_apm_get_rate(void)
+{
+ if (ccm_readl(MX5_CCM_CCSR) & MX5_CCM_CCSR_LP_APM_SEL)
+ return fpm_get_rate();
+ else
+ return osc_get_rate();
+}
+
static unsigned long pll_get_rate(void __iomem *pllbase)
{
long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
@@ -123,7 +131,7 @@ unsigned long imx_get_uartclk(void)
pll1_main_get_rate,
pll2_sw_get_rate,
pll3_sw_get_rate,
- NULL);
+ lp_apm_get_rate);
reg = ccm_readl(MX5_CCM_CSCDR1);
prediv = ((reg & MX5_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
@@ -180,7 +188,7 @@ unsigned long imx_get_mmcclk(void)
pll1_main_get_rate,
pll2_sw_get_rate,
pll3_sw_get_rate,
- NULL);
+ lp_apm_get_rate);
reg = ccm_readl(MX5_CCM_CSCDR1);
prediv = ((reg & MX5_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK) >>
@@ -191,13 +199,37 @@ unsigned long imx_get_mmcclk(void)
return rate / (prediv * podf);
}
+unsigned long imx_get_usbclk(void)
+{
+ u32 reg, prediv, podf, rate;
+
+ reg = ccm_readl(MX5_CCM_CSCMR1);
+ reg &= MX5_CCM_CSCMR1_USBOH3_CLK_SEL_MASK;
+ reg >>= MX5_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET;
+ rate = get_rate_select(reg,
+ pll1_main_get_rate,
+ pll2_sw_get_rate,
+ pll3_sw_get_rate,
+ lp_apm_get_rate);
+
+ reg = ccm_readl(MX5_CCM_CSCDR1);
+ prediv = ((reg & MX5_CCM_CSCDR1_USBOH3_CLK_PRED_MASK) >>
+ MX5_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET) + 1;
+ podf = ((reg & MX5_CCM_CSCDR1_USBOH3_CLK_PODF_MASK) >>
+ MX5_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET) + 1;
+
+ return rate / (prediv * podf);
+}
+
void imx_dump_clocks(void)
{
- printf("pll1: %ld\n", pll1_main_get_rate());
- printf("pll2: %ld\n", pll2_sw_get_rate());
- printf("pll3: %ld\n", pll3_sw_get_rate());
- printf("uart: %ld\n", imx_get_uartclk());
- printf("ipg: %ld\n", imx_get_ipgclk());
- printf("fec: %ld\n", imx_get_fecclk());
- printf("gpt: %ld\n", imx_get_gptclk());
+ printf("pll1: %ld\n", pll1_main_get_rate());
+ printf("pll2: %ld\n", pll2_sw_get_rate());
+ printf("pll3: %ld\n", pll3_sw_get_rate());
+ printf("lp_apm: %ld\n", lp_apm_get_rate());
+ printf("uart: %ld\n", imx_get_uartclk());
+ printf("ipg: %ld\n", imx_get_ipgclk());
+ printf("fec: %ld\n", imx_get_fecclk());
+ printf("gpt: %ld\n", imx_get_gptclk());
+ printf("usb: %ld\n", imx_get_usbclk());
}
diff --git a/arch/arm/mach-omap/devices-gpmc-nand.c b/arch/arm/mach-omap/devices-gpmc-nand.c
index 0fc32f1d07..cf87b57d7f 100644
--- a/arch/arm/mach-omap/devices-gpmc-nand.c
+++ b/arch/arm/mach-omap/devices-gpmc-nand.c
@@ -49,7 +49,7 @@ static struct gpmc_nand_platform_data nand_plat = {
/**
* @brief gpmc_generic_nand_devices_init - init generic nand device
*
- * @return success/fail based on device funtion
+ * @return success/fail based on device function
*/
int gpmc_generic_nand_devices_init(int cs, int width,
enum gpmc_ecc_mode eccmode, struct gpmc_config *nand_cfg)
diff --git a/arch/arm/mach-omap/xload.c b/arch/arm/mach-omap/xload.c
index 59f75e237a..13024abac7 100644
--- a/arch/arm/mach-omap/xload.c
+++ b/arch/arm/mach-omap/xload.c
@@ -14,7 +14,7 @@ void *omap_xload_boot_nand(int offset, int size)
void *to = xmalloc(size);
struct cdev *cdev;
- devfs_add_partition("nand0", offset, size, PARTITION_FIXED, "x");
+ devfs_add_partition("nand0", offset, size, DEVFS_PARTITION_FIXED, "x");
dev_add_bb_dev("x", "bbx");
cdev = cdev_open("bbx", O_RDONLY);
diff --git a/arch/arm/mach-samsung/Kconfig b/arch/arm/mach-samsung/Kconfig
index bc283dc947..c60f5ed272 100644
--- a/arch/arm/mach-samsung/Kconfig
+++ b/arch/arm/mach-samsung/Kconfig
@@ -14,6 +14,10 @@ config BOARDINFO
default "Digi A9M2440" if MACH_A9M2440
default "Digi A9M2410" if MACH_A9M2410
+config ARCH_BAREBOX_MAX_BARE_INIT_SIZE
+ hex
+ default 0x1ff0 if ARCH_S5PCxx
+
if ARCH_S3C24xx
config CPU_S3C2410
@@ -30,8 +34,8 @@ config MACH_A9M2410
bool "Digi A9M2410"
select CPU_S3C2410
select MACH_HAS_LOWLEVEL_INIT
- select S3C24XX_PLL_INIT
- select S3C24XX_SDRAM_INIT
+ select S3C_PLL_INIT
+ select S3C_SDRAM_INIT
help
Say Y here if you are using Digi's Connect Core 9M equipped
with a Samsung S3C2410 Processor
@@ -40,7 +44,7 @@ config MACH_A9M2440
bool "Digi A9M2440"
select CPU_S3C2440
select MACH_HAS_LOWLEVEL_INIT
- select S3C24XX_PLL_INIT
+ select S3C_PLL_INIT
help
Say Y here if you are using Digi's Connect Core 9M equipped
with a Samsung S3C2440 Processor
@@ -50,8 +54,8 @@ config MACH_MINI2440
select CPU_S3C2440
select MACH_HAS_LOWLEVEL_INIT
select MACH_DO_LOWLEVEL_INIT
- select S3C24XX_PLL_INIT
- select S3C24XX_SDRAM_INIT
+ select S3C_PLL_INIT
+ select S3C_SDRAM_INIT
select HAS_DM9000
help
Say Y here if you are using Mini 2440 dev board equipped
@@ -78,29 +82,49 @@ source arch/arm/boards/mini2440/Kconfig
endmenu
-menu "S3C24X0 Features "
+endif
+
+if ARCH_S5PCxx
-config S3C24XX_LOW_LEVEL_INIT
+config CPU_S5PC110
bool
-config S3C24XX_PLL_INIT
+config CPU_S5PV210
+ bool
+
+#choice
+#
+# prompt "S5PCxx board type"
+#
+#
+#endchoice
+
+endif
+
+
+menu "S3C Features "
+
+config S3C_LOWLEVEL_INIT
+ bool
+
+config S3C_PLL_INIT
bool
prompt "Reconfigure PLL"
- select S3C24XX_LOW_LEVEL_INIT
+ select S3C_LOWLEVEL_INIT
help
This adds generic code to reconfigure the internal PLL very early
after reset.
-config S3C24XX_SDRAM_INIT
+config S3C_SDRAM_INIT
bool
prompt "Initialize SDRAM"
- select S3C24XX_LOW_LEVEL_INIT
+ select S3C_LOWLEVEL_INIT
help
This adds generic code to configure the SDRAM controller after reset.
The initialisation will be skipped if the code is already running
from SDRAM.
-config S3C24XX_NAND_BOOT
+config S3C_NAND_BOOT
bool
prompt "Booting from NAND"
select MTD
@@ -113,5 +137,3 @@ config S3C24XX_NAND_BOOT
endmenu
endif
-
-endif
diff --git a/arch/arm/mach-samsung/Makefile b/arch/arm/mach-samsung/Makefile
index 2ba5c3f1e2..d7344c89fc 100644
--- a/arch/arm/mach-samsung/Makefile
+++ b/arch/arm/mach-samsung/Makefile
@@ -1,3 +1,6 @@
obj-y += s3c-timer.o generic.o
-obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o s3c24xx-clocks.o
-obj-$(CONFIG_S3C24XX_LOW_LEVEL_INIT) += lowlevel-init.o
+obj-lowlevel-$(CONFIG_ARCH_S3C24xx) += lowlevel-s3c24x0.o
+obj-lowlevel-$(CONFIG_ARCH_S5PCxx) += lowlevel-s5pcxx.o
+obj-$(CONFIG_ARCH_S3C24xx) += gpio-s3c24x0.o s3c24xx-clocks.o mem-s3c24x0.o
+obj-$(CONFIG_ARCH_S5PCxx) += gpio-s5pcxx.o clocks-s5pcxx.o
+obj-$(CONFIG_S3C_LOWLEVEL_INIT) += $(obj-lowlevel-y)
diff --git a/arch/arm/mach-samsung/clocks-s5pcxx.c b/arch/arm/mach-samsung/clocks-s5pcxx.c
new file mode 100644
index 0000000000..1f4790bc07
--- /dev/null
+++ b/arch/arm/mach-samsung/clocks-s5pcxx.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2012 Alexey Galakhov
+ * Copyright (C) 2012 Juergen Beisert, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <init.h>
+#include <clock.h>
+#include <io.h>
+#include <mach/s3c-iomap.h>
+#include <mach/s3c-generic.h>
+#include <mach/s3c-clocks.h>
+
+static inline uint32_t clkdiv(uint32_t clk, unsigned bit, unsigned mask)
+{
+ uint32_t ratio = (readl(S5P_CLK_DIV0) >> bit) & mask;
+ return clk / (ratio + 1);
+}
+
+uint32_t s3c_get_mpllclk(void)
+{
+ uint32_t m, p, s;
+ uint32_t reg = readl(S5P_xPLL_CON + S5P_MPLL);
+ m = (reg >> 16) & 0x3ff;
+ p = (reg >> 8) & 0x3f;
+ s = (reg >> 0) & 0x7;
+ return m * ((S5PCXX_CLOCK_REFERENCE) / (p << s));
+}
+
+uint32_t s3c_get_apllclk(void)
+{
+ uint32_t m, p, s;
+ uint32_t reg = readl(S5P_xPLL_CON + S5P_APLL);
+ m = (reg >> 16) & 0x3ff;
+ p = (reg >> 8) & 0x3f;
+ s = (reg >> 0) & 0x7;
+ s -= 1;
+ return m * ((S5PCXX_CLOCK_REFERENCE) / (p << s));
+}
+
+static uint32_t s5p_get_a2mclk(void)
+{
+ return clkdiv(s3c_get_apllclk(), 4, 0x7);
+}
+
+static uint32_t s5p_get_moutpsysclk(void)
+{
+ if (readl(S5P_CLK_SRC0) & (1 << 24)) /* MUX_PSYS */
+ return s5p_get_a2mclk();
+ else
+ return s3c_get_mpllclk();
+}
+
+uint32_t s3c_get_hclk(void)
+{
+ return clkdiv(s5p_get_moutpsysclk(), 24, 0xf);
+}
+
+uint32_t s3c_get_pclk(void)
+{
+ return clkdiv(s3c_get_hclk(), 28, 0x7);
+}
+
+/* we are using the internal 'uclk1' as the UART source */
+static unsigned s3c_get_uart_clk_uclk1(void)
+{
+ unsigned clk = s3c_get_mpllclk(); /* TODO check for EPLL */
+ unsigned uartpdiv = ((readl(S5P_CLK_DIV4) >> 16) & 0x3) + 1; /* TODO this is UART0 only */
+ return clk / uartpdiv;
+}
+
+unsigned s3c_get_uart_clk(unsigned src) {
+ return (src & 1) ? s3c_get_uart_clk_uclk1() : s3c_get_pclk();
+}
+
+int s5pcxx_dump_clocks(void)
+{
+ printf("refclk: %7d kHz\n", S5PCXX_CLOCK_REFERENCE / 1000);
+ printf("apll: %7d kHz\n", s3c_get_apllclk() / 1000);
+ printf("mpll: %7d kHz\n", s3c_get_mpllclk() / 1000);
+/* printf("CPU: %7d kHz\n", s3c_get_cpuclk() / 1000); */
+ printf("hclk: %7d kHz\n", s3c_get_hclk() / 1000);
+ printf("pclk: %7d kHz\n", s3c_get_pclk() / 1000);
+ return 0;
+}
+
+late_initcall(s5pcxx_dump_clocks);
diff --git a/arch/arm/mach-samsung/generic.c b/arch/arm/mach-samsung/generic.c
index 7706be2628..7095294d52 100644
--- a/arch/arm/mach-samsung/generic.c
+++ b/arch/arm/mach-samsung/generic.c
@@ -25,65 +25,9 @@
#include <config.h>
#include <common.h>
#include <init.h>
-#include <clock.h>
#include <io.h>
-#include <sizes.h>
#include <mach/s3c-iomap.h>
#include <mach/s3c-generic.h>
-#include <mach/s3c-busctl.h>
-#include <mach/s3c24xx-gpio.h>
-
-/**
- * Calculate the amount of connected and available memory
- * @return Memory size in bytes
- */
-uint32_t s3c24xx_get_memory_size(void)
-{
- uint32_t reg, size;
-
- /*
- * detect the current memory size
- */
- reg = readl(S3C_BANKSIZE);
-
- switch (reg & 0x7) {
- case 0:
- size = SZ_32M;
- break;
- case 1:
- size = SZ_64M;
- break;
- case 2:
- size = SZ_128M;
- break;
- case 4:
- size = SZ_2M;
- break;
- case 5:
- size = SZ_4M;
- break;
- case 6:
- size = SZ_8M;
- break;
- default:
- size = SZ_16M;
- break;
- }
-
- /*
- * Is bank7 also configured for SDRAM usage?
- */
- if ((readl(S3C_BANKCON7) & (0x3 << 15)) == (0x3 << 15))
- size <<= 1; /* also count this bank */
-
- return size;
-}
-
-void s3c24xx_disable_second_sdram_bank(void)
-{
- writel(readl(S3C_BANKCON7) & ~(0x3 << 15), S3C_BANKCON7);
- writel(readl(S3C_MISCCR) | (1 << 18), S3C_MISCCR); /* disable its clock */
-}
#define S3C_WTCON (S3C_WATCHDOG_BASE)
#define S3C_WTDAT (S3C_WATCHDOG_BASE + 0x04)
@@ -105,60 +49,3 @@ void __noreturn reset_cpu(unsigned long addr)
;
}
EXPORT_SYMBOL(reset_cpu);
-
-/**
-
-@page dev_s3c24xx_arch Samsung's S3C24xx Platforms in barebox
-
-@section s3c24xx_boards Boards using S3C24xx Processors
-
-@li @subpage arch/arm/boards/a9m2410/a9m2410.c
-@li @subpage arch/arm/boards/a9m2440/a9m2440.c
-
-@section s3c24xx_arch Documentation for S3C24xx Architectures Files
-
-@li @subpage arch/arm/mach-s3c24xx/generic.c
-
-@section s3c24xx_mem_map SDRAM Memory Map
-
-SDRAM starts at address 0x3000.0000 up to the available amount of connected
-SDRAM memory. Physically this CPU can handle up to 256MiB (two areas with
-up to 128MiB each).
-
-@subsection s3c24xx_mem_generic_map Generic Map
-- 0x0000.0000 Start of the internal SRAM when booting from NAND flash memory or CS signal to a NOR flash memory.
-- 0x0800.0000 Start of I/O space.
-- 0x3000.0000 Start of SDRAM area.
- - 0x3000.0100 Start of the TAG list area.
- - 0x3000.8000 Start of the linux kernel (physical address).
-- 0x4000.0000 Start of internal SRAM, when booting from NOR flash memory
-- 0x4800.0000 Start of the internal I/O area
-
-@section s3c24xx_asm_arm include/asm-arm/arch-s3c24xx directory guidelines
-All S3C24xx common headers are located here.
-
-@note Do not add board specific header files/information here.
-*/
-
-/** @page dev_s3c24xx_mach Samsung's S3C24xx based platforms
-
-@par barebox Map
-
-The location of the @a barebox itself depends on the available amount of
-installed SDRAM memory:
-
-- 0x30fc.0000 Start of @a barebox when 16MiB SDRAM is available
-- 0x31fc.0000 Start of @a barebox when 32MiB SDRAM is available
-- 0x33fc.0000 Start of @a barebox when 64MiB SDRAM is available
-
-Adjust the @p CONFIG_TEXT_BASE/CONFIG_ARCH_TEXT_BASE symbol in accordance to
-the available memory.
-
-@note The RAM based filesystem and the stack resides always below the
-@a barebox start address.
-
-@li @subpage dev_s3c24xx_wd_handling
-@li @subpage dev_s3c24xx_pll_handling
-@li @subpage dev_s3c24xx_sdram_handling
-@li @subpage dev_s3c24xx_nandboot_handling
-*/
diff --git a/arch/arm/mach-samsung/gpio-s5pcxx.c b/arch/arm/mach-samsung/gpio-s5pcxx.c
new file mode 100644
index 0000000000..604a63fd6b
--- /dev/null
+++ b/arch/arm/mach-samsung/gpio-s5pcxx.c
@@ -0,0 +1,123 @@
+/*
+ * Copyright (C) 2012 Alexey Galakhov
+ * Copyright (C) 2012 Juergen Beisert, Pengutronix
+ *
+ * This codes bases partially on code from the Linux kernel:
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ * http://armlinux.simtec.co.uk/
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <io.h>
+#include <gpio.h>
+#include <mach/s3c-iomap.h>
+
+#define S3C_GPACON (S3C_GPIO_BASE)
+#define S3C_GPADAT (S3C_GPIO_BASE + 0x04)
+#define S3C_GPAPUD (S3C_GPIO_BASE + 0x08)
+
+static inline unsigned group_offset(unsigned group)
+{
+ return group * 0x20;
+}
+
+void gpio_set_value(unsigned gpio, int value)
+{
+ unsigned group = GET_GROUP(gpio);
+ unsigned bit = GET_BIT(gpio);
+ unsigned offset = group_offset(group);
+ uint32_t reg;
+
+ reg = readl(S3C_GPADAT + offset);
+ reg &= ~(1 << bit);
+ reg |= (!!value) << bit;
+ writel(reg, S3C_GPADAT + offset);
+}
+
+int gpio_get_value(unsigned gpio)
+{
+ unsigned group = GET_GROUP(gpio);
+ unsigned bit = GET_BIT(gpio);
+ unsigned offset = group_offset(group);
+ uint32_t reg;
+
+ /* value */
+ reg = readl(S3C_GPADAT + offset);
+
+ return !!(reg & (1 << bit));
+}
+
+int gpio_direction_input(unsigned gpio)
+{
+ unsigned group = GET_GROUP(gpio);
+ unsigned bit = GET_BIT(gpio);
+ unsigned offset = group_offset(group);
+ uint32_t reg;
+
+ bit <<= 2;
+ reg = readl(S3C_GPACON + offset) & ~(0xf << bit);
+ writel(reg, S3C_GPACON + offset);
+
+ return 0;
+}
+
+int gpio_direction_output(unsigned gpio, int value)
+{
+ unsigned group = GET_GROUP(gpio);
+ unsigned bit = GET_BIT(gpio);
+ unsigned offset = group_offset(group);
+ uint32_t reg;
+
+ gpio_set_value(gpio, value);
+
+ bit <<= 2;
+ reg = readl(S3C_GPACON + offset) & ~(0xf << bit);
+ reg |= 0x1 << bit;
+ writel(reg, S3C_GPACON + offset);
+
+ return 0;
+}
+
+
+/* 'gpio_mode' must be one of the 'GP?_*' macros */
+void s3c_gpio_mode(unsigned gpio_mode)
+{
+ unsigned group = GET_GROUP(gpio_mode);
+ unsigned bit = GET_BIT(gpio_mode);
+ unsigned func = GET_FUNC(gpio_mode);
+ unsigned offset = group_offset(group);
+ unsigned reg;
+
+ bit <<= 1;
+ if (PUD_PRESENT(gpio_mode)) {
+ reg = readl(S3C_GPAPUD + offset);
+ reg &= ~(PUD_MASK << bit);
+ reg |= GET_PUD(gpio_mode) << bit;
+ writel(reg, S3C_GPAPUD + offset);
+ }
+
+ bit <<= 1;
+ reg = readl(S3C_GPACON + offset) & ~(0xf << bit);
+ writel(reg | (func << bit), S3C_GPACON + offset);
+
+ if (func == 1) { /* output? if yes, also set the initial value */
+ reg = readl(S3C_GPADAT + offset) & ~(1 << (bit >> 2));
+ reg |= GET_GPIOVAL(gpio_mode) << (bit >> 2);
+ writel(reg, S3C_GPADAT + offset);
+ }
+
+}
diff --git a/arch/arm/mach-samsung/include/mach/gpio.h b/arch/arm/mach-samsung/include/mach/gpio.h
index 372339490c..4d7d2174dd 100644
--- a/arch/arm/mach-samsung/include/mach/gpio.h
+++ b/arch/arm/mach-samsung/include/mach/gpio.h
@@ -16,6 +16,9 @@
#ifdef CONFIG_ARCH_S3C24xx
# include <mach/iomux-s3c24x0.h>
#endif
+#ifdef CONFIG_ARCH_S5PCxx
+# include <mach/iomux-s5pcxx.h>
+#endif
void gpio_set_value(unsigned, int);
int gpio_direction_input(unsigned);
diff --git a/arch/arm/mach-samsung/include/mach/iomux-s5pcxx.h b/arch/arm/mach-samsung/include/mach/iomux-s5pcxx.h
new file mode 100644
index 0000000000..0677de46dd
--- /dev/null
+++ b/arch/arm/mach-samsung/include/mach/iomux-s5pcxx.h
@@ -0,0 +1,798 @@
+/*
+ * Copyright (C) 2012 Juergen Beisert
+ * Copyright (C) 2012 Alexey Galakhov
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Tested with S5PV210 */
+
+#ifndef __MACH_IOMUX_S5PCXX_H
+# define __MACH_IOMUX_S5PCXX_H
+
+/* 3322222222221111111111
+ * 10987654321098765432109876543210
+ * ^^^^^^_ Bit offset
+ * ^^^^^_______ Group Number
+ * ^^^^____________ Function
+ * ^________________ initial GPIO out value
+ * ^_________________ Pull up/down feature present
+ * ^^__________________ initial pull up/down setting
+ */
+
+#define PIN(group,bit) ((group << 6) + bit)
+#define FUNC(x) (((x) & 0xf) << 11)
+#define GET_FUNC(x) (((x) >> 11) & 0xf)
+#define GET_GROUP(x) (((x) >> 6) & 0x1f)
+#define GET_BIT(x) ((x) & 0x3f)
+#define GET_GPIOVAL(x) (!!((x) & (1 << 15)))
+#define GPIO_OUT (1 << 11)
+#define GPIO_IN (0 << 11)
+#define GPIO_VAL(x) ((!!(x)) << 15)
+#define PUD_MASK 0x3
+#define PUD (1 << 16)
+#define PUD_PRESENT(x) (!!((x) & (1 << 16)))
+#define DISABLE_PUD (0 << 17)
+#define ENABLE_PU (2 << 17)
+#define ENABLE_PD (1 << 17)
+#define GET_PUD(x) (((x) >> 17) & PUD_MASK)
+
+/*
+ * To have a chance for simple GPIO manipulation routines
+ * define the GPIO numbers with a real simple scheme.
+ *
+ * Keep in mind: The 'GPIO_2_NO' creates a value to be used with the real gpio
+ * routines and *not* for the multiplexer routines!
+ */
+#define GPIO_2_NO(x,y) (PIN(x,y))
+
+/*
+ * Group A0: GPIO 0...7
+ * Used GPIO: 0...7
+ * These pins can also act as GPIO outputs
+ */
+#define GPA00 (PIN(0,0) | PUD)
+#define GPA00_GPIO (GPA00 | FUNC(0))
+#define GPA00_RXD0 (GPA00 | FUNC(2))
+#define GPA01 (PIN(0,1) | PUD)
+#define GPA01_GPIO (GPA01 | FUNC(0))
+#define GPA01_TXD0 (GPA01 | FUNC(2))
+#define GPA02 (PIN(0,2) | PUD)
+#define GPA02_GPIO (GPA02 | FUNC(0))
+#define GPA02_NCTS0 (GPA02 | FUNC(2))
+#define GPA03 (PIN(0,3) | PUD)
+#define GPA03_GPIO (GPA03 | FUNC(0))
+#define GPA03_NRTS0 (GPA03 | FUNC(2))
+#define GPA04 (PIN(0,4) | PUD)
+#define GPA04_GPIO (GPA04 | FUNC(0))
+#define GPA04_RXD1 (GPA04 | FUNC(2))
+#define GPA05 (PIN(0,5) | PUD)
+#define GPA05_GPIO (GPA05 | FUNC(0))
+#define GPA05_TXD1 (GPA05 | FUNC(2))
+#define GPA06 (PIN(0,6) | PUD)
+#define GPA06_GPIO (GPA06 | FUNC(0))
+#define GPA06_NCTS1 (GPA06 | FUNC(2))
+#define GPA07 (PIN(0,7) | PUD)
+#define GPA07_GPIO (GPA07 | FUNC(0))
+#define GPA07_NRTS1 (GPA07 | FUNC(2))
+
+/*
+ * Group A1: GPIO 0..3
+ * Used GPIO: 0..3
+ * These pins can also act as GPIO outputs
+ */
+#define GPA10 (PIN(1,0) | PUD)
+#define GPA10_GPIO (GPA10 | FUNC(0))
+#define GPA10_RXD2 (GPA10 | FUNC(2))
+#define GPA10_RXDAUD (GPA0 | FUNC(4))
+#define GPA11 (PIN(1,1) | PUD)
+#define GPA11_GPIO (GPA11 | FUNC(0))
+#define GPA11_TXD2 (GPA11 | FUNC(2))
+#define GPA11_TXDAUD (GPA1 | FUNC(4))
+#define GPA12 (PIN(1,2) | PUD)
+#define GPA12_GPIO (GPA12 | FUNC(0))
+#define GPA12_RXD3 (GPA12 | FUNC(2))
+#define GPA12_NCTS2 (GPA12 | FUNC(3))
+#define GPA13 (PIN(1,3) | PUD)
+#define GPA13_GPIO (GPA13 | FUNC(0))
+#define GPA13_TXD3 (GPA13 | FUNC(2))
+#define GPA13_NRTS2 (GPA13 | FUNC(3))
+
+
+/*
+ * Group B: GPIO 0...7
+ * Used GPIO: 0...7
+ * These pins can also act as GPIO outputs
+ */
+#define GPB0 (PIN(2,0) | PUD)
+#define GPB0_GPIO (GPB0 | FUNC(0))
+#define GPB0_SPI0_CLK (GPB0 | FUNC(2))
+#define GPB1 (PIN(2,1) | PUD)
+#define GPB1_GPIO (GPB1 | FUNC(0))
+#define GPB1_SPI0_NCS (GPB1 | FUNC(2))
+#define GPB2 (PIN(2,2) | PUD)
+#define GPB2_GPIO (GPB2 | FUNC(0))
+#define GPB2_SPI0_MISO (GPB2 | FUNC(2))
+#define GPB3 (PIN(2,3) | PUD)
+#define GPB3_GPIO (GPB3 | FUNC(0))
+#define GPB3_SPI0_MOSI (GPB3 | FUNC(2))
+#define GPB4 (PIN(2,4) | PUD)
+#define GPB4_GPIO (GPB4 | FUNC(0))
+#define GPB4_SPI1_CLK (GPB4 | FUNC(2))
+#define GPB5 (PIN(2,5) | PUD)
+#define GPB5_GPIO (GPB5 | FUNC(0))
+#define GPB5_SPI1_NCS (GPB5 | FUNC(0))
+#define GPB6 (PIN(2,6) | PUD)
+#define GPB6_GPIO (GPB6 | FUNC(0))
+#define GPB6_SPI1_MISO (GPB6 | FUNC(0))
+#define GPB7 (PIN(2,7) | PUD)
+#define GPB7_GPIO (GPB7 | FUNC(0))
+#define GPB7_SPI1_MOSI (GPB7 | FUNC(0))
+
+/*
+ * Group C0: GPIO 0...4
+ */
+#define GPC00 (PIN(3,0) | PUD)
+#define GPC00_GPIO (GPC00 | FUNC(0))
+#define GPC00_I2S1_SCLK (GPC00 | FUNC(2))
+#define GPC00_PCM1_SCLK (GPC00 | FUNC(3))
+#define GPC00_AC97_BITCLK (GPC00 | FUNC(4))
+#define GPC01 (PIN(3,1) | PUD)
+#define GPC01_GPIO (GPC01 | FUNC(0))
+#define GPC01_I2S1_CDCLK (GPC01 | FUNC(2))
+#define GPC01_PCM1_EXTCLK (GPC01 | FUNC(3))
+#define GPC01_AC97_NRESET (GPC01 | FUNC(4))
+#define GPC02 (PIN(3,2) | PUD)
+#define GPC02_GPIO (GPC02 | FUNC(0))
+#define GPC02_I2S1_LRCK (GPC02 | FUNC(2))
+#define GPC02_PCM1_FSYNC (GPC02 | FUNC(3))
+#define GPC02_AC97_SYNC (GPC02 | FUNC(4))
+#define GPC03 (PIN(3,3) | PUD)
+#define GPC03_GPIO (GPC03 | FUNC(0))
+#define GPC03_I2S1_SDI (GPC03 | FUNC(2))
+#define GPC03_PCM1_SIN (GPC03 | FUNC(3))
+#define GPC03_AC97_SDI (GPC03 | FUNC(4))
+#define GPC04 (PIN(3,4) | PUD)
+#define GPC04_GPIO (GPC04 | FUNC(0))
+#define GPC04_I2S1_SDO (GPC04 | FUNC(2))
+#define GPC04_PCM1_SOUT (GPC04 | FUNC(3))
+#define GPC04_AC97_SDO (GPC04 | FUNC(4))
+
+/*
+ * Group C1: GPIO 0...4
+ */
+#define GPC10 (PIN(4,0) | PUD)
+#define GPC10_GPIO (GPC10 | FUNC(0))
+#define GPC10_PCM2_SCLK (GPC10 | FUNC(2))
+#define GPC10_SPDIF_0_OUT (GPC10 | FUNC(3))
+#define GPC10_I2S2_SCLK (GPC10 | FUNC(4))
+#define GPC11 (PIN(4,1) | PUD)
+#define GPC11_GPIO (GPC11 | FUNC(0))
+#define GPC11_PCM2_EXTCLK (GPC11 | FUNC(2))
+#define GPC11_SPDIF_EXTCLK (GPC11 | FUNC(3))
+#define GPC11_I2S2_CDCLK (GPC11 | FUNC(4))
+#define GPC12 (PIN(4,2) | PUD)
+#define GPC12_GPIO (GPC12 | FUNC(0))
+#define GPC12_PCM2_FSYNC (GPC12 | FUNC(2))
+#define GPC12_LCD_FRM (GPC12 | FUNC(3))
+#define GPC12_I2S2_LRCK (GPC12 | FUNC(4))
+#define GPC13 (PIN(4,3) | PUD)
+#define GPC13_GPIO (GPC13 | FUNC(0))
+#define GPC13_PCM2_SIN (GPC13 | FUNC(2))
+#define GPC13_I2S2_SDI (GPC13 | FUNC(4))
+#define GPC14 (PIN(4,4) | PUD)
+#define GPC14_GPIO (GPC14 | FUNC(0))
+#define GPC14_PCM2_SOUT (GPC14 | FUNC(2))
+#define GPC14_I2S2_SDO (GPC14 | FUNC(4))
+
+/*
+ * Group D0: GPIO 0...3
+ */
+#define GPD00 (PIN(5,0) | PUD)
+#define GPD00_GPIO (GPD00 | FUNC(0))
+#define GPD00_TOUT_0 (GPD00 | FUNC(2))
+#define GPD01 (PIN(5,1) | PUD)
+#define GPD01_GPIO (GPD01 | FUNC(0))
+#define GPD01_TOUT_1 (GPD01 | FUNC(2))
+#define GPD02 (PIN(5,2) | PUD)
+#define GPD02_GPIO (GPD02 | FUNC(0))
+#define GPD02_TOUT_2 (GPD02 | FUNC(2))
+#define GPD03 (PIN(5,3) | PUD)
+#define GPD03_GPIO (GPD03 | FUNC(0))
+#define GPD03_TOUT_3 (GPD03 | FUNC(2))
+
+/*
+ * Group D1: GPIO 0...5
+ */
+#define GPD10 (PIN(6,0) | PUD)
+#define GPD10_GPIO (GPD10 | FUNC(0))
+#define GPD10_I2C0_SDA (GPD10 | FUNC(2))
+#define GPD11 (PIN(6,0) | PUD)
+#define GPD11_GPIO (GPD11 | FUNC(0))
+#define GPD11_I2C0_SCL (GPD11 | FUNC(2))
+#define GPD12 (PIN(6,0) | PUD)
+#define GPD12_GPIO (GPD12 | FUNC(0))
+#define GPD12_I2C1_SDA (GPD12 | FUNC(2))
+#define GPD13 (PIN(6,0) | PUD)
+#define GPD13_GPIO (GPD13 | FUNC(0))
+#define GPD13_I2C1_SCL (GPD13 | FUNC(2))
+#define GPD14 (PIN(6,0) | PUD)
+#define GPD14_GPIO (GPD14 | FUNC(0))
+#define GPD14_I2C2_SDA (GPD14 | FUNC(2))
+#define GPD15 (PIN(6,0) | PUD)
+#define GPD15_GPIO (GPD15 | FUNC(0))
+#define GPD15_I2C2_SCL (GPD15 | FUNC(2))
+
+/*
+ * Group E0: GPIO 0...7
+ */
+#define GPE00 (PIN(7,0) | PUD)
+#define GPE00_GPIO (GPE00 | FUNC(0))
+#define GPE00_CAM_A_PCLK (GPE00 | FUNC(2))
+#define GPE01 (PIN(7,1) | PUD)
+#define GPE01_GPIO (GPE01 | FUNC(0))
+#define GPE01_CAM_A_VSYNC (GPE01 | FUNC(2))
+#define GPE02 (PIN(7,2) | PUD)
+#define GPE02_GPIO (GPE02 | FUNC(0))
+#define GPE02_CAM_A_HREF (GPE02 | FUNC(2))
+#define GPE03 (PIN(7,3) | PUD)
+#define GPE03_GPIO (GPE03 | FUNC(0))
+#define GPE03_CAM_A_DATA0 (GPE03 | FUNC(2))
+#define GPE04 (PIN(7,4) | PUD)
+#define GPE04_GPIO (GPE04 | FUNC(0))
+#define GPE04_CAM_A_DATA1 (GPE04 | FUNC(2))
+#define GPE05 (PIN(7,5) | PUD)
+#define GPE05_GPIO (GPE05 | FUNC(0))
+#define GPE05_CAM_A_DATA2 (GPE05 | FUNC(2))
+#define GPE06 (PIN(7,6) | PUD)
+#define GPE06_GPIO (GPE06 | FUNC(0))
+#define GPE06_CAM_A_DATA3 (GPE06 | FUNC(2))
+#define GPE07 (PIN(7,7) | PUD)
+#define GPE07_GPIO (GPE07 | FUNC(0))
+#define GPE07_CAM_A_DATA4 (GPE07 | FUNC(2))
+
+/*
+ * Group E1: GPIO 0...4
+ */
+#define GPE10 (PIN(8,0) | PUD)
+#define GPE10_GPIO (GPE10 | FUNC(0))
+#define GPE10_CAM_A_DATA5 (GPE10 | FUNC(2))
+#define GPE11 (PIN(8,1) | PUD)
+#define GPE11_GPIO (GPE11 | FUNC(0))
+#define GPE11_CAM_A_DATA6 (GPE11 | FUNC(2))
+#define GPE12 (PIN(8,2) | PUD)
+#define GPE12_GPIO (GPE12 | FUNC(0))
+#define GPE12_CAM_A_DATA7 (GPE12 | FUNC(2))
+#define GPE13 (PIN(8,3) | PUD)
+#define GPE13_GPIO (GPE13 | FUNC(0))
+#define GPE13_CAM_A_CLKOUT (GPE13 | FUNC(2))
+#define GPE14 (PIN(8,4) | PUD)
+#define GPE14_GPIO (GPE14 | FUNC(0))
+#define GPE14_CAM_A_FIELD (GPE14 | FUNC(2))
+
+/*
+ * Group F0: GPIO 0...7
+ */
+#define GPF00 (PIN(9,0) | PUD)
+#define GPF00_GPIO (GPF00 | FUNC(0))
+#define GPF00_LCD_HSYNC (GPF00 | FUNC(2))
+#define GPF00_SYS_CS0 (GPF00 | FUNC(3))
+#define GPF00_VEN_HSYNC (GPF00 | FUNC(4))
+#define GPF01 (PIN(9,1) | PUD)
+#define GPF01_GPIO (GPF01 | FUNC(0))
+#define GPF01_LCD_VSYNC (GPF01 | FUNC(2))
+#define GPF01_SYS_CS1 (GPF01 | FUNC(3))
+#define GPF01_VEN_VSYNC (GPF01 | FUNC(4))
+#define GPF02 (PIN(9,2) | PUD)
+#define GPF02_GPIO (GPF02 | FUNC(0))
+#define GPF02_LCD_VDEN (GPF02 | FUNC(2))
+#define GPF02_SYS_RS (GPF02 | FUNC(3))
+#define GPF02_VEN_HREF (GPF02 | FUNC(4))
+#define GPF03 (PIN(9,3) | PUD)
+#define GPF03_GPIO (GPF03 | FUNC(0))
+#define GPF03_LCD_VCLK (GPF03 | FUNC(2))
+#define GPF03_SYS_WE (GPF03 | FUNC(3))
+#define GPF03_V601_CLK (GPF03 | FUNC(4))
+#define GPF04 (PIN(9,4) | PUD)
+#define GPF04_GPIO (GPF04 | FUNC(0))
+#define GPF04_LCD_VD0 (GPF04 | FUNC(2))
+#define GPF04_SYS_VS0 (GPF04 | FUNC(3))
+#define GPF04_VEN_DATA0 (GPF04 | FUNC(4))
+#define GPF05 (PIN(9,5) | PUD)
+#define GPF05_GPIO (GPF05 | FUNC(0))
+#define GPF05_LCD_VD1 (GPF05 | FUNC(2))
+#define GPF05_SYS_VD1 (GPF05 | FUNC(3))
+#define GPF05_VEN_DATA1 (GPF05 | FUNC(4))
+#define GPF06 (PIN(9,6) | PUD)
+#define GPF06_GPIO (GPF06 | FUNC(0))
+#define GPF06_LCD_VD2 (GPF06 | FUNC(2))
+#define GPF06_SYS_VD2 (GPF06 | FUNC(3))
+#define GPF06_VEN_DATA2 (GPF06 | FUNC(4))
+#define GPF07 (PIN(9,7) | PUD)
+#define GPF07_GPIO (GPF07 | FUNC(0))
+#define GPF07_LCD_VD3 (GPF07 | FUNC(2))
+#define GPF07_SYS_VD3 (GPF07 | FUNC(3))
+#define GPF07_VEN_DATA3 (GPF07 | FUNC(4))
+
+/*
+ * Group F1: GPIO 0...7
+ */
+#define GPF10 (PIN(10,0) | PUD)
+#define GPF10_GPIO (GPF10 | FUNC(0))
+#define GPF10_LCD_VD4 (GPF10 | FUNC(2))
+#define GPF10_SYS_VD4 (GPF10 | FUNC(3))
+#define GPF10_VEN_DATA4 (GPF10 | FUNC(4))
+#define GPF11 (PIN(10,1) | PUD)
+#define GPF11_GPIO (GPF11 | FUNC(0))
+#define GPF11_LCD_VD5 (GPF11 | FUNC(2))
+#define GPF11_SYS_VD5 (GPF11 | FUNC(3))
+#define GPF11_VEN_DATA5 (GPF11 | FUNC(4))
+#define GPF12 (PIN(10,2) | PUD)
+#define GPF12_GPIO (GPF12 | FUNC(0))
+#define GPF12_LCD_VD6 (GPF12 | FUNC(2))
+#define GPF12_SYS_VD6 (GPF12 | FUNC(3))
+#define GPF12_VEN_DATA6 (GPF12 | FUNC(4))
+#define GPF13 (PIN(10,3) | PUD)
+#define GPF13_GPIO (GPF13 | FUNC(0))
+#define GPF13_LCD_VD7 (GPF13 | FUNC(2))
+#define GPF13_SYS_VD7 (GPF13 | FUNC(3))
+#define GPF13_VEN_DATA7 (GPF13 | FUNC(4))
+#define GPF14 (PIN(10,4) | PUD)
+#define GPF14_GPIO (GPF14 | FUNC(0))
+#define GPF14_LCD_VD8 (GPF14 | FUNC(2))
+#define GPF14_SYS_VD8 (GPF14 | FUNC(3))
+#define GPF14_V656_DATA0 (GPF14 | FUNC(4))
+#define GPF15 (PIN(10,5) | PUD)
+#define GPF15_GPIO (GPF15 | FUNC(0))
+#define GPF15_LCD_VD9 (GPF15 | FUNC(2))
+#define GPF15_SYS_VD9 (GPF15 | FUNC(3))
+#define GPF15_V656_DATA1 (GPF15 | FUNC(4))
+#define GPF16 (PIN(10,6) | PUD)
+#define GPF16_GPIO (GPF16 | FUNC(0))
+#define GPF16_LCD_VD10 (GPF16 | FUNC(2))
+#define GPF16_SYS_VD10 (GPF16 | FUNC(3))
+#define GPF16_V656_DATA2 (GPF16 | FUNC(4))
+#define GPF17 (PIN(10,7) | PUD)
+#define GPF17_GPIO (GPF17 | FUNC(0))
+#define GPF17_LCD_VD11 (GPF17 | FUNC(2))
+#define GPF17_SYS_VD11 (GPF17 | FUNC(3))
+#define GPF17_V656_DATA3 (GPF17 | FUNC(4))
+
+/*
+ * Group F2: GPIO 0...7
+ */
+#define GPF20 (PIN(11,0) | PUD)
+#define GPF20_GPIO (GPF20 | FUNC(0))
+#define GPF20_LCD_VD_12 (GPF20 | FUNC(2))
+#define GPF20_SYS_VD_12 (GPF20 | FUNC(3))
+#define GPF20_V656_DATA_4 (GPF20 | FUNC(4))
+#define GPF21 (PIN(11,1) | PUD)
+#define GPF21_GPIO (GPF21 | FUNC(0))
+#define GPF21_LCD_VD_13 (GPF21 | FUNC(2))
+#define GPF21_SYS_VD_13 (GPF21 | FUNC(3))
+#define GPF21_V656_DATA_5 (GPF21 | FUNC(4))
+#define GPF22 (PIN(11,2) | PUD)
+#define GPF22_GPIO (GPF22 | FUNC(0))
+#define GPF22_LCD_VD_14 (GPF22 | FUNC(2))
+#define GPF22_SYS_VD_14 (GPF22 | FUNC(3))
+#define GPF22_V656_DATA_6 (GPF22 | FUNC(4))
+#define GPF23 (PIN(11,3) | PUD)
+#define GPF23_GPIO (GPF23 | FUNC(0))
+#define GPF23_LCD_VD_15 (GPF23 | FUNC(2))
+#define GPF23_SYS_VD_15 (GPF23 | FUNC(3))
+#define GPF23_V656_DATA_7 (GPF23 | FUNC(4))
+#define GPF24 (PIN(11,4) | PUD)
+#define GPF24_GPIO (GPF24 | FUNC(0))
+#define GPF24_LCD_VD_16 (GPF24 | FUNC(2))
+#define GPF24_SYS_VD_16 (GPF24 | FUNC(3))
+#define GPF25 (PIN(11,5) | PUD)
+#define GPF25_GPIO (GPF25 | FUNC(0))
+#define GPF25_LCD_VD_17 (GPF25 | FUNC(2))
+#define GPF25_SYS_VD_17 (GPF25 | FUNC(3))
+#define GPF26 (PIN(11,6) | PUD)
+#define GPF26_GPIO (GPF26 | FUNC(0))
+#define GPF26_LCD_VD_18 (GPF26 | FUNC(2))
+#define GPF26_SYS_VD_18 (GPF26 | FUNC(3))
+#define GPF27 (PIN(11,7) | PUD)
+#define GPF27_GPIO (GPF27 | FUNC(0))
+#define GPF27_LCD_VD_19 (GPF27 | FUNC(2))
+#define GPF27_SYS_VD_19 (GPF27 | FUNC(3))
+
+/*
+ * Group F3: GPIO 0...5
+ */
+#define GPF30 (PIN(12,0) | PUD)
+#define GPF30_GPIO (GPF30 | FUNC(0))
+#define GPF30_LCD_VD20 (GPF30 | FUNC(2))
+#define GPF30_SYS_VD20 (GPF30 | FUNC(3))
+#define GPF31 (PIN(12,1) | PUD)
+#define GPF31_GPIO (GPF31 | FUNC(0))
+#define GPF31_LCD_VD21 (GPF31 | FUNC(2))
+#define GPF31_SYS_VD21 (GPF31 | FUNC(3))
+#define GPF32 (PIN(12,2) | PUD)
+#define GPF32_GPIO (GPF32 | FUNC(0))
+#define GPF32_LCD_VD22 (GPF32 | FUNC(2))
+#define GPF32_SYS_VD22 (GPF32 | FUNC(3))
+#define GPF33 (PIN(12,3) | PUD)
+#define GPF33_GPIO (GPF33 | FUNC(0))
+#define GPF33_LCD_VD23 (GPF33 | FUNC(2))
+#define GPF33_SYS_VD23 (GPF33 | FUNC(3))
+#define GPF33_V656_CLK (GPF33 | FUNC(4))
+#define GPF34 (PIN(12,4) | PUD)
+#define GPF34_GPIO (GPF34 | FUNC(0))
+#define GPF34_VSYNC_LDI (GPF34 | FUNC(3))
+#define GPF35 (PIN(12,5) | PUD)
+#define GPF35_GPIO (GPF35 | FUNC(0))
+#define GPF35_SYS_OE (GPF35 | FUNC(3))
+#define GPF35_VEN_FIELD (GPF35 | FUNC(4))
+
+/*
+ * Group G0: GPIO 0...6
+ */
+#define GPG00 (PIN(13,0) | PUD)
+#define GPG00_GPIO (GPG00 | FUNC(0))
+#define GPG00_SD0_CLK (GPG00 | FUNC(2))
+#define GPG01 (PIN(13,1) | PUD)
+#define GPG01_GPIO (GPG01 | FUNC(0))
+#define GPG01_SD0_CMD (GPG01 | FUNC(2))
+#define GPG02 (PIN(13,2) | PUD)
+#define GPG02_GPIO (GPG02 | FUNC(0))
+#define GPG02_SD0_NCD (GPG02 | FUNC(2))
+#define GPG03 (PIN(13,3) | PUD)
+#define GPG03_GPIO (GPG03 | FUNC(0))
+#define GPG03_SD0_DATA0 (GPG03 | FUNC(2))
+#define GPG04 (PIN(13,4) | PUD)
+#define GPG04_GPIO (GPG04 | FUNC(0))
+#define GPG04_SD0_DATA1 (GPG04 | FUNC(2))
+#define GPG05 (PIN(13,5) | PUD)
+#define GPG05_GPIO (GPG05 | FUNC(0))
+#define GPG05_SD0_DATA2 (GPG05 | FUNC(2))
+#define GPG06 (PIN(13,6) | PUD)
+#define GPG06_GPIO (GPG06 | FUNC(0))
+#define GPG06_SD0_DATA3 (GPG06 | FUNC(2))
+
+/*
+ * Group G1: GPIO 0...6
+ */
+#define GPG10 (PIN(14,0) | PUD)
+#define GPG10_GPIO (GPG10 | FUNC(0))
+#define GPG10_SD1_CLK (GPG10 | FUNC(2))
+#define GPG11 (PIN(14,1) | PUD)
+#define GPG11_GPIO (GPG11 | FUNC(0))
+#define GPG11_SD1_CMD (GPG11 | FUNC(2))
+#define GPG12 (PIN(14,2) | PUD)
+#define GPG12_GPIO (GPG12 | FUNC(0))
+#define GPG12_SD1_NCD (GPG12 | FUNC(2))
+#define GPG13 (PIN(14,3) | PUD)
+#define GPG13_GPIO (GPG13 | FUNC(0))
+#define GPG13_SD1_DATA0 (GPG13 | FUNC(2))
+#define GPG13_SD0_DATA4 (GPG13 | FUNC(3))
+#define GPG14 (PIN(14,4) | PUD)
+#define GPG14_GPIO (GPG14 | FUNC(0))
+#define GPG14_SD1_DATA1 (GPG14 | FUNC(2))
+#define GPG14_SD0_DATA5 (GPG14 | FUNC(3))
+#define GPG15 (PIN(14,5) | PUD)
+#define GPG15_GPIO (GPG15 | FUNC(0))
+#define GPG15_SD1_DATA2 (GPG15 | FUNC(2))
+#define GPG15_SD0_DATA6 (GPG15 | FUNC(3))
+#define GPG16 (PIN(14,6) | PUD)
+#define GPG16_GPIO (GPG16 | FUNC(0))
+#define GPG16_SD1_DATA3 (GPG16 | FUNC(2))
+#define GPG16_SD0_DATA7 (GPG16 | FUNC(3))
+
+/*
+ * Group G2: GPIO 0...6
+ */
+#define GPG20 (PIN(15,0) | PUD)
+#define GPG20_GPIO (GPG20 | FUNC(0))
+#define GPG20_SD2_CLK (GPG20 | FUNC(2))
+#define GPG21 (PIN(15,1) | PUD)
+#define GPG21_GPIO (GPG21 | FUNC(0))
+#define GPG21_SD2_CMD (GPG21 | FUNC(2))
+#define GPG22 (PIN(15,2) | PUD)
+#define GPG22_GPIO (GPG22 | FUNC(0))
+#define GPG22_SD2_NCD (GPG22 | FUNC(2))
+#define GPG23 (PIN(15,3) | PUD)
+#define GPG23_GPIO (GPG23 | FUNC(0))
+#define GPG23_SD2_DATA0 (GPG23 | FUNC(2))
+#define GPG24 (PIN(15,4) | PUD)
+#define GPG24_GPIO (GPG24 | FUNC(0))
+#define GPG24_SD2_DATA1 (GPG24 | FUNC(2))
+#define GPG25 (PIN(15,5) | PUD)
+#define GPG25_GPIO (GPG25 | FUNC(0))
+#define GPG25_SD2_DATA2 (GPG25 | FUNC(2))
+#define GPG26 (PIN(15,6) | PUD)
+#define GPG26_GPIO (GPG26 | FUNC(0))
+#define GPG26_SD2_DATA3 (GPG26 | FUNC(2))
+
+/*
+ * Group G3: GPIO 0...6
+ */
+#define GPG30 (PIN(16,0) | PUD)
+#define GPG30_GPIO (GPG30 | FUNC(0))
+#define GPG30_SD3_CLK (GPG30 | FUNC(2))
+#define GPG31 (PIN(16,1) | PUD)
+#define GPG31_GPIO (GPG31 | FUNC(0))
+#define GPG31_SD3_CMD (GPG31 | FUNC(2))
+#define GPG32 (PIN(16,2) | PUD)
+#define GPG32_GPIO (GPG32 | FUNC(0))
+#define GPG32_SD3_NCD (GPG32 | FUNC(2))
+#define GPG33 (PIN(16,3) | PUD)
+#define GPG33_GPIO (GPG33 | FUNC(0))
+#define GPG33_SD3_DATA0 (GPG33 | FUNC(2))
+#define GPG33_SD2_DATA4 (GPG33 | FUNC(3))
+#define GPG34 (PIN(16,4) | PUD)
+#define GPG34_GPIO (GPG34 | FUNC(0))
+#define GPG34_SD3_DATA1 (GPG34 | FUNC(2))
+#define GPG34_SD2_DATA5 (GPG34 | FUNC(3))
+#define GPG35 (PIN(16,5) | PUD)
+#define GPG35_GPIO (GPG35 | FUNC(0))
+#define GPG35_SD3_DATA2 (GPG35 | FUNC(2))
+#define GPG35_SD2_DATA6 (GPG35 | FUNC(3))
+#define GPG36 (PIN(16,6) | PUD)
+#define GPG36_GPIO (GPG36 | FUNC(0))
+#define GPG36_SD3_DATA3 (GPG36 | FUNC(2))
+#define GPG36_SD2_DATA7 (GPG36 | FUNC(3))
+
+/*
+ * Group I - no GPIO
+ */
+#define GPI0 (PIN(17,0) | PUD)
+#define GPI0_I2S0_SCLK (GPI0 | FUNC(2))
+#define GPI0_PCM0_SCLK (GPI0 | FUNC(3))
+#define GPI1 (PIN(17,1) | PUD)
+#define GPI1_I2S0_CDCLK (GPI1 | FUNC(2))
+#define GPI1_PCM0_EXTCLK (GPI1 | FUNC(3))
+#define GPI2 (PIN(17,2) | PUD)
+#define GPI2_I2S0_LRCK (GPI2 | FUNC(2))
+#define GPI2_PCM0_FSYNC (GPI2 | FUNC(3))
+#define GPI3 (PIN(17,3) | PUD)
+#define GPI3_I2S0_SDI (GPI3 | FUNC(2))
+#define GPI3_PCM0_SIN (GPI3 | FUNC(3))
+#define GPI4 (PIN(17,4) | PUD)
+#define GPI4_I2S0_SDO0 (GPI4 | FUNC(2))
+#define GPI4_PCM0_SOUT (GPI4 | FUNC(3))
+#define GPI5 (PIN(17,5) | PUD)
+#define GPI5_I2S0_SDO1 (GPI5 | FUNC(2))
+#define GPI6 (PIN(17,6) | PUD)
+#define GPI6_I2S0_SDO2 (GPI6 | FUNC(2))
+
+/*
+ * Group J0: GPIO 0...7
+ */
+#define GPJ00 (PIN(18,0) | PUD)
+#define GPJ00_GPIO (GPJ00 | FUNC(0))
+#define GPJ00_MSM_ADDR0 (GPJ00 | FUNC(2))
+#define GPJ00_CAM_B_DATA0 (GPJ00 | FUNC(3))
+#define GPJ00_CF_ADDR0 (GPJ00 | FUNC(4))
+#define GPJ00_MIPI_BYTE_CLK (GPJ00 | FUNC(5))
+#define GPJ01 (PIN(18,1) | PUD)
+#define GPJ01_GPIO (GPJ01 | FUNC(0))
+#define GPJ01_MSM_ADDR1 (GPJ01 | FUNC(2))
+#define GPJ01_CAM_B_DATA1 (GPJ01 | FUNC(3))
+#define GPJ01_CF_ADDR1 (GPJ01 | FUNC(4))
+#define GPJ01_MIPI_ESC_CLK (GPJ01 | FUNC(5))
+#define GPJ02 (PIN(18,2) | PUD)
+#define GPJ02_GPIO (GPJ02 | FUNC(0))
+#define GPJ02_MSM_ADDR2 (GPJ02 | FUNC(2))
+#define GPJ02_CAM_B_DATA2 (GPJ02 | FUNC(3))
+#define GPJ02_CF_ADDR2 (GPJ02 | FUNC(4))
+#define GPJ02_TS_CLK (GPJ02 | FUNC(5))
+#define GPJ03 (PIN(18,3) | PUD)
+#define GPJ03_GPIO (GPJ03 | FUNC(0))
+#define GPJ03_MSM_ADDR3 (GPJ03 | FUNC(2))
+#define GPJ03_CAM_B_DATA3 (GPJ03 | FUNC(3))
+#define GPJ03_CF_IORDY (GPJ03 | FUNC(4))
+#define GPJ03_TS_SYNC (GPJ03 | FUNC(5))
+#define GPJ04 (PIN(18,4) | PUD)
+#define GPJ04_GPIO (GPJ04 | FUNC(0))
+#define GPJ04_MSM_ADDR4 (GPJ04 | FUNC(2))
+#define GPJ04_CAM_B_DATA4 (GPJ04 | FUNC(3))
+#define GPJ04_CF_INTRQ (GPJ04 | FUNC(4))
+#define GPJ04_TS_VAL (GPJ04 | FUNC(5))
+#define GPJ05 (PIN(18,5) | PUD)
+#define GPJ05_GPIO (GPJ05 | FUNC(0))
+#define GPJ05_MSM_ADDR5 (GPJ05 | FUNC(2))
+#define GPJ05_CAM_B_DATA5 (GPJ05 | FUNC(3))
+#define GPJ05_CF_DMARQ (GPJ05 | FUNC(4))
+#define GPJ05_TS_DATA (GPJ05 | FUNC(5))
+#define GPJ06 (PIN(18,6) | PUD)
+#define GPJ06_GPIO (GPJ06 | FUNC(0))
+#define GPJ06_MSM_ADDR6 (GPJ06 | FUNC(2))
+#define GPJ06_CAM_B_DATA6 (GPJ06 | FUNC(3))
+#define GPJ06_CF_NDRESET (GPJ06 | FUNC(4))
+#define GPJ06_TS_ERROR (GPJ06 | FUNC(5))
+#define GPJ07 (PIN(18,7) | PUD)
+#define GPJ07_GPIO (GPJ07 | FUNC(0))
+#define GPJ07_MSM_ADDR7 (GPJ07 | FUNC(2))
+#define GPJ07_CAM_B_DATA7 (GPJ07 | FUNC(3))
+#define GPJ07_CF_NDMACK (GPJ07 | FUNC(4))
+#define GPJ07_MHL_D0 (GPJ07 | FUNC(5))
+
+/*
+ * Group J1: GPIO 0...5
+ */
+#define GPJ10 (PIN(19,0) | PUD)
+#define GPJ10_GPIO (GPJ10 | FUNC(0))
+#define GPJ10_MSM_ADDR8 (GPJ10 | FUNC(2))
+#define GPJ10_CAM_B_PCLK (GPJ10 | FUNC(3))
+#define GPJ10_SROM_ADDR_16to220 (GPJ10 | FUNC(4))
+#define GPJ10_MHL_D1 (GPJ10 | FUNC(5))
+#define GPJ11 (PIN(19,1) | PUD)
+#define GPJ11_GPIO (GPJ11 | FUNC(0))
+#define GPJ11_MSM_ADDR9 (GPJ11 | FUNC(2))
+#define GPJ11_CAM_B_VSYNC (GPJ11 | FUNC(3))
+#define GPJ11_SROM_ADDR_16to221 (GPJ11 | FUNC(4))
+#define GPJ11_MHL_D2 (GPJ11 | FUNC(5))
+#define GPJ12 (PIN(19,2) | PUD)
+#define GPJ12_GPIO (GPJ12 | FUNC(0))
+#define GPJ12_MSM_ADDR10 (GPJ12 | FUNC(2))
+#define GPJ12_CAM_B_HREF (GPJ12 | FUNC(3))
+#define GPJ12_SROM_ADDR_16to222 (GPJ12 | FUNC(4))
+#define GPJ12_MHL_D3 (GPJ12 | FUNC(5))
+#define GPJ13 (PIN(19,3) | PUD)
+#define GPJ13_GPIO (GPJ13 | FUNC(0))
+#define GPJ13_MSM_ADDR11 (GPJ13 | FUNC(2))
+#define GPJ13_CAM_B_FIELD (GPJ13 | FUNC(3))
+#define GPJ13_SROM_ADDR_16to223 (GPJ13 | FUNC(4))
+#define GPJ13_MHL_D4 (GPJ13 | FUNC(5))
+#define GPJ14 (PIN(19,4) | PUD)
+#define GPJ14_GPIO (GPJ14 | FUNC(0))
+#define GPJ14_MSM_ADDR12 (GPJ14 | FUNC(2))
+#define GPJ14_CAM_B_CLKOUT (GPJ14 | FUNC(3))
+#define GPJ14_SROM_ADDR_16to224 (GPJ14 | FUNC(4))
+#define GPJ14_MHL_D5 (GPJ14 | FUNC(5))
+#define GPJ15 (PIN(19,5) | PUD)
+#define GPJ15_GPIO (GPJ15 | FUNC(0))
+#define GPJ15_MSM_ADDR13 (GPJ15 | FUNC(2))
+#define GPJ15_KP_COL0 (GPJ15 | FUNC(3))
+#define GPJ15_SROM_ADDR_16to225 (GPJ15 | FUNC(4))
+#define GPJ15_MHL_D6 (GPJ15 | FUNC(5))
+
+/*
+ * Group J2: GPIO 0...7
+ */
+#define GPJ20 (PIN(20,0) | PUD)
+#define GPJ20_GPIO (GPJ20 | FUNC(0))
+#define GPJ20_MSM_DATA0 (GPJ20 | FUNC(2))
+#define GPJ20_KP_COL1 (GPJ20 | FUNC(3))
+#define GPJ20_CF_DATA0 (GPJ20 | FUNC(4))
+#define GPJ20_MHL_D7 (GPJ20 | FUNC(5))
+#define GPJ21 (PIN(20,1) | PUD)
+#define GPJ21_GPIO (GPJ21 | FUNC(0))
+#define GPJ21_MSM_DATA1 (GPJ21 | FUNC(2))
+#define GPJ21_KP_COL2 (GPJ21 | FUNC(3))
+#define GPJ21_CF_DATA1 (GPJ21 | FUNC(4))
+#define GPJ21_MHL_D8 (GPJ21 | FUNC(5))
+#define GPJ22 (PIN(20,2) | PUD)
+#define GPJ22_GPIO (GPJ22 | FUNC(0))
+#define GPJ22_MSM_DATA2 (GPJ22 | FUNC(2))
+#define GPJ22_KP_COL3 (GPJ22 | FUNC(3))
+#define GPJ22_CF_DATA2 (GPJ22 | FUNC(4))
+#define GPJ22_MHL_D9 (GPJ22 | FUNC(5))
+#define GPJ23 (PIN(20,3) | PUD)
+#define GPJ23_GPIO (GPJ23 | FUNC(0))
+#define GPJ23_MSM_DATA3 (GPJ23 | FUNC(2))
+#define GPJ23_KP_COL4 (GPJ23 | FUNC(3))
+#define GPJ23_CF_DATA3 (GPJ23 | FUNC(4))
+#define GPJ23_MHL_D10 (GPJ23 | FUNC(5))
+#define GPJ24 (PIN(20,4) | PUD)
+#define GPJ24_GPIO (GPJ24 | FUNC(0))
+#define GPJ24_MSM_DATA4 (GPJ24 | FUNC(2))
+#define GPJ24_KP_COL5 (GPJ24 | FUNC(3))
+#define GPJ24_CF_DATA4 (GPJ24 | FUNC(4))
+#define GPJ24_MHL_D11 (GPJ24 | FUNC(5))
+#define GPJ25 (PIN(20,5) | PUD)
+#define GPJ25_GPIO (GPJ25 | FUNC(0))
+#define GPJ25_MSM_DATA5 (GPJ25 | FUNC(2))
+#define GPJ25_KP_COL6 (GPJ25 | FUNC(3))
+#define GPJ25_CF_DATA5 (GPJ25 | FUNC(4))
+#define GPJ25_MHL_D12 (GPJ25 | FUNC(5))
+#define GPJ26 (PIN(20,6) | PUD)
+#define GPJ26_GPIO (GPJ26 | FUNC(0))
+#define GPJ26_MSM_DATA6 (GPJ26 | FUNC(2))
+#define GPJ26_KP_COL7 (GPJ26 | FUNC(3))
+#define GPJ26_CF_DATA6 (GPJ26 | FUNC(4))
+#define GPJ26_MHL_D13 (GPJ26 | FUNC(5))
+#define GPJ27 (PIN(20,7) | PUD)
+#define GPJ27_GPIO (GPJ27 | FUNC(0))
+#define GPJ27_MSM_DATA7 (GPJ27 | FUNC(2))
+#define GPJ27_KP_ROW0 (GPJ27 | FUNC(3))
+#define GPJ27_CF_DATA7 (GPJ27 | FUNC(4))
+#define GPJ27_MHL_D14 (GPJ27 | FUNC(5))
+
+/*
+ * Group J3: GPIO 0...7
+ */
+#define GPJ30 (PIN(21,0) | PUD)
+#define GPJ30_GPIO (GPJ30 | FUNC(0))
+#define GPJ30_MSM_DATA8 (GPJ30 | FUNC(2))
+#define GPJ30_KP_ROW1 (GPJ30 | FUNC(3))
+#define GPJ30_CF_DATA8 (GPJ30 | FUNC(4))
+#define GPJ30_MHL_D15 (GPJ30 | FUNC(5))
+#define GPJ31 (PIN(21,1) | PUD)
+#define GPJ31_GPIO (GPJ31 | FUNC(0))
+#define GPJ31_MSM_DATA9 (GPJ31 | FUNC(2))
+#define GPJ31_KP_ROW2 (GPJ31 | FUNC(3))
+#define GPJ31_CF_DATA9 (GPJ31 | FUNC(4))
+#define GPJ31_MHL_D16 (GPJ31 | FUNC(5))
+#define GPJ32 (PIN(21,2) | PUD)
+#define GPJ32_GPIO (GPJ32 | FUNC(0))
+#define GPJ32_MSM_DATA10 (GPJ32 | FUNC(2))
+#define GPJ32_KP_ROW3 (GPJ32 | FUNC(3))
+#define GPJ32_CF_DATA10 (GPJ32 | FUNC(4))
+#define GPJ32_MHL_D17 (GPJ32 | FUNC(5))
+#define GPJ33 (PIN(21,3) | PUD)
+#define GPJ33_GPIO (GPJ33 | FUNC(0))
+#define GPJ33_MSM_DATA11 (GPJ33 | FUNC(2))
+#define GPJ33_KP_ROW4 (GPJ33 | FUNC(3))
+#define GPJ33_CF_DATA11 (GPJ33 | FUNC(4))
+#define GPJ33_MHL_D18 (GPJ33 | FUNC(5))
+#define GPJ34 (PIN(21,4) | PUD)
+#define GPJ34_GPIO (GPJ34 | FUNC(0))
+#define GPJ34_MSM_DATA12 (GPJ34 | FUNC(2))
+#define GPJ34_KP_ROW5 (GPJ34 | FUNC(3))
+#define GPJ34_CF_DATA12 (GPJ34 | FUNC(4))
+#define GPJ34_MHL_D19 (GPJ34 | FUNC(5))
+#define GPJ35 (PIN(21,5) | PUD)
+#define GPJ35_GPIO (GPJ35 | FUNC(0))
+#define GPJ35_MSM_DATA13 (GPJ35 | FUNC(2))
+#define GPJ35_KP_ROW6 (GPJ35 | FUNC(3))
+#define GPJ35_CF_DATA13 (GPJ35 | FUNC(4))
+#define GPJ35_MHL_D20 (GPJ35 | FUNC(5))
+#define GPJ36 (PIN(21,6) | PUD)
+#define GPJ36_GPIO (GPJ36 | FUNC(0))
+#define GPJ36_MSM_DATA14 (GPJ36 | FUNC(2))
+#define GPJ36_KP_ROW7 (GPJ36 | FUNC(3))
+#define GPJ36_CF_DATA14 (GPJ36 | FUNC(4))
+#define GPJ36_MHL_D21 (GPJ36 | FUNC(5))
+#define GPJ37 (PIN(21,7) | PUD)
+#define GPJ37_GPIO (GPJ37 | FUNC(0))
+#define GPJ37_MSM_DATA15 (GPJ37 | FUNC(2))
+#define GPJ37_KP_ROW8 (GPJ37 | FUNC(3))
+#define GPJ37_CF_DATA15 (GPJ37 | FUNC(4))
+#define GPJ37_MHL_D22 (GPJ37 | FUNC(5))
+
+/*
+ * Group J4: GPIO 0...4
+ */
+#define GPJ40 (PIN(22,0) | PUD)
+#define GPJ40_GPIO (GPJ40 | FUNC(0))
+#define GPJ40_MSM_NCS (GPJ40 | FUNC(2))
+#define GPJ40_KP_ROW9 (GPJ40 | FUNC(3))
+#define GPJ40_CF_NCS0 (GPJ40 | FUNC(4))
+#define GPJ40_MHL_D23 (GPJ40 | FUNC(5))
+#define GPJ41 (PIN(22,1) | PUD)
+#define GPJ41_GPIO (GPJ41 | FUNC(0))
+#define GPJ41_MSM_NWE (GPJ41 | FUNC(2))
+#define GPJ41_KP_ROW10 (GPJ41 | FUNC(3))
+#define GPJ41_CF_NCS1 (GPJ41 | FUNC(4))
+#define GPJ41_MHL_IDCK (GPJ41 | FUNC(5))
+#define GPJ42 (PIN(22,2) | PUD)
+#define GPJ42_GPIO (GPJ42 | FUNC(0))
+#define GPJ42_MSM_NR (GPJ42 | FUNC(2))
+#define GPJ42_KP_ROW11 (GPJ42 | FUNC(3))
+#define GPJ42_CF_IORN (GPJ42 | FUNC(4))
+#define GPJ42_MHL_IDCK (GPJ42 | FUNC(5))
+#define GPJ43 (PIN(22,3) | PUD)
+#define GPJ43_GPIO (GPJ43 | FUNC(0))
+#define GPJ43_MSM_NIRQ (GPJ43 | FUNC(2))
+#define GPJ43_KP_ROW12 (GPJ43 | FUNC(3))
+#define GPJ43_CF_IOWN (GPJ43 | FUNC(4))
+#define GPJ43_MHL_VSYNC (GPJ43 | FUNC(5))
+#define GPJ44 (PIN(22,4) | PUD)
+#define GPJ44_GPIO (GPJ44 | FUNC(0))
+#define GPJ44_MSM_ADVN (GPJ44 | FUNC(2))
+#define GPJ44_KP_ROW13 (GPJ44 | FUNC(3))
+#define GPJ44_SROM_ADDR_16to226 (GPJ44 | FUNC(4))
+#define GPJ44_MHL_DE (GPJ44 | FUNC(5))
+
+#endif /* __MACH_IOMUX_S5PCXX_H */
diff --git a/arch/arm/mach-samsung/include/mach/s3c-clocks.h b/arch/arm/mach-samsung/include/mach/s3c-clocks.h
index 44b2a6c8ee..f577306ba5 100644
--- a/arch/arm/mach-samsung/include/mach/s3c-clocks.h
+++ b/arch/arm/mach-samsung/include/mach/s3c-clocks.h
@@ -1,5 +1,6 @@
/*
- * Copyright (C) 2011 Juergen Beisert, Pengutronix
+ * See file CREDITS for list of people who contributed to this
+ * project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -10,22 +11,22 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
*/
#ifndef __MACH_S3C_CLOCKS_H
-# define __MACH_S3C_CLOCKS_H
+#define __MACH_S3C_CLOCKS_H
#ifdef CONFIG_ARCH_S3C24xx
-# define S3C_LOCKTIME (S3C_CLOCK_POWER_BASE)
-# define S3C_MPLLCON (S3C_CLOCK_POWER_BASE + 0x4)
-# define S3C_UPLLCON (S3C_CLOCK_POWER_BASE + 0x8)
-# define S3C_CLKCON (S3C_CLOCK_POWER_BASE + 0xc)
-# define S3C_CLKSLOW (S3C_CLOCK_POWER_BASE + 0x10)
-# define S3C_CLKDIVN (S3C_CLOCK_POWER_BASE + 0x14)
-
-# define S3C_MPLLCON_GET_MDIV(x) ((((x) >> 12) & 0xff) + 8)
-# define S3C_MPLLCON_GET_PDIV(x) ((((x) >> 4) & 0x3f) + 2)
-# define S3C_MPLLCON_GET_SDIV(x) ((x) & 0x3)
+# include <mach/s3c24xx-clocks.h>
+#endif
+#ifdef CONFIG_ARCH_S5PCxx
+# include <mach/s5pcxx-clocks.h>
#endif
#endif /* __MACH_S3C_CLOCKS_H */
diff --git a/arch/arm/mach-samsung/include/mach/s3c-generic.h b/arch/arm/mach-samsung/include/mach/s3c-generic.h
index 4ea3dd7ea4..11b083d4a8 100644
--- a/arch/arm/mach-samsung/include/mach/s3c-generic.h
+++ b/arch/arm/mach-samsung/include/mach/s3c-generic.h
@@ -30,5 +30,14 @@ uint32_t s3c_get_fclk(void);
uint32_t s3c_get_hclk(void);
uint32_t s3c_get_pclk(void);
uint32_t s3c_get_uclk(void);
+
+unsigned s3c_get_uart_clk(unsigned src);
+
+#ifdef CONFIG_ARCH_S3C24xx
uint32_t s3c24xx_get_memory_size(void);
void s3c24xx_disable_second_sdram_bank(void);
+#endif
+
+#ifdef CONFIG_ARCH_S5PCxx
+void s5p_init_pll(void);
+#endif
diff --git a/arch/arm/mach-samsung/include/mach/s3c-iomap.h b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
index 9e867f8a34..d34ace47cd 100644
--- a/arch/arm/mach-samsung/include/mach/s3c-iomap.h
+++ b/arch/arm/mach-samsung/include/mach/s3c-iomap.h
@@ -1,5 +1,6 @@
/*
- * Copyright (C) 2009 Juergen Beisert, Pengutronix
+ * See file CREDITS for list of people who contributed to this
+ * project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -18,52 +19,9 @@
*
*/
-/* S3C2410 device base addresses */
-#define S3C_MEMCTL_BASE 0x48000000
-#define S3C2410_USB_HOST_BASE 0x49000000
-#define S3C2410_INTERRUPT_BASE 0x4A000000
-#define S3C2410_DMA_BASE 0x4B000000
-#define S3C_CLOCK_POWER_BASE 0x4C000000
-#define S3C2410_LCD_BASE 0x4D000000
-#define S3C24X0_NAND_BASE 0x4E000000
-#define S3C_UART_BASE 0x50000000
-#define S3C_TIMER_BASE 0x51000000
-#define S3C2410_USB_DEVICE_BASE 0x52000140
-#define S3C_WATCHDOG_BASE 0x53000000
-#define S3C2410_I2C_BASE 0x54000000
-#define S3C2410_I2S_BASE 0x55000000
-#define S3C_GPIO_BASE 0x56000000
-#define S3C2410_RTC_BASE 0x57000000
-#define S3C2410_ADC_BASE 0x58000000
-#define S3C2410_SPI_BASE 0x59000000
-#define S3C2410_SDI_BASE 0x5A000000
-
-/* external IO space */
-#define S3C_CS0_BASE 0x00000000
-#define S3C_CS1_BASE 0x08000000
-#define S3C_CS2_BASE 0x10000000
-#define S3C_CS3_BASE 0x18000000
-#define S3C_CS4_BASE 0x20000000
-#define S3C_CS5_BASE 0x28000000
-#define S3C_CS6_BASE 0x30000000
-
-#define S3C_SDRAM_BASE S3C_CS6_BASE
-#define S3C_SDRAM_END (S3C_SDRAM_BASE + 0x10000000)
-
-/*
- * if we are booting from NAND, its internal SRAM occures at
- * a different address than without this feature
- */
-#ifdef CONFIG_S3C24XX_NAND_BOOT
-# define NFC_RAM_AREA 0x00000000
-#else
-# define NFC_RAM_AREA 0x40000000
+#ifdef CONFIG_ARCH_S3C24xx
+# include <mach/s3c24xx-iomap.h>
+#endif
+#ifdef CONFIG_ARCH_S5PCxx
+# include <mach/s5pcxx-iomap.h>
#endif
-#define NFC_RAM_SIZE 4096
-
-#define S3C_UART1_BASE (S3C_UART_BASE)
-#define S3C_UART1_SIZE 0x4000
-#define S3C_UART2_BASE (S3C_UART_BASE + 0x4000)
-#define S3C_UART2_SIZE 0x4000
-#define S3C_UART3_BASE (S3C_UART_BASE + 0x8000)
-#define S3C_UART3_SIZE 0x4000
diff --git a/arch/arm/mach-samsung/include/mach/s3c24xx-clocks.h b/arch/arm/mach-samsung/include/mach/s3c24xx-clocks.h
new file mode 100644
index 0000000000..839dfe3c99
--- /dev/null
+++ b/arch/arm/mach-samsung/include/mach/s3c24xx-clocks.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2011 Juergen Beisert, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+# define S3C_LOCKTIME (S3C_CLOCK_POWER_BASE)
+# define S3C_MPLLCON (S3C_CLOCK_POWER_BASE + 0x4)
+# define S3C_UPLLCON (S3C_CLOCK_POWER_BASE + 0x8)
+# define S3C_CLKCON (S3C_CLOCK_POWER_BASE + 0xc)
+# define S3C_CLKSLOW (S3C_CLOCK_POWER_BASE + 0x10)
+# define S3C_CLKDIVN (S3C_CLOCK_POWER_BASE + 0x14)
+
+# define S3C_MPLLCON_GET_MDIV(x) ((((x) >> 12) & 0xff) + 8)
+# define S3C_MPLLCON_GET_PDIV(x) ((((x) >> 4) & 0x3f) + 2)
+# define S3C_MPLLCON_GET_SDIV(x) ((x) & 0x3)
diff --git a/arch/arm/mach-samsung/include/mach/s3c24xx-gpio.h b/arch/arm/mach-samsung/include/mach/s3c24xx-gpio.h
index c83597410c..ffb57fbd1f 100644
--- a/arch/arm/mach-samsung/include/mach/s3c24xx-gpio.h
+++ b/arch/arm/mach-samsung/include/mach/s3c24xx-gpio.h
@@ -12,8 +12,8 @@
* GNU General Public License for more details.
*/
-#ifndef __MACH_S3C24XX_GPIO_H
-# define __MACH_S3C24XX_GPIO_H
+#ifndef __MACH_GPIO_S3C24X0_H
+# define __MACH_GPIO_S3C24X0_H
#define S3C_GPACON (S3C_GPIO_BASE)
#define S3C_GPADAT (S3C_GPIO_BASE + 0x04)
@@ -74,4 +74,4 @@
# define S3C_DSC1 (S3C_GPIO_BASE + 0xc8)
#endif
-#endif /* __MACH_S3C24XX_GPIO_H */
+#endif /* __MACH_GPIO_S3C24X0_H */
diff --git a/arch/arm/mach-samsung/include/mach/s3c24xx-iomap.h b/arch/arm/mach-samsung/include/mach/s3c24xx-iomap.h
new file mode 100644
index 0000000000..60d44e3165
--- /dev/null
+++ b/arch/arm/mach-samsung/include/mach/s3c24xx-iomap.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2009 Juergen Beisert, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/* S3C2410 device base addresses */
+#define S3C_MEMCTL_BASE 0x48000000
+#define S3C2410_USB_HOST_BASE 0x49000000
+#define S3C2410_INTERRUPT_BASE 0x4A000000
+#define S3C2410_DMA_BASE 0x4B000000
+#define S3C_CLOCK_POWER_BASE 0x4C000000
+#define S3C2410_LCD_BASE 0x4D000000
+#define S3C24X0_NAND_BASE 0x4E000000
+#define S3C_UART_BASE 0x50000000
+#define S3C_TIMER_BASE 0x51000000
+#define S3C2410_USB_DEVICE_BASE 0x52000140
+#define S3C_WATCHDOG_BASE 0x53000000
+#define S3C2410_I2C_BASE 0x54000000
+#define S3C2410_I2S_BASE 0x55000000
+#define S3C_GPIO_BASE 0x56000000
+#define S3C2410_RTC_BASE 0x57000000
+#define S3C2410_ADC_BASE 0x58000000
+#define S3C2410_SPI_BASE 0x59000000
+#define S3C2410_SDI_BASE 0x5A000000
+
+/* external IO space */
+#define S3C_CS0_BASE 0x00000000
+#define S3C_CS1_BASE 0x08000000
+#define S3C_CS2_BASE 0x10000000
+#define S3C_CS3_BASE 0x18000000
+#define S3C_CS4_BASE 0x20000000
+#define S3C_CS5_BASE 0x28000000
+#define S3C_CS6_BASE 0x30000000
+
+#define S3C_SDRAM_BASE S3C_CS6_BASE
+#define S3C_SDRAM_END (S3C_SDRAM_BASE + 0x10000000)
+
+/*
+ * if we are booting from NAND, its internal SRAM occures at
+ * a different address than without this feature
+ */
+#ifdef CONFIG_S3C_NAND_BOOT
+# define NFC_RAM_AREA 0x00000000
+#else
+# define NFC_RAM_AREA 0x40000000
+#endif
+#define NFC_RAM_SIZE 4096
+
+#define S3C_UART1_BASE (S3C_UART_BASE)
+#define S3C_UART1_SIZE 0x4000
+#define S3C_UART2_BASE (S3C_UART_BASE + 0x4000)
+#define S3C_UART2_SIZE 0x4000
+#define S3C_UART3_BASE (S3C_UART_BASE + 0x8000)
+#define S3C_UART3_SIZE 0x4000
diff --git a/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h b/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h
index 7610b4e29d..acd78b8cd6 100644
--- a/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h
+++ b/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h
@@ -18,7 +18,7 @@
*
*/
-#ifdef CONFIG_S3C24XX_NAND_BOOT
+#ifdef CONFIG_S3C_NAND_BOOT
extern void s3c24x0_nand_load_image(void*, int, int);
#endif
diff --git a/arch/arm/mach-samsung/include/mach/s5pcxx-clocks.h b/arch/arm/mach-samsung/include/mach/s5pcxx-clocks.h
new file mode 100644
index 0000000000..f9d49c5156
--- /dev/null
+++ b/arch/arm/mach-samsung/include/mach/s5pcxx-clocks.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2012 Alexey Galakhov
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+# define S5P_APLL 0x00
+# define S5P_MPLL 0x08
+# define S5P_EPLL 0x10
+# define S5P_VPLL 0x20
+# define S5P_xPLL_LOCK (S5P_CLOCK_POWER_BASE)
+# define S5P_xPLL_CON (S5P_CLOCK_POWER_BASE + 0x100)
+# define S5P_xPLL_CON0 (S5P_xPLL_CON)
+# define S5P_xPLL_CON1 (S5P_xPLL_CON + 0x4)
+
+# define S5P_xPLLCON_GET_MDIV(x) (((x) >> 16) & 0x3ff)
+# define S5P_xPLLCON_GET_PDIV(x) (((x) >> 8) & 0x3f)
+# define S5P_xPLLCON_GET_SDIV(x) ((x) & 0x3)
+
+# define S5P_CLK_SRC0 (S5P_CLOCK_POWER_BASE + 0x200)
+# define S5P_CLK_SRC1 (S5P_CLOCK_POWER_BASE + 0x204)
+# define S5P_CLK_SRC2 (S5P_CLOCK_POWER_BASE + 0x208)
+# define S5P_CLK_SRC3 (S5P_CLOCK_POWER_BASE + 0x20C)
+# define S5P_CLK_SRC4 (S5P_CLOCK_POWER_BASE + 0x210)
+# define S5P_CLK_SRC5 (S5P_CLOCK_POWER_BASE + 0x214)
+# define S5P_CLK_SRC6 (S5P_CLOCK_BASE + 0x218)
+
+# define S5P_CLK_DIV0 (S5P_CLOCK_POWER_BASE + 0x300)
+# define S5P_CLK_DIV1 (S5P_CLOCK_POWER_BASE + 0x304)
+# define S5P_CLK_DIV2 (S5P_CLOCK_POWER_BASE + 0x308)
+# define S5P_CLK_DIV3 (S5P_CLOCK_POWER_BASE + 0x30C)
+# define S5P_CLK_DIV4 (S5P_CLOCK_POWER_BASE + 0x310)
+# define S5P_CLK_DIV5 (S5P_CLOCK_POWER_BASE + 0x314)
+# define S5P_CLK_DIV6 (S5P_CLOCK_POWER_BASE + 0x318)
+# define S5P_CLK_DIV7 (S5P_CLOCK_POWER_BASE + 0x31C)
+
+# define S5P_CLK_GATE_SCLK (S5P_CLOCK_POWER_BASE + 0x444)
+# define S5P_CLK_GATE_IP0 (S5P_CLOCK_POWER_BASE + 0x460)
+# define S5P_CLK_GATE_IP1 (S5P_CLOCK_POWER_BASE + 0x464)
+# define S5P_CLK_GATE_IP2 (S5P_CLOCK_POWER_BASE + 0x468)
+# define S5P_CLK_GATE_IP3 (S5P_CLOCK_POWER_BASE + 0x46C)
+# define S5P_CLK_GATE_IP4 (S5P_CLOCK_POWER_BASE + 0x470)
+# define S5P_CLK_GATE_BLOCK (S5P_CLOCK_POWER_BASE + 0x480)
+# define S5P_CLK_GATE_IP5 (S5P_CLOCK_POWER_BASE + 0x484)
+
+# define S5P_OTHERS (S5P_CLOCK_POWER_BASE + 0xE000)
+# define S5P_USB_PHY_CONTROL (S5P_CLOCK_POWER_BASE + 0xE80C)
diff --git a/arch/arm/mach-samsung/include/mach/s5pcxx-iomap.h b/arch/arm/mach-samsung/include/mach/s5pcxx-iomap.h
new file mode 100644
index 0000000000..cb055272ff
--- /dev/null
+++ b/arch/arm/mach-samsung/include/mach/s5pcxx-iomap.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2012 Alexey Galakhov
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/* S5PV210 device base addresses */
+
+#define S5P_CLOCK_POWER_BASE 0xE0100000
+#define S3C_GPIO_BASE 0xE0200000
+#define S3C_TIMER_BASE 0xE2500000
+#define S3C_WATCHDOG_BASE 0xE2700000
+#define S3C_UART_BASE 0xE2900000
+#define S3C_USB_HOST_BASE 0xEC200000
+#define S3C_NAND_BASE 0xB0E00000
+
+/* external IO space */
+#define S3C_CS0_BASE 0x80000000
+#define S3C_CS1_BASE 0x88000000
+#define S3C_CS2_BASE 0x90000000
+#define S3C_CS3_BASE 0x98000000
+#define S3C_CS4_BASE 0xA0000000
+#define S3C_CS5_BASE 0xA8000000
+
+#define S3C_SDRAM_BASE 0x20000000
+#define S3C_SDRAM_END (S3C_SDRAM_BASE + 0x60000000)
+
+#define S3C_UART1_BASE (S3C_UART_BASE)
+#define S3C_UART1_SIZE 0x400
+#define S3C_UART2_BASE (S3C_UART_BASE + 0x400)
+#define S3C_UART2_SIZE 0x400
+#define S3C_UART3_BASE (S3C_UART_BASE + 0x800)
+#define S3C_UART3_SIZE 0x400
+#define S3C_UART_HAS_UBRDIVSLOT
+#define S3C_UART_HAS_UINTM
diff --git a/arch/arm/mach-samsung/lowlevel-init.S b/arch/arm/mach-samsung/lowlevel-s3c24x0.S
index 31c619609f..e9471a5a17 100644
--- a/arch/arm/mach-samsung/lowlevel-init.S
+++ b/arch/arm/mach-samsung/lowlevel-s3c24x0.S
@@ -70,7 +70,7 @@ routine very early in your board_init_lowlevel routine.
* Note: Do not use "r10" here in this code
*/
-#ifdef CONFIG_S3C24XX_PLL_INIT
+#ifdef CONFIG_S3C_PLL_INIT
.section ".text_bare_init.s3c24x0_pll_init","ax"
@@ -146,7 +146,7 @@ shared with all other system on chip components. Most of the time this
configuration is to slow for the CPU and to fast for the other components.
PLL reprogramming can be done in the machine specific manner very early when
-the CONFIG_S3C24XX_PLL_INIT and CONFIG_MACH_HAS_LOWLEVEL_INIT symbols are
+the CONFIG_S3C_PLL_INIT and CONFIG_MACH_HAS_LOWLEVEL_INIT symbols are
defined. The board must provide a board_init_lowlevel() assembler function in
this case and calling the s3c24x0_pll_init() assembler function.
@@ -184,7 +184,7 @@ With m = MDIV + 8, p = PDIV + 2 and s = SDIV.
/* ----------------------------------------------------------------------- */
-#ifdef CONFIG_S3C24XX_SDRAM_INIT
+#ifdef CONFIG_S3C_SDRAM_INIT
.section ".text_bare_init.s3c24x0_sdram_init","ax"
@@ -225,7 +225,7 @@ SDRAMDATA:
The SDRAM controller is very simple and its initialisation requires only a
few steps. barebox provides a generic routine to do this step.
-Enable CONFIG_S3C24XX_SDRAM_INIT and CONFIG_MACH_HAS_LOWLEVEL_INIT to be able
+Enable CONFIG_S3C_SDRAM_INIT and CONFIG_MACH_HAS_LOWLEVEL_INIT to be able
to call the generic s3c24x0_sdram_init() assembler function from within the
machine specific board_init_lowlevel() assembler function.
@@ -245,7 +245,7 @@ Define in the machine specific config.h the following list of symbols:
/* ----------------------------------------------------------------------- */
-#ifdef CONFIG_S3C24XX_NAND_BOOT
+#ifdef CONFIG_S3C_NAND_BOOT
.section ".text_bare_init.s3c24x0_nand_boot","ax"
@@ -284,7 +284,7 @@ s3c24x0_nand_boot:
@page dev_s3c24xx_nandboot_handling Booting from NAND
To be able to boot from NAND memory only, enable the S3C24x0 NAND driver. Also
-enable CONFIG_S3C24XX_NAND_BOOT and CONFIG_MACH_HAS_LOWLEVEL_INIT to be
+enable CONFIG_S3C_NAND_BOOT and CONFIG_MACH_HAS_LOWLEVEL_INIT to be
able to call the s3c24x0_nand_boot() assembler routine from within the
machine specific board_init_lowlevel() assembler function.
diff --git a/arch/arm/mach-samsung/lowlevel-s5pcxx.c b/arch/arm/mach-samsung/lowlevel-s5pcxx.c
new file mode 100644
index 0000000000..15afa47ce3
--- /dev/null
+++ b/arch/arm/mach-samsung/lowlevel-s5pcxx.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2012 Alexey Galakhov
+ *
+ * Based on code from u-boot found somewhere on the web
+ * that seems to originate from Samsung
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <io.h>
+#include <init.h>
+#include <mach/s3c-iomap.h>
+#include <mach/s3c-clocks.h>
+#include <mach/s3c-generic.h>
+
+#ifdef CONFIG_S3C_PLL_INIT
+void __bare_init s5p_init_pll(void)
+{
+ uint32_t reg;
+ int i;
+
+ /* Set Mux to FIN */
+ writel(0, S5P_CLK_SRC0);
+
+ writel(BOARD_APLL_LOCKTIME, S5P_xPLL_LOCK + S5P_APLL);
+
+ /* Disable PLL */
+ writel(0, S5P_xPLL_CON + S5P_APLL);
+ writel(0, S5P_xPLL_CON + S5P_MPLL);
+
+ /* Set up dividers */
+ reg = readl(S5P_CLK_DIV0);
+ reg &= ~(BOARD_CLK_DIV0_MASK);
+ reg |= (BOARD_CLK_DIV0_VAL);
+ writel(reg, S5P_CLK_DIV0);
+
+ /* Set up PLLs */
+ writel(BOARD_APLL_VAL, S5P_xPLL_CON + S5P_APLL);
+ writel(BOARD_MPLL_VAL, S5P_xPLL_CON + S5P_MPLL);
+ writel(BOARD_EPLL_VAL, S5P_xPLL_CON + S5P_EPLL);
+ writel(BOARD_VPLL_VAL, S5P_xPLL_CON + S5P_VPLL);
+
+ /* Wait for sync */
+ for (i = 0; i < 0x10000; ++i)
+ barrier();
+
+ reg = readl(S5P_CLK_SRC0);
+ reg |= 0x1111; /* switch MUX to PLL outputs */
+ writel(reg, S5P_CLK_SRC0);
+}
+#endif /* CONFIG_S3C_PLL_INIT */
diff --git a/arch/arm/mach-samsung/mem-s3c24x0.c b/arch/arm/mach-samsung/mem-s3c24x0.c
new file mode 100644
index 0000000000..6fae72b5a1
--- /dev/null
+++ b/arch/arm/mach-samsung/mem-s3c24x0.c
@@ -0,0 +1,143 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/**
+ * @file
+ * @brief Basic clock, sdram and timer handling for S3C24xx CPUs
+ */
+
+#include <config.h>
+#include <common.h>
+#include <init.h>
+#include <clock.h>
+#include <io.h>
+#include <sizes.h>
+#include <mach/s3c-iomap.h>
+#include <mach/s3c-generic.h>
+#include <mach/s3c-busctl.h>
+#include <mach/s3c24xx-gpio.h>
+
+/**
+ * Calculate the amount of connected and available memory
+ * @return Memory size in bytes
+ */
+uint32_t s3c24xx_get_memory_size(void)
+{
+ uint32_t reg, size;
+
+ /*
+ * detect the current memory size
+ */
+ reg = readl(S3C_BANKSIZE);
+
+ switch (reg & 0x7) {
+ case 0:
+ size = SZ_32M;
+ break;
+ case 1:
+ size = SZ_64M;
+ break;
+ case 2:
+ size = SZ_128M;
+ break;
+ case 4:
+ size = SZ_2M;
+ break;
+ case 5:
+ size = SZ_4M;
+ break;
+ case 6:
+ size = SZ_8M;
+ break;
+ default:
+ size = SZ_16M;
+ break;
+ }
+
+ /*
+ * Is bank7 also configured for SDRAM usage?
+ */
+ if ((readl(S3C_BANKCON7) & (0x3 << 15)) == (0x3 << 15))
+ size <<= 1; /* also count this bank */
+
+ return size;
+}
+
+void s3c24xx_disable_second_sdram_bank(void)
+{
+ writel(readl(S3C_BANKCON7) & ~(0x3 << 15), S3C_BANKCON7);
+ writel(readl(S3C_MISCCR) | (1 << 18), S3C_MISCCR); /* disable its clock */
+}
+
+/**
+
+@page dev_s3c24xx_arch Samsung's S3C24xx Platforms in barebox
+
+@section s3c24xx_boards Boards using S3C24xx Processors
+
+@li @subpage arch/arm/boards/a9m2410/a9m2410.c
+@li @subpage arch/arm/boards/a9m2440/a9m2440.c
+
+@section s3c24xx_arch Documentation for S3C24xx Architectures Files
+
+@li @subpage arch/arm/mach-s3c24xx/generic.c
+
+@section s3c24xx_mem_map SDRAM Memory Map
+
+SDRAM starts at address 0x3000.0000 up to the available amount of connected
+SDRAM memory. Physically this CPU can handle up to 256MiB (two areas with
+up to 128MiB each).
+
+@subsection s3c24xx_mem_generic_map Generic Map
+- 0x0000.0000 Start of the internal SRAM when booting from NAND flash memory or CS signal to a NOR flash memory.
+- 0x0800.0000 Start of I/O space.
+- 0x3000.0000 Start of SDRAM area.
+ - 0x3000.0100 Start of the TAG list area.
+ - 0x3000.8000 Start of the linux kernel (physical address).
+- 0x4000.0000 Start of internal SRAM, when booting from NOR flash memory
+- 0x4800.0000 Start of the internal I/O area
+
+@section s3c24xx_asm_arm include/asm-arm/arch-s3c24xx directory guidelines
+All S3C24xx common headers are located here.
+
+@note Do not add board specific header files/information here.
+*/
+
+/** @page dev_s3c24xx_mach Samsung's S3C24xx based platforms
+
+@par barebox Map
+
+The location of the @a barebox itself depends on the available amount of
+installed SDRAM memory:
+
+- 0x30fc.0000 Start of @a barebox when 16MiB SDRAM is available
+- 0x31fc.0000 Start of @a barebox when 32MiB SDRAM is available
+- 0x33fc.0000 Start of @a barebox when 64MiB SDRAM is available
+
+Adjust the @p CONFIG_TEXT_BASE/CONFIG_ARCH_TEXT_BASE symbol in accordance to
+the available memory.
+
+@note The RAM based filesystem and the stack resides always below the
+@a barebox start address.
+
+@li @subpage dev_s3c24xx_wd_handling
+@li @subpage dev_s3c24xx_pll_handling
+@li @subpage dev_s3c24xx_sdram_handling
+@li @subpage dev_s3c24xx_nandboot_handling
+*/
diff --git a/arch/arm/mach-samsung/s3c24xx-clocks.c b/arch/arm/mach-samsung/s3c24xx-clocks.c
index a99d1b9d18..13e68678e1 100644
--- a/arch/arm/mach-samsung/s3c24xx-clocks.c
+++ b/arch/arm/mach-samsung/s3c24xx-clocks.c
@@ -118,6 +118,23 @@ uint32_t s3c24_get_uclk(void)
}
/**
+ * Return correct UART frequency based on the UCON register
+ */
+unsigned s3c_get_uart_clk(unsigned src)
+{
+ switch (src & 3) {
+ case 0:
+ case 2:
+ return s3c_get_pclk();
+ case 1:
+ return 0; /* TODO UEXTCLK */
+ case 3:
+ return 0; /* TODO FCLK/n */
+ }
+ return 0; /* not reached, to make compiler happy */
+}
+
+/**
* Show the user the current clock settings
*/
int s3c24xx_dump_clocks(void)
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
new file mode 100644
index 0000000000..eda786bafb
--- /dev/null
+++ b/arch/arm/mach-tegra/Kconfig
@@ -0,0 +1,19 @@
+if ARCH_TEGRA
+
+config ARCH_TEXT_BASE
+ hex
+ default 0x31fc0000
+
+choice
+ prompt "Tegra Board Type"
+
+config MACH_TOSHIBA_AC100
+ bool "Toshiba AC100"
+ help
+ Say Y here if you are using Toshiba AC100 smartbook.
+
+endchoice
+
+source arch/arm/boards/toshiba-ac100/Kconfig
+
+endif
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
new file mode 100644
index 0000000000..11915e5e23
--- /dev/null
+++ b/arch/arm/mach-tegra/Makefile
@@ -0,0 +1,2 @@
+obj-y += clock.o
+obj-y += reset.o
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
new file mode 100644
index 0000000000..0881698c44
--- /dev/null
+++ b/arch/arm/mach-tegra/clock.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2011 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+/**
+ * @file
+ * @brief Clocksource based on Tegra internal timer
+ */
+
+#include <common.h>
+#include <clock.h>
+#include <linux/list.h>
+#include <linux/clk.h>
+#include <init.h>
+#include <asm/io.h>
+#include <mach/iomap.h>
+
+static void __iomem *timer_reg_base = (void __iomem *) (TEGRA_TMR1_BASE);
+
+#define timer_writel(value, reg) \
+ __raw_writel(value, (u32)timer_reg_base + (reg))
+#define timer_readl(reg) \
+ __raw_readl((u32)timer_reg_base + (reg))
+
+static uint64_t tegra_clocksource_read(void)
+{
+ return timer_readl(0x10);
+}
+
+static struct clocksource cs = {
+ .read = tegra_clocksource_read,
+ .mask = 0xffffffff,
+};
+
+/* FIXME: here we have no initialization. All initialization made by U-Boot */
+static int clocksource_init(void)
+{
+ cs.mult = clocksource_hz2mult(1000000, cs.shift);
+ init_clock(&cs);
+
+ return 0;
+}
+core_initcall(clocksource_init);
diff --git a/arch/arm/mach-tegra/include/mach/debug_ll.h b/arch/arm/mach-tegra/include/mach/debug_ll.h
new file mode 100644
index 0000000000..bc7801aa6d
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/debug_ll.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2011 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+/** @file
+ * This File contains declaration for early output support
+ */
+#ifndef __INCLUDE_ARCH_DEBUG_LL_H__
+#define __INCLUDE_ARCH_DEBUG_LL_H__
+
+#include <asm/io.h>
+#include <mach/iomap.h>
+
+#define DEBUG_LL_UART_ADDR TEGRA_UARTA_BASE
+#define DEBUG_LL_UART_RSHFT 2
+
+#define rbr (0 << DEBUG_LL_UART_RSHFT)
+#define lsr (5 << DEBUG_LL_UART_RSHFT)
+#define LSR_THRE 0x20 /* Xmit holding register empty */
+
+static inline void putc(char ch)
+{
+ while (!(__raw_readb(DEBUG_LL_UART_ADDR + lsr) & LSR_THRE))
+ ;
+
+ __raw_writeb(ch, DEBUG_LL_UART_ADDR + rbr);
+}
+
+#endif /* __INCLUDE_ARCH_DEBUG_LL_H__ */
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
new file mode 100644
index 0000000000..ba478e7b25
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/iomap.h
@@ -0,0 +1,292 @@
+/*
+ * arch/arm/mach-tegra/include/mach/iomap.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ * Colin Cross <ccross@google.com>
+ * Erik Gilling <konkers@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_IOMAP_H
+#define __MACH_TEGRA_IOMAP_H
+
+#include <sizes.h>
+
+#define TEGRA_IRAM_BASE 0x40000000
+#define TEGRA_IRAM_SIZE SZ_256K
+
+#define TEGRA_HOST1X_BASE 0x50000000
+#define TEGRA_HOST1X_SIZE 0x24000
+
+#define TEGRA_ARM_PERIF_BASE 0x50040000
+#define TEGRA_ARM_PERIF_SIZE SZ_8K
+
+#define TEGRA_ARM_PL310_BASE 0x50043000
+#define TEGRA_ARM_PL310_SIZE SZ_4K
+
+#define TEGRA_ARM_INT_DIST_BASE 0x50041000
+#define TEGRA_ARM_INT_DIST_SIZE SZ_4K
+
+#define TEGRA_MPE_BASE 0x54040000
+#define TEGRA_MPE_SIZE SZ_256K
+
+#define TEGRA_VI_BASE 0x54080000
+#define TEGRA_VI_SIZE SZ_256K
+
+#define TEGRA_ISP_BASE 0x54100000
+#define TEGRA_ISP_SIZE SZ_256K
+
+#define TEGRA_DISPLAY_BASE 0x54200000
+#define TEGRA_DISPLAY_SIZE SZ_256K
+
+#define TEGRA_DISPLAY2_BASE 0x54240000
+#define TEGRA_DISPLAY2_SIZE SZ_256K
+
+#define TEGRA_HDMI_BASE 0x54280000
+#define TEGRA_HDMI_SIZE SZ_256K
+
+#define TEGRA_GART_BASE 0x58000000
+#define TEGRA_GART_SIZE SZ_32M
+
+#define TEGRA_RES_SEMA_BASE 0x60001000
+#define TEGRA_RES_SEMA_SIZE SZ_4K
+
+#define TEGRA_HDMI_BASE 0x54280000
+#define TEGRA_HDMI_SIZE SZ_256K
+
+#define TEGRA_GART_BASE 0x58000000
+#define TEGRA_GART_SIZE SZ_32M
+
+#define TEGRA_RES_SEMA_BASE 0x60001000
+#define TEGRA_RES_SEMA_SIZE SZ_4K
+
+#define TEGRA_ARB_SEMA_BASE 0x60002000
+#define TEGRA_ARB_SEMA_SIZE SZ_4K
+
+#define TEGRA_PRIMARY_ICTLR_BASE 0x60004000
+#define TEGRA_PRIMARY_ICTLR_SIZE 64
+
+#define TEGRA_ARBGNT_ICTLR_BASE 0x60004040
+#define TEGRA_ARBGNT_ICTLR_SIZE 192
+
+#define TEGRA_SECONDARY_ICTLR_BASE 0x60004100
+#define TEGRA_SECONDARY_ICTLR_SIZE 64
+
+#define TEGRA_TERTIARY_ICTLR_BASE 0x60004200
+#define TEGRA_TERTIARY_ICTLR_SIZE 64
+
+#define TEGRA_QUATERNARY_ICTLR_BASE 0x60004300
+#define TEGRA_QUATERNARY_ICTLR_SIZE 64
+
+#define TEGRA_TMR1_BASE 0x60005000
+#define TEGRA_TMR1_SIZE 8
+
+#define TEGRA_TMR2_BASE 0x60005008
+#define TEGRA_TMR2_SIZE 8
+
+#define TEGRA_TMRUS_BASE 0x60005010
+#define TEGRA_TMRUS_SIZE 64
+
+#define TEGRA_TMR3_BASE 0x60005050
+#define TEGRA_TMR3_SIZE 8
+
+#define TEGRA_TMR4_BASE 0x60005058
+#define TEGRA_TMR4_SIZE 8
+
+#define TEGRA_CLK_RESET_BASE 0x60006000
+#define TEGRA_CLK_RESET_SIZE SZ_4K
+
+#define TEGRA_FLOW_CTRL_BASE 0x60007000
+#define TEGRA_FLOW_CTRL_SIZE 20
+
+#define TEGRA_AHB_DMA_BASE 0x60008000
+#define TEGRA_AHB_DMA_SIZE SZ_4K
+
+#define TEGRA_AHB_DMA_CH0_BASE 0x60009000
+#define TEGRA_AHB_DMA_CH0_SIZE 32
+
+#define TEGRA_APB_DMA_BASE 0x6000A000
+#define TEGRA_APB_DMA_SIZE SZ_4K
+
+#define TEGRA_APB_DMA_CH0_BASE 0x6000B000
+#define TEGRA_APB_DMA_CH0_SIZE 32
+
+#define TEGRA_AHB_GIZMO_BASE 0x6000C004
+#define TEGRA_AHB_GIZMO_SIZE 0x10C
+
+#define TEGRA_STATMON_BASE 0x6000C400
+#define TEGRA_STATMON_SIZE SZ_1K
+
+#define TEGRA_GPIO_BASE 0x6000D000
+#define TEGRA_GPIO_SIZE SZ_4K
+
+#define TEGRA_EXCEPTION_VECTORS_BASE 0x6000F000
+#define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K
+
+#define TEGRA_VDE_BASE 0x6001A000
+#define TEGRA_VDE_SIZE (SZ_8K + SZ_4K - SZ_256)
+
+#define TEGRA_APB_MISC_BASE 0x70000000
+#define TEGRA_APB_MISC_SIZE SZ_4K
+
+#define TEGRA_APB_MISC_DAS_BASE 0x70000c00
+#define TEGRA_APB_MISC_DAS_SIZE SZ_128
+
+#define TEGRA_AC97_BASE 0x70002000
+#define TEGRA_AC97_SIZE SZ_512
+
+#define TEGRA_SPDIF_BASE 0x70002400
+#define TEGRA_SPDIF_SIZE SZ_512
+
+#define TEGRA_I2S1_BASE 0x70002800
+#define TEGRA_I2S1_SIZE SZ_256
+
+#define TEGRA_I2S2_BASE 0x70002A00
+#define TEGRA_I2S2_SIZE SZ_256
+
+#define TEGRA_UARTA_BASE 0x70006000
+#define TEGRA_UARTA_SIZE 64
+
+#define TEGRA_UARTB_BASE 0x70006040
+#define TEGRA_UARTB_SIZE 64
+
+#define TEGRA_UARTC_BASE 0x70006200
+#define TEGRA_UARTC_SIZE SZ_256
+
+#define TEGRA_UARTD_BASE 0x70006300
+#define TEGRA_UARTD_SIZE SZ_256
+
+#define TEGRA_UARTE_BASE 0x70006400
+#define TEGRA_UARTE_SIZE SZ_256
+
+#define TEGRA_NAND_BASE 0x70008000
+#define TEGRA_NAND_SIZE SZ_256
+
+#define TEGRA_HSMMC_BASE 0x70008500
+#define TEGRA_HSMMC_SIZE SZ_256
+
+#define TEGRA_SNOR_BASE 0x70009000
+#define TEGRA_SNOR_SIZE SZ_4K
+
+#define TEGRA_PWFM_BASE 0x7000A000
+#define TEGRA_PWFM_SIZE SZ_256
+
+#define TEGRA_PWFM0_BASE 0x7000A000
+#define TEGRA_PWFM0_SIZE 4
+
+#define TEGRA_PWFM1_BASE 0x7000A010
+#define TEGRA_PWFM1_SIZE 4
+
+#define TEGRA_PWFM2_BASE 0x7000A020
+#define TEGRA_PWFM2_SIZE 4
+
+#define TEGRA_PWFM3_BASE 0x7000A030
+#define TEGRA_PWFM3_SIZE 4
+
+#define TEGRA_MIPI_BASE 0x7000B000
+#define TEGRA_MIPI_SIZE SZ_256
+
+#define TEGRA_I2C_BASE 0x7000C000
+#define TEGRA_I2C_SIZE SZ_256
+
+#define TEGRA_TWC_BASE 0x7000C100
+#define TEGRA_TWC_SIZE SZ_256
+
+#define TEGRA_SPI_BASE 0x7000C380
+#define TEGRA_SPI_SIZE 48
+
+#define TEGRA_I2C2_BASE 0x7000C400
+#define TEGRA_I2C2_SIZE SZ_256
+
+#define TEGRA_I2C3_BASE 0x7000C500
+#define TEGRA_I2C3_SIZE SZ_256
+
+#define TEGRA_OWR_BASE 0x7000C600
+#define TEGRA_OWR_SIZE 80
+
+#define TEGRA_DVC_BASE 0x7000D000
+#define TEGRA_DVC_SIZE SZ_512
+
+#define TEGRA_SPI1_BASE 0x7000D400
+#define TEGRA_SPI1_SIZE SZ_512
+
+#define TEGRA_SPI2_BASE 0x7000D600
+#define TEGRA_SPI2_SIZE SZ_512
+
+#define TEGRA_SPI3_BASE 0x7000D800
+#define TEGRA_SPI3_SIZE SZ_512
+
+#define TEGRA_SPI4_BASE 0x7000DA00
+#define TEGRA_SPI4_SIZE SZ_512
+
+#define TEGRA_RTC_BASE 0x7000E000
+#define TEGRA_RTC_SIZE SZ_256
+
+#define TEGRA_KBC_BASE 0x7000E200
+#define TEGRA_KBC_SIZE SZ_256
+
+#define TEGRA_PMC_BASE 0x7000E400
+#define TEGRA_PMC_SIZE SZ_256
+
+#define TEGRA_MC_BASE 0x7000F000
+#define TEGRA_MC_SIZE SZ_1K
+
+#define TEGRA_EMC_BASE 0x7000F400
+#define TEGRA_EMC_SIZE SZ_1K
+
+#define TEGRA_FUSE_BASE 0x7000F800
+#define TEGRA_FUSE_SIZE SZ_1K
+
+#define TEGRA_KFUSE_BASE 0x7000FC00
+#define TEGRA_KFUSE_SIZE SZ_1K
+
+#define TEGRA_CSITE_BASE 0x70040000
+#define TEGRA_CSITE_SIZE SZ_256K
+
+#define TEGRA_USB_BASE 0xC5000000
+#define TEGRA_USB_SIZE SZ_16K
+
+#define TEGRA_USB2_BASE 0xC5004000
+#define TEGRA_USB2_SIZE SZ_16K
+
+#define TEGRA_USB3_BASE 0xC5008000
+#define TEGRA_USB3_SIZE SZ_16K
+
+#define TEGRA_SDMMC1_BASE 0xC8000000
+#define TEGRA_SDMMC1_SIZE SZ_512
+
+#define TEGRA_SDMMC2_BASE 0xC8000200
+#define TEGRA_SDMMC2_SIZE SZ_512
+
+#define TEGRA_SDMMC3_BASE 0xC8000400
+#define TEGRA_SDMMC3_SIZE SZ_512
+
+#define TEGRA_SDMMC4_BASE 0xC8000600
+#define TEGRA_SDMMC4_SIZE SZ_512
+
+#if defined(CONFIG_TEGRA_DEBUG_UART_NONE)
+# define TEGRA_DEBUG_UART_BASE 0
+#elif defined(CONFIG_TEGRA_DEBUG_UARTA)
+# define TEGRA_DEBUG_UART_BASE TEGRA_UARTA_BASE
+#elif defined(CONFIG_TEGRA_DEBUG_UARTB)
+# define TEGRA_DEBUG_UART_BASE TEGRA_UARTB_BASE
+#elif defined(CONFIG_TEGRA_DEBUG_UARTC)
+# define TEGRA_DEBUG_UART_BASE TEGRA_UARTC_BASE
+#elif defined(CONFIG_TEGRA_DEBUG_UARTD)
+# define TEGRA_DEBUG_UART_BASE TEGRA_UARTD_BASE
+#elif defined(CONFIG_TEGRA_DEBUG_UARTE)
+# define TEGRA_DEBUG_UART_BASE TEGRA_UARTE_BASE
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c
new file mode 100644
index 0000000000..4dd75938ac
--- /dev/null
+++ b/arch/arm/mach-tegra/reset.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2011 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+/**
+ * @file
+ * @brief Resetting an malta board
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mach/iomap.h>
+
+#define PRM_RSTCTRL TEGRA_PMC_BASE
+
+void __noreturn reset_cpu(ulong addr)
+{
+ int rstctrl;
+
+ rstctrl = __raw_readl((char *)PRM_RSTCTRL);
+ rstctrl |= 0x10;
+ __raw_writel(rstctrl, (char *)PRM_RSTCTRL);
+
+ unreachable();
+}
+EXPORT_SYMBOL(reset_cpu);
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index ff97af41df..325513f31a 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -12,7 +12,7 @@
#
# http://www.arm.linux.org.uk/developer/machines/?action=new
#
-# Last update: Thu Feb 9 12:00:12 2012
+# Last update: Mon May 14 09:28:07 2012
#
# machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number
#
@@ -3424,7 +3424,7 @@ h1600 MACH_H1600 H1600 3465
mini210 MACH_MINI210 MINI210 3466
mini8168 MACH_MINI8168 MINI8168 3467
pc7308 MACH_PC7308 PC7308 3468
-ge863pro3 MACH_GE863 GE863 3469
+ge863_pro3_evk MACH_GE863 GE863 3469
kmm2m01 MACH_KMM2M01 KMM2M01 3470
mx51erebus MACH_MX51EREBUS MX51EREBUS 3471
wm8650refboard MACH_WM8650REFBOARD WM8650REFBOARD 3472
@@ -3733,7 +3733,7 @@ shelter MACH_SHELTER SHELTER 3778
omap3_devkit8500 MACH_OMAP3_DEVKIT8500 OMAP3_DEVKIT8500 3779
edgetd MACH_EDGETD EDGETD 3780
copperyard MACH_COPPERYARD COPPERYARD 3781
-edge MACH_EDGE EDGE 3782
+edge_test MACH_EDGE EDGE 3782
edge_u MACH_EDGE_U EDGE_U 3783
edge_td MACH_EDGE_TD EDGE_TD 3784
wdss MACH_WDSS WDSS 3785
@@ -3945,7 +3945,7 @@ u8520 MACH_U8520 U8520 3990
manta MACH_MANTA MANTA 3991
spear1340_lcad MACH_SPEAR_EM_S900 SPEAR_EM_S900 3992
mpq8064_cdp MACH_MPQ8064_CDP MPQ8064_CDP 3993
-mpq8064_stb MACH_MPQ8064_STB MPQ8064_STB 3994
+mpq8064_hrd MACH_MPQ8064_STB MPQ8064_STB 3994
mpq8064_dtv MACH_MPQ8064_DTV MPQ8064_DTV 3995
dm368som MACH_DM368SOM DM368SOM 3996
gprisb2 MACH_GPRISB2 GPRISB2 3997
@@ -3963,3 +3963,188 @@ pcats_9307_type_a MACH_PCATS_9307_TYPE_A PCATS_9307_TYPE_A 4008
pcats_9307_type_o MACH_PCATS_9307_TYPE_O PCATS_9307_TYPE_O 4009
pcats_9307_type_r MACH_PCATS_9307_TYPE_R PCATS_9307_TYPE_R 4010
streamplug MACH_STREAMPLUG STREAMPLUG 4011
+icechicken_dev MACH_ICECHICKEN_DEV ICECHICKEN_DEV 4012
+hedgehog MACH_HEDGEHOG HEDGEHOG 4013
+yusend_obc MACH_YUSEND_OBC YUSEND_OBC 4014
+imxninja MACH_IMXNINJA IMXNINJA 4015
+omap4_jarod MACH_OMAP4_JAROD OMAP4_JAROD 4016
+eco5_pk MACH_ECO5_PK ECO5_PK 4017
+qj2440 MACH_QJ2440 QJ2440 4018
+mx6q_mercury MACH_MX6Q_MERCURY MX6Q_MERCURY 4019
+cm6810 MACH_CM6810 CM6810 4020
+omap4_torpedo MACH_OMAP4_TORPEDO OMAP4_TORPEDO 4021
+nsa310 MACH_NSA310 NSA310 4022
+tmx536 MACH_TMX536 TMX536 4023
+ktt20 MACH_KTT20 KTT20 4024
+dragonix MACH_DRAGONIX DRAGONIX 4025
+lungching MACH_LUNGCHING LUNGCHING 4026
+bulogics MACH_BULOGICS BULOGICS 4027
+mx535_sx MACH_MX535_SX MX535_SX 4028
+ngui3250 MACH_NGUI3250 NGUI3250 4029
+salutec_dac MACH_SALUTEC_DAC SALUTEC_DAC 4030
+loco MACH_LOCO LOCO 4031
+ctera_plug_usi MACH_CTERA_PLUG_USI CTERA_PLUG_USI 4032
+scepter MACH_SCEPTER SCEPTER 4033
+sga MACH_SGA SGA 4034
+p_81_j5 MACH_P_81_J5 P_81_J5 4035
+p_81_o4 MACH_P_81_O4 P_81_O4 4036
+msm8625_surf MACH_MSM8625_SURF MSM8625_SURF 4037
+carallon_shark MACH_CARALLON_SHARK CARALLON_SHARK 4038
+lsgc_icam MACH_LSGCICAM LSGCICAM 4039
+ordog MACH_ORDOG ORDOG 4040
+puente_io MACH_PUENTE_IO PUENTE_IO 4041
+msm8625_evb MACH_MSM8625_EVB MSM8625_EVB 4042
+ev_am1707 MACH_EV_AM1707 EV_AM1707 4043
+ev_am1707e2 MACH_EV_AM1707E2 EV_AM1707E2 4044
+ev_am3517e2 MACH_EV_AM3517E2 EV_AM3517E2 4045
+calabria MACH_CALABRIA CALABRIA 4046
+ev_imx287 MACH_EV_IMX287 EV_IMX287 4047
+erau MACH_ERAU ERAU 4048
+sichuan MACH_SICHUAN SICHUAN 4049
+sopdm MACH_WIRMA3 WIRMA3 4050
+davinci_da850 MACH_DAVINCI_DA850 DAVINCI_DA850 4051
+omap138_trunarc MACH_OMAP138_TRUNARC OMAP138_TRUNARC 4052
+bcm4761 MACH_BCM4761 BCM4761 4053
+picasso_e2 MACH_PICASSO_E2 PICASSO_E2 4054
+picasso_mf MACH_PICASSO_MF PICASSO_MF 4055
+miro MACH_MIRO MIRO 4056
+at91sam9g20ewon3 MACH_AT91SAM9G20EWON3 AT91SAM9G20EWON3 4057
+yoyo MACH_YOYO YOYO 4058
+windjkl MACH_WINDJKL WINDJKL 4059
+monarudo MACH_MONARUDO MONARUDO 4060
+batan MACH_BATAN BATAN 4061
+tadao MACH_TADAO TADAO 4062
+baso MACH_BASO BASO 4063
+mahon MACH_MAHON MAHON 4064
+villec2 MACH_VILLEC2 VILLEC2 4065
+asi1230 MACH_ASI1230 ASI1230 4066
+alaska MACH_ALASKA ALASKA 4067
+swarco_shdsl2 MACH_SWARCO_SHDSL2 SWARCO_SHDSL2 4068
+oxrtu MACH_OXRTU OXRTU 4069
+omap5_panda MACH_OMAP5_PANDA OMAP5_PANDA 4070
+imx286 MACH_MX28XDI MX28XDI 4071
+c8000 MACH_C8000 C8000 4072
+bje_display3_5 MACH_BJE_DISPLAY3_5 BJE_DISPLAY3_5 4073
+picomod7 MACH_PICOMOD7 PICOMOD7 4074
+picocom5 MACH_PICOCOM5 PICOCOM5 4075
+qblissa8 MACH_QBLISSA8 QBLISSA8 4076
+armstonea8 MACH_ARMSTONEA8 ARMSTONEA8 4077
+netdcu14 MACH_NETDCU14 NETDCU14 4078
+at91sam9x5_epiphan MACH_AT91SAM9X5_EPIPHAN AT91SAM9X5_EPIPHAN 4079
+p2u MACH_P2U P2U 4080
+doris MACH_DORIS DORIS 4081
+j49 MACH_J49 J49 4082
+vdss2e MACH_VDSS2E VDSS2E 4083
+vc300 MACH_VC300 VC300 4084
+ns115_pad_test MACH_NS115_PAD_TEST NS115_PAD_TEST 4085
+ns115_pad_ref MACH_NS115_PAD_REF NS115_PAD_REF 4086
+ns115_phone_test MACH_NS115_PHONE_TEST NS115_PHONE_TEST 4087
+ns115_phone_ref MACH_NS115_PHONE_REF NS115_PHONE_REF 4088
+golfc MACH_GOLFC GOLFC 4089
+xerox_olympus MACH_XEROX_OLYMPUS XEROX_OLYMPUS 4090
+mx6sl_arm2 MACH_MX6SL_ARM2 MX6SL_ARM2 4091
+csb1701_csb1726 MACH_CSB1701_CSB1726 CSB1701_CSB1726 4092
+at91sam9xeek MACH_AT91SAM9XEEK AT91SAM9XEEK 4093
+ebv210 MACH_EBV210 EBV210 4094
+msm7627a_qrd7 MACH_MSM7627A_QRD7 MSM7627A_QRD7 4095
+svthin MACH_SVTHIN SVTHIN 4096
+duovero MACH_DUOVERO DUOVERO 4097
+chupacabra MACH_CHUPACABRA CHUPACABRA 4098
+scorpion MACH_SCORPION SCORPION 4099
+davinci_he_hmi10 MACH_DAVINCI_HE_HMI10 DAVINCI_HE_HMI10 4100
+topkick MACH_TOPKICK TOPKICK 4101
+m3_auguestrush MACH_M3_AUGUESTRUSH M3_AUGUESTRUSH 4102
+ipc335x MACH_IPC335X IPC335X 4103
+sun4i MACH_SUN4I SUN4I 4104
+imx233_olinuxino MACH_IMX233_OLINUXINO IMX233_OLINUXINO 4105
+k2_wl MACH_K2_WL K2_WL 4106
+k2_ul MACH_K2_UL K2_UL 4107
+k2_cl MACH_K2_CL K2_CL 4108
+minbari_w MACH_MINBARI_W MINBARI_W 4109
+minbari_m MACH_MINBARI_M MINBARI_M 4110
+k035 MACH_K035 K035 4111
+ariel MACH_ARIEL ARIEL 4112
+arielsaarc MACH_ARIELSAARC ARIELSAARC 4113
+arieldkb MACH_ARIELDKB ARIELDKB 4114
+armadillo810 MACH_ARMADILLO810 ARMADILLO810 4115
+tam335x MACH_TAM335X TAM335X 4116
+grouper MACH_GROUPER GROUPER 4117
+mpcsa21_9g20 MACH_MPCSA21_9G20 MPCSA21_9G20 4118
+m6u_cpu MACH_M6U_CPU M6U_CPU 4119
+davinci_dp10 MACH_DAVINCI_DP10 DAVINCI_DP10 4120
+ginkgo MACH_GINKGO GINKGO 4121
+cgt_qmx6 MACH_CGT_QMX6 CGT_QMX6 4122
+profpga MACH_PROFPGA PROFPGA 4123
+acfx100oc MACH_ACFX100OC ACFX100OC 4124
+acfx100nb MACH_ACFX100NB ACFX100NB 4125
+capricorn MACH_CAPRICORN CAPRICORN 4126
+pisces MACH_PISCES PISCES 4127
+aries MACH_ARIES ARIES 4128
+cancer MACH_CANCER CANCER 4129
+leo MACH_LEO LEO 4130
+virgo MACH_VIRGO VIRGO 4131
+sagittarius MACH_SAGITTARIUS SAGITTARIUS 4132
+devil MACH_DEVIL DEVIL 4133
+ballantines MACH_BALLANTINES BALLANTINES 4134
+omap3_procerusvpu MACH_OMAP3_PROCERUSVPU OMAP3_PROCERUSVPU 4135
+my27 MACH_MY27 MY27 4136
+sun6i MACH_SUN6I SUN6I 4137
+sun5i MACH_SUN5I SUN5I 4138
+mx512_mx MACH_MX512_MX MX512_MX 4139
+kzm9g MACH_KZM9G KZM9G 4140
+vdstbn MACH_VDSTBN VDSTBN 4141
+cfa10036 MACH_CFA10036 CFA10036 4142
+cfa10049 MACH_CFA10049 CFA10049 4143
+pcm051 MACH_PCM051 PCM051 4144
+vybrid_vf7xx MACH_VYBRID_VF7XX VYBRID_VF7XX 4145
+vybrid_vf6xx MACH_VYBRID_VF6XX VYBRID_VF6XX 4146
+vybrid_vf5xx MACH_VYBRID_VF5XX VYBRID_VF5XX 4147
+vybrid_vf4xx MACH_VYBRID_VF4XX VYBRID_VF4XX 4148
+aria_g25 MACH_ARIA_G25 ARIA_G25 4149
+bcm21553 MACH_BCM21553 BCM21553 4150
+smdk5410 MACH_SMDK5410 SMDK5410 4151
+lpc18xx MACH_LPC18XX LPC18XX 4152
+oratisparty MACH_ORATISPARTY ORATISPARTY 4153
+qseven MACH_QSEVEN QSEVEN 4154
+gmv_generic MACH_GMV_GENERIC GMV_GENERIC 4155
+th_link_eth MACH_TH_LINK_ETH TH_LINK_ETH 4156
+tn_muninn MACH_TN_MUNINN TN_MUNINN 4157
+rampage MACH_RAMPAGE RAMPAGE 4158
+visstrim_mv10 MACH_VISSTRIM_MV10 VISSTRIM_MV10 4159
+monacotdu MACH_MONACO_TDU MONACO_TDU 4160
+monacoul MACH_MONACO_UL MONACO_UL 4161
+enrc2u MACH_ENRC2_U ENRC2_U 4162
+evitareul MACH_EVITA_UL EVITA_UL 4163
+mx28_wilma MACH_MX28_WILMA MX28_WILMA 4164
+monacou MACH_MONACO_U MONACO_U 4165
+msm8625_ffa MACH_MSM8625_FFA MSM8625_FFA 4166
+vpu101 MACH_VPU101 VPU101 4167
+operaul MACH_OPERA_UL OPERA_UL 4168
+baileys MACH_BAILEYS BAILEYS 4169
+familybox MACH_FAMILYBOX FAMILYBOX 4170
+ensemble_mx35 MACH_ENSEMBLE_MX35 ENSEMBLE_MX35 4171
+sc_sps_1 MACH_SC_SPS_1 SC_SPS_1 4172
+ucsimply_sam9260 MACH_UCSIMPLY_SAM9260 UCSIMPLY_SAM9260 4173
+unicorn MACH_UNICORN UNICORN 4174
+m9g45a MACH_M9G45A M9G45A 4175
+mtwebif MACH_MTWEBIF MTWEBIF 4176
+playstone MACH_PLAYSTONE PLAYSTONE 4177
+chelsea MACH_CHELSEA CHELSEA 4178
+bayern MACH_BAYERN BAYERN 4179
+mitwo MACH_MITWO MITWO 4180
+mx25_noah MACH_MX25_NOAH MX25_NOAH 4181
+stm_b2020 MACH_STM_B2020 STM_B2020 4182
+annax_src MACH_ANNAX_SRC ANNAX_SRC 4183
+ionics_stratus MACH_IONICS_STRATUS IONICS_STRATUS 4184
+hugo MACH_HUGO HUGO 4185
+em300 MACH_EM300 EM300 4186
+mmp3_qseven MACH_MMP3_QSEVEN MMP3_QSEVEN 4187
+bosphorus2 MACH_BOSPHORUS2 BOSPHORUS2 4188
+tt2200 MACH_TT2200 TT2200 4189
+ocelot3 MACH_OCELOT3 OCELOT3 4190
+tek_cobra MACH_TEK_COBRA TEK_COBRA 4191
+protou MACH_PROTOU PROTOU 4192
+msm8625_evt MACH_MSM8625_EVT MSM8625_EVT 4193
+mx53_sellwood MACH_MX53_SELLWOOD MX53_SELLWOOD 4194
+somiq_am35 MACH_SOMIQ_AM35 SOMIQ_AM35 4195
+somiq_am37 MACH_SOMIQ_AM37 SOMIQ_AM37 4196
diff --git a/arch/blackfin/boards/ipe337/ipe337.c b/arch/blackfin/boards/ipe337/ipe337.c
index 3c5566d704..b3f07bbb6d 100644
--- a/arch/blackfin/boards/ipe337/ipe337.c
+++ b/arch/blackfin/boards/ipe337/ipe337.c
@@ -19,8 +19,8 @@ static int ipe337_devices_init(void) {
add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, 0x24000000, 4096,
IORESOURCE_MEM, NULL);
- devfs_add_partition("nor0", 0x00000, 0x20000, PARTITION_FIXED, "self0");
- devfs_add_partition("nor0", 0x20000, 0x20000, PARTITION_FIXED, "env0");
+ devfs_add_partition("nor0", 0x00000, 0x20000, DEVFS_PARTITION_FIXED, "self0");
+ devfs_add_partition("nor0", 0x20000, 0x20000, DEVFS_PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
diff --git a/arch/blackfin/lib/blackfin_linux.c b/arch/blackfin/lib/blackfin_linux.c
index 458d1b180b..7798bbd34b 100644
--- a/arch/blackfin/lib/blackfin_linux.c
+++ b/arch/blackfin/lib/blackfin_linux.c
@@ -43,7 +43,7 @@
static int do_bootm_linux(struct image_data *idata)
{
int (*appl)(char *cmdline);
- const char *cmdline = getenv("bootargs");
+ const char *cmdline = linux_bootargs_get();
char *cmdlinedest = (char *) CMD_LINE_ADDR;
if (!idata->os_res)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 50d5c67738..7a1eeac706 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -46,10 +46,18 @@ config MACH_MIPS_BCM47XX
select SYS_SUPPORTS_LITTLE_ENDIAN
select HAS_DEBUG_LL
+config MACH_MIPS_XBURST
+ bool "Ingenic XBurst-based boards"
+ select SYS_HAS_CPU_MIPS32_R1
+ select SYS_SUPPORTS_LITTLE_ENDIAN
+ select SYS_SUPPORTS_32BIT_KERNEL
+ select DRIVER_SERIAL_NS16550
+ select HAS_DEBUG_LL
endchoice
source arch/mips/mach-malta/Kconfig
source arch/mips/mach-bcm47xx/Kconfig
+source arch/mips/mach-xburst/Kconfig
endmenu
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 43b8ae6638..6b7dae9faf 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -66,6 +66,9 @@ board-$(CONFIG_BOARD_QEMU_MALTA) := qemu-malta
machine-$(CONFIG_MACH_MIPS_BCM47XX) := bcm47xx
board-$(CONFIG_BOARD_DLINK_DIR320) := dlink-dir-320
+machine-$(CONFIG_MACH_MIPS_XBURST) := xburst
+board-$(CONFIG_BOARD_RZX50) := rzx50
+
machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
ifeq ($(KBUILD_SRC),)
@@ -93,6 +96,8 @@ else
MACH :=
endif
+CPPFLAGS += -I$(BOARD)/include
+
common-y += $(BOARD) $(MACH)
common-y += arch/mips/lib/
common-y += arch/mips/boot/
diff --git a/arch/mips/boards/qemu-malta/init.c b/arch/mips/boards/qemu-malta/init.c
index 16dc77c559..2a6eadbfb7 100644
--- a/arch/mips/boards/qemu-malta/init.c
+++ b/arch/mips/boards/qemu-malta/init.c
@@ -34,8 +34,8 @@ static int malta_devices_init(void)
{
add_cfi_flash_device(0, 0x1e000000, SZ_4M, 0);
- devfs_add_partition("nor0", 0x0, SZ_512K, PARTITION_FIXED, "self");
- devfs_add_partition("nor0", SZ_512K, SZ_64K, PARTITION_FIXED, "env0");
+ devfs_add_partition("nor0", 0x0, SZ_512K, DEVFS_PARTITION_FIXED, "self");
+ devfs_add_partition("nor0", SZ_512K, SZ_64K, DEVFS_PARTITION_FIXED, "env0");
return 0;
}
diff --git a/arch/mips/boards/rzx50/Kconfig b/arch/mips/boards/rzx50/Kconfig
new file mode 100644
index 0000000000..38401aa69a
--- /dev/null
+++ b/arch/mips/boards/rzx50/Kconfig
@@ -0,0 +1,6 @@
+if BOARD_RZX50
+
+config BOARDINFO
+ default "Ritmix RZX-50"
+
+endif
diff --git a/arch/mips/boards/rzx50/Makefile b/arch/mips/boards/rzx50/Makefile
new file mode 100644
index 0000000000..ff1a655afe
--- /dev/null
+++ b/arch/mips/boards/rzx50/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_DRIVER_SERIAL_NS16550) += serial.o
diff --git a/arch/mips/boards/rzx50/config.h b/arch/mips/boards/rzx50/config.h
new file mode 100644
index 0000000000..eb4ab083c3
--- /dev/null
+++ b/arch/mips/boards/rzx50/config.h
@@ -0,0 +1,19 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/* nothing special yet */
diff --git a/arch/mips/boards/rzx50/include/board/debug_ll.h b/arch/mips/boards/rzx50/include/board/debug_ll.h
new file mode 100644
index 0000000000..4164e47b53
--- /dev/null
+++ b/arch/mips/boards/rzx50/include/board/debug_ll.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2012 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __INCLUDE_RZX50_BOARD_DEBUG_LL_H__
+#define __INCLUDE_RZX50_BOARD_DEBUG_LL_H__
+
+#include <mach/jz4750d_regs.h>
+
+#define DEBUG_LL_UART_ADDR UART1_BASE
+#define DEBUG_LL_UART_SHIFT 2
+
+#endif /* __INCLUDE_RZX50_BOARD_DEBUG_LL_H__ */
diff --git a/arch/mips/boards/rzx50/rzx50.dox b/arch/mips/boards/rzx50/rzx50.dox
new file mode 100644
index 0000000000..963473cb51
--- /dev/null
+++ b/arch/mips/boards/rzx50/rzx50.dox
@@ -0,0 +1,46 @@
+/** @page rzx50 Ritmix RZX-50 game console
+
+Ritmix RZX-50 is a portable game console for the Russian market.
+
+The portable game console has
+@li Ingenic JZ4755 SoC;
+@li 64 MiB SDRAM;
+@li 4 GiB microSDHC card / 4 GiB NAND type Flash Memory;
+@li RS232 serial interface (LV-TTL levels on the board!);
+@li LCD display (480x272);
+@li Video out interface;
+@li 1xUSB interface;
+@li buttons.
+
+The game console uses U-Boot 1.1.6 as bootloader.
+
+barebox-rzx50 mini-howto:
+
+1. Connect to the game console's UART (see. http://a320.emulate.su/2012/01/19/uart-na-ritmix-rzx-50/);
+
+2. Unblock U-Boot console (see. http://a320.emulate.su/2012/01/25/rzx-50-dostup-k-konsoli-u-boot/); Please note that U-Boot's Zmodem support does not work;
+
+3. Boot Ritmix linux and login;
+
+4. Upload barebox.bin via Zmodem
+@verbatim
+ # cd /tmp
+ # rz
+@endverbatim
+
+5. Write barebox to onboard flash
+@verbatim
+ # dd if=barebox.bin of=/dev/mmcblk0 seek=1048576 bs=1 count=262144
+@endverbatim
+
+6. Reboot RZX-50, next in U-Boot console start barebox:
+@verbatim
+ CETUS # msc read 0xa0800000 0x100000 0x40000; g a0800000
+@endverbatim
+
+Ritmix RZX-50 links:
+@li http://www.ritmixrussia.ru/products/252/entertainment/game/rzx-50
+@li ftp://ftp.ingenic.cn/2soc/4755/JZ4755_ds.pdf
+@li ftp://ftp.ingenic.cn/3sw/01linux/01loader/u-boot/u-boot-1.1.6-jz-20110719-r1728-add-jz4770.patch.bz2
+
+*/
diff --git a/arch/mips/boards/rzx50/serial.c b/arch/mips/boards/rzx50/serial.c
new file mode 100644
index 0000000000..308cd18eaf
--- /dev/null
+++ b/arch/mips/boards/rzx50/serial.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2012 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <types.h>
+#include <driver.h>
+#include <init.h>
+#include <ns16550.h>
+#include <mach/jz4750d_regs.h>
+#include <io.h>
+#include <asm/common.h>
+
+#define JZ4750D_UART_SHIFT 2
+
+#define ier (1 << JZ4750D_UART_SHIFT)
+#define fcr (2 << JZ4750D_UART_SHIFT)
+
+static void jz4750d_serial_reg_write(unsigned int val, unsigned long base,
+ unsigned char reg_offset)
+{
+ switch (reg_offset) {
+ case fcr:
+ val |= 0x10; /* Enable uart module */
+ break;
+ case ier:
+ val |= (val & 0x4) << 2;
+ break;
+ default:
+ break;
+ }
+
+ writeb(val & 0xff, (void *)(base + reg_offset));
+}
+
+static struct NS16550_plat serial_plat = {
+ .clock = 12000000,
+ .shift = JZ4750D_UART_SHIFT,
+ .reg_write = &jz4750d_serial_reg_write,
+};
+
+static int rzx50_console_init(void)
+{
+ /* Register the serial port */
+ add_ns16550_device(-1, UART1_BASE, 8 << JZ4750D_UART_SHIFT,
+ IORESOURCE_MEM_8BIT, &serial_plat);
+
+ return 0;
+}
+console_initcall(rzx50_console_init);
diff --git a/arch/mips/boot/Makefile b/arch/mips/boot/Makefile
index f9151d28a1..d6d28ce652 100644
--- a/arch/mips/boot/Makefile
+++ b/arch/mips/boot/Makefile
@@ -1 +1,2 @@
obj-y += start.o
+obj-y += main_entry.o
diff --git a/arch/mips/boot/main_entry.c b/arch/mips/boot/main_entry.c
new file mode 100644
index 0000000000..8f5f6fc00e
--- /dev/null
+++ b/arch/mips/boot/main_entry.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2012 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <string.h>
+#include <asm/sections.h>
+#include <asm/cpu-features.h>
+
+extern void start_barebox(void);
+
+void main_entry(void);
+
+/**
+ * Called plainly from assembler code
+ *
+ * @note The C environment isn't initialized yet
+ */
+void main_entry(void)
+{
+ /* clear the BSS first */
+ memset(__bss_start, 0x00, __bss_stop - __bss_start);
+
+ cpu_probe();
+
+ if (cpu_has_4k_cache) {
+ extern void r4k_cache_init(void);
+
+ r4k_cache_init();
+ }
+
+ start_barebox();
+}
diff --git a/arch/mips/boot/start.S b/arch/mips/boot/start.S
index b756d40d3d..dd302fcd35 100644
--- a/arch/mips/boot/start.S
+++ b/arch/mips/boot/start.S
@@ -25,6 +25,8 @@
#include <asm/mipsregs.h>
#include <asm/asm.h>
#include <asm-generic/memory_layout.h>
+#include <generated/compile.h>
+#include <generated/utsrelease.h>
/*
* ADR macro instruction (inspired by ARM)
@@ -52,6 +54,16 @@ _pc: addiu \rd, ra, \label - _pc # label is assumed to be
.align 4
EXPORT(_start)
+
+ b __start
+ nop
+
+ .org 0x10
+ .ascii "barebox " UTS_RELEASE " " UTS_VERSION
+ .byte 0
+
+ .align 4
+__start:
/* disable watchpoints */
mtc0 zero, CP0_WATCHLO
mtc0 zero, CP0_WATCHHI
@@ -67,7 +79,7 @@ EXPORT(_start)
la a1, _start /* link (RAM) _start address */
- beq a0, a1, clear_bss
+ beq a0, a1, stack_setup
nop
la t0, _start
@@ -93,16 +105,6 @@ copy_loop:
blez t3, copy_loop
addi a1, LONGSIZE * 4
-clear_bss:
- la t0, __bss_start
- sw zero, (t0)
- la t1, _end - 4
-1:
- addiu t0, LONGSIZE
- sw zero, (t0)
- bne t0, t1, 1b
- nop
-
/*
* Dominic Sweetman, See MIPS Run, Morgan Kaufmann, 2nd edition, 2006
*
@@ -132,7 +134,7 @@ stack_setup:
/* reserve four 32-bit argument slots */
addiu sp, -16
- la v0, start_barebox
+ la v0, main_entry
jal v0
nop
diff --git a/arch/mips/configs/rzx50_defconfig b/arch/mips/configs/rzx50_defconfig
new file mode 100644
index 0000000000..722d977f50
--- /dev/null
+++ b/arch/mips/configs/rzx50_defconfig
@@ -0,0 +1,29 @@
+CONFIG_MACH_MIPS_XBURST=y
+CONFIG_BAUDRATE=57600
+CONFIG_GLOB=y
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_HUSH_GETOPT=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+# CONFIG_DEFAULT_ENVIRONMENT is not set
+CONFIG_DEBUG_LL=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_LOADB=y
+CONFIG_CMD_LOADY=y
+CONFIG_CMD_LOADS=y
+CONFIG_CMD_SAVES=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_BOOTM_SHOW_TYPE=y
+CONFIG_CMD_BOOTM_VERBOSE=y
+CONFIG_CMD_BOOTM_INITRD=y
+CONFIG_CMD_BOOTM_OFTREE=y
+CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
+CONFIG_CMD_UIMAGE=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_GO=y
+# CONFIG_SPI is not set
+CONFIG_SHA1=y
+CONFIG_SHA224=y
+CONFIG_SHA256=y
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index 36d34b62a3..001ebf2e72 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -27,6 +27,6 @@
#ifndef _ASM_MIPS_BITOPS_H_
#define _ASM_MIPS_BITOPS_H_
-/* nothing special yet */
+#include <asm-generic/bitops/__ffs.h>
#endif /* _ASM_MIPS_BITOPS_H_ */
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
new file mode 100644
index 0000000000..168d854454
--- /dev/null
+++ b/arch/mips/include/asm/cpu-features.h
@@ -0,0 +1,254 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ * Copyright (C) 2004 Maciej W. Rozycki
+ */
+#ifndef __ASM_CPU_FEATURES_H
+#define __ASM_CPU_FEATURES_H
+
+#include <asm/cpu.h>
+#include <asm/cpu-info.h>
+
+#ifndef current_cpu_type
+#define current_cpu_type() current_cpu_data.cputype
+#endif
+
+/*
+ * SMP assumption: Options of CPU 0 are a superset of all processors.
+ * This is true for all known MIPS systems.
+ */
+#ifndef cpu_has_tlb
+#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
+#endif
+#ifndef cpu_has_4kex
+#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
+#endif
+#ifndef cpu_has_3k_cache
+#define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE)
+#endif
+#define cpu_has_6k_cache 0
+#define cpu_has_8k_cache 0
+#ifndef cpu_has_4k_cache
+#define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE)
+#endif
+#ifndef cpu_has_tx39_cache
+#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
+#endif
+#ifndef cpu_has_octeon_cache
+#define cpu_has_octeon_cache 0
+#endif
+#ifndef cpu_has_fpu
+#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
+#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU)
+#else
+#define raw_cpu_has_fpu cpu_has_fpu
+#endif
+#ifndef cpu_has_32fpr
+#define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
+#endif
+#ifndef cpu_has_counter
+#define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER)
+#endif
+#ifndef cpu_has_watch
+#define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
+#endif
+#ifndef cpu_has_divec
+#define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
+#endif
+#ifndef cpu_has_vce
+#define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE)
+#endif
+#ifndef cpu_has_cache_cdex_p
+#define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
+#endif
+#ifndef cpu_has_cache_cdex_s
+#define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
+#endif
+#ifndef cpu_has_prefetch
+#define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH)
+#endif
+#ifndef cpu_has_mcheck
+#define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK)
+#endif
+#ifndef cpu_has_ejtag
+#define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG)
+#endif
+#ifndef cpu_has_llsc
+#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
+#endif
+#ifndef kernel_uses_llsc
+#define kernel_uses_llsc cpu_has_llsc
+#endif
+#ifndef cpu_has_mips16
+#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
+#endif
+#ifndef cpu_has_mdmx
+#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
+#endif
+#ifndef cpu_has_mips3d
+#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
+#endif
+#ifndef cpu_has_smartmips
+#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
+#endif
+#ifndef kernel_uses_smartmips_rixi
+#define kernel_uses_smartmips_rixi 0
+#endif
+#ifndef cpu_has_vtag_icache
+#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
+#endif
+#ifndef cpu_has_dc_aliases
+#define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
+#endif
+#ifndef cpu_has_ic_fills_f_dc
+#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
+#endif
+#ifndef cpu_has_pindexed_dcache
+#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
+#endif
+
+/*
+ * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
+ * such as the R10000 have I-Caches that snoop local stores; the embedded ones
+ * don't. For maintaining I-cache coherency this means we need to flush the
+ * D-cache all the way back to whever the I-cache does refills from, so the
+ * I-cache has a chance to see the new data at all. Then we have to flush the
+ * I-cache also.
+ * Note we may have been rescheduled and may no longer be running on the CPU
+ * that did the store so we can't optimize this into only doing the flush on
+ * the local CPU.
+ */
+#ifndef cpu_icache_snoops_remote_store
+#ifdef CONFIG_SMP
+#define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
+#else
+#define cpu_icache_snoops_remote_store 1
+#endif
+#endif
+
+# ifndef cpu_has_mips32r1
+# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
+# endif
+# ifndef cpu_has_mips32r2
+# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
+# endif
+# ifndef cpu_has_mips64r1
+# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
+# endif
+# ifndef cpu_has_mips64r2
+# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
+# endif
+
+/*
+ * Shortcuts ...
+ */
+#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2)
+#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2)
+#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
+#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
+#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
+ cpu_has_mips64r1 | cpu_has_mips64r2)
+
+#ifndef cpu_has_mips_r2_exec_hazard
+#define cpu_has_mips_r2_exec_hazard cpu_has_mips_r2
+#endif
+
+/*
+ * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
+ * pre-MIPS32/MIPS53 processors have CLO, CLZ. The IDT RC64574 is 64-bit and
+ * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels
+ * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
+ */
+# ifndef cpu_has_clo_clz
+# define cpu_has_clo_clz cpu_has_mips_r
+# endif
+
+#ifndef cpu_has_dsp
+#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
+#endif
+
+#ifndef cpu_has_mipsmt
+#define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT)
+#endif
+
+#ifndef cpu_has_userlocal
+#define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI)
+#endif
+
+#ifdef CONFIG_32BIT
+# ifndef cpu_has_nofpuex
+# define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
+# endif
+# ifndef cpu_has_64bits
+# define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
+# endif
+# ifndef cpu_has_64bit_zero_reg
+# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
+# endif
+# ifndef cpu_has_64bit_gp_regs
+# define cpu_has_64bit_gp_regs 0
+# endif
+# ifndef cpu_has_64bit_addresses
+# define cpu_has_64bit_addresses 0
+# endif
+# ifndef cpu_vmbits
+# define cpu_vmbits 31
+# endif
+#endif
+
+#ifdef CONFIG_64BIT
+# ifndef cpu_has_nofpuex
+# define cpu_has_nofpuex 0
+# endif
+# ifndef cpu_has_64bits
+# define cpu_has_64bits 1
+# endif
+# ifndef cpu_has_64bit_zero_reg
+# define cpu_has_64bit_zero_reg 1
+# endif
+# ifndef cpu_has_64bit_gp_regs
+# define cpu_has_64bit_gp_regs 1
+# endif
+# ifndef cpu_has_64bit_addresses
+# define cpu_has_64bit_addresses 1
+# endif
+# ifndef cpu_vmbits
+# define cpu_vmbits cpu_data[0].vmbits
+# define __NEED_VMBITS_PROBE
+# endif
+#endif
+
+#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
+# define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT)
+#elif !defined(cpu_has_vint)
+# define cpu_has_vint 0
+#endif
+
+#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
+# define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC)
+#elif !defined(cpu_has_veic)
+# define cpu_has_veic 0
+#endif
+
+#ifndef cpu_has_inclusive_pcaches
+#define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
+#endif
+
+#ifndef cpu_dcache_line_size
+#define cpu_dcache_line_size() cpu_data[0].dcache.linesz
+#endif
+#ifndef cpu_icache_line_size
+#define cpu_icache_line_size() cpu_data[0].icache.linesz
+#endif
+#ifndef cpu_scache_line_size
+#define cpu_scache_line_size() cpu_data[0].scache.linesz
+#endif
+
+#ifndef cpu_hwrena_impl_bits
+#define cpu_hwrena_impl_bits 0
+#endif
+
+#endif /* __ASM_CPU_FEATURES_H */
diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h
new file mode 100644
index 0000000000..6701730465
--- /dev/null
+++ b/arch/mips/include/asm/cpu-info.h
@@ -0,0 +1,71 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 Waldorf GMBH
+ * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
+ * Copyright (C) 1996 Paul M. Antoine
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2004 Maciej W. Rozycki
+ */
+#ifndef __ASM_CPU_INFO_H
+#define __ASM_CPU_INFO_H
+
+#include <linux/types.h>
+
+/*
+ * Descriptor for a cache
+ */
+struct cache_desc {
+ unsigned int waysize; /* Bytes per way */
+ unsigned short sets; /* Number of lines per set */
+ unsigned char ways; /* Number of ways */
+ unsigned char linesz; /* Size of line in bytes */
+ unsigned char waybit; /* Bits to select in a cache set */
+ unsigned char flags; /* Flags describing cache properties */
+};
+
+/*
+ * Flag definitions
+ */
+#define MIPS_CACHE_NOT_PRESENT 0x00000001
+#define MIPS_CACHE_VTAG 0x00000002 /* Virtually tagged cache */
+#define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */
+#define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */
+#define MIPS_IC_SNOOPS_REMOTE 0x00000010 /* Ic snoops remote stores */
+#define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */
+
+struct cpuinfo_mips {
+ unsigned int udelay_val;
+ unsigned int asid_cache;
+
+ /*
+ * Capability and feature descriptor structure for MIPS CPU
+ */
+ unsigned long options;
+ unsigned long ases;
+ unsigned int processor_id;
+ unsigned int fpu_id;
+ unsigned int cputype;
+ int isa_level;
+ int tlbsize;
+ struct cache_desc icache; /* Primary I-cache */
+ struct cache_desc dcache; /* Primary D or combined I/D cache */
+ struct cache_desc scache; /* Secondary cache */
+ struct cache_desc tcache; /* Tertiary/split secondary cache */
+ int srsets; /* Shadow register sets */
+ int core; /* physical core number */
+#ifdef CONFIG_64BIT
+ int vmbits; /* Virtual memory size in bits */
+#endif
+};
+
+extern struct cpuinfo_mips cpu_data[];
+#define current_cpu_data cpu_data[0]
+
+extern void cpu_probe(void);
+
+extern const char *__cpu_name;
+
+#endif /* __ASM_CPU_INFO_H */
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
new file mode 100644
index 0000000000..e63f847f2b
--- /dev/null
+++ b/arch/mips/include/asm/cpu.h
@@ -0,0 +1,143 @@
+/*
+ * cpu.h: Values of the PRId register used to match up
+ * various MIPS cpu types.
+ *
+ * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
+ * Copyright (C) 2004 Maciej W. Rozycki
+ */
+#ifndef _ASM_CPU_H
+#define _ASM_CPU_H
+
+/* Assigned Company values for bits 23:16 of the PRId Register
+ (CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from
+ MTI, the PRId register is defined in this (backwards compatible)
+ way:
+
+ +----------------+----------------+----------------+----------------+
+ | Company Options| Company ID | Processor ID | Revision |
+ +----------------+----------------+----------------+----------------+
+ 31 24 23 16 15 8 7
+
+ I don't have docs for all the previous processors, but my impression is
+ that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
+ spec.
+*/
+
+#define PRID_COMP_LEGACY 0x000000
+#define PRID_COMP_MIPS 0x010000
+#define PRID_COMP_BROADCOM 0x020000
+#define PRID_COMP_INGENIC 0xd00000
+
+#define PRID_IMP_UNKNOWN 0xff00
+
+/*
+ * These are the PRID's for when 23:16 == PRID_COMP_MIPS
+ */
+
+#define PRID_IMP_24K 0x9300
+#define PRID_IMP_24KE 0x9600
+
+/*
+ * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
+ */
+
+#define PRID_IMP_BMIPS3300 0x9000
+
+/*
+ * These are the PRID's for when 23:16 == PRID_COMP_INGENIC
+ */
+
+#define PRID_IMP_JZRISC 0x0200
+
+/*
+ * Older processors used to encode processor version and revision in two
+ * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
+ * have switched to use the 8-bits as 3:3:2 bitfield with the last field as
+ * the patch number. *ARGH*
+ */
+#define PRID_REV_ENCODE_44(ver, rev) \
+ ((ver) << 4 | (rev))
+#define PRID_REV_ENCODE_332(ver, rev, patch) \
+ ((ver) << 5 | (rev) << 2 | (patch))
+
+/*
+ * FPU implementation/revision register (CP1 control register 0).
+ *
+ * +---------------------------------+----------------+----------------+
+ * | 0 | Implementation | Revision |
+ * +---------------------------------+----------------+----------------+
+ * 31 16 15 8 7 0
+ */
+
+#define FPIR_IMP_NONE 0x0000
+
+enum cpu_type_enum {
+ CPU_UNKNOWN,
+
+ /*
+ * MIPS32 class processors
+ */
+ CPU_24K,
+ CPU_BMIPS3300,
+ CPU_JZRISC,
+
+ CPU_LAST
+};
+
+/*
+ * ISA Level encodings
+ *
+ */
+#define MIPS_CPU_ISA_I 0x00000001
+#define MIPS_CPU_ISA_II 0x00000002
+#define MIPS_CPU_ISA_III 0x00000004
+#define MIPS_CPU_ISA_IV 0x00000008
+#define MIPS_CPU_ISA_V 0x00000010
+#define MIPS_CPU_ISA_M32R1 0x00000020
+#define MIPS_CPU_ISA_M32R2 0x00000040
+#define MIPS_CPU_ISA_M64R1 0x00000080
+#define MIPS_CPU_ISA_M64R2 0x00000100
+
+#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \
+ MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 )
+#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
+ MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)
+
+/*
+ * CPU Option encodings
+ */
+#define MIPS_CPU_TLB 0x00000001 /* CPU has TLB */
+#define MIPS_CPU_4KEX 0x00000002 /* "R4K" exception model */
+#define MIPS_CPU_3K_CACHE 0x00000004 /* R3000-style caches */
+#define MIPS_CPU_4K_CACHE 0x00000008 /* R4000-style caches */
+#define MIPS_CPU_TX39_CACHE 0x00000010 /* TX3900-style caches */
+#define MIPS_CPU_FPU 0x00000020 /* CPU has FPU */
+#define MIPS_CPU_32FPR 0x00000040 /* 32 dbl. prec. FP registers */
+#define MIPS_CPU_COUNTER 0x00000080 /* Cycle count/compare */
+#define MIPS_CPU_WATCH 0x00000100 /* watchpoint registers */
+#define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */
+#define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */
+#define MIPS_CPU_CACHE_CDEX_P 0x00000800 /* Create_Dirty_Exclusive CACHE op */
+#define MIPS_CPU_CACHE_CDEX_S 0x00001000 /* ... same for seconary cache ... */
+#define MIPS_CPU_MCHECK 0x00002000 /* Machine check exception */
+#define MIPS_CPU_EJTAG 0x00004000 /* EJTAG exception */
+#define MIPS_CPU_NOFPUEX 0x00008000 /* no FPU exception */
+#define MIPS_CPU_LLSC 0x00010000 /* CPU has ll/sc instructions */
+#define MIPS_CPU_INCLUSIVE_CACHES 0x00020000 /* P-cache subset enforced */
+#define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */
+#define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */
+#define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */
+#define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */
+#define MIPS_CPU_CP2 0x00400000 /* CPU has CP2 */
+
+/*
+ * CPU ASE encodings
+ */
+#define MIPS_ASE_MIPS16 0x00000001 /* code compression */
+#define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */
+#define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */
+#define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */
+#define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */
+#define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */
+
+#endif /* _ASM_CPU_H */
diff --git a/arch/mips/include/debug_ll_ns16550.h b/arch/mips/include/debug_ll_ns16550.h
new file mode 100644
index 0000000000..9280219449
--- /dev/null
+++ b/arch/mips/include/debug_ll_ns16550.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2012 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+/** @file
+ * This file contains declaration for early output support
+ */
+#ifndef __INCLUDE_ARCH_DEBUG_LL_NS16550_H__
+#define __INCLUDE_ARCH_DEBUG_LL_NS16550_H__
+
+#include <asm/io.h>
+
+#define rbr (0 << DEBUG_LL_UART_SHIFT)
+#define lsr (5 << DEBUG_LL_UART_SHIFT)
+
+#define LSR_THRE 0x20 /* Xmit holding register empty */
+
+static __inline__ void putc(char ch)
+{
+ while (!(__raw_readb((u8 *)DEBUG_LL_UART_ADDR + lsr) & LSR_THRE));
+ __raw_writeb(ch, (u8 *)DEBUG_LL_UART_ADDR + rbr);
+}
+
+#endif /* __INCLUDE_ARCH_DEBUG_LL_NS16550_H__ */
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index 45fe920c44..b99bb71837 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -4,5 +4,10 @@ obj-y += lshrdi3.o
obj-y += ashldi3.o
obj-y += ashrdi3.o
obj-y += memory.o
+obj-y += cpu-probe.o
+
+obj-$(CONFIG_CPU_MIPS32) += c-r4k.o
+obj-$(CONFIG_CPU_MIPS64) += c-r4k.o
obj-$(CONFIG_CMD_MIPS_CPUINFO) += cpuinfo.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
new file mode 100644
index 0000000000..3d6a4ce648
--- /dev/null
+++ b/arch/mips/lib/bootm.c
@@ -0,0 +1,43 @@
+#include <boot.h>
+#include <common.h>
+#include <init.h>
+#include <fs.h>
+#include <errno.h>
+#include <binfmt.h>
+
+#include <asm/byteorder.h>
+
+static int do_bootm_barebox(struct image_data *data)
+{
+ void (*barebox)(void);
+
+ barebox = read_file(data->os_file, NULL);
+ if (!barebox)
+ return -EINVAL;
+
+ shutdown_barebox();
+
+ barebox();
+
+ reset_cpu(0);
+}
+
+static struct image_handler barebox_handler = {
+ .name = "MIPS barebox",
+ .bootm = do_bootm_barebox,
+ .filetype = filetype_mips_barebox,
+};
+
+static struct binfmt_hook binfmt_barebox_hook = {
+ .type = filetype_mips_barebox,
+ .exec = "bootm",
+};
+
+static int mips_register_image_handler(void)
+{
+ register_image_handler(&barebox_handler);
+ binfmt_register(&binfmt_barebox_hook);
+
+ return 0;
+}
+late_initcall(mips_register_image_handler);
diff --git a/arch/mips/lib/c-r4k.c b/arch/mips/lib/c-r4k.c
new file mode 100644
index 0000000000..01b8665193
--- /dev/null
+++ b/arch/mips/lib/c-r4k.c
@@ -0,0 +1,97 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
+ * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/mipsregs.h>
+#include <asm/cpu.h>
+#include <asm/cpu-info.h>
+#include <asm/bitops.h>
+
+void r4k_cache_init(void);
+
+static void probe_pcache(void)
+{
+ struct cpuinfo_mips *c = &current_cpu_data;
+ unsigned int icache_size, dcache_size;
+ unsigned int config = read_c0_config();
+ unsigned long config1;
+ unsigned int lsize;
+
+ switch (c->cputype) {
+
+ default:
+ /*
+ * So we seem to be a MIPS32 or MIPS64 CPU
+ * So let's probe the I-cache ...
+ */
+ config1 = read_c0_config1();
+
+ if ((lsize = ((config1 >> 19) & 7)))
+ c->icache.linesz = 2 << lsize;
+ else
+ c->icache.linesz = lsize;
+ c->icache.sets = 64 << ((config1 >> 22) & 7);
+ c->icache.ways = 1 + ((config1 >> 16) & 7);
+
+ icache_size = c->icache.sets *
+ c->icache.ways *
+ c->icache.linesz;
+ c->icache.waybit = __ffs(icache_size/c->icache.ways);
+
+ if (config & 0x8) /* VI bit */
+ c->icache.flags |= MIPS_CACHE_VTAG;
+
+ /*
+ * Now probe the MIPS32 / MIPS64 data cache.
+ */
+ c->dcache.flags = 0;
+
+ if ((lsize = ((config1 >> 10) & 7)))
+ c->dcache.linesz = 2 << lsize;
+ else
+ c->dcache.linesz= lsize;
+ c->dcache.sets = 64 << ((config1 >> 13) & 7);
+ c->dcache.ways = 1 + ((config1 >> 7) & 7);
+
+ dcache_size = c->dcache.sets *
+ c->dcache.ways *
+ c->dcache.linesz;
+ c->dcache.waybit = __ffs(dcache_size/c->dcache.ways);
+
+ c->options |= MIPS_CPU_PREFETCH;
+ break;
+ }
+
+ /* compute a couple of other cache variables */
+ c->icache.waysize = icache_size / c->icache.ways;
+ c->dcache.waysize = dcache_size / c->dcache.ways;
+
+ c->icache.sets = c->icache.linesz ?
+ icache_size / (c->icache.linesz * c->icache.ways) : 0;
+ c->dcache.sets = c->dcache.linesz ?
+ dcache_size / (c->dcache.linesz * c->dcache.ways) : 0;
+
+ /*
+ * R10000 and R12000 P-caches are odd in a positive way. They're 32kB
+ * 2-way virtually indexed so normally would suffer from aliases. So
+ * normally they'd suffer from aliases but magic in the hardware deals
+ * with that for us so we don't need to take care ourselves.
+ */
+ switch (c->cputype) {
+ default:
+ if (c->dcache.waysize > PAGE_SIZE)
+ c->dcache.flags |= MIPS_CACHE_ALIASES;
+ }
+}
+
+void r4k_cache_init(void)
+{
+ probe_pcache();
+}
diff --git a/arch/mips/lib/cpu-probe.c b/arch/mips/lib/cpu-probe.c
new file mode 100644
index 0000000000..de45421df7
--- /dev/null
+++ b/arch/mips/lib/cpu-probe.c
@@ -0,0 +1,143 @@
+/*
+ * Processor capabilities determination functions.
+ *
+ * Copyright (C) xxxx the Anonymous
+ * Copyright (C) 1994 - 2006 Ralf Baechle
+ * Copyright (C) 2003, 2004 Maciej W. Rozycki
+ * Copyright (C) 2001, 2004 MIPS Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <common.h>
+#include <asm/mipsregs.h>
+#include <asm/cpu-info.h>
+#include <asm/cpu.h>
+
+const char *__cpu_name;
+struct cpuinfo_mips cpu_data[1];
+
+static char unknown_isa[] = KERN_ERR \
+ "Unsupported ISA type, c0.config0: %d.";
+
+static inline unsigned int decode_config0(struct cpuinfo_mips *c)
+{
+ unsigned int config0;
+ int isa;
+
+ config0 = read_c0_config();
+
+ if (((config0 & MIPS_CONF_MT) >> 7) == 1)
+ c->options |= MIPS_CPU_TLB;
+ isa = (config0 & MIPS_CONF_AT) >> 13;
+ switch (isa) {
+ case 0:
+ switch ((config0 & MIPS_CONF_AR) >> 10) {
+ case 0:
+ c->isa_level = MIPS_CPU_ISA_M32R1;
+ break;
+ case 1:
+ c->isa_level = MIPS_CPU_ISA_M32R2;
+ break;
+ default:
+ goto unknown;
+ }
+ break;
+ case 2:
+ switch ((config0 & MIPS_CONF_AR) >> 10) {
+ case 0:
+ c->isa_level = MIPS_CPU_ISA_M64R1;
+ break;
+ case 1:
+ c->isa_level = MIPS_CPU_ISA_M64R2;
+ break;
+ default:
+ goto unknown;
+ }
+ break;
+ default:
+ goto unknown;
+ }
+
+ return config0 & MIPS_CONF_M;
+
+unknown:
+ panic(unknown_isa, config0);
+}
+
+static void decode_configs(struct cpuinfo_mips *c)
+{
+ int ok;
+
+ /* MIPS32 or MIPS64 compliant CPU. */
+ c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
+ MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
+
+ c->scache.flags = MIPS_CACHE_NOT_PRESENT;
+
+ ok = decode_config0(c); /* Read Config registers. */
+ BUG_ON(!ok); /* Arch spec violation! */
+}
+
+static inline void cpu_probe_mips(struct cpuinfo_mips *c)
+{
+ decode_configs(c);
+ switch (c->processor_id & 0xff00) {
+ case PRID_IMP_24K:
+ case PRID_IMP_24KE:
+ c->cputype = CPU_24K;
+ __cpu_name = "MIPS 24Kc";
+ break;
+ }
+}
+
+static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
+{
+ decode_configs(c);
+ switch (c->processor_id & 0xff00) {
+ case PRID_IMP_BMIPS3300:
+ c->cputype = CPU_BMIPS3300;
+ __cpu_name = "Broadcom BMIPS3300";
+ break;
+ }
+}
+
+static inline void cpu_probe_ingenic(struct cpuinfo_mips *c)
+{
+ decode_configs(c);
+ /* JZRISC does not implement the CP0 counter. */
+ c->options &= ~MIPS_CPU_COUNTER;
+ switch (c->processor_id & 0xff00) {
+ case PRID_IMP_JZRISC:
+ c->cputype = CPU_JZRISC;
+ __cpu_name = "Ingenic JZRISC";
+ break;
+ default:
+ panic("Unknown Ingenic Processor ID!");
+ break;
+ }
+}
+
+void cpu_probe(void)
+{
+ struct cpuinfo_mips *c = &current_cpu_data;
+
+ c->processor_id = PRID_IMP_UNKNOWN;
+ c->fpu_id = FPIR_IMP_NONE;
+ c->cputype = CPU_UNKNOWN;
+
+ c->processor_id = read_c0_prid();
+ switch (c->processor_id & 0xff0000) {
+ case PRID_COMP_MIPS:
+ cpu_probe_mips(c);
+ break;
+ case PRID_COMP_BROADCOM:
+ cpu_probe_broadcom(c);
+ break;
+ case PRID_COMP_INGENIC:
+ cpu_probe_ingenic(c);
+ break;
+ }
+}
diff --git a/arch/mips/lib/cpuinfo.c b/arch/mips/lib/cpuinfo.c
index fc8fb00f0f..c0bb87a5fe 100644
--- a/arch/mips/lib/cpuinfo.c
+++ b/arch/mips/lib/cpuinfo.c
@@ -23,11 +23,34 @@
#include <common.h>
#include <command.h>
#include <asm/mipsregs.h>
+#include <asm/cpu-info.h>
+
+static char *way_string[] = { NULL, "direct mapped", "2-way",
+ "3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
+};
static int do_cpuinfo(int argc, char *argv[])
{
- printf("CP0_PRID = 0x%08x\n", read_c0_prid());
- printf("CP0_CONFIG = 0x%08x\n", read_c0_config());
+ unsigned int icache_size, dcache_size;
+ struct cpuinfo_mips *c = &current_cpu_data;
+
+ printk(KERN_INFO "CPU revision is: %08x (%s)\n",
+ current_cpu_data.processor_id, __cpu_name);
+
+ icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
+ dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
+
+ printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
+ icache_size >> 10,
+ c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",
+ way_string[c->icache.ways], c->icache.linesz);
+
+ printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
+ dcache_size >> 10, way_string[c->dcache.ways],
+ (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
+ (c->dcache.flags & MIPS_CACHE_ALIASES) ?
+ "cache aliases" : "no aliases",
+ c->dcache.linesz);
return 0;
}
diff --git a/arch/mips/mach-malta/include/mach/debug_ll.h b/arch/mips/mach-malta/include/mach/debug_ll.h
index ccc9d9bfc7..9de469ba86 100644
--- a/arch/mips/mach-malta/include/mach/debug_ll.h
+++ b/arch/mips/mach-malta/include/mach/debug_ll.h
@@ -24,17 +24,8 @@
#ifndef __INCLUDE_ARCH_DEBUG_LL_H__
#define __INCLUDE_ARCH_DEBUG_LL_H__
-#include <io.h>
#include <mach/hardware.h>
-#define rbr 0
-#define lsr 5
-#define LSR_THRE 0x20 /* Xmit holding register empty */
-
-static __inline__ void putc(char ch)
-{
- while (!(__raw_readb(DEBUG_LL_UART_ADDR + lsr) & LSR_THRE));
- __raw_writeb(ch, DEBUG_LL_UART_ADDR + rbr);
-}
+#include <debug_ll_ns16550.h>
#endif /* __INCLUDE_ARCH_DEBUG_LL_H__ */
diff --git a/arch/mips/mach-malta/include/mach/hardware.h b/arch/mips/mach-malta/include/mach/hardware.h
index f827cc3557..ddeb1b7dd0 100644
--- a/arch/mips/mach-malta/include/mach/hardware.h
+++ b/arch/mips/mach-malta/include/mach/hardware.h
@@ -22,6 +22,7 @@
#define __INCLUDE_ARCH_HARDWARE_H__
#define DEBUG_LL_UART_ADDR 0xb00003f8
+#define DEBUG_LL_UART_SHIFT 0
/*
* Reset register.
diff --git a/arch/mips/mach-mips.dox b/arch/mips/mach-mips.dox
index 9bcec13a3d..750a45154d 100644
--- a/arch/mips/mach-mips.dox
+++ b/arch/mips/mach-mips.dox
@@ -58,4 +58,8 @@ ISBN-13: 978-0120884216
@subsection mach_bcm47xx_info BCM47xx-based boards
@li @subpage dev_bcm47xx_mach
+
+@subsection mach_xburst_info XBurst-based boards
+
+@li @subpage dev_xburst_mach
*/
diff --git a/arch/mips/mach-xburst/Kconfig b/arch/mips/mach-xburst/Kconfig
new file mode 100644
index 0000000000..60e411cce6
--- /dev/null
+++ b/arch/mips/mach-xburst/Kconfig
@@ -0,0 +1,21 @@
+if MACH_MIPS_XBURST
+
+config ARCH_TEXT_BASE
+ hex
+ default 0xa0800000
+
+config CPU_JZ4755
+ bool
+
+choice
+ prompt "Board type"
+
+config BOARD_RZX50
+ bool "Ritmix RZX-50"
+ select CPU_JZ4755
+
+endchoice
+
+source arch/mips/boards/rzx50/Kconfig
+
+endif
diff --git a/arch/mips/mach-xburst/Makefile b/arch/mips/mach-xburst/Makefile
new file mode 100644
index 0000000000..e5634ba9cc
--- /dev/null
+++ b/arch/mips/mach-xburst/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_CPU_JZ4755) += csrc-jz4750.o reset-jz4750.o
diff --git a/arch/mips/mach-xburst/csrc-jz4750.c b/arch/mips/mach-xburst/csrc-jz4750.c
new file mode 100644
index 0000000000..f625b703a1
--- /dev/null
+++ b/arch/mips/mach-xburst/csrc-jz4750.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2012 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+/**
+ * @file
+ * @brief Clocksource based on JZ475x OS timer
+ */
+
+#include <init.h>
+#include <clock.h>
+#include <io.h>
+#include <mach/jz4750d_regs.h>
+
+#define JZ_TIMER_CLOCK 40000
+
+static uint64_t jz4750_cs_read(void)
+{
+ return (uint64_t)__raw_readl((void *)TCU_OSTCNT);
+}
+
+static struct clocksource jz4750_cs = {
+ .read = jz4750_cs_read,
+ .mask = CLOCKSOURCE_MASK(32),
+ .shift = 10,
+};
+
+static int clocksource_init(void)
+{
+ jz4750_cs.mult = clocksource_hz2mult(JZ_TIMER_CLOCK, jz4750_cs.shift);
+ init_clock(&jz4750_cs);
+
+ __raw_writel(TCU_OSTCSR_PRESCALE1 | TCU_OSTCSR_EXT_EN,
+ (void *)TCU_OSTCSR);
+ __raw_writel(0, (void *)TCU_OSTCNT);
+ __raw_writel(0xffffffff, (void *)TCU_OSTDR);
+
+ /* enable timer clock */
+ __raw_writel(TCU_TSCR_OSTSC, (void *)TCU_TSCR);
+ /* start counting up */
+ __raw_writel(TCU_TESR_OSTST, (void *)TCU_TESR);
+
+ return 0;
+}
+core_initcall(clocksource_init);
diff --git a/arch/mips/mach-xburst/include/mach/debug_ll.h b/arch/mips/mach-xburst/include/mach/debug_ll.h
new file mode 100644
index 0000000000..6e0cc931fb
--- /dev/null
+++ b/arch/mips/mach-xburst/include/mach/debug_ll.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2012 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __MACH_XBURST_DEBUG_LL__
+#define __MACH_XBURST_DEBUG_LL__
+
+/** @file
+ * This File contains declaration for early output support
+ */
+#include <board/debug_ll.h>
+#include <debug_ll_ns16550.h>
+
+#endif /* __MACH_XBURST_DEBUG_LL__ */
diff --git a/arch/mips/mach-xburst/include/mach/jz4750d_regs.h b/arch/mips/mach-xburst/include/mach/jz4750d_regs.h
new file mode 100644
index 0000000000..717493ba5c
--- /dev/null
+++ b/arch/mips/mach-xburst/include/mach/jz4750d_regs.h
@@ -0,0 +1,80 @@
+/*
+ * based on linux/include/asm-mips/mach-jz4750d/regs.h
+ *
+ * JZ4750D register definition.
+ *
+ * Copyright (C) 2008 Ingenic Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __JZ4750D_REGS_H__
+#define __JZ4750D_REGS_H__
+
+#define TCU_BASE 0xb0002000
+#define WDT_BASE 0xb0002000
+#define UART1_BASE 0xb0031000
+
+/*************************************************************************
+ * TCU (Timer Counter Unit)
+ *************************************************************************/
+#define TCU_TESR (TCU_BASE + 0x14) /* Timer Counter Enable Set Register */
+ #define TCU_TESR_OSTST (1 << 15)
+ #define TCU_TESR_TCST5 (1 << 5)
+ #define TCU_TESR_TCST4 (1 << 4)
+ #define TCU_TESR_TCST3 (1 << 3)
+ #define TCU_TESR_TCST2 (1 << 2)
+ #define TCU_TESR_TCST1 (1 << 1)
+ #define TCU_TESR_TCST0 (1 << 0)
+
+#define TCU_TSCR (TCU_BASE + 0x3c) /* Timer Stop Clear Register */
+ #define TCU_TSCR_WDTSC (1 << 16)
+ #define TCU_TSCR_OSTSC (1 << 15)
+ #define TCU_TSCR_STPC5 (1 << 5)
+ #define TCU_TSCR_STPC4 (1 << 4)
+ #define TCU_TSCR_STPC3 (1 << 3)
+ #define TCU_TSCR_STPC2 (1 << 2)
+ #define TCU_TSCR_STPC1 (1 << 1)
+ #define TCU_TSCR_STPC0 (1 << 0)
+
+/* Operating System Timer */
+#define TCU_OSTDR (TCU_BASE + 0xe0)
+#define TCU_OSTCNT (TCU_BASE + 0xe8)
+#define TCU_OSTCSR (TCU_BASE + 0xec)
+#define TCU_OSTCSR_PRESCALE_BIT 3
+#define TCU_OSTCSR_PRESCALE_MASK (0x7 << TCU_OSTCSR_PRESCALE_BIT)
+ #define TCU_OSTCSR_PRESCALE1 (0x0 << TCU_OSTCSR_PRESCALE_BIT)
+ #define TCU_OSTCSR_PRESCALE4 (0x1 << TCU_OSTCSR_PRESCALE_BIT)
+ #define TCU_OSTCSR_PRESCALE16 (0x2 << TCU_OSTCSR_PRESCALE_BIT)
+ #define TCU_OSTCSR_PRESCALE64 (0x3 << TCU_OSTCSR_PRESCALE_BIT)
+ #define TCU_OSTCSR_PRESCALE256 (0x4 << TCU_OSTCSR_PRESCALE_BIT)
+ #define TCU_OSTCSR_PRESCALE1024 (0x5 << TCU_OSTCSR_PRESCALE_BIT)
+#define TCU_OSTCSR_EXT_EN (1 << 2) /* select extal as the timer clock input */
+#define TCU_OSTCSR_RTC_EN (1 << 1) /* select rtcclk as the timer clock input */
+#define TCU_OSTCSR_PCK_EN (1 << 0) /* select pclk as the timer clock input */
+
+/*************************************************************************
+ * WDT (WatchDog Timer)
+ *************************************************************************/
+#define WDT_TDR (WDT_BASE + 0x00)
+#define WDT_TCER (WDT_BASE + 0x04)
+#define WDT_TCNT (WDT_BASE + 0x08)
+#define WDT_TCSR (WDT_BASE + 0x0c)
+
+#define WDT_TCSR_PRESCALE_BIT 3
+#define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT)
+ #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT)
+ #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT)
+ #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT)
+ #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT)
+ #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT)
+ #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT)
+#define WDT_TCSR_EXT_EN (1 << 2)
+#define WDT_TCSR_RTC_EN (1 << 1)
+#define WDT_TCSR_PCK_EN (1 << 0)
+
+#define WDT_TCER_TCEN (1 << 0)
+
+#endif /* __JZ4750D_REGS_H__ */
diff --git a/arch/mips/mach-xburst/mach-xburst.dox b/arch/mips/mach-xburst/mach-xburst.dox
new file mode 100644
index 0000000000..a5e524d25c
--- /dev/null
+++ b/arch/mips/mach-xburst/mach-xburst.dox
@@ -0,0 +1,7 @@
+/** @page dev_xburst_mach XBurst in barebox
+
+@section xburst_boards XBurst-based boards
+
+@li @subpage rzx50
+
+*/
diff --git a/arch/mips/mach-xburst/reset-jz4750.c b/arch/mips/mach-xburst/reset-jz4750.c
new file mode 100644
index 0000000000..3540ca92c7
--- /dev/null
+++ b/arch/mips/mach-xburst/reset-jz4750.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2012 Antony Pavlov <antonynpavlov@gmail.com>
+ *
+ * This file is part of barebox.
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+/**
+ * @file
+ * @brief Resetting an JZ4755-based board
+ */
+
+#include <common.h>
+#include <io.h>
+#include <mach/jz4750d_regs.h>
+
+#define JZ_EXTAL 24000000
+
+void __noreturn reset_cpu(ulong addr)
+{
+ __raw_writew(WDT_TCSR_PRESCALE4 | WDT_TCSR_EXT_EN, (u16 *)WDT_TCSR);
+ __raw_writew(0, (u16 *)WDT_TCNT);
+
+ /* reset after 4ms */
+ __raw_writew(JZ_EXTAL / 1000, (u16 *)WDT_TDR);
+ /* enable wdt clock */
+ __raw_writel(TCU_TSCR_WDTSC, (u32 *)TCU_TSCR);
+ /* start wdt */
+ __raw_writeb(WDT_TCER_TCEN, (u8 *)WDT_TCER);
+
+ unreachable();
+}
+EXPORT_SYMBOL(reset_cpu);
diff --git a/arch/nios2/boards/generic/generic.c b/arch/nios2/boards/generic/generic.c
index 758e75a812..b51b94afbf 100644
--- a/arch/nios2/boards/generic/generic.c
+++ b/arch/nios2/boards/generic/generic.c
@@ -40,8 +40,8 @@ static int generic_devices_init(void)
register_device(&mac_dev);
/*register_device(&epcs_flash_device);*/
- devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
- devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
+ devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0");
+ devfs_add_partition("nor0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
diff --git a/arch/nios2/lib/bootm.c b/arch/nios2/lib/bootm.c
index 1cd43c81af..5713a893cb 100644
--- a/arch/nios2/lib/bootm.c
+++ b/arch/nios2/lib/bootm.c
@@ -39,7 +39,7 @@
static int do_bootm_linux(struct image_data *idata)
{
void (*kernel)(int, int, int, const char *);
- const char *commandline = getenv ("bootargs");
+ const char *commandline = linux_bootargs_get();
if (!idata->os_res)
return -EINVAL;
diff --git a/arch/ppc/Kconfig b/arch/ppc/Kconfig
index 164598f5de..d12406522e 100644
--- a/arch/ppc/Kconfig
+++ b/arch/ppc/Kconfig
@@ -12,9 +12,12 @@ choice
config ARCH_MPC5XXX
bool "Freescale MPC5xxx"
+config ARCH_MPC85XX
+ bool "Freescale MPC85xx"
endchoice
source arch/ppc/mach-mpc5xxx/Kconfig
+source arch/ppc/mach-mpc85xx/Kconfig
source common/Kconfig
source commands/Kconfig
source net/Kconfig
diff --git a/arch/ppc/Makefile b/arch/ppc/Makefile
index 2d9e47fe56..f0322a26b4 100644
--- a/arch/ppc/Makefile
+++ b/arch/ppc/Makefile
@@ -7,9 +7,17 @@ ifdef CONFIG_RELOCATABLE
CPPFLAGS += -fPIC -mrelocatable
endif
+ifdef CONFIG_MPC85xx
+CPPFLAGS += -Wa,-me500x2 -msoft-float -mno-string
+endif
board-$(CONFIG_MACH_PHYCORE_MPC5200B_TINY) := pcm030
+board-$(CONFIG_P2020RDB) := freescale-p2020rdb
+
machine-$(CONFIG_ARCH_MPC5200) := mpc5xxx
+machine-$(CONFIG_ARCH_MPC85XX) := mpc85xx
+
+cpu-$(CONFIG_ARCH_MPC85XX) := 85xx
TEXT_BASE = $(CONFIG_TEXT_BASE)
diff --git a/arch/ppc/boards/freescale-p2020rdb/Makefile b/arch/ppc/boards/freescale-p2020rdb/Makefile
new file mode 100644
index 0000000000..141b6806e2
--- /dev/null
+++ b/arch/ppc/boards/freescale-p2020rdb/Makefile
@@ -0,0 +1,4 @@
+obj-y += p2020rdb.o
+obj-y += law.o
+obj-y += tlb.o
+extra-y += barebox.lds
diff --git a/arch/ppc/boards/freescale-p2020rdb/barebox.lds.S b/arch/ppc/boards/freescale-p2020rdb/barebox.lds.S
new file mode 100644
index 0000000000..cfccea94df
--- /dev/null
+++ b/arch/ppc/boards/freescale-p2020rdb/barebox.lds.S
@@ -0,0 +1,144 @@
+/*
+ * Copyright 2012 GE Intelligent Platforms, Inc.
+ * Copyright 2007-2009, 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-generic/barebox.lds.h>
+
+#define RESET_VECTOR_ADDRESS 0xeffffffc
+
+OUTPUT_ARCH("powerpc")
+
+PHDRS
+{
+ text PT_LOAD;
+ bss PT_LOAD;
+}
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = TEXT_BASE;
+
+ .text :
+ {
+ *(.text*)
+ } :text
+
+ _etext = .;
+ PROVIDE (etext = .);
+
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ } :text
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ _GOT2_TABLE_ = .;
+ KEEP(*(.got2))
+ KEEP(*(.got))
+ PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data*)
+ *(.data1*)
+ *(.sdata*)
+ *(.sdata2*)
+ *(.dynamic*)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __barebox_cmd_start = .;
+ .barebox_cmd : { BAREBOX_CMDS }
+ __barebox_cmd_end = .;
+
+ __barebox_initcalls_start = .;
+ .barebox_initcalls : { INITCALLS }
+ __barebox_initcalls_end = .;
+ __initcall_entries = (__barebox_initcalls_end - __barebox_initcalls_start)>>2;
+
+ __usymtab_start = .;
+ __usymtab : { BAREBOX_SYMS }
+ __usymtab_end = .;
+
+ __early_init_data_begin = .;
+ .early_init_data : { *(.early_init_data) }
+ __early_init_data_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __init_size = __init_end - _start;
+
+ .bootpg RESET_VECTOR_ADDRESS - 0xffc :
+ {
+ _text = .;
+ _stext = .;
+ arch/ppc/cpu-85xx/start.o (.bootpg)
+ } :text = 0xffff
+
+ .resetvec RESET_VECTOR_ADDRESS :
+ {
+ arch/ppc/cpu-85xx/resetvec.o (.resetvec)
+ } :text = 0xffff
+
+ . = RESET_VECTOR_ADDRESS + 0x4;
+
+ . = 0x10000;
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss*) *(.scommon*)
+ *(.dynbss*)
+ *(.bss*)
+ *(COMMON)
+ } :bss
+
+ . = ALIGN(4);
+ __bss_stop = .;
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/arch/ppc/boards/freescale-p2020rdb/config.h b/arch/ppc/boards/freescale-p2020rdb/config.h
new file mode 100644
index 0000000000..c780747d00
--- /dev/null
+++ b/arch/ppc/boards/freescale-p2020rdb/config.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright 2012 GE Intelligent Platforms, Inc.
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * P2020RDB board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+#endif
+#define CFG_SYS_CLK_FREQ get_board_sys_clk(0)
+#define CFG_DDR_CLK_FREQ 66666666
+
+#define CFG_BTB /* toggle branch predition */
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT 0xff700000
+
+#define CFG_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS CFG_CCSRBAR
+
+#define CFG_IMMR CFG_CCSRBAR
+
+/* DDR Setup */
+
+#define CFG_CHIP_SELECTS_PER_CTRL 1
+
+#define CFG_SDRAM_BASE 0x00000000
+
+/* These timings are adjusted for a 667Mhz clock. */
+#define CFG_SYS_DDR_CS0_BNDS 0x0000003f /* 1GB */
+#define CFG_SYS_DDR_CS0_CONFIG 0x80014202
+#define CFG_SYS_DDR_TIMING_3 0x00030000
+#define CFG_SYS_DDR_TIMING_0 0x55770802
+#define CFG_SYS_DDR_TIMING_1 0x5f599543
+#define CFG_SYS_DDR_TIMING_2 0x0fa074d1
+
+#define CFG_SYS_DDR_CONTROL 0xc3000000
+#define CFG_SYS_DDR_CONTROL2 0x24401000
+#define CFG_SYS_DDR_MODE_1 0x00040852
+#define CFG_SYS_DDR_MODE_2 0x00000000
+#define CFG_SYS_MD_CNTL 0x00000000
+#define CFG_SYS_DDR_INTERVAL 0x0a280100
+
+#define CFG_SYS_DDR_DATA_INIT 0xdeadbeef
+#define CFG_SYS_DDR_CLK_CTRL 0x03000000
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000 0x3fff_ffff DDR 1G cacheablen
+ *
+ * Localbus non-cacheable
+ * 0xef00_0000 0xefff_ffff FLASH 16M non-cacheable
+ * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
+ */
+
+/*
+ * Local Bus Definitions
+ */
+#define CFG_FLASH_BASE 0xef000000
+#define CFG_FLASH_BASE_PHYS CFG_FLASH_BASE
+
+#define CFG_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
+/* Leave 256 bytes for global data */
+#define CFG_INIT_SP_OFFSET (0x00004000 - 256)
+
+#define CFG_BR0_PRELIM (BR_PHYS_ADDR(CFG_FLASH_BASE_PHYS) | \
+ BR_PS_16 | BR_V) /* NOR Base Address */
+#define CFG_OR0_PRELIM 0xff000ff7 /* NOR Options */
+
+#endif /* __CONFIG_H */
diff --git a/arch/ppc/boards/freescale-p2020rdb/law.c b/arch/ppc/boards/freescale-p2020rdb/law.c
new file mode 100644
index 0000000000..394c512210
--- /dev/null
+++ b/arch/ppc/boards/freescale-p2020rdb/law.c
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ FSL_SET_LAW(CFG_FLASH_BASE_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c b/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c
new file mode 100644
index 0000000000..20897cbaee
--- /dev/null
+++ b/arch/ppc/boards/freescale-p2020rdb/p2020rdb.c
@@ -0,0 +1,230 @@
+/*
+ * Copyright 2012 GE Intelligent Platforms, Inc.
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <init.h>
+#include <driver.h>
+#include <ns16550.h>
+#include <types.h>
+#include <partition.h>
+#include <memory.h>
+#include <asm/cache.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_law.h>
+#include <mach/mpc85xx.h>
+#include <mach/mmu.h>
+#include <mach/immap_85xx.h>
+#include <mach/clocks.h>
+#include <mach/early_udelay.h>
+
+#define VSC7385_RST_SET 0x00080000
+#define SLIC_RST_SET 0x00040000
+#define SGMII_PHY_RST_SET 0x00020000
+#define PCIE_RST_SET 0x00010000
+#define RGMII_PHY_RST_SET 0x02000000
+
+#define USB_RST_CLR 0x04000000
+
+#define GPIO_DIR 0x060f0000
+
+#define BOARD_PERI_RST_SET (VSC7385_RST_SET | SLIC_RST_SET | \
+ SGMII_PHY_RST_SET | PCIE_RST_SET | \
+ RGMII_PHY_RST_SET)
+
+#define SYSCLK_MASK 0x00200000
+#define BOARDREV_MASK 0x10100000
+#define BOARDREV_B 0x10100000
+#define BOARDREV_C 0x00100000
+#define BOARDREV_D 0x00000000
+
+#define SYSCLK_66 66666666
+#define SYSCLK_50 50000000
+#define SYSCLK_100 100000000
+
+static int devices_init(void)
+{
+ add_cfi_flash_device(-1, CFG_FLASH_BASE, 16 << 20, 0);
+
+ devfs_add_partition("nor0", 0xf80000, 0x80000, DEVFS_PARTITION_FIXED,
+ "self0");
+ return 0;
+}
+
+device_initcall(devices_init);
+
+static struct NS16550_plat serial_plat = {
+ .clock = 0,
+ .shift = 0,
+};
+
+static int p2020_console_init(void)
+{
+ serial_plat.clock = fsl_get_bus_freq(0);
+
+ add_ns16550_device(-1, 0xffe04500, 16, IORESOURCE_MEM_8BIT,
+ &serial_plat);
+ return 0;
+}
+
+console_initcall(p2020_console_init);
+
+static int mem_init(void)
+{
+ barebox_add_memory_bank("ram0", 0x0, 1024 << 20);
+
+ return 0;
+}
+mem_initcall(mem_init);
+
+/*
+ * fixed_sdram: fixed sdram settings.
+ */
+phys_size_t fixed_sdram(void)
+{
+ void __iomem *regs = (void __iomem *)(MPC85xx_DDR_ADDR);
+ int sdram_cfg = (SDRAM_CFG_MEM_EN | SDRAM_CFG_SREN |
+ SDRAM_CFG_SDRAM_TYPE_DDR2);
+ phys_size_t dram_size;
+
+ /* If already enabled (running from RAM), get out */
+ if (in_be32(regs + DDR_OFF(SDRAM_CFG)) & SDRAM_CFG_MEM_EN)
+ return fsl_get_effective_memsize();
+
+ out_be32(regs + DDR_OFF(CS0_BNDS), CFG_SYS_DDR_CS0_BNDS);
+ out_be32(regs + DDR_OFF(CS0_CONFIG), CFG_SYS_DDR_CS0_CONFIG);
+ out_be32(regs + DDR_OFF(TIMING_CFG_3), CFG_SYS_DDR_TIMING_3);
+ out_be32(regs + DDR_OFF(TIMING_CFG_0), CFG_SYS_DDR_TIMING_0);
+ out_be32(regs + DDR_OFF(TIMING_CFG_1), CFG_SYS_DDR_TIMING_1);
+ out_be32(regs + DDR_OFF(TIMING_CFG_2), CFG_SYS_DDR_TIMING_2);
+ out_be32(regs + DDR_OFF(SDRAM_CFG_2), CFG_SYS_DDR_CONTROL2);
+ out_be32(regs + DDR_OFF(SDRAM_MODE), CFG_SYS_DDR_MODE_1);
+ out_be32(regs + DDR_OFF(SDRAM_MODE_2), CFG_SYS_DDR_MODE_2);
+ out_be32(regs + DDR_OFF(SDRAM_MD_CNTL), CFG_SYS_MD_CNTL);
+ /* Basic refresh rate (7.8us),high temp is 3.9us */
+ out_be32(regs + DDR_OFF(SDRAM_INTERVAL),
+ CFG_SYS_DDR_INTERVAL);
+ out_be32(regs + DDR_OFF(SDRAM_DATA_INIT),
+ CFG_SYS_DDR_DATA_INIT);
+ out_be32(regs + DDR_OFF(SDRAM_CLK_CNTL),
+ CFG_SYS_DDR_CLK_CTRL);
+
+ out_be32(regs + DDR_OFF(SDRAM_INIT_ADDR), 0);
+ out_be32(regs + DDR_OFF(SDRAM_INIT_ADDR_EXT), 0);
+ /*
+ * Wait 200us for the DDR clock to stabilize.
+ */
+ early_udelay(200);
+ asm volatile ("sync;isync");
+
+ out_be32(regs + DDR_OFF(SDRAM_CFG), sdram_cfg);
+
+ dram_size = fsl_get_effective_memsize();
+ if (fsl_set_ddr_laws(0, dram_size, LAW_TRGT_IF_DDR) < 0)
+ return 0;
+
+ return dram_size;
+}
+
+unsigned long get_board_sys_clk(ulong dummy)
+{
+ u32 val_gpdat, sysclk_gpio, board_rev_gpio;
+ void __iomem *gpio_regs = (void __iomem *)MPC85xx_GPIO_ADDR;
+
+ val_gpdat = in_be32(gpio_regs + MPC85xx_GPIO_GPDAT);
+ sysclk_gpio = val_gpdat & SYSCLK_MASK;
+ board_rev_gpio = val_gpdat & BOARDREV_MASK;
+
+ if (board_rev_gpio == BOARDREV_C) {
+ if (sysclk_gpio == 0)
+ return SYSCLK_66;
+ else
+ return SYSCLK_100;
+ } else if (board_rev_gpio == BOARDREV_B) {
+ if (sysclk_gpio == 0)
+ return SYSCLK_66;
+ else
+ return SYSCLK_50;
+ } else if (board_rev_gpio == BOARDREV_D) {
+ if (sysclk_gpio == 0)
+ return SYSCLK_66;
+ else
+ return SYSCLK_100;
+ }
+ return 0;
+}
+
+static void checkboard(void)
+{
+ u32 val_gpdat, board_rev_gpio;
+ void __iomem *gpio_regs = (void __iomem *)MPC85xx_GPIO_ADDR;
+
+ val_gpdat = in_be32(gpio_regs + MPC85xx_GPIO_GPDAT);
+ board_rev_gpio = val_gpdat & BOARDREV_MASK;
+
+ if ((board_rev_gpio != BOARDREV_C) && (board_rev_gpio != BOARDREV_B) &&
+ (board_rev_gpio != BOARDREV_D))
+ panic("Unexpected Board REV %x detected!!\n", board_rev_gpio);
+
+ setbits_be32((gpio_regs + MPC85xx_GPIO_GPDIR), GPIO_DIR);
+
+ /*
+ * Bringing the following peripherals out of reset via GPIOs
+ * 0 = reset and 1 = out of reset
+ * GPIO12 - Reset to Ethernet Switch
+ * GPIO13 - Reset to SLIC/SLAC devices
+ * GPIO14 - Reset to SGMII_PHY_N
+ * GPIO15 - Reset to PCIe slots
+ * GPIO6 - Reset to RGMII PHY
+ * GPIO5 - Reset to USB3300 devices 1 = reset and 0 = out of reset
+ */
+ clrsetbits_be32((gpio_regs + MPC85xx_GPIO_GPDAT), USB_RST_CLR,
+ BOARD_PERI_RST_SET);
+}
+
+static int board_init_r(void)
+{
+ const unsigned int flashbase = CFG_FLASH_BASE;
+ const u8 flash_esel = e500_find_tlb_idx((void *)flashbase, 1);
+
+ checkboard();
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* invalidate existing TLB entry for flash */
+ e500_disable_tlb(flash_esel);
+
+ /*
+ * Remap Boot flash region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+ e500_set_tlb(1, flashbase, CFG_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_16M, 1);
+
+ fsl_l2_cache_init();
+
+ return 0;
+}
+core_initcall(board_init_r);
diff --git a/arch/ppc/boards/freescale-p2020rdb/tlb.c b/arch/ppc/boards/freescale-p2020rdb/tlb.c
new file mode 100644
index 0000000000..5f3b4a7ec7
--- /dev/null
+++ b/arch/ppc/boards/freescale-p2020rdb/tlb.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mach/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ FSL_SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ FSL_SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + (4 * 1024),
+ CFG_INIT_RAM_ADDR + (4 * 1024),
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ FSL_SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + (8 * 1024),
+ CFG_INIT_RAM_ADDR + (8 * 1024),
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ FSL_SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + (12 * 1024),
+ CFG_INIT_RAM_ADDR + (12 * 1024),
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+ FSL_SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+
+ /* *I*G* - CCSRBAR */
+ FSL_SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_1M, 1),
+
+ /* W**G* - Flash/promjet, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ FSL_SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_16M, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/arch/ppc/boards/pcm030/pcm030.c b/arch/ppc/boards/pcm030/pcm030.c
index 36e80a10eb..ba6aa43182 100644
--- a/arch/ppc/boards/pcm030/pcm030.c
+++ b/arch/ppc/boards/pcm030/pcm030.c
@@ -62,8 +62,8 @@ static int devices_init (void)
if (ret)
return 0;
- devfs_add_partition("nor0", s.st_size - SZ_1M, SZ_512K, PARTITION_FIXED, "self0");
- devfs_add_partition("nor0", s.st_size - SZ_512K, SZ_512K, PARTITION_FIXED, "env0");
+ devfs_add_partition("nor0", s.st_size - SZ_1M, SZ_512K, DEVFS_PARTITION_FIXED, "self0");
+ devfs_add_partition("nor0", s.st_size - SZ_512K, SZ_512K, DEVFS_PARTITION_FIXED, "env0");
return 0;
}
diff --git a/arch/ppc/configs/p2020rdb_defconfig b/arch/ppc/configs/p2020rdb_defconfig
new file mode 100644
index 0000000000..f8a0687251
--- /dev/null
+++ b/arch/ppc/configs/p2020rdb_defconfig
@@ -0,0 +1,23 @@
+CONFIG_ARCH_MPC85XX=y
+CONFIG_P2020RDB=y
+CONFIG_P2020=y
+CONFIG_LONGHELP=y
+CONFIG_GLOB=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_GO=y
+CONFIG_FSL_ELBC=y
+CONFIG_DRIVER_CFI=y
+CONFIG_DRIVER_CFI_AMD=y
+CONFIG_DRIVER_CFI_INTEL=n
+CONFIG_DRIVER_CFI_BANK_WIDTH_1=n
+CONFIG_DRIVER_CFI_BANK_WIDTH_2=y
+CONFIG_DRIVER_CFI_BANK_WIDTH_4=n
+CONFIG_MTD=y
+CONFIG_MALLOC_SIZE=0x200000
+CONFIG_BAUDRATE=115200
+CONFIG_DRIVER_SERIAL_NS16550=y
+CONFIG_RELOCATABLE=y
diff --git a/arch/ppc/cpu-85xx/Makefile b/arch/ppc/cpu-85xx/Makefile
new file mode 100644
index 0000000000..3ee039778c
--- /dev/null
+++ b/arch/ppc/cpu-85xx/Makefile
@@ -0,0 +1,4 @@
+obj-y += traps.o
+obj-y += tlb.o
+extra-y += start.o
+extra-y += resetvec.o
diff --git a/arch/ppc/cpu-85xx/fixed_ivor.S b/arch/ppc/cpu-85xx/fixed_ivor.S
new file mode 100644
index 0000000000..a00a4355d3
--- /dev/null
+++ b/arch/ppc/cpu-85xx/fixed_ivor.S
@@ -0,0 +1,61 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * Kumar Gala <kumar.gala@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* This file is intended to be included by other asm code since
+ * we will want to execute this on both the primary core when
+ * it does a bootm and the secondary core's that get released
+ * out of the spin table.
+ */
+
+#define SET_IVOR(vector_number, vector_offset) \
+ li r3,vector_offset@l; \
+ mtspr SPRN_IVOR##vector_number,r3;
+
+#define SET_GIVOR(vector_number, vector_offset) \
+ li r3,vector_offset@l; \
+ mtspr SPRN_GIVOR##vector_number,r3;
+
+ SET_IVOR(0, 0x020) /* Critical Input */
+ SET_IVOR(1, 0x000) /* Machine Check */
+ SET_IVOR(2, 0x060) /* Data Storage */
+ SET_IVOR(3, 0x080) /* Instruction Storage */
+ SET_IVOR(4, 0x0a0) /* External Input */
+ SET_IVOR(5, 0x0c0) /* Alignment */
+ SET_IVOR(6, 0x0e0) /* Program */
+ SET_IVOR(7, 0x100) /* FP Unavailable */
+ SET_IVOR(8, 0x120) /* System Call */
+ SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */
+ SET_IVOR(10, 0x160) /* Decrementer */
+ SET_IVOR(11, 0x180) /* Fixed Interval Timer */
+ SET_IVOR(12, 0x1a0) /* Watchdog Timer */
+ SET_IVOR(13, 0x1c0) /* Data TLB Error */
+ SET_IVOR(14, 0x1e0) /* Instruction TLB Error */
+ SET_IVOR(15, 0x040) /* Debug */
+
+ /* e500v1 & e500v2 only */
+ SET_IVOR(32, 0x200) /* SPE Unavailable */
+ SET_IVOR(33, 0x220) /* Embedded FP Data */
+ SET_IVOR(34, 0x240) /* Embedded FP Round */
+
+ SET_IVOR(35, 0x260) /* Performance monitor */
diff --git a/arch/ppc/cpu-85xx/resetvec.S b/arch/ppc/cpu-85xx/resetvec.S
new file mode 100644
index 0000000000..29555d4a00
--- /dev/null
+++ b/arch/ppc/cpu-85xx/resetvec.S
@@ -0,0 +1,2 @@
+ .section .resetvec,"ax"
+ b _start_e500
diff --git a/arch/ppc/cpu-85xx/start.S b/arch/ppc/cpu-85xx/start.S
new file mode 100644
index 0000000000..b4a4a9b3de
--- /dev/null
+++ b/arch/ppc/cpu-85xx/start.S
@@ -0,0 +1,1085 @@
+/*
+ * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
+ * Copyright (C) 2003 Motorola,Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
+ *
+ * The processor starts at 0xfffffffc and the code is first executed in the
+ * last 4K page(0xfffff000-0xffffffff) in flash/rom.
+ */
+
+#include <config.h>
+#include <asm/config.h>
+
+#include <asm/processor.h>
+#include <asm/ppc_asm.tmpl>
+#include <asm/ppc_defs.h>
+#include <asm/cache.h>
+
+#include <mach/mpc85xx.h>
+#include <mach/mmu.h>
+
+#undef MSR_KERNEL
+#define MSR_KERNEL ( MSR_ME ) /* Machine Check */
+
+/*
+ * Set up GOT: Global Offset Table
+ *
+ * Use r12 to access the GOT
+ */
+ START_GOT
+ GOT_ENTRY(_GOT2_TABLE_)
+ GOT_ENTRY(_FIXUP_TABLE_)
+
+ GOT_ENTRY(_start)
+ GOT_ENTRY(_start_of_vectors)
+ GOT_ENTRY(_end_of_vectors)
+ GOT_ENTRY(transfer_to_handler)
+ GOT_ENTRY(__init_end)
+ GOT_ENTRY(_end)
+ GOT_ENTRY(__bss_start)
+ END_GOT
+
+/*
+ * e500 Startup -- after reset only the last 4KB of the effective
+ * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
+ * section is located at THIS LAST page and basically does three
+ * things: clear some registers, set up exception tables and
+ * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
+ * continue the boot procedure.
+ * Once the boot rom is mapped by TLB entries we can proceed
+ * with normal startup.
+ */
+
+ .section .bootpg,"ax"
+ .globl _start_e500
+
+_start_e500:
+
+/* clear registers/arrays not reset by hardware */
+
+ /* L1 */
+ li r0,2
+ mtspr L1CSR0,r0 /* invalidate d-cache */
+ mtspr L1CSR1,r0 /* invalidate i-cache */
+
+ mfspr r1,DBSR
+ mtspr DBSR,r1 /* Clear all valid bits */
+
+ /* Enable/invalidate the I-Cache */
+ lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
+ ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
+ mtspr SPRN_L1CSR1,r2
+1:
+ mfspr r3,SPRN_L1CSR1
+ and. r1,r3,r2
+ bne 1b
+
+ lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
+ ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
+ mtspr SPRN_L1CSR1,r3
+ isync
+2:
+ mfspr r3,SPRN_L1CSR1
+ andi. r1,r3,L1CSR1_ICE@l
+ beq 2b
+
+ /* Enable/invalidate the D-Cache */
+ lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
+ ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
+ mtspr SPRN_L1CSR0,r2
+1:
+ mfspr r3,SPRN_L1CSR0
+ and. r1,r3,r2
+ bne 1b
+
+ lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
+ ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
+ mtspr SPRN_L1CSR0,r3
+ isync
+2:
+ mfspr r3,SPRN_L1CSR0
+ andi. r1,r3,L1CSR0_DCE@l
+ beq 2b
+
+ /* Setup interrupt vectors */
+ lis r1,TEXT_BASE@h
+ mtspr IVPR,r1
+
+ li r1,0x0100
+ mtspr IVOR0,r1 /* 0: Critical input */
+ li r1,0x0200
+ mtspr IVOR1,r1 /* 1: Machine check */
+ li r1,0x0300
+ mtspr IVOR2,r1 /* 2: Data storage */
+ li r1,0x0400
+ mtspr IVOR3,r1 /* 3: Instruction storage */
+ li r1,0x0500
+ mtspr IVOR4,r1 /* 4: External interrupt */
+ li r1,0x0600
+ mtspr IVOR5,r1 /* 5: Alignment */
+ li r1,0x0700
+ mtspr IVOR6,r1 /* 6: Program check */
+ li r1,0x0800
+ mtspr IVOR7,r1 /* 7: floating point unavailable */
+ li r1,0x0900
+ mtspr IVOR8,r1 /* 8: System call */
+ /* 9: Auxiliary processor unavailable(unsupported) */
+ li r1,0x0a00
+ mtspr IVOR10,r1 /* 10: Decrementer */
+ li r1,0x0b00
+ mtspr IVOR11,r1 /* 11: Interval timer */
+ li r1,0x0c00
+ mtspr IVOR12,r1 /* 12: Watchdog timer */
+ li r1,0x0d00
+ mtspr IVOR13,r1 /* 13: Data TLB error */
+ li r1,0x0e00
+ mtspr IVOR14,r1 /* 14: Instruction TLB error */
+ li r1,0x0f00
+ mtspr IVOR15,r1 /* 15: Debug */
+
+ /* Clear and set up some registers. */
+ li r0,0x0000
+ lis r1,0xffff
+ mtspr DEC,r0 /* prevent dec exceptions */
+ mttbl r0 /* prevent fit & wdt exceptions */
+ mttbu r0
+ mtspr TSR,r1 /* clear all timer exception status */
+ mtspr TCR,r0 /* disable all */
+ mtspr ESR,r0 /* clear exception syndrome register */
+ mtspr MCSR,r0 /* machine check syndrome register */
+ mtxer r0 /* clear integer exception register */
+
+ /* Enable Time Base and Select Time Base Clock */
+ lis r0,HID0_EMCP@h /* Enable machine check */
+ ori r0,r0,HID0_TBEN@l /* Enable Timebase */
+ mtspr HID0,r0
+
+ li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
+ mfspr r3,PVR
+ andi. r3,r3, 0xff
+ cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */
+ blt 1f
+ /* Set MBDD bit also */
+ ori r0, r0, HID1_MBDD@l
+1:
+ mtspr HID1,r0
+
+ /* Enable Branch Prediction */
+#if defined(CFG_BTB)
+ lis r0,BUCSR_ENABLE@h
+ ori r0,r0,BUCSR_ENABLE@l
+ mtspr SPRN_BUCSR,r0
+#endif
+
+ lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
+ ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
+
+ /* create a temp mapping in AS=1 to the 4M boot window */
+ lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h
+ ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l
+
+ lis r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h
+ ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l
+
+ lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
+ ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
+
+ mtspr MAS0,r6
+ mtspr MAS1,r7
+ mtspr MAS2,r8
+ mtspr MAS3,r9
+ isync
+ msync
+ tlbwe
+
+ /* create a temp mapping in AS=1 to the stack */
+ lis r6,FSL_BOOKE_MAS0(1, 14, 0)@h
+ ori r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l
+
+ lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h
+ ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l
+
+ lis r8,FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)@h
+ ori r8,r8,FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)@l
+
+ lis r9,FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0,
+ (MAS3_SX|MAS3_SW|MAS3_SR))@h
+ ori r9,r9,FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0,
+ (MAS3_SX|MAS3_SW|MAS3_SR))@l
+
+ mtspr MAS0,r6
+ mtspr MAS1,r7
+ mtspr MAS2,r8
+ mtspr MAS3,r9
+ isync
+ msync
+ tlbwe
+
+ lis r6,MSR_IS|MSR_DS@h
+ ori r6,r6,MSR_IS|MSR_DS@l
+ lis r7,switch_as@h
+ ori r7,r7,switch_as@l
+
+ mtspr SPRN_SRR0,r7
+ mtspr SPRN_SRR1,r6
+ rfi
+
+switch_as:
+/* L1 DCache is used for initial RAM */
+
+ /* Allocate initial RAM in data cache. */
+ lis r3,CFG_INIT_RAM_ADDR@h
+ ori r3,r3,CFG_INIT_RAM_ADDR@l
+ mfspr r2, L1CFG0
+ andi. r2, r2, 0x1ff
+ /* cache size * 1024 / (2 * L1 line size) */
+ slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT)
+ mtctr r2
+ li r0,0
+1:
+ dcbz r0,r3
+ dcbtls 0,r0,r3
+ addi r3,r3,CACHELINE_SIZE
+ bdnz 1b
+
+ /*
+ * Jump out the last 4K page and continue to 'normal' start.
+ * Calculate absolute address in FLASH and jump there.
+ */
+ lis r3,TEXT_BASE@h
+ ori r3,r3,TEXT_BASE@l
+ addi r3,r3,_start_cont - _start + _START_OFFSET
+ mtlr r3
+ blr
+
+ .text
+ .globl _start
+_start:
+ .long 0x62626F78 /* Magic Number */
+
+ .align 4
+ .globl _start_cont
+_start_cont:
+ /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache */
+ lis r1,CFG_INIT_RAM_ADDR@h
+ ori r1,r1,CFG_INIT_SP_OFFSET@l
+
+ li r0,0
+ stwu r0,-4(r1)
+ stwu r0,-4(r1) /* Terminate call chain */
+
+ stwu r1,-8(r1) /* Save back chain and move SP */
+ lis r0,RESET_VECTOR@h /* Address of reset vector */
+ ori r0,r0,RESET_VECTOR@l
+ stwu r1,-8(r1) /* Save back chain and move SP */
+ stw r0,+12(r1) /* Save return addr (underflow vect) */
+
+ GET_GOT
+ bl cpu_init_early_f
+
+ /* switch back to AS = 0 */
+ lis r3,(MSR_CE|MSR_ME|MSR_DE)@h
+ ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
+ mtmsr r3
+ isync
+
+ bl cpu_init_f
+ bl initdram
+ b relocate_code
+ isync
+
+ /* NOTREACHED - board_init_f() does not return */
+
+ . = EXC_OFF_SYS_RESET
+ .globl _start_of_vectors
+_start_of_vectors:
+
+/* Critical input. */
+ CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
+
+/* Machine check */
+ MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
+
+/* Data Storage exception. */
+ STD_EXCEPTION(0x0300, DataStorage, UnknownException)
+
+/* Instruction Storage exception. */
+ STD_EXCEPTION(0x0400, InstStorage, UnknownException)
+
+/* Alignment exception. */
+ . = 0x0600
+Alignment:
+ EXCEPTION_PROLOG(SRR0, SRR1)
+ mfspr r4,DAR
+ stw r4,_DAR(r21)
+ mfspr r5,DSISR
+ stw r5,_DSISR(r21)
+ addi r3,r1,STACK_FRAME_OVERHEAD
+ EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
+
+/* Program check exception */
+ . = 0x0700
+ProgramCheck:
+ EXCEPTION_PROLOG(SRR0, SRR1)
+ addi r3,r1,STACK_FRAME_OVERHEAD
+ EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
+ MSR_KERNEL, COPY_EE)
+
+ /* No FPU on MPC85xx. This exception is not supposed to happen. */
+ STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
+
+ . = 0x0900
+/*
+ * r0 - SYSCALL number
+ * r3-... arguments
+ */
+SystemCall:
+ addis r11,r0,0 /* get functions table addr */
+ ori r11,r11,0 /* Note: this code is patched in trap_init */
+ addis r12,r0,0 /* get number of functions */
+ ori r12,r12,0
+
+ cmplw 0,r0,r12
+ bge 1f
+
+ rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
+ add r11,r11,r0
+ lwz r11,0(r11)
+
+ li r20,0xd00-4 /* Get stack pointer */
+ lwz r12,0(r20)
+ subi r12,r12,12 /* Adjust stack pointer */
+ li r0,0xc00+_end_back-SystemCall
+ cmplw 0,r0,r12 /* Check stack overflow */
+ bgt 1f
+ stw r12,0(r20)
+
+ mflr r0
+ stw r0,0(r12)
+ mfspr r0,SRR0
+ stw r0,4(r12)
+ mfspr r0,SRR1
+ stw r0,8(r12)
+
+ li r12,0xc00+_back-SystemCall
+ mtlr r12
+ mtspr SRR0,r11
+
+1: SYNC
+ rfi
+_back:
+
+ mfmsr r11 /* Disable interrupts */
+ li r12,0
+ ori r12,r12,MSR_EE
+ andc r11,r11,r12
+ SYNC /* Some chip revs need this... */
+ mtmsr r11
+ SYNC
+
+ li r12,0xd00-4 /* restore regs */
+ lwz r12,0(r12)
+
+ lwz r11,0(r12)
+ mtlr r11
+ lwz r11,4(r12)
+ mtspr SRR0,r11
+ lwz r11,8(r12)
+ mtspr SRR1,r11
+
+ addi r12,r12,12 /* Adjust stack pointer */
+ li r20,0xd00-4
+ stw r12,0(r20)
+
+ SYNC
+ rfi
+_end_back:
+
+ STD_EXCEPTION(0x0a00, Decrementer, UnknownException)
+ STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
+ STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
+
+ STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
+ STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
+
+ CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
+
+ .globl _end_of_vectors
+_end_of_vectors:
+
+ . = . + (0x100 - ( . & 0xff )) /* align for debug */
+
+/*
+ * This code finishes saving the registers to the exception frame
+ * and jumps to the appropriate handler for the exception.
+ * Register r21 is pointer into trap frame, r1 has new stack pointer.
+ */
+ .globl transfer_to_handler
+transfer_to_handler:
+ stw r22,_NIP(r21)
+ lis r22,MSR_POW@h
+ andc r23,r23,r22
+ stw r23,_MSR(r21)
+ SAVE_GPR(7, r21)
+ SAVE_4GPRS(8, r21)
+ SAVE_8GPRS(12, r21)
+ SAVE_8GPRS(24, r21)
+
+ mflr r23
+ andi. r24,r23,0x3f00 /* get vector offset */
+ stw r24,TRAP(r21)
+ li r22,0
+ stw r22,RESULT(r21)
+ mtspr SPRG2,r22 /* r1 is now kernel sp */
+
+ lwz r24,0(r23) /* virtual address of handler */
+ lwz r23,4(r23) /* where to go when done */
+ mtspr SRR0,r24
+ mtspr SRR1,r20
+ mtlr r23
+ SYNC
+ rfi /* jump to handler, enable MMU */
+
+int_return:
+ mfmsr r28 /* Disable interrupts */
+ li r4,0
+ ori r4,r4,MSR_EE
+ andc r28,r28,r4
+ SYNC /* Some chip revs need this... */
+ mtmsr r28
+ SYNC
+ lwz r2,_CTR(r1)
+ lwz r0,_LINK(r1)
+ mtctr r2
+ mtlr r0
+ lwz r2,_XER(r1)
+ lwz r0,_CCR(r1)
+ mtspr XER,r2
+ mtcrf 0xFF,r0
+ REST_10GPRS(3, r1)
+ REST_10GPRS(13, r1)
+ REST_8GPRS(23, r1)
+ REST_GPR(31, r1)
+ lwz r2,_NIP(r1) /* Restore environment */
+ lwz r0,_MSR(r1)
+ mtspr SRR0,r2
+ mtspr SRR1,r0
+ lwz r0,GPR0(r1)
+ lwz r2,GPR2(r1)
+ lwz r1,GPR1(r1)
+ SYNC
+ rfi
+
+crit_return:
+ mfmsr r28 /* Disable interrupts */
+ li r4,0
+ ori r4,r4,MSR_EE
+ andc r28,r28,r4
+ SYNC /* Some chip revs need this... */
+ mtmsr r28
+ SYNC
+ lwz r2,_CTR(r1)
+ lwz r0,_LINK(r1)
+ mtctr r2
+ mtlr r0
+ lwz r2,_XER(r1)
+ lwz r0,_CCR(r1)
+ mtspr XER,r2
+ mtcrf 0xFF,r0
+ REST_10GPRS(3, r1)
+ REST_10GPRS(13, r1)
+ REST_8GPRS(23, r1)
+ REST_GPR(31, r1)
+ lwz r2,_NIP(r1) /* Restore environment */
+ lwz r0,_MSR(r1)
+ mtspr SPRN_CSRR0,r2
+ mtspr SPRN_CSRR1,r0
+ lwz r0,GPR0(r1)
+ lwz r2,GPR2(r1)
+ lwz r1,GPR1(r1)
+ SYNC
+ rfci
+
+mck_return:
+ mfmsr r28 /* Disable interrupts */
+ li r4,0
+ ori r4,r4,MSR_EE
+ andc r28,r28,r4
+ SYNC /* Some chip revs need this... */
+ mtmsr r28
+ SYNC
+ lwz r2,_CTR(r1)
+ lwz r0,_LINK(r1)
+ mtctr r2
+ mtlr r0
+ lwz r2,_XER(r1)
+ lwz r0,_CCR(r1)
+ mtspr XER,r2
+ mtcrf 0xFF,r0
+ REST_10GPRS(3, r1)
+ REST_10GPRS(13, r1)
+ REST_8GPRS(23, r1)
+ REST_GPR(31, r1)
+ lwz r2,_NIP(r1) /* Restore environment */
+ lwz r0,_MSR(r1)
+ mtspr SPRN_MCSRR0,r2
+ mtspr SPRN_MCSRR1,r0
+ lwz r0,GPR0(r1)
+ lwz r2,GPR2(r1)
+ lwz r1,GPR1(r1)
+ SYNC
+ rfmci
+
+/*
+ * Cache functions.
+ */
+.globl invalidate_icache
+invalidate_icache:
+ mfspr r0,L1CSR1
+ ori r0,r0,L1CSR1_ICFI
+ msync
+ isync
+ mtspr L1CSR1,r0
+ isync
+ blr
+
+.globl invalidate_dcache
+invalidate_dcache:
+ mfspr r0,L1CSR0
+ ori r0,r0,L1CSR0_DCFI
+ msync
+ isync
+ mtspr L1CSR0,r0
+ isync
+ blr
+
+ .globl icache_enable
+icache_enable:
+ mflr r8
+ bl invalidate_icache
+ mtlr r8
+ isync
+ mfspr r4,L1CSR1
+ ori r4,r4,0x0001
+ oris r4,r4,0x0001
+ mtspr L1CSR1,r4
+ isync
+ blr
+
+ .globl icache_disable
+icache_disable:
+ mfspr r0,L1CSR1
+ lis r3,0
+ ori r3,r3,L1CSR1_ICE
+ andc r0,r0,r3
+ mtspr L1CSR1,r0
+ isync
+ blr
+
+ .globl icache_status
+icache_status:
+ mfspr r3,L1CSR1
+ andi. r3,r3,L1CSR1_ICE
+ blr
+
+ .globl dcache_enable
+dcache_enable:
+ mflr r8
+ bl invalidate_dcache
+ mtlr r8
+ isync
+ mfspr r0,L1CSR0
+ ori r0,r0,0x0001
+ oris r0,r0,0x0001
+ msync
+ isync
+ mtspr L1CSR0,r0
+ isync
+ blr
+
+ .globl dcache_disable
+dcache_disable:
+ mfspr r3,L1CSR0
+ lis r4,0
+ ori r4,r4,L1CSR0_DCE
+ andc r3,r3,r4
+ mtspr L1CSR0,r3
+ isync
+ blr
+
+ .globl dcache_status
+dcache_status:
+ mfspr r3,L1CSR0
+ andi. r3,r3,L1CSR0_DCE
+ blr
+
+ .globl get_pir
+get_pir:
+ mfspr r3,PIR
+ blr
+
+ .globl get_pvr
+get_pvr:
+ mfspr r3,PVR
+ blr
+
+ .globl get_svr
+get_svr:
+ mfspr r3,SVR
+ blr
+
+ .globl wr_tcr
+wr_tcr:
+ mtspr TCR,r3
+ blr
+
+/*
+ * Function: in8
+ * Description: Input 8 bits
+ */
+ .globl in8
+in8:
+ lbz r3,0x0000(r3)
+ blr
+
+/*
+ * Function: out8
+ * Description: Output 8 bits
+ */
+ .globl out8
+out8:
+ stb r4,0x0000(r3)
+ sync
+ blr
+
+/*
+ * Function: out16
+ * Description: Output 16 bits
+ */
+ .globl out16
+out16:
+ sth r4,0x0000(r3)
+ sync
+ blr
+
+/*
+ * Function: out16r
+ * Description: Byte reverse and output 16 bits
+ */
+ .globl out16r
+out16r:
+ sthbrx r4,r0,r3
+ sync
+ blr
+
+/*
+ * Function: out32
+ * Description: Output 32 bits
+ */
+ .globl out32
+out32:
+ stw r4,0x0000(r3)
+ sync
+ blr
+
+/*
+ * Function: out32r
+ * Description: Byte reverse and output 32 bits
+ */
+ .globl out32r
+out32r:
+ stwbrx r4,r0,r3
+ sync
+ blr
+
+/*
+ * Function: in16
+ * Description: Input 16 bits
+ */
+ .globl in16
+in16:
+ lhz r3,0x0000(r3)
+ blr
+
+/*
+ * Function: in16r
+ * Description: Input 16 bits and byte reverse
+ */
+ .globl in16r
+in16r:
+ lhbrx r3,r0,r3
+ blr
+
+/*
+ * Function: in32
+ * Description: Input 32 bits
+ */
+ .globl in32
+in32:
+ lwz 3,0x0000(3)
+ blr
+
+/*
+ * Function: in32r
+ * Description: Input 32 bits and byte reverse
+ */
+ .globl in32r
+in32r:
+ lwbrx r3,r0,r3
+ blr
+
+/*
+ * void e500_write_tlb(mas0, mas1, mas2, mas3, mas7)
+ */
+ .globl e500_write_tlb
+e500_write_tlb:
+ mtspr MAS0,r3
+ mtspr MAS1,r4
+ mtspr MAS2,r5
+ mtspr MAS3,r6
+ li r3,0
+ isync
+ tlbwe
+ msync
+ isync
+ blr
+
+/*
+ * void relocate_code (end of ram)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r3 = dest
+ * r4 = src
+ * r5 = length in bytes
+ * r6 = cachelinesize
+ */
+ .globl relocate_code
+relocate_code:
+ mr r9, r3 /* Save end of RAM */
+
+ lis r10, (_end - _start)@h /* Size */
+ ori r10, r10, (_end - _start)@l
+ sub r3, r3, r10
+
+ /* 64KB aligned */
+ lis r10, 0xffff0000@h
+ ori r10, r10, 0xffff0000@l
+ and r3, r3, r10
+
+ mr r1, r3 /* Set new stack just below barebox code */
+ mr r10, r3 /* Save copy of Destination Address */
+
+ bl calc_source
+calc_source:
+ mfspr r4, LR /* r4 = address in memory (flash, RAM) */
+ subi r4, r4, (calc_source - _start)
+
+ GET_GOT
+ lis r5, __init_size@h
+ ori r5, r5, __init_size@l
+
+ li r6,CACHELINE_SIZE
+
+ /*
+ * Fix GOT pointer:
+ *
+ * New GOT-PTR = (old GOT-PTR - TEXT_BASE) + Destination Address
+ *
+ * Offset:
+ */
+ sub r15,r10,r4
+
+ /* First our own GOT */
+ add r14,r14,r15
+ /* then the one used by the C code */
+ add r30,r30,r15
+
+ /*
+ * Now relocate code
+ */
+
+ cmplw cr1,r3,r4
+ addi r0,r5,3
+ srwi. r0,r0,2
+ beq cr1,4f /* In place copy is not necessary */
+ beq 7f /* Protect against 0 count */
+ mtctr r0
+ bge cr1,2f
+
+ la r8,-4(r4)
+ la r7,-4(r3)
+1: lwzu r0,4(r8)
+ stwu r0,4(r7)
+ bdnz 1b
+ b 4f
+
+2: slwi r0,r0,2
+ add r8,r4,r0
+ add r7,r3,r0
+3: lwzu r0,-4(r8)
+ stwu r0,-4(r7)
+ bdnz 3b
+
+ /*
+ * Now flush the cache: note that we must start from a cache aligned
+ * address. Otherwise we might miss one cache line.
+ */
+4: cmpwi r6,0
+ add r5,r3,r5
+ beq 7f /* Always flush prefetch queue in any case */
+ subi r0,r6,1
+ andc r3,r3,r0
+ mr r4,r3
+5: dcbst 0,r4
+ add r4,r4,r6
+ cmplw r4,r5
+ blt 5b
+ sync /* Wait for all dcbst to complete on bus */
+ mr r4,r3
+6: icbi 0,r4
+ add r4,r4,r6
+ cmplw r4,r5
+ blt 6b
+7: sync /* Wait for all icbi to complete on bus */
+ isync
+
+ /*
+ * Re-point the IVPR at RAM
+ */
+ mtspr IVPR,r10
+
+ /*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+
+ addi r0,r10,in_ram - _start + _START_OFFSET
+ mtlr r0
+ blr /* NEVER RETURNS! */
+
+ .globl in_ram
+in_ram:
+
+ /*
+ * Relocation Function, r14 point to got2+0x8000
+ *
+ * Adjust got2 pointers, no need to check for 0, this code
+ * already puts a few entries in the table.
+ */
+ li r0,__got2_entries@sectoff@l
+ la r3,GOT(_GOT2_TABLE_)
+ lwz r11,GOT(_GOT2_TABLE_)
+ mtctr r0
+ sub r11,r3,r11
+ addi r3,r3,-4
+1: lwzu r0,4(r3)
+ cmpwi r0,0
+ beq- 2f
+ add r0,r0,r11
+ stw r0,0(r3)
+2: bdnz 1b
+
+ /*
+ * Now adjust the fixups and the pointers to the fixups
+ * in case we need to move ourselves again.
+ */
+ li r0,__fixup_entries@sectoff@l
+ lwz r3,GOT(_FIXUP_TABLE_)
+ cmpwi r0,0
+ mtctr r0
+ addi r3,r3,-4
+ beq 4f
+3: lwzu r4,4(r3)
+ lwzux r0,r4,r11
+ cmpwi r0,0
+ add r0,r0,r11
+ stw r4,0(r3)
+ beq- 5f
+ stw r0,0(r4)
+5: bdnz 3b
+4:
+clear_bss:
+ /*
+ * Now clear BSS segment
+ */
+ lwz r3,GOT(__bss_start)
+ lwz r4,GOT(_end)
+
+ cmplw 0,r3,r4
+ beq 6f
+
+ li r0,0
+5:
+ stw r0,0(r3)
+ addi r3,r3,4
+ cmplw 0,r3,r4
+ bne 5b
+6:
+ mr r3, r10 /* Destination Address */
+ bl board_init_r
+
+ /*
+ * Copy exception vector code to low memory
+ *
+ * r3: dest_addr
+ * r7: source address, r8: end address, r9: target address
+ */
+ .globl trap_init
+trap_init:
+ mflr r4 /* save link register */
+ GET_GOT
+ lwz r7,GOT(_start_of_vectors)
+ lwz r8,GOT(_end_of_vectors)
+
+ li r9,0x100 /* reset vector always at 0x100 */
+
+ cmplw 0,r7,r8
+ bgelr /* return if r7>=r8 - just in case */
+1:
+ lwz r0,0(r7)
+ stw r0,0(r9)
+ addi r7,r7,4
+ addi r9,r9,4
+ cmplw 0,r7,r8
+ bne 1b
+
+ /*
+ * relocate `hdlr' and `int_return' entries
+ */
+ li r7,.L_CriticalInput - _start + _START_OFFSET
+ bl trap_reloc
+ li r7,.L_MachineCheck - _start + _START_OFFSET
+ bl trap_reloc
+ li r7,.L_DataStorage - _start + _START_OFFSET
+ bl trap_reloc
+ li r7,.L_InstStorage - _start + _START_OFFSET
+ bl trap_reloc
+ li r7,.L_Alignment - _start + _START_OFFSET
+ bl trap_reloc
+ li r7,.L_ProgramCheck - _start + _START_OFFSET
+ bl trap_reloc
+ li r7,.L_FPUnavailable - _start + _START_OFFSET
+ bl trap_reloc
+ li r7,.L_Decrementer - _start + _START_OFFSET
+ bl trap_reloc
+ li r7,.L_IntervalTimer - _start + _START_OFFSET
+ li r8,_end_of_vectors - _start + _START_OFFSET
+2:
+ bl trap_reloc
+ addi r7,r7,0x100 /* next exception vector */
+ cmplw 0,r7,r8
+ blt 2b
+
+ lis r7,0x0
+ mtspr IVPR,r7
+
+ mtlr r4 /* restore link register */
+ blr
+
+
+.globl _text_base
+_text_base:
+ .long TEXT_BASE
+
+.globl unlock_ram_in_cache
+unlock_ram_in_cache:
+ /* invalidate the INIT_RAM section */
+ lis r3,(CFG_INIT_RAM_ADDR & ~(CACHELINE_SIZE-1))@h
+ ori r3,r3,(CFG_INIT_RAM_ADDR & ~(CACHELINE_SIZE-1))@l
+ mfspr r4,L1CFG0
+ andi. r4,r4,0x1ff
+ slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
+ mtctr r4
+1: dcbi r0,r3
+ addi r3,r3,CACHELINE_SIZE
+ bdnz 1b
+ sync
+
+ /* Invalidate the TLB entries for the cache */
+ lis r3,CFG_INIT_RAM_ADDR@h
+ ori r3,r3,CFG_INIT_RAM_ADDR@l
+ tlbivax 0,r3
+ addi r3,r3,0x1000
+ tlbivax 0,r3
+ addi r3,r3,0x1000
+ tlbivax 0,r3
+ addi r3,r3,0x1000
+ tlbivax 0,r3
+ isync
+ blr
+
+.globl flush_dcache
+flush_dcache:
+ mfspr r3,SPRN_L1CFG0
+
+ rlwinm r5,r3,9,3 /* Extract cache block size */
+ twlgti r5,1 /* Only 32 and 64 byte cache blocks
+ * are currently defined.
+ */
+ li r4,32
+ subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
+ * log2(number of ways)
+ */
+ slw r5,r4,r5 /* r5 = cache block size */
+
+ rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
+ mulli r7,r7,13 /* An 8-way cache will require 13
+ * loads per set.
+ */
+ slw r7,r7,r6
+
+ /* save off HID0 and set DCFA */
+ mfspr r8,SPRN_HID0
+ ori r9,r8,HID0_DCFA@l
+ mtspr SPRN_HID0,r9
+ isync
+
+ lis r4,0
+ mtctr r7
+
+1: lwz r3,0(r4) /* Load... */
+ add r4,r4,r5
+ bdnz 1b
+
+ msync
+ lis r4,0
+ mtctr r7
+
+1: dcbf 0,r4 /* ...and flush. */
+ add r4,r4,r5
+ bdnz 1b
+
+ /* restore HID0 */
+ mtspr SPRN_HID0,r8
+ isync
+
+ blr
+
+.globl setup_ivors
+setup_ivors:
+
+#include "fixed_ivor.S"
+ blr
diff --git a/arch/ppc/cpu-85xx/tlb.c b/arch/ppc/cpu-85xx/tlb.c
new file mode 100644
index 0000000000..07ecdef5e8
--- /dev/null
+++ b/arch/ppc/cpu-85xx/tlb.c
@@ -0,0 +1,175 @@
+/*
+ * Copyright 2012 GE Intelligent Platforms, Inc.
+ *
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/config.h>
+#include <asm/bitops.h>
+#include <mach/mmu.h>
+
+void e500_invalidate_tlb(u8 tlb)
+{
+ if (tlb == 0)
+ mtspr(MMUCSR0, 0x4);
+ if (tlb == 1)
+ mtspr(MMUCSR0, 0x2);
+}
+
+void e500_init_tlbs(void)
+{
+ int i;
+
+ for (i = 0; i < num_tlb_entries; i++) {
+ e500_write_tlb(tlb_table[i].mas0,
+ tlb_table[i].mas1,
+ tlb_table[i].mas2,
+ tlb_table[i].mas3,
+ tlb_table[i].mas7);
+ }
+
+ return ;
+}
+
+static int e500_find_free_tlbcam(void)
+{
+ int ix;
+ u32 _mas1;
+ unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
+
+ for (ix = 0; ix < num_cam; ix++) {
+ mtspr(MAS0, FSL_BOOKE_MAS0(1, ix, 0));
+ asm volatile("tlbre;isync");
+ _mas1 = mfspr(MAS1);
+ if (!(_mas1 & MAS1_VALID))
+ return ix;
+ }
+
+ if (ix >= NUM_TLBCAMS)
+ panic("No more free TLBs");
+
+ return ix;
+}
+
+void e500_set_tlb(u8 tlb, u32 epn, u64 rpn,
+ u8 perms, u8 wimge,
+ u8 ts, u8 esel, u8 tsize, u8 iprot)
+{
+ u32 _mas0, _mas1, _mas2, _mas3, _mas7;
+
+ _mas0 = FSL_BOOKE_MAS0(tlb, esel, 0);
+ _mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize);
+ _mas2 = FSL_BOOKE_MAS2(epn, wimge);
+ _mas3 = FSL_BOOKE_MAS3(rpn, 0, perms);
+ _mas7 = FSL_BOOKE_MAS7(rpn);
+
+ e500_write_tlb(_mas0, _mas1, _mas2, _mas3, _mas7);
+}
+
+void e500_disable_tlb(u8 esel)
+{
+ mtspr(MAS0, FSL_BOOKE_MAS0(1, esel, 0));
+ mtspr(MAS1, 0);
+ mtspr(MAS2, 0);
+ mtspr(MAS3, 0);
+ asm volatile("isync;msync;tlbwe;isync");
+}
+
+static inline void tlbsx(const unsigned *addr)
+{
+ __asm__ __volatile__ ("tlbsx 0,%0" : : "r" (addr), "m" (*addr));
+}
+
+int e500_find_tlb_idx(void *addr, u8 tlbsel)
+{
+ u32 _mas0, _mas1;
+
+ /* zero out Search PID, AS */
+ mtspr(MAS6, 0);
+ tlbsx(addr);
+
+ _mas0 = mfspr(MAS0);
+ _mas1 = mfspr(MAS1);
+
+ /* we found something, and its in the TLB we expect */
+ if ((MAS1_VALID & _mas1) &&
+ (MAS0_TLBSEL(tlbsel) == (_mas0 & MAS0_TLBSEL_MSK))) {
+ return (_mas0 & MAS0_ESEL_MSK) >> 16;
+ }
+
+ panic("Address 0x%p not found in TLB %d\n", addr, tlbsel);
+}
+
+static unsigned int e500_setup_ddr_tlbs_phys(phys_addr_t p_addr,
+ unsigned int memsize_in_meg)
+{
+ int i;
+ unsigned int tlb_size;
+ unsigned int wimge = 0;
+ unsigned int ram_tlb_address = (unsigned int)CFG_SDRAM_BASE;
+ unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf;
+ u64 size, memsize = (u64)memsize_in_meg << 20;
+
+ size = min((u64)memsize, (u64)MAX_MEM_MAPPED);
+
+ /* Convert (4^max) kB to (2^max) bytes */
+ max_cam = (max_cam * 2) + 10;
+
+ for (i = 0; size && (i < 8); i++) {
+ int ram_tlb_index = e500_find_free_tlbcam();
+ u32 camsize = __ilog2_u64(size) & ~1U;
+ u32 align = __ilog2(ram_tlb_address) & ~1U;
+
+ if (align == -2)
+ align = max_cam;
+ if (camsize > align)
+ camsize = align;
+
+ if (camsize > max_cam)
+ camsize = max_cam;
+
+ tlb_size = (camsize - 10) / 2;
+
+ e500_set_tlb(1, ram_tlb_address, p_addr,
+ MAS3_SX|MAS3_SW|MAS3_SR, wimge,
+ 0, ram_tlb_index, tlb_size, 1);
+
+ size -= 1ULL << camsize;
+ memsize -= 1ULL << camsize;
+ ram_tlb_address += 1UL << camsize;
+ p_addr += 1UL << camsize;
+ }
+
+ if (memsize)
+ printf("%lld left unmapped\n", memsize);
+
+ return memsize_in_meg;
+}
+
+inline unsigned int e500_setup_ddr_tlbs(unsigned int memsize_in_meg)
+{
+ return e500_setup_ddr_tlbs_phys(CFG_SDRAM_BASE, memsize_in_meg);
+}
diff --git a/arch/ppc/cpu-85xx/traps.c b/arch/ppc/cpu-85xx/traps.c
new file mode 100644
index 0000000000..caead96dda
--- /dev/null
+++ b/arch/ppc/cpu-85xx/traps.c
@@ -0,0 +1,272 @@
+/*
+ * linux/arch/powerpc/kernel/traps.c
+ *
+ * Copyright 2007 Freescale Semiconductor.
+ * Copyright (C) 2003 Motorola
+ * Modified by Xianghua Xiao(x.xiao@motorola.com)
+ *
+ * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
+ *
+ * Modified by Cort Dougan (cort@cs.nmt.edu)
+ * and Paul Mackerras (paulus@cs.anu.edu.au)
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file handles the architecture-dependent parts of hardware exceptions
+ */
+
+#include <common.h>
+#include <command.h>
+#include <init.h>
+#include <asm/processor.h>
+#include <mach/mpc85xx.h>
+
+int machinecheck_count;
+int machinecheck_error;
+
+static inline void set_tsr(unsigned long val)
+{
+ asm volatile("mtspr 0x150, %0" : : "r" (val));
+}
+
+static inline unsigned long get_esr(void)
+{
+ unsigned long val;
+ asm volatile("mfspr %0, 0x03e" : "=r" (val) : );
+ return val;
+}
+
+#define ESR_MCI 0x80000000
+#define ESR_PIL 0x08000000
+#define ESR_PPR 0x04000000
+#define ESR_PTR 0x02000000
+#define ESR_DST 0x00800000
+#define ESR_DIZ 0x00400000
+#define ESR_U0F 0x00008000
+
+/*
+ * Trap & Exception support
+ */
+void print_backtrace(unsigned long *sp)
+{
+ int cnt = 0;
+ unsigned long i;
+
+ printf("Call backtrace: ");
+ while (sp) {
+ if ((uint)sp > END_OF_MEM)
+ break;
+
+ i = sp[1];
+ if ((cnt++ % 7) == 0)
+ printf("\n");
+ printf("%08lX ", i);
+ if (cnt > 32)
+ break;
+ sp = (unsigned long *)*sp;
+ }
+ printf("\n");
+}
+
+void show_regs(struct pt_regs *regs)
+{
+ int i;
+
+ printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx "
+ "DAR: %08lX\n",
+ regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
+ printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x "
+ "IR/DR: %01x%01x\n",
+ regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0,
+ regs->msr & MSR_FP ? 1 : 0, regs->msr&MSR_ME ? 1 : 0,
+ regs->msr&MSR_IR ? 1 : 0,
+ regs->msr&MSR_DR ? 1 : 0);
+
+ printf("\n");
+ for (i = 0; i < 32; i++) {
+ if ((i % 8) == 0)
+ printf("GPR%02d: ", i);
+
+ printf("%08lX ", regs->gpr[i]);
+ if ((i % 8) == 7)
+ printf("\n");
+ }
+}
+
+void _exception(int signr, struct pt_regs *regs)
+{
+ show_regs(regs);
+ print_backtrace((unsigned long *)regs->gpr[1]);
+ panic("Exception in kernel pc %lx signal %d", regs->nip, signr);
+}
+
+void CritcalInputException(struct pt_regs *regs)
+{
+ panic("Critical Input Exception");
+}
+
+static int exception_init(void)
+{
+ machinecheck_count = 0;
+ machinecheck_error = 0;
+
+ return 0;
+}
+core_initcall(exception_init);
+
+void MachineCheckException(struct pt_regs *regs)
+{
+ unsigned long fixup;
+ unsigned int mcsr, mcsrr0, mcsrr1, mcar;
+
+ /*
+ * Probing PCI using config cycles cause this exception
+ * when a device is not present. Catch it and return to
+ * the PCI exception handler.
+ */
+ fixup = search_exception_table(regs->nip);
+ if (fixup != 0) {
+ regs->nip = fixup;
+ return;
+ }
+
+ mcsrr0 = mfspr(SPRN_MCSRR0);
+ mcsrr1 = mfspr(SPRN_MCSRR1);
+ mcsr = mfspr(SPRN_MCSR);
+ mcar = mfspr(SPRN_MCAR);
+
+ machinecheck_count++;
+ machinecheck_error = 1;
+
+#if defined(CONFIG_KGDB)
+ if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+ return;
+#endif
+
+ printf("Machine check in kernel mode.\n");
+ printf("Caused by (from mcsr): ");
+ printf("mcsr = 0x%08x\n", mcsr);
+ if (mcsr & 0x80000000)
+ printf("Machine check input pin\n");
+ if (mcsr & 0x40000000)
+ printf("Instruction cache parity error\n");
+ if (mcsr & 0x20000000)
+ printf("Data cache push parity error\n");
+ if (mcsr & 0x10000000)
+ printf("Data cache parity error\n");
+ if (mcsr & 0x00000080)
+ printf("Bus instruction address error\n");
+ if (mcsr & 0x00000040)
+ printf("Bus Read address error\n");
+ if (mcsr & 0x00000020)
+ printf("Bus Write address error\n");
+ if (mcsr & 0x00000010)
+ printf("Bus Instruction data bus error\n");
+ if (mcsr & 0x00000008)
+ printf("Bus Read data bus error\n");
+ if (mcsr & 0x00000004)
+ printf("Bus Write bus error\n");
+ if (mcsr & 0x00000002)
+ printf("Bus Instruction parity error\n");
+ if (mcsr & 0x00000001)
+ printf("Bus Read parity error\n");
+
+ show_regs(regs);
+ printf("MCSR=0x%08x\tMCSRR0=0x%08x\nMCSRR1=0x%08x\tMCAR=0x%08x\n",
+ mcsr, mcsrr0, mcsrr1, mcar);
+ print_backtrace((unsigned long *)regs->gpr[1]);
+
+ if (machinecheck_count > 10)
+ panic("machine check count too high\n");
+
+ if (machinecheck_count > 1) {
+ regs->nip += 4; /* skip offending instruction */
+ printf("Skipping current instr, Returning to 0x%08lx\n",
+ regs->nip);
+ } else {
+ printf("Returning back to 0x%08lx\n", regs->nip);
+ }
+}
+
+void AlignmentException(struct pt_regs *regs)
+{
+#if defined(CONFIG_KGDB)
+ if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+ return;
+#endif
+
+ show_regs(regs);
+ print_backtrace((unsigned long *)regs->gpr[1]);
+ panic("Alignment Exception");
+}
+
+void ProgramCheckException(struct pt_regs *regs)
+{
+ long esr_val;
+
+#if defined(CONFIG_KGDB)
+ if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+ return;
+#endif
+
+ show_regs(regs);
+
+ esr_val = get_esr();
+ if (esr_val & ESR_PIL)
+ printf("** Illegal Instruction **\n");
+ else if (esr_val & ESR_PPR)
+ printf("** Privileged Instruction **\n");
+ else if (esr_val & ESR_PTR)
+ printf("** Trap Instruction **\n");
+
+ print_backtrace((unsigned long *)regs->gpr[1]);
+ panic("Program Check Exception");
+}
+
+void PITException(struct pt_regs *regs)
+{
+ /* Reset PIT interrupt */
+ set_tsr(0x0c000000);
+}
+
+void UnknownException(struct pt_regs *regs)
+{
+#if defined(CONFIG_KGDB)
+ if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+ return;
+#endif
+
+ printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
+ regs->nip, regs->msr, regs->trap);
+ _exception(0, regs);
+}
+
+void DebugException(struct pt_regs *regs)
+{
+ printf("Debugger trap at @ %lx\n", regs->nip);
+ show_regs(regs);
+#if defined(CONFIG_BEDBUG)
+ do_bedbug_breakpoint(regs);
+#endif
+}
diff --git a/arch/ppc/include/asm/cache.h b/arch/ppc/include/asm/cache.h
index 4f7ca86881..147ceb6714 100644
--- a/arch/ppc/include/asm/cache.h
+++ b/arch/ppc/include/asm/cache.h
@@ -31,6 +31,8 @@
extern void flush_dcache_range(unsigned long start, unsigned long stop);
extern void clean_dcache_range(unsigned long start, unsigned long stop);
extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
+extern void flush_dcache(void);
+extern void invalidate_icache(void);
#ifdef CFG_INIT_RAM_LOCK
extern void unlock_ram_in_cache(void);
#endif /* CFG_INIT_RAM_LOCK */
diff --git a/arch/ppc/include/asm/config.h b/arch/ppc/include/asm/config.h
new file mode 100644
index 0000000000..4abded9aac
--- /dev/null
+++ b/arch/ppc/include/asm/config.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2012 GE Intelligent Platforms, Inc.
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_CONFIG_H_
+#define _ASM_CONFIG_H_
+
+#ifdef CONFIG_MPC85xx
+#include <mach/config_mpc85xx.h>
+#endif
+
+#ifndef MAX_MEM_MAPPED
+#if defined(CONFIG_E500)
+#define MAX_MEM_MAPPED ((phys_size_t)(2 << 30))
+#endif
+#endif
+
+/*
+ * Provide a default boot page translation virtual address that lines up with
+ * Freescale's default e500 reset page.
+ */
+#if (defined(CONFIG_E500) && defined(CONFIG_MP))
+#ifndef BPTR_VIRT_ADDR
+#define BPTR_VIRT_ADDR 0xfffff000
+#endif
+#endif
+
+#endif /* _ASM_CONFIG_H_ */
diff --git a/arch/ppc/include/asm/fsl_ddr_sdram.h b/arch/ppc/include/asm/fsl_ddr_sdram.h
new file mode 100644
index 0000000000..ef793c9d65
--- /dev/null
+++ b/arch/ppc/include/asm/fsl_ddr_sdram.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2012 GE Intelligent Platforms, Inc.
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#ifndef FSL_DDR_MEMCTL_H
+#define FSL_DDR_MEMCTL_H
+
+/*
+ * DDR_SDRAM_CFG - DDR SDRAM Control Configuration
+ */
+#define SDRAM_CFG_MEM_EN 0x80000000
+#define SDRAM_CFG_SREN 0x40000000
+#define SDRAM_CFG_ECC_EN 0x20000000
+#define SDRAM_CFG_RD_EN 0x10000000
+#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
+#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
+#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
+#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
+#define SDRAM_CFG_DYN_PWR 0x00200000
+#define SDRAM_CFG_32_BE 0x00080000
+#define SDRAM_CFG_8_BE 0x00040000
+#define SDRAM_CFG_NCAP 0x00020000
+#define SDRAM_CFG_2T_EN 0x00008000
+#define SDRAM_CFG_BI 0x00000001
+
+extern phys_size_t fixed_sdram(void);
+
+#endif
diff --git a/arch/ppc/include/asm/fsl_law.h b/arch/ppc/include/asm/fsl_law.h
new file mode 100644
index 0000000000..813a8ee0b3
--- /dev/null
+++ b/arch/ppc/include/asm/fsl_law.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#ifndef _FSL_LAW_H_
+#define _FSL_LAW_H_
+
+#include <asm/io.h>
+
+#define LAW_EN 0x80000000
+
+#define FSL_SET_LAW_ENTRY(idx, a, sz, trgt) \
+ { .index = idx, .addr = a, .size = sz, .trgt_id = trgt }
+
+#define FSL_SET_LAW(a, sz, trgt) \
+ { .index = -1, .addr = a, .size = sz, .trgt_id = trgt }
+
+enum law_size {
+ LAW_SIZE_4K = 0xb,
+ LAW_SIZE_8K,
+ LAW_SIZE_16K,
+ LAW_SIZE_32K,
+ LAW_SIZE_64K,
+ LAW_SIZE_128K,
+ LAW_SIZE_256K,
+ LAW_SIZE_512K,
+ LAW_SIZE_1M,
+ LAW_SIZE_2M,
+ LAW_SIZE_4M,
+ LAW_SIZE_8M,
+ LAW_SIZE_16M,
+ LAW_SIZE_32M,
+ LAW_SIZE_64M,
+ LAW_SIZE_128M,
+ LAW_SIZE_256M,
+ LAW_SIZE_512M,
+ LAW_SIZE_1G,
+ LAW_SIZE_2G,
+ LAW_SIZE_4G,
+ LAW_SIZE_8G,
+ LAW_SIZE_16G,
+ LAW_SIZE_32G,
+};
+
+#define fsl_law_size_bits(sz) (__ilog2_u64(sz) - 1)
+#define fsl_lawar_size(x) (1ULL << (((x) & 0x3f) + 1))
+
+enum law_trgt_if {
+ LAW_TRGT_IF_PCI = 0x00,
+ LAW_TRGT_IF_PCI_2 = 0x01,
+ LAW_TRGT_IF_PCIE_1 = 0x02,
+#if !defined(CONFIG_P2020)
+ LAW_TRGT_IF_PCIE_3 = 0x03,
+#endif
+ LAW_TRGT_IF_LBC = 0x04,
+ LAW_TRGT_IF_CCSR = 0x08,
+ LAW_TRGT_IF_DDR_INTRLV = 0x0b,
+ LAW_TRGT_IF_RIO = 0x0c,
+ LAW_TRGT_IF_RIO_2 = 0x0d,
+ LAW_TRGT_IF_DDR = 0x0f,
+ LAW_TRGT_IF_DDR_2 = 0x16, /* 2nd controller */
+};
+#define LAW_TRGT_IF_DDR_1 LAW_TRGT_IF_DDR
+#define LAW_TRGT_IF_PCI_1 LAW_TRGT_IF_PCI
+#define LAW_TRGT_IF_PCIX LAW_TRGT_IF_PCI
+#define LAW_TRGT_IF_PCIE_2 LAW_TRGT_IF_PCI_2
+#define LAW_TRGT_IF_RIO_1 LAW_TRGT_IF_RIO
+
+
+#if defined(CONFIG_P2020)
+#define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI
+#endif
+
+struct law_entry {
+ int index;
+ phys_addr_t addr;
+ enum law_size size;
+ enum law_trgt_if trgt_id;
+};
+
+extern int fsl_set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id);
+extern void fsl_init_laws(void);
+
+/* define in board code */
+extern struct law_entry law_table[];
+extern int num_law_entries;
+#endif
diff --git a/arch/ppc/include/asm/fsl_lbc.h b/arch/ppc/include/asm/fsl_lbc.h
new file mode 100644
index 0000000000..47205e7ab9
--- /dev/null
+++ b/arch/ppc/include/asm/fsl_lbc.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright 2012 GE Intelligent Platforms, Inc.
+ * Copyright (C) 2004-2008,2010-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef __ASM_PPC_FSL_LBC_H
+#define __ASM_PPC_FSL_LBC_H
+
+#include <config.h>
+#include <common.h>
+
+/*
+ * BR - Base Registers
+ */
+#define BR_PS 0x00001800
+#define BR_PS_SHIFT 11
+#define BR_PS_8 0x00000800 /* Port Size 8 bit */
+#define BR_PS_16 0x00001000 /* Port Size 16 bit */
+#define BR_PS_32 0x00001800 /* Port Size 32 bit */
+#define BR_V 0x00000001
+#define BR_V_SHIFT 0
+
+/* Convert an address into the right format for the BR registers */
+#define BR_PHYS_ADDR(x) ((x) & 0xffff8000)
+
+/*
+ * CLKDIV is five bits only on 8536, 8572, and 8610, so far, but the fifth bit
+ * should always be zero on older parts that have a four bit CLKDIV.
+ */
+#define LCRR_CLKDIV 0x0000001f
+#define LCRR_CLKDIV_SHIFT 0
+#define LCRR_CLKDIV_4 0x00000002
+#define LCRR_CLKDIV_8 0x00000004
+#define LCRR_CLKDIV_16 0x00000008
+
+#ifndef __ASSEMBLY__
+#include <asm/io.h>
+
+extern void fsl_init_early_memctl_regs(void);
+
+/* LBC register offsets. */
+#define FSL_LBC_BRX(x) ((x) * 8) /* bank register offsets. */
+#define FSL_LBC_ORX(x) (4 + ((x) * 8)) /* option register offset. */
+#define FSL_LBC_LCCR 0x0d4 /* Clock ration register. */
+
+#define LBC_BASE_ADDR ((void __iomem *)LBC_ADDR)
+#define fsl_get_lbc_br(x) (in_be32((LBC_BASE_ADDR + FSL_LBC_BRX(x))))
+#define fsl_get_lbc_or(x) (in_be32((LBC_BASE_ADDR + FSL_LBC_ORX(x))))
+#define fsl_set_lbc_br(x, v) (out_be32((LBC_BASE_ADDR + FSL_LBC_BRX(x)), v))
+#define fsl_set_lbc_or(x, v) (out_be32((LBC_BASE_ADDR + FSL_LBC_ORX(x)), v))
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_PPC_FSL_LBC_H */
diff --git a/arch/ppc/include/asm/io.h b/arch/ppc/include/asm/io.h
index 13187cae24..00529898dd 100644
--- a/arch/ppc/include/asm/io.h
+++ b/arch/ppc/include/asm/io.h
@@ -105,6 +105,34 @@ extern void _outsl_ns(volatile u32 *port, const void *buf, int nl);
#define iobarrier_w() eieio()
/*
+ * Non ordered and non-swapping "raw" accessors
+ */
+static inline unsigned char __raw_readb(const volatile void __iomem *addr)
+{
+ return *(volatile unsigned char __force *)(addr);
+}
+static inline unsigned short __raw_readw(const volatile void __iomem *addr)
+{
+ return *(volatile unsigned short __force *)(addr);
+}
+static inline unsigned int __raw_readl(const volatile void __iomem *addr)
+{
+ return *(volatile unsigned int __force *)(addr);
+}
+static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
+{
+ *(volatile unsigned char __force *)(addr) = v;
+}
+static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
+{
+ *(volatile unsigned short __force *)(addr) = v;
+}
+static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
+{
+ *(volatile unsigned int __force *)(addr) = v;
+}
+
+/*
* 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
*/
extern inline int in_8(volatile u8 *addr)
diff --git a/arch/ppc/lib/Makefile b/arch/ppc/lib/Makefile
index 0f5e01761d..ba2f078b62 100644
--- a/arch/ppc/lib/Makefile
+++ b/arch/ppc/lib/Makefile
@@ -8,4 +8,5 @@ obj-y += misc.o
obj-$(CONFIG_CMD_BOOTM) += ppclinux.o
obj-$(CONFIG_MODULES) += module.o
obj-y += crtsavres.o
+obj-y += reloc.o
diff --git a/arch/ppc/lib/board.c b/arch/ppc/lib/board.c
index a840c75204..6b6268f679 100644
--- a/arch/ppc/lib/board.c
+++ b/arch/ppc/lib/board.c
@@ -46,6 +46,10 @@ void board_init_r (ulong end_of_ram)
asm ("sync ; isync");
+#ifdef CONFIG_MPC85xx
+ _text_base = end_of_ram;
+#endif
+
/*
* FIXME: 128k stack size. Is this enough? should
* it be configurable?
diff --git a/arch/ppc/lib/reloc.S b/arch/ppc/lib/reloc.S
new file mode 100644
index 0000000000..92ee189494
--- /dev/null
+++ b/arch/ppc/lib/reloc.S
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2009 Wolfgang Denk <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/ppc_asm.tmpl>
+
+ .file "reloc.S"
+
+ .text
+ /*
+ * Function: relocate entries for one exception vector
+ */
+ .globl trap_reloc
+ .type trap_reloc, @function
+trap_reloc:
+ lwz r0, 0(r7) /* hdlr ... */
+ add r0, r0, r3 /* ... += dest_addr */
+ stw r0, 0(r7)
+
+ lwz r0, 4(r7) /* int_return ... */
+ add r0, r0, r3 /* ... += dest_addr */
+ stw r0, 4(r7)
+
+ lwz r0, 8(r7) /* transfer_to_handler ...*/
+ add r0, r0, r3 /* ... += dest_addr */
+ stw r0, 8(r7)
+
+ blr
+ .size trap_reloc, .-trap_reloc
diff --git a/arch/ppc/mach-mpc5xxx/start.S b/arch/ppc/mach-mpc5xxx/start.S
index e098a87cc1..04e8fe3f4b 100644
--- a/arch/ppc/mach-mpc5xxx/start.S
+++ b/arch/ppc/mach-mpc5xxx/start.S
@@ -726,20 +726,6 @@ trap_init:
mtlr r4 /* restore link register */
blr
- /*
- * Function: relocate entries for one exception vector
- */
-trap_reloc:
- lwz r0, 0(r7) /* hdlr ... */
- add r0, r0, r3 /* ... += dest_addr */
- stw r0, 0(r7)
-
- lwz r0, 4(r7) /* int_return ... */
- add r0, r0, r3 /* ... += dest_addr */
- stw r0, 4(r7)
-
- blr
-
.globl _text_base
_text_base:
.long TEXT_BASE
diff --git a/arch/ppc/mach-mpc85xx/Kconfig b/arch/ppc/mach-mpc85xx/Kconfig
new file mode 100644
index 0000000000..b2af05ec59
--- /dev/null
+++ b/arch/ppc/mach-mpc85xx/Kconfig
@@ -0,0 +1,41 @@
+if ARCH_MPC85XX
+
+config TEXT_BASE
+ hex
+ default 0xeff80000 if P2020RDB
+
+config BOARDINFO
+ default "P2020_RDB" if P2020RDB
+
+config MPC85xx
+ bool
+ default y if P2020RDB
+
+choice
+ prompt "Select your board"
+
+config P2020RDB
+ bool "P2020RDB"
+ help
+ Say Y here if you are using the Freescale P2020RDB
+
+endchoice
+endif
+
+if P2020RDB
+config P2020
+ bool
+ default y
+
+config BOOKE
+ bool
+ default y
+
+config E500
+ bool
+ default y
+
+config FSL_ELBC
+ bool
+ default y
+endif
diff --git a/arch/ppc/mach-mpc85xx/Makefile b/arch/ppc/mach-mpc85xx/Makefile
new file mode 100644
index 0000000000..03addaf47b
--- /dev/null
+++ b/arch/ppc/mach-mpc85xx/Makefile
@@ -0,0 +1,8 @@
+obj-y += cpuid.o
+obj-y += cpu.o
+obj-y += cpu_init.o
+obj-y += fsl_lbc.o
+obj-y += fsl_law.o
+obj-y += speed.o
+obj-y +=time.o
+obj-$(CONFIG_MP) += mp.o
diff --git a/arch/ppc/mach-mpc85xx/cpu.c b/arch/ppc/mach-mpc85xx/cpu.c
new file mode 100644
index 0000000000..f7308383c7
--- /dev/null
+++ b/arch/ppc/mach-mpc85xx/cpu.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright 2012 GE Intelligent Platforms, Inc
+ * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
+ * (C) Copyright 2002, 2003 Motorola Inc.
+ * Xianghua Xiao (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <mach/mmu.h>
+#include <mach/immap_85xx.h>
+
+void __noreturn reset_cpu(unsigned long addr)
+{
+ void __iomem *regs = (void __iomem *)MPC85xx_GUTS_ADDR;
+
+ /* Everything after the first generation of PQ3 parts has RSTCR */
+ out_be32(regs + MPC85xx_GUTS_RSTCR_OFFSET, 0x2); /* HRESET_REQ */
+ udelay(100);
+
+ while (1)
+ ;
+}
+
+long int initdram(int board_type)
+{
+ phys_size_t dram_size = 0;
+
+ dram_size = fixed_sdram();
+
+ dram_size = e500_setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
+ return dram_size;
+}
+
+/*
+ * Return the memory size based on the configuration registers.
+ */
+phys_size_t fsl_get_effective_memsize(void)
+{
+ void __iomem *regs = (void __iomem *)(MPC85xx_DDR_ADDR);
+ phys_size_t sdram_size;
+ uint san , ean;
+ uint reg;
+ int ix;
+
+ sdram_size = 0;
+
+ for (ix = 0; ix < CFG_CHIP_SELECTS_PER_CTRL; ix++) {
+ if (in_be32(regs + DDR_OFF(CS0_CONFIG) + (ix * 8)) &
+ SDRAM_CFG_MEM_EN) {
+ reg = in_be32(regs + DDR_OFF(CS0_BNDS) + (ix * 8));
+ /* start address */
+ san = (reg & 0x0fff00000) >> 16;
+ /* end address */
+ ean = (reg & 0x00000fff);
+ sdram_size = ((ean - san + 1) << 24);
+ }
+ }
+
+ return sdram_size;
+}
diff --git a/arch/ppc/mach-mpc85xx/cpu_init.c b/arch/ppc/mach-mpc85xx/cpu_init.c
new file mode 100644
index 0000000000..958250db54
--- /dev/null
+++ b/arch/ppc/mach-mpc85xx/cpu_init.c
@@ -0,0 +1,127 @@
+/*
+ * Copyright 2012 GE Intelligent Platforms, Inc.
+ *
+ * Copyright 2007-2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2003 Motorola Inc.
+ * Modified by Xianghua Xiao, X.Xiao@motorola.com
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <init.h>
+#include <asm/processor.h>
+#include <asm/fsl_law.h>
+#include <mach/mpc85xx.h>
+#include <mach/mmu.h>
+#include <mach/immap_85xx.h>
+
+static void fsl_setup_ccsrbar(void)
+{
+ u32 temp;
+ u32 mas0, mas1, mas2, mas3, mas7;
+ u32 *ccsr_virt = (u32 *)(CFG_CCSRBAR + 0x1000);
+
+ mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(1);
+ mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_4K);
+ mas2 = FSL_BOOKE_MAS2(CFG_CCSRBAR + 0x1000, MAS2_I|MAS2_G);
+ mas3 = FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, MAS3_SW|MAS3_SR);
+ mas7 = FSL_BOOKE_MAS7(CFG_CCSRBAR_DEFAULT);
+
+ e500_write_tlb(mas0, mas1, mas2, mas3, mas7);
+
+ temp = in_be32(ccsr_virt);
+ out_be32(ccsr_virt, CFG_CCSRBAR_PHYS >> 12);
+ temp = in_be32((u32 *)CFG_CCSRBAR);
+}
+
+int fsl_l2_cache_init(void)
+{
+ void __iomem *l2cache = (void __iomem *)MPC85xx_L2_ADDR;
+ uint cache_ctl;
+ uint svr, ver;
+ u32 l2siz_field;
+
+ svr = get_svr();
+ ver = SVR_SOC_VER(svr);
+
+ asm("msync;isync");
+ cache_ctl = in_be32(l2cache + MPC85xx_L2_CTL_OFFSET);
+
+ l2siz_field = (cache_ctl >> 28) & 0x3;
+
+ switch (l2siz_field) {
+ case 0x0:
+ return -1;
+ break;
+ case 0x1:
+ cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, L2SRAM=0 */
+ break;
+ case 0x2:
+ /* set L2E=1, L2I=1, & L2SRAM=0 */
+ cache_ctl = 0xc0000000;
+ break;
+ case 0x3:
+ /* set L2E=1, L2I=1, & L2SRAM=0 */
+ cache_ctl = 0xc0000000;
+ break;
+ }
+
+ if (!(in_be32(l2cache + MPC85xx_L2_CTL_OFFSET) & MPC85xx_L2CTL_L2E)) {
+ asm("msync;isync");
+ /* invalidate & enable */
+ out_be32(l2cache + MPC85xx_L2_CTL_OFFSET, cache_ctl);
+ asm("msync;isync");
+ }
+
+ return 0;
+}
+
+void cpu_init_early_f(void)
+{
+ u32 mas0, mas1, mas2, mas3, mas7;
+
+ mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(0);
+ mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_4K);
+ mas2 = FSL_BOOKE_MAS2(CFG_CCSRBAR, MAS2_I|MAS2_G);
+ mas3 = FSL_BOOKE_MAS3(CFG_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR);
+ mas7 = FSL_BOOKE_MAS7(CFG_CCSRBAR_PHYS);
+
+ e500_write_tlb(mas0, mas1, mas2, mas3, mas7);
+
+ /* set up CCSR if we want it moved */
+ if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR_PHYS)
+ fsl_setup_ccsrbar();
+
+ fsl_init_laws();
+ e500_invalidate_tlb(0);
+ e500_init_tlbs();
+}
+
+void cpu_init_f(void)
+{
+ e500_disable_tlb(14);
+ e500_disable_tlb(15);
+
+ fsl_init_early_memctl_regs();
+}
diff --git a/arch/ppc/mach-mpc85xx/cpuid.c b/arch/ppc/mach-mpc85xx/cpuid.c
new file mode 100644
index 0000000000..598201b5b5
--- /dev/null
+++ b/arch/ppc/mach-mpc85xx/cpuid.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and
+ * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains
+ * cpu specific common code for 85xx/86xx processors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/cache.h>
+#include <asm/io.h>
+#include <mach/immap_85xx.h>
+
+struct cpu_type cpu_type_list[] = {
+ CPU_TYPE_ENTRY(P2020, P2020, 2),
+ CPU_TYPE_ENTRY(P2020, P2020_E, 2),
+};
+
+struct cpu_type cpu_type_unknown = CPU_TYPE_ENTRY(Unknown, Unknown, 1);
+
+struct cpu_type *identify_cpu(u32 ver)
+{
+ int i;
+ for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) {
+ if (cpu_type_list[i].soc_ver == ver)
+ return &cpu_type_list[i];
+ }
+ return &cpu_type_unknown;
+}
+
+int fsl_cpu_numcores(void)
+{
+ void __iomem *pic = (void __iomem *)MPC8xxx_PIC_ADDR;
+ struct cpu_type *cpu;
+ uint svr;
+ uint ver;
+ int tmp;
+
+ svr = get_svr();
+ ver = SVR_SOC_VER(svr);
+ cpu = identify_cpu(ver);
+
+ /* better to query feature reporting register than just assume 1 */
+ if (cpu == &cpu_type_unknown) {
+ tmp = in_be32(pic + MPC85xx_PIC_FRR_OFFSET);
+ tmp = (tmp & MPC8xxx_PICFRR_NCPU_MASK) >>
+ MPC8xxx_PICFRR_NCPU_SHIFT;
+ tmp += 1;
+ } else {
+ tmp = cpu->num_cores;
+ }
+
+ return tmp;
+}
diff --git a/arch/ppc/mach-mpc85xx/fsl_law.c b/arch/ppc/mach-mpc85xx/fsl_law.c
new file mode 100644
index 0000000000..422943dea2
--- /dev/null
+++ b/arch/ppc/mach-mpc85xx/fsl_law.c
@@ -0,0 +1,160 @@
+/*
+ * Copyright 2012 GE Intelligent Platforms, Inc.
+ *
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/config.h>
+#include <asm/fsl_law.h>
+
+#define FSL_HW_NUM_LAWS FSL_NUM_LAWS
+
+#define LAW_BASE (CFG_IMMR + 0xc08)
+#define LAWAR_ADDR(x) ((u32 *)LAW_BASE + 8 * (x) + 2)
+#define LAWBAR_ADDR(x) ((u32 *)LAW_BASE + 8 * (x))
+#define LAWBAR_SHIFT 12
+
+static inline phys_addr_t fsl_get_law_base_addr(int idx)
+{
+ return (phys_addr_t)in_be32(LAWBAR_ADDR(idx)) << LAWBAR_SHIFT;
+}
+
+static inline void fsl_set_law_base_addr(int idx, phys_addr_t addr)
+{
+ out_be32(LAWBAR_ADDR(idx), addr >> LAWBAR_SHIFT);
+}
+
+static void fsl_set_law(u8 idx, phys_addr_t addr, enum law_size sz,
+ enum law_trgt_if id)
+{
+ out_be32(LAWAR_ADDR(idx), 0);
+ fsl_set_law_base_addr(idx, addr);
+ out_be32(LAWAR_ADDR(idx), LAW_EN | ((u32)id << 20) | (u32)sz);
+
+ /* Read back so that we sync the writes */
+ in_be32(LAWAR_ADDR(idx));
+}
+
+static int fsl_is_free_law(int idx)
+{
+ u32 lawar;
+
+ lawar = in_be32(LAWAR_ADDR(idx));
+ if (!(lawar & LAW_EN))
+ return 1;
+
+ return 0;
+}
+
+static void fsl_set_next_law(phys_addr_t addr, enum law_size sz,
+ enum law_trgt_if id)
+{
+ u32 idx;
+
+ for (idx = 0; idx < FSL_HW_NUM_LAWS; idx++) {
+ if (fsl_is_free_law(idx)) {
+ fsl_set_law(idx, addr, sz, id);
+ break;
+ }
+ }
+
+ if (idx >= FSL_HW_NUM_LAWS)
+ panic("No more LAWS available\n");
+}
+
+static void fsl_set_last_law(phys_addr_t addr, enum law_size sz,
+ enum law_trgt_if id)
+{
+ u32 idx;
+
+ for (idx = (FSL_HW_NUM_LAWS - 1); idx >= 0; idx--) {
+ if (fsl_is_free_law(idx)) {
+ fsl_set_law(idx, addr, sz, id);
+ break;
+ }
+ }
+
+ if (idx < 0)
+ panic("No more LAWS available\n");
+}
+
+/* use up to 2 LAWs for DDR, use the last available LAWs */
+int fsl_set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
+{
+ u64 start_align, law_sz;
+ int law_sz_enc;
+
+ if (start == 0)
+ start_align = 1ull << (LAW_SIZE_32G + 1);
+ else
+ start_align = 1ull << (ffs64(start) - 1);
+
+ law_sz = min(start_align, sz);
+ law_sz_enc = __ilog2_u64(law_sz) - 1;
+
+ fsl_set_last_law(start, law_sz_enc, id);
+
+ /* recalculate size based on what was actually covered by the law */
+ law_sz = 1ull << __ilog2_u64(law_sz);
+
+ /* do we still have anything to map */
+ sz = sz - law_sz;
+ if (sz) {
+ start += law_sz;
+
+ start_align = 1ull << (ffs64(start) - 1);
+ law_sz = min(start_align, sz);
+ law_sz_enc = __ilog2_u64(law_sz) - 1;
+
+ fsl_set_last_law(start, law_sz_enc, id);
+ } else {
+ return 0;
+ }
+
+ /* do we still have anything to map */
+ sz = sz - law_sz;
+ if (sz)
+ return 1;
+
+ return 0;
+}
+
+void fsl_init_laws(void)
+{
+ int i;
+
+ if (FSL_HW_NUM_LAWS > 32)
+ panic("FSL_HW_NUM_LAWS can not be > 32 w/o code changes");
+
+ for (i = 0; i < num_law_entries; i++) {
+ if (law_table[i].index == -1)
+ fsl_set_next_law(law_table[i].addr,
+ law_table[i].size,
+ law_table[i].trgt_id);
+ else
+ fsl_set_law(law_table[i].index, law_table[i].addr,
+ law_table[i].size, law_table[i].trgt_id);
+ }
+}
diff --git a/arch/ppc/mach-mpc85xx/fsl_lbc.c b/arch/ppc/mach-mpc85xx/fsl_lbc.c
new file mode 100644
index 0000000000..ac9ca7402b
--- /dev/null
+++ b/arch/ppc/mach-mpc85xx/fsl_lbc.c
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <asm/fsl_lbc.h>
+#include <mach/immap_85xx.h>
+
+void fsl_init_early_memctl_regs(void)
+{
+ fsl_set_lbc_br(0, CFG_BR0_PRELIM);
+ fsl_set_lbc_or(0, CFG_OR0_PRELIM);
+}
diff --git a/arch/ppc/mach-mpc85xx/include/mach/clocks.h b/arch/ppc/mach-mpc85xx/include/mach/clocks.h
new file mode 100644
index 0000000000..94771682e8
--- /dev/null
+++ b/arch/ppc/mach-mpc85xx/include/mach/clocks.h
@@ -0,0 +1,18 @@
+#ifndef __ASM_ARCH_CLOCKS_H
+#define __ASM_ARCH_CLOCKS_H
+
+#include <mach/config_mpc85xx.h>
+
+struct sys_info {
+ unsigned long freqProcessor[MAX_CPUS];
+ unsigned long freqSystemBus;
+ unsigned long freqDDRBus;
+ unsigned long freqLocalBus;
+};
+
+#define NSEC_PER_SEC 1000000000L
+
+unsigned long fsl_get_bus_freq(ulong dummy);
+unsigned long fsl_get_timebase_clock(void);
+void fsl_get_sys_info(struct sys_info *sysInfo);
+#endif /* __ASM_ARCH_CLOCKS_H */
diff --git a/arch/ppc/mach-mpc85xx/include/mach/config_mpc85xx.h b/arch/ppc/mach-mpc85xx/include/mach/config_mpc85xx.h
new file mode 100644
index 0000000000..9b095c71a4
--- /dev/null
+++ b/arch/ppc/mach-mpc85xx/include/mach/config_mpc85xx.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2012 GE Intelligent Platforms, Inc.
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_MPC85xx_CONFIG_H_
+#define _ASM_MPC85xx_CONFIG_H_
+
+#define RESET_VECTOR 0xfffffffc
+
+/* Number of TLB CAM entries we have on FSL Book-E chips */
+#if defined(CONFIG_E500)
+#define NUM_TLBCAMS 16
+#endif
+
+#if defined(CONFIG_P2020)
+#define MAX_CPUS 2
+#define FSL_NUM_LAWS 12
+#define FSL_SEC_COMPAT 2
+#else
+#error Processor type not defined for this platform
+#endif
+
+#endif /* _ASM_MPC85xx_CONFIG_H_ */
diff --git a/arch/ppc/mach-mpc85xx/include/mach/early_udelay.h b/arch/ppc/mach-mpc85xx/include/mach/early_udelay.h
new file mode 100644
index 0000000000..dc2d8bcdd0
--- /dev/null
+++ b/arch/ppc/mach-mpc85xx/include/mach/early_udelay.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2012 GE Intelligent Platforms, Inc.
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* early_udelay: delay execution before timers are initialized
+ *
+ * "usecs * 100" gives a time of around 1 second on a 1Ghz CPU.
+ */
+static inline void early_udelay(unsigned long usecs)
+{
+ uint64_t start;
+ uint32_t loops = usecs * 100;
+
+ start = get_ticks();
+
+ while ((get_ticks() - start) < loops)
+ ;
+}
diff --git a/arch/ppc/mach-mpc85xx/include/mach/immap_85xx.h b/arch/ppc/mach-mpc85xx/include/mach/immap_85xx.h
new file mode 100644
index 0000000000..b80224952d
--- /dev/null
+++ b/arch/ppc/mach-mpc85xx/include/mach/immap_85xx.h
@@ -0,0 +1,132 @@
+/*
+ * MPC85xx Internal Memory Map
+ *
+ * Copyright 2007-2011 Freescale Semiconductor, Inc.
+ *
+ * Copyright(c) 2002,2003 Motorola Inc.
+ * Xianghua Xiao (x.xiao@motorola.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMMAP_85xx__
+#define __IMMAP_85xx__
+
+#include <asm/types.h>
+#include <asm/fsl_lbc.h>
+#include <asm/config.h>
+
+#define MPC85xx_LOCAL_OFFSET 0x0000
+#define MPC85xx_ECM_OFFSET 0x1000
+#define MPC85xx_DDR_OFFSET 0x2000
+#define MPC85xx_LBC_OFFSET 0x5000
+
+#define MPC85xx_GPIO_OFFSET 0xf000
+#define MPC85xx_L2_OFFSET 0x20000
+
+#define MPC85xx_PIC_OFFSET 0x40000
+#define MPC85xx_GUTS_OFFSET 0xe0000
+
+#define MPC85xx_LOCAL_ADDR (CFG_IMMR + MPC85xx_LOCAL_OFFSET)
+#define MPC85xx_ECM_ADDR (CFG_IMMR + MPC85xx_ECM_OFFSET)
+#define MPC85xx_GUTS_ADDR (CFG_IMMR + MPC85xx_GUTS_OFFSET)
+#define MPC85xx_DDR_ADDR (CFG_IMMR + MPC85xx_DDR_OFFSET)
+#define LBC_ADDR (CFG_IMMR + MPC85xx_LBC_OFFSET)
+#define MPC85xx_GPIO_ADDR (CFG_IMMR + MPC85xx_GPIO_OFFSET)
+#define MPC85xx_L2_ADDR (CFG_IMMR + MPC85xx_L2_OFFSET)
+#define MPC8xxx_PIC_ADDR (CFG_IMMR + MPC85xx_PIC_OFFSET)
+
+/* Local-Access Registers */
+#define MPC85xx_LOCAL_BPTR_OFFSET 0x20 /* Boot Page Translation */
+
+/* ECM Registers */
+#define MPC85xx_ECM_EEBPCR_OFFSET 0x00 /* ECM CCB Port Configuration */
+
+/*
+ * DDR Memory Controller Register Offsets
+ */
+/* Chip Select 0, 1,2, 3 Memory Bounds */
+#define MPC85xx_DDR_CS0_BNDS_OFFSET 0x000
+#define MPC85xx_DDR_CS1_BNDS_OFFSET 0x008
+#define MPC85xx_DDR_CS2_BNDS_OFFSET 0x010
+#define MPC85xx_DDR_CS3_BNDS_OFFSET 0x018
+/* Chip Select 0, 1, 2, 3 Configuration */
+#define MPC85xx_DDR_CS0_CONFIG_OFFSET 0x080
+#define MPC85xx_DDR_CS1_CONFIG_OFFSET 0x084
+#define MPC85xx_DDR_CS2_CONFIG_OFFSET 0x088
+#define MPC85xx_DDR_CS3_CONFIG_OFFSET 0x08c
+/* SDRAM Timing Configuration 0, 1, 2, 3 */
+#define MPC85xx_DDR_TIMING_CFG_3_OFFSET 0x100
+#define MPC85xx_DDR_TIMING_CFG_0_OFFSET 0x104
+#define MPC85xx_DDR_TIMING_CFG_1_OFFSET 0x108
+#define MPC85xx_DDR_TIMING_CFG_2_OFFSET 0x10c
+/* SDRAM Control Configuration */
+#define MPC85xx_DDR_SDRAM_CFG_OFFSET 0x110
+#define MPC85xx_DDR_SDRAM_CFG_2_OFFSET 0x114
+/* SDRAM Mode Configuration */
+#define MPC85xx_DDR_SDRAM_MODE_OFFSET 0x118
+#define MPC85xx_DDR_SDRAM_MODE_2_OFFSET 0x11c
+/* SDRAM Mode Control */
+#define MPC85xx_DDR_SDRAM_MD_CNTL_OFFSET 0x120
+/* SDRAM Interval Configuration */
+#define MPC85xx_DDR_SDRAM_INTERVAL_OFFSET 0x124
+/* SDRAM Data initialization */
+#define MPC85xx_DDR_SDRAM_DATA_INIT_OFFSET 0x128
+/* SDRAM Clock Control */
+#define MPC85xx_DDR_SDRAM_CLK_CNTL_OFFSET 0x130
+/* training init and extended addr */
+#define MPC85xx_DDR_SDRAM_INIT_ADDR_OFFSET 0x148
+#define MPC85xx_DDR_SDRAM_INIT_ADDR_EXT_OFFSET 0x14c
+
+#define DDR_OFF(REGNAME) (MPC85xx_DDR_##REGNAME##_OFFSET)
+
+/*
+ * GPIO Register Offsets
+ */
+#define MPC85xx_GPIO_GPDIR 0x00
+#define MPC85xx_GPIO_GPDAT 0x08
+
+/*
+ * L2 Cache Register Offsets
+ */
+#define MPC85xx_L2_CTL_OFFSET 0x0 /* L2 configuration 0 */
+#define MPC85xx_L2CTL_L2E 0x80000000
+
+/* PIC registers offsets */
+#define MPC85xx_PIC_WHOAMI_OFFSET 0x090
+#define MPC85xx_PIC_FRR_OFFSET 0x1000 /* Feature Reporting */
+/* PIC registers fields values and masks. */
+#define MPC8xxx_PICFRR_NCPU_MASK 0x00001f00
+#define MPC8xxx_PICFRR_NCPU_SHIFT 8
+#define MPC85xx_PICGCR_RST 0x80000000
+#define MPC85xx_PICGCR_M 0x20000000
+
+#define MPC85xx_PIC_IACK0_OFFSET 0x600a0 /* IRQ Acknowledge for
+ Processor 0 */
+
+/* Global Utilities Register Offsets and field values */
+#define MPC85xx_GUTS_PORPLLSR_OFFSET 0x0
+#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
+#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9
+#define MPC85xx_GUTS_DEVDISR_OFFSET 0x70
+#define MPC85xx_DEVDISR_TB0 0x00004000
+#define MPC85xx_DEVDISR_TB1 0x00001000
+#define MPC85xx_GUTS_RSTCR_OFFSET 0xb0
+
+#endif /*__IMMAP_85xx__*/
diff --git a/arch/ppc/mach-mpc85xx/include/mach/mmu.h b/arch/ppc/mach-mpc85xx/include/mach/mmu.h
new file mode 100644
index 0000000000..00459e2d29
--- /dev/null
+++ b/arch/ppc/mach-mpc85xx/include/mach/mmu.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2012 GE Intelligent Platforms, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#ifndef _MPC85XX_MMU_H_
+#define _MPC85XX_MMU_H_
+
+#ifdef CONFIG_E500
+#include <asm/mmu.h>
+
+#ifndef __ASSEMBLY__
+extern void e500_set_tlb(u8 tlb, u32 epn, u64 rpn, u8 perms, u8 wimge,
+ u8 ts, u8 esel, u8 tsize, u8 iprot);
+extern void e500_disable_tlb(u8 esel);
+extern void e500_invalidate_tlb(u8 tlb);
+extern void e500_init_tlbs(void);
+extern int e500_find_tlb_idx(void *addr, u8 tlbsel);
+extern void e500_init_used_tlb_cams(void);
+
+extern unsigned int e500_setup_ddr_tlbs(unsigned int memsize_in_meg);
+extern void e500_write_tlb(u32 _mas0, u32 _mas1, u32 _mas2, u32 _mas3,
+ u32 _mas7);
+
+#define FSL_SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz,\
+ _iprot) \
+ { .mas0 = FSL_BOOKE_MAS0(_tlb, _esel, 0), \
+ .mas1 = FSL_BOOKE_MAS1(1, _iprot, 0, _ts, _sz), \
+ .mas2 = FSL_BOOKE_MAS2(_epn, _wimge), \
+ .mas3 = FSL_BOOKE_MAS3(_rpn, 0, _perms), \
+ .mas7 = FSL_BOOKE_MAS7(_rpn), }
+
+struct fsl_e_tlb_entry {
+ u32 mas0;
+ u32 mas1;
+ u32 mas2;
+ u32 mas3;
+ u32 mas7;
+};
+extern struct fsl_e_tlb_entry tlb_table[];
+extern int num_tlb_entries;
+#endif
+#endif
+#endif /* _MPC85XX_MMU_H_ */
diff --git a/arch/ppc/mach-mpc85xx/include/mach/mpc85xx.h b/arch/ppc/mach-mpc85xx/include/mach/mpc85xx.h
new file mode 100644
index 0000000000..1d9993ace9
--- /dev/null
+++ b/arch/ppc/mach-mpc85xx/include/mach/mpc85xx.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2004, 2007 Freescale Semiconductor.
+ * Copyright(c) 2003 Motorola Inc.
+ */
+
+#ifndef __MPC85xx_H__
+#define __MPC85xx_H__
+
+/* define for common ppc_asm.tmpl */
+#define EXC_OFF_SYS_RESET 0x100 /* System reset */
+#define _START_OFFSET 0
+
+#ifndef __ASSEMBLY__
+int fsl_l2_cache_init(void);
+int fsl_cpu_numcores(void);
+
+phys_size_t fsl_get_effective_memsize(void);
+
+#endif /* __ASSEMBLY__ */
+
+#define END_OF_MEM (fsl_get_effective_memsize())
+
+#endif /* __MPC85xx_H__ */
diff --git a/arch/ppc/mach-mpc85xx/speed.c b/arch/ppc/mach-mpc85xx/speed.c
new file mode 100644
index 0000000000..40d3664188
--- /dev/null
+++ b/arch/ppc/mach-mpc85xx/speed.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright 2012 GE Intelligent Platforms, Inc.
+ *
+ * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2003 Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <mach/clocks.h>
+#include <mach/immap_85xx.h>
+#include <mach/mpc85xx.h>
+
+void fsl_get_sys_info(struct sys_info *sysInfo)
+{
+ void __iomem *gur = (void __iomem *)(MPC85xx_GUTS_ADDR);
+ uint plat_ratio, e500_ratio, half_freqSystemBus;
+ uint lcrr_div;
+ int i;
+
+ plat_ratio = in_be32(gur + MPC85xx_GUTS_PORPLLSR_OFFSET) & 0x0000003e;
+ plat_ratio >>= 1;
+ sysInfo->freqSystemBus = plat_ratio * CFG_SYS_CLK_FREQ;
+
+ /*
+ * Divide before multiply to avoid integer
+ * overflow for processor speeds above 2GHz.
+ */
+ half_freqSystemBus = sysInfo->freqSystemBus/2;
+ for (i = 0; i < fsl_cpu_numcores(); i++) {
+ e500_ratio = (in_be32(gur + MPC85xx_GUTS_PORPLLSR_OFFSET) >>
+ (i * 8 + 16)) & 0x3f;
+ sysInfo->freqProcessor[i] = e500_ratio * half_freqSystemBus;
+ }
+
+ /* Note: freqDDRBus is the MCLK frequency, not the data rate. */
+ sysInfo->freqDDRBus = sysInfo->freqSystemBus;
+
+#ifdef CFG_DDR_CLK_FREQ
+ {
+ u32 ddr_ratio = (in_be32(gur + MPC85xx_GUTS_PORPLLSR_OFFSET) &
+ MPC85xx_PORPLLSR_DDR_RATIO) >>
+ MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
+ if (ddr_ratio != 0x7)
+ sysInfo->freqDDRBus = ddr_ratio * CFG_DDR_CLK_FREQ;
+ }
+#endif
+
+ lcrr_div = in_be32(LBC_BASE_ADDR + FSL_LBC_LCCR) & LCRR_CLKDIV;
+
+ if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
+ /*
+ * The entire PQ38 family use the same bit-representation
+ * for twice the clock divider values.
+ */
+ lcrr_div *= 2;
+
+ sysInfo->freqLocalBus = sysInfo->freqSystemBus / lcrr_div;
+ } else {
+ /* In case anyone cares what the unknown value is */
+ sysInfo->freqLocalBus = lcrr_div;
+ }
+}
+
+unsigned long fsl_get_bus_freq(ulong dummy)
+{
+ struct sys_info sys_info;
+
+ fsl_get_sys_info(&sys_info);
+
+ return sys_info.freqSystemBus;
+}
+
+unsigned long fsl_get_timebase_clock(void)
+{
+ struct sys_info sysinfo;
+
+ fsl_get_sys_info(&sysinfo);
+
+ return (sysinfo.freqSystemBus + 4UL)/8UL;
+}
diff --git a/arch/ppc/mach-mpc85xx/time.c b/arch/ppc/mach-mpc85xx/time.c
new file mode 100644
index 0000000000..408a28a2eb
--- /dev/null
+++ b/arch/ppc/mach-mpc85xx/time.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2012 GE Intelligent Platforms, Inc.
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <clock.h>
+#include <init.h>
+#include <mach/clocks.h>
+
+uint64_t ppc_clocksource_read(void)
+{
+ return get_ticks();
+}
+
+static struct clocksource cs = {
+ .read = ppc_clocksource_read,
+ .mask = CLOCKSOURCE_MASK(64),
+};
+
+static int clocksource_init(void)
+{
+ /* reset time base */
+ asm ("li 3,0 ; mttbu 3 ; mttbl 3 ;");
+
+ clocks_calc_mult_shift(&cs.mult, &cs.shift,
+ fsl_get_timebase_clock(), NSEC_PER_SEC, 10);
+
+ init_clock(&cs);
+
+ return 0;
+}
+
+core_initcall(clocksource_init);
diff --git a/commands/Kconfig b/commands/Kconfig
index 49a56ca2ff..52e1f171bb 100644
--- a/commands/Kconfig
+++ b/commands/Kconfig
@@ -113,6 +113,13 @@ config CMD_LINUX_EXEC
help
This command executes a command on the Linux host.
+config CMD_GLOBAL
+ select GLOBALVAR
+ tristate
+ prompt "global"
+ help
+ The global command allows to create global variables
+
endmenu
menu "file commands "
@@ -322,6 +329,7 @@ config CMD_BOOTM
select CRC32
select UNCOMPRESS
select FILETYPE
+ select GLOBALVAR
prompt "bootm"
config CMD_BOOTM_SHOW_TYPE
@@ -389,6 +397,18 @@ config CMD_BOOTU
compile in the 'bootu' command to start raw (uncompressed)
Linux images
+config FLEXIBLE_BOOTARGS
+ bool
+ prompt "flexible Linux bootargs generation"
+ depends on CMD_GLOBAL
+ help
+ Select this to get a more flexible bootargs generation. With this
+ option the bootargs are concatenated together from global variables
+ beginning with 'global.linux.bootargs.' and 'global.linux.mtdparts.'
+ This allows for more flexible scripting since with it it's possible
+ to replace parts of the bootargs string without reconstructing it
+ completely
+
config CMD_LINUX16
tristate
depends on X86
diff --git a/commands/Makefile b/commands/Makefile
index f02b5cac3a..4c8a0a9595 100644
--- a/commands/Makefile
+++ b/commands/Makefile
@@ -65,3 +65,4 @@ obj-$(CONFIG_CMD_MAGICVAR) += magicvar.o
obj-$(CONFIG_CMD_IOMEM) += iomem.o
obj-$(CONFIG_CMD_LINUX_EXEC) += linux_exec.o
obj-$(CONFIG_CMD_AUTOMOUNT) += automount.o
+obj-$(CONFIG_CMD_GLOBAL) += global.o
diff --git a/commands/bootm.c b/commands/bootm.c
index 0c0e56a617..2989d39311 100644
--- a/commands/bootm.c
+++ b/commands/bootm.c
@@ -47,6 +47,8 @@
#include <memory.h>
#include <filetype.h>
#include <binfmt.h>
+#include <globalvar.h>
+#include <magicvar.h>
#include <asm-generic/memory_layout.h>
static LIST_HEAD(handler_list);
@@ -136,7 +138,7 @@ static int bootm_open_initrd_uimage(struct image_data *data)
}
#ifdef CONFIG_OFTREE
-static int bootm_open_oftree(struct image_data *data, char *oftree, int num)
+static int bootm_open_oftree(struct image_data *data, const char *oftree, int num)
{
enum filetype ft;
struct fdt_header *fdt, *fixfdt;
@@ -231,19 +233,25 @@ static struct image_handler *bootm_find_handler(enum filetype filetype,
return NULL;
}
-static void bootm_image_name_and_no(char *name, int *no)
+static char *bootm_image_name_and_no(const char *name, int *no)
{
- char *at;
+ char *at, *ret;
+
+ if (!name || !*name)
+ return NULL;
*no = 0;
- at = strchr(name, '@');
+ ret = xstrdup(name);
+ at = strchr(ret, '@');
if (!at)
- return;
+ return ret;
*at++ = 0;
*no = simple_strtoul(at, NULL, 10);
+
+ return ret;
}
#define BOOTM_OPTS_COMMON "ca:e:vo:f"
@@ -261,7 +269,7 @@ static int do_bootm(int argc, char *argv[])
struct image_data data;
int ret = 1;
enum filetype os_type, initrd_type = filetype_unknown;
- char *oftree = NULL;
+ const char *oftree = NULL, *initrd_file = NULL, *os_file = NULL;
int fallback = 0;
memset(&data, 0, sizeof(struct image_data));
@@ -271,6 +279,11 @@ static int do_bootm(int argc, char *argv[])
data.verify = 0;
data.verbose = 0;
+ oftree = getenv("global.bootm.oftree");
+ os_file = getenv("global.bootm.image");
+ if (IS_ENABLED(CONFIG_CMD_BOOTM_INITRD))
+ initrd_file = getenv("global.bootm.initrd");
+
while ((opt = getopt(argc, argv, BOOTM_OPTS)) > 0) {
switch(opt) {
case 'c':
@@ -281,7 +294,7 @@ static int do_bootm(int argc, char *argv[])
data.initrd_address = simple_strtoul(optarg, NULL, 0);
break;
case 'r':
- data.initrd_file = optarg;
+ initrd_file = optarg;
break;
#endif
case 'a':
@@ -304,12 +317,21 @@ static int do_bootm(int argc, char *argv[])
}
}
- if (optind == argc)
- return COMMAND_ERROR_USAGE;
+ if (optind != argc)
+ os_file = argv[optind];
+
+ if (!os_file || !*os_file) {
+ printf("no boot image given\n");
+ goto err_out;
+ }
+
+ if (initrd_file && !*initrd_file)
+ initrd_file = NULL;
- data.os_file = argv[optind];
+ if (oftree && !*oftree)
+ oftree = NULL;
- bootm_image_name_and_no(data.os_file, &data.os_num);
+ data.os_file = bootm_image_name_and_no(os_file, &data.os_num);
os_type = file_name_detect_type(data.os_file);
if ((int)os_type < 0) {
@@ -332,8 +354,8 @@ static int do_bootm(int argc, char *argv[])
}
}
- if (IS_ENABLED(CONFIG_CMD_BOOTM_INITRD) && data.initrd_file) {
- bootm_image_name_and_no(data.initrd_file, &data.initrd_num);
+ if (IS_ENABLED(CONFIG_CMD_BOOTM_INITRD) && initrd_file) {
+ data.initrd_file = bootm_image_name_and_no(initrd_file, &data.initrd_num);
initrd_type = file_name_detect_type(data.initrd_file);
if ((int)initrd_type < 0) {
@@ -388,7 +410,7 @@ static int do_bootm(int argc, char *argv[])
if (oftree) {
int oftree_num;
- bootm_image_name_and_no(oftree, &oftree_num);
+ oftree = bootm_image_name_and_no(oftree, &oftree_num);
ret = bootm_open_oftree(&data, oftree, oftree_num);
if (ret)
@@ -417,6 +439,8 @@ static int do_bootm(int argc, char *argv[])
printf("handler failed with %s\n", strerror(-ret));
err_out:
+ free(data.initrd_file);
+ free(data.os_file);
if (data.os_res)
release_sdram_region(data.os_res);
if (data.initrd_res)
@@ -428,6 +452,18 @@ err_out:
return 1;
}
+static int bootm_init(void)
+{
+
+ globalvar_add_simple("bootm.image");
+ globalvar_add_simple("bootm.oftree");
+ if (IS_ENABLED(CONFIG_CMD_BOOTM_INITRD))
+ globalvar_add_simple("bootm.initrd");
+
+ return 0;
+}
+late_initcall(bootm_init);
+
BAREBOX_CMD_HELP_START(bootm)
BAREBOX_CMD_HELP_USAGE("bootm [OPTIONS] image\n")
BAREBOX_CMD_HELP_SHORT("Boot an application image.\n")
@@ -453,6 +489,8 @@ BAREBOX_CMD_START(bootm)
BAREBOX_CMD_END
BAREBOX_MAGICVAR(bootargs, "Linux Kernel parameters");
+BAREBOX_MAGICVAR_NAMED(global_bootm_image, global.bootm.image, "bootm default boot image");
+BAREBOX_MAGICVAR_NAMED(global_bootm_initrd, global.bootm.initrd, "bootm default initrd");
static struct binfmt_hook binfmt_uimage_hook = {
.type = filetype_uimage,
diff --git a/commands/edit.c b/commands/edit.c
index fae76cdb55..eddec0b935 100644
--- a/commands/edit.c
+++ b/commands/edit.c
@@ -62,7 +62,7 @@ static int scrcol = 0; /* the first column on screen */
static void pos(int x, int y)
{
- printf("%c[%d;%dH", 27, y + 1, x + 1);
+ printf("%c[%d;%dH", 27, y + 2, x + 1);
}
static char *screenline(char *line, int *pos)
@@ -409,6 +409,17 @@ static int do_edit(int argc, char *argv[])
lastscrcol = 0;
printf("%c[2J", 27);
+
+ pos(0, -1);
+
+ printf("%c[7m %-25s <ctrl-d>: Save and quit <ctrl-c>: quit %c[0m",
+ 27, argv[1], 27);
+ printf("%c[2;%dr", 27, screenheight);
+
+ screenheight--; /* status line */
+
+ pos(0, 0);
+
refresh(1);
while (1) {
@@ -416,7 +427,7 @@ static int do_edit(int argc, char *argv[])
if (textx > curlen)
textx = curlen;
- if (textx < 0)
+ if (textx < 1)
textx = 0;
screenline(curline->data, &linepos);
@@ -531,7 +542,7 @@ static int do_edit(int argc, char *argv[])
}
out:
free_buffer();
- printf("%c[2J", 27);
+ printf("%c[2J%c[r", 27, 27);
printf("\n");
return 0;
}
diff --git a/commands/global.c b/commands/global.c
new file mode 100644
index 0000000000..de6b13e7bd
--- /dev/null
+++ b/commands/global.c
@@ -0,0 +1,62 @@
+/*
+ * global.c - global shell variables
+ *
+ * Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <common.h>
+#include <malloc.h>
+#include <command.h>
+#include <globalvar.h>
+#include <environment.h>
+
+static int do_global(int argc, char *argv[])
+{
+ int ret;
+ char *value;
+
+ if (argc != 2)
+ return COMMAND_ERROR_USAGE;
+
+ value = strchr(argv[1], '=');
+ if (value) {
+ *value = 0;
+ value++;
+ }
+
+ ret = globalvar_add_simple(argv[1]);
+
+ if (value) {
+ char *name = asprintf("global.%s", argv[1]);
+ ret = setenv(name, value);
+ free(name);
+ }
+
+ return ret ? 1 : 0;
+}
+
+BAREBOX_CMD_HELP_START(global)
+BAREBOX_CMD_HELP_USAGE("global <var>[=<value]\n")
+BAREBOX_CMD_HELP_SHORT("add a new global variable named <var>, optionally set to <value>\n")
+BAREBOX_CMD_HELP_END
+
+BAREBOX_CMD_START(global)
+ .cmd = do_global,
+ .usage = "create global variables",
+ BAREBOX_CMD_HELP(cmd_global_help)
+BAREBOX_CMD_END
diff --git a/commands/i2c.c b/commands/i2c.c
index 39bae35a33..763db8a1ab 100644
--- a/commands/i2c.c
+++ b/commands/i2c.c
@@ -74,10 +74,10 @@ static int do_i2c_write(int argc, char *argv[])
{
struct i2c_adapter *adapter = NULL;
struct i2c_client client;
- int addr = -1, reg = -1, count = -1, verbose = 0, ret, opt, i, bus = 0;
+ int addr = -1, reg = -1, count = -1, verbose = 0, ret, opt, i, bus = 0, wide = 0;
u8 *buf;
- while ((opt = getopt(argc, argv, "a:b:r:v")) > 0) {
+ while ((opt = getopt(argc, argv, "a:b:r:v:w")) > 0) {
switch (opt) {
case 'a':
addr = simple_strtol(optarg, NULL, 0);
@@ -91,6 +91,9 @@ static int do_i2c_write(int argc, char *argv[])
case 'v':
verbose = 1;
break;
+ case 'w':
+ wide = 1;
+ break;
}
}
@@ -112,13 +115,13 @@ static int do_i2c_write(int argc, char *argv[])
for (i = 0; i < count; i++)
*(buf + i) = (char) simple_strtol(argv[optind+i], NULL, 16);
- ret = i2c_write_reg(&client, reg, buf, count);
+ ret = i2c_write_reg(&client, reg | (wide ? I2C_ADDR_16_BIT : 0), buf, count);
if (ret != count)
goto out;
ret = 0;
if (verbose) {
- printf("wrote %i bytes starting at reg 0x%02x to i2cdev 0x%02x on bus %i\n",
+ printf("wrote %i bytes starting at reg 0x%04x to i2cdev 0x%02x on bus %i\n",
count, reg, addr, adapter->nr);
for (i = 0; i < count; i++)
printf("0x%02x ", *(buf + i));
@@ -135,7 +138,8 @@ static const __maybe_unused char cmd_i2c_write_help[] =
"write to i2c device.\n"
" -a 0x<addr> i2c device address\n"
" -b <bus_num> i2c bus number (default = 0)\n"
-" -r 0x<reg> start register\n";
+" -r 0x<reg> start register\n"
+" -w use 16bit-wide address access\n";
BAREBOX_CMD_START(i2c_write)
.cmd = do_i2c_write,
@@ -148,9 +152,9 @@ static int do_i2c_read(int argc, char *argv[])
struct i2c_adapter *adapter = NULL;
struct i2c_client client;
u8 *buf;
- int count = -1, addr = -1, reg = -1, verbose = 0, ret, opt, bus = 0;
+ int count = -1, addr = -1, reg = -1, verbose = 0, ret, opt, bus = 0, wide = 0;
- while ((opt = getopt(argc, argv, "a:b:c:r:v")) > 0) {
+ while ((opt = getopt(argc, argv, "a:b:c:r:v:w")) > 0) {
switch (opt) {
case 'a':
addr = simple_strtol(optarg, NULL, 0);
@@ -167,6 +171,9 @@ static int do_i2c_read(int argc, char *argv[])
case 'v':
verbose = 1;
break;
+ case 'w':
+ wide = 1;
+ break;
}
}
@@ -183,11 +190,11 @@ static int do_i2c_read(int argc, char *argv[])
client.addr = addr;
buf = xmalloc(count);
- ret = i2c_read_reg(&client, reg, buf, count);
+ ret = i2c_read_reg(&client, reg | (wide ? I2C_ADDR_16_BIT : 0), buf, count);
if (ret == count) {
int i;
if (verbose)
- printf("read %i bytes starting at reg 0x%02x from i2cdev 0x%02x on bus %i\n",
+ printf("read %i bytes starting at reg 0x%04x from i2cdev 0x%02x on bus %i\n",
count, reg, addr, adapter->nr);
for (i = 0; i < count; i++)
printf("0x%02x ", *(buf + i));
@@ -205,6 +212,7 @@ static const __maybe_unused char cmd_i2c_read_help[] =
" -a 0x<addr> i2c device address\n"
" -b <bus_num> i2c bus number (default = 0)\n"
" -r 0x<reg> start register\n"
+" -w use 16bit-wide address access\n"
" -c <count> byte count\n";
BAREBOX_CMD_START(i2c_read)
diff --git a/commands/linux16.c b/commands/linux16.c
index 20413b6f0d..eccafa8b57 100644
--- a/commands/linux16.c
+++ b/commands/linux16.c
@@ -162,7 +162,7 @@ static int do_linux16(int argc, char *argv[])
unsigned real_mode_size;
int vid_mode = NORMAL_VGA;
size_t image_size;
- const char *cmdline = getenv("bootargs");
+ const char *cmdline = linux_bootargs_get();
const char *kernel_file;
while((opt = getopt(argc, argv, "v:")) > 0) {
diff --git a/commands/ls.c b/commands/ls.c
index c98d2dad57..ad609f3133 100644
--- a/commands/ls.c
+++ b/commands/ls.c
@@ -49,7 +49,7 @@ int ls(const char *path, ulong flags)
string_list_init(&sl);
if (stat(path, &s))
- return errno;
+ return -errno;
if (flags & LS_SHOWARG && s.st_mode & S_IFDIR)
printf("%s:\n", path);
@@ -61,7 +61,7 @@ int ls(const char *path, ulong flags)
dir = opendir(path);
if (!dir)
- return errno;
+ return -errno;
while ((d = readdir(dir))) {
sprintf(tmp, "%s/%s", path, d->d_name);
@@ -85,7 +85,7 @@ int ls(const char *path, ulong flags)
dir = opendir(path);
if (!dir) {
- errno = -ENOENT;
+ errno = ENOENT;
return -ENOENT;
}
diff --git a/commands/mem.c b/commands/mem.c
index d8e90e056f..080bfdef3f 100644
--- a/commands/mem.c
+++ b/commands/mem.c
@@ -125,7 +125,7 @@ static int open_and_lseek(const char *filename, int mode, off_t pos)
if (ret == -1) {
perror("lseek");
close(fd);
- return ret;
+ return -errno;
}
return fd;
@@ -170,7 +170,6 @@ static int do_mem_md(int argc, char *argv[])
char *filename = DEVMEM;
int mode = O_RWSIZE_4;
- errno = 0;
if (mem_parse_options(argc, argv, "bwls:", &mode, &filename, NULL) < 0)
return 1;
@@ -207,7 +206,7 @@ static int do_mem_md(int argc, char *argv[])
out:
close(fd);
- return errno;
+ return ret ? 1 : 0;
}
static const __maybe_unused char cmd_md_help[] =
@@ -243,8 +242,6 @@ static int do_mem_mw(int argc, char *argv[])
int mode = O_RWSIZE_4;
ulong adr;
- errno = 0;
-
if (mem_parse_options(argc, argv, "bwld:", &mode, NULL, &filename) < 0)
return 1;
@@ -279,12 +276,13 @@ static int do_mem_mw(int argc, char *argv[])
perror("write");
break;
}
+ ret = 0;
optind++;
}
close(fd);
- return errno;
+ return ret ? 1 : 0;
}
static const __maybe_unused char cmd_mw_help[] =
diff --git a/commands/partition.c b/commands/partition.c
index 6cce0423d3..4c3f30c257 100644
--- a/commands/partition.c
+++ b/commands/partition.c
@@ -97,7 +97,7 @@ static int mtd_part_do_parse_one(char *devname, const char *partstr,
partstr = end;
if (*partstr == 'r' && *(partstr + 1) == 'o') {
- flags |= PARTITION_READONLY;
+ flags |= DEVFS_PARTITION_READONLY;
end = (char *)(partstr + 2);
}
diff --git a/commands/saveenv.c b/commands/saveenv.c
index a4b279676d..549fcd4279 100644
--- a/commands/saveenv.c
+++ b/commands/saveenv.c
@@ -54,7 +54,7 @@ static int do_saveenv(int argc, char *argv[])
ret = protect(fd, ~0, 0, 0);
/* ENOSYS is no error here, many devices do not need it */
- if (ret && errno != -ENOSYS) {
+ if (ret && errno != ENOSYS) {
printf("could not unprotect %s: %s\n", filename, errno_str());
close(fd);
return 1;
@@ -63,7 +63,7 @@ static int do_saveenv(int argc, char *argv[])
ret = erase(fd, ~0, 0);
/* ENOSYS is no error here, many devices do not need it */
- if (ret && errno != -ENOSYS) {
+ if (ret && errno != ENOSYS) {
printf("could not erase %s: %s\n", filename, errno_str());
close(fd);
return 1;
@@ -82,7 +82,7 @@ static int do_saveenv(int argc, char *argv[])
ret = protect(fd, ~0, 0, 1);
/* ENOSYS is no error here, many devices do not need it */
- if (ret && errno != -ENOSYS) {
+ if (ret && errno != ENOSYS) {
printf("could not protect %s: %s\n", filename, errno_str());
close(fd);
return 1;
diff --git a/commands/timeout.c b/commands/timeout.c
index 01ece52ac3..d4e90cd897 100644
--- a/commands/timeout.c
+++ b/commands/timeout.c
@@ -25,6 +25,7 @@
#include <errno.h>
#include <getopt.h>
#include <clock.h>
+#include <environment.h>
#define TIMEOUT_RETURN (1 << 0)
#define TIMEOUT_CTRLC (1 << 1)
@@ -35,9 +36,11 @@ static int do_timeout(int argc, char *argv[])
{
int timeout = 3, ret = 1;
int flags = 0, opt, countdown;
+ int key = 0;
uint64_t start, second;
+ const char *varname = NULL;
- while((opt = getopt(argc, argv, "t:crsa")) > 0) {
+ while((opt = getopt(argc, argv, "t:crsav:")) > 0) {
switch(opt) {
case 'r':
flags |= TIMEOUT_RETURN;
@@ -51,6 +54,9 @@ static int do_timeout(int argc, char *argv[])
case 's':
flags |= TIMEOUT_SILENT;
break;
+ case 'v':
+ varname = optarg;
+ break;
default:
return 1;
}
@@ -71,13 +77,14 @@ static int do_timeout(int argc, char *argv[])
do {
if (tstc()) {
- int key = getc();
+ key = getc();
if (flags & TIMEOUT_CTRLC && key == 3)
goto out;
if (flags & TIMEOUT_ANYKEY)
goto out;
if (flags & TIMEOUT_RETURN && key == '\n')
goto out;
+ key = 0;
}
if (!(flags & TIMEOUT_SILENT) && is_timeout(second, SECOND)) {
printf("\b\b%2d", countdown--);
@@ -87,6 +94,11 @@ static int do_timeout(int argc, char *argv[])
ret = 0;
out:
+ if (varname && key) {
+ char str[2] = { };
+ str[0] = key;
+ setenv(varname, str);
+ }
if (!(flags & TIMEOUT_SILENT))
printf("\n");
diff --git a/common/Kconfig b/common/Kconfig
index 73d620a576..b776031bad 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -47,6 +47,9 @@ config BINFMT
bool
select FILETYPE
+config GLOBALVAR
+ bool
+
menu "General Settings "
config LOCALVERSION
@@ -307,7 +310,13 @@ config GLOB
depends on SHELL_HUSH
help
If you want to use wildcards like * or ? say y here.
-
+
+config GLOB_SORT
+ select QSORT
+ bool
+ prompt "glob sort support"
+ depends on GLOB
+
config PROMPT_HUSH_PS2
string
depends on SHELL_HUSH
@@ -342,6 +351,7 @@ config AUTO_COMPLETE
config MENU
bool
prompt "Menu Framework"
+ depends on PROCESS_ESCAPE_SEQUENCE
help
a menu framework that allow us to create list menu to simplify
barebox and make it more user-frendly
@@ -486,13 +496,30 @@ endchoice
endif
+config HAVE_DEFAULT_ENVIRONMENT_NEW
+ bool
+
+config DEFAULT_ENVIRONMENT_GENERIC_NEW
+ bool
+ depends on DEFAULT_ENVIRONMENT
+ depends on SHELL_HUSH
+ select HUSH_GETOPT
+ select GLOB
+ select GLOB_SORT
+ select CMD_GLOBAL
+ select CMD_AUTOMOUNT
+ select FLEXIBLE_BOOTARGS
+ prompt "Generic environment template"
+
config DEFAULT_ENVIRONMENT_GENERIC
bool
+ depends on !HAVE_DEFAULT_ENVIRONMENT_NEW
depends on DEFAULT_ENVIRONMENT
depends on SHELL_HUSH
select HUSH_GETOPT
select CMD_CRC
select CMD_CRC_CMP
+ select CMD_AUTOMOUNT if HAVE_DEFAULT_ENVIRONMENT_NEW
prompt "Default environment generic"
help
With this option barebox will use the generic default
diff --git a/common/Makefile b/common/Makefile
index a58aef94c8..a1926d346d 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -29,17 +29,26 @@ obj-$(CONFIG_CMD_BOOTM) += uimage.o
obj-y += startup.o
obj-y += misc.o
obj-y += memsize.o
+obj-$(CONFIG_GLOBALVAR) += globalvar.o
obj-$(CONFIG_FILETYPE) += filetype.o
obj-y += resource.o
obj-$(CONFIG_MENU) += menu.o
obj-$(CONFIG_PASSWORD) += password.o
obj-$(CONFIG_MODULES) += module.o
+obj-$(CONFIG_FLEXIBLE_BOOTARGS) += bootargs.o
extra-$(CONFIG_MODULES) += module.lds
ifdef CONFIG_DEFAULT_ENVIRONMENT
$(obj)/startup.o: include/generated/barebox_default_env.h
$(obj)/env.o: include/generated/barebox_default_env.h
+ifeq ($(CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW),y)
+DEFAULT_ENVIRONMENT_PATH = "defaultenv-2/base"
+ifeq ($(CONFIG_CMD_MENU_MANAGEMENT),y)
+DEFAULT_ENVIRONMENT_PATH += "defaultenv-2/menu"
+endif
+endif
+
ifeq ($(CONFIG_DEFAULT_ENVIRONMENT_GENERIC),y)
DEFAULT_ENVIRONMENT_PATH = "defaultenv"
endif
diff --git a/common/block.c b/common/block.c
index 4253fc44e1..71ecfd5ab7 100644
--- a/common/block.c
+++ b/common/block.c
@@ -136,7 +136,7 @@ static int block_cache(struct block_device *blk, int block)
chunk = get_chunk(blk);
chunk->block_start = block & ~blk->blkmask;
- debug("%s: %d to %d %s\n", __func__, chunk->block_start,
+ debug("%s: %d to %d\n", __func__, chunk->block_start,
chunk->num);
num_blocks = min(blk->rdbufsize, blk->num_blocks - chunk->block_start);
@@ -161,7 +161,7 @@ static void *block_get(struct block_device *blk, int block)
int ret;
if (block >= blk->num_blocks)
- return NULL;
+ return ERR_PTR(-ENXIO);
outdata = block_get_cached(blk, block);
if (outdata)
@@ -169,7 +169,7 @@ static void *block_get(struct block_device *blk, int block)
ret = block_cache(blk, block);
if (ret)
- return NULL;
+ return ERR_PTR(ret);
outdata = block_get_cached(blk, block);
if (!outdata)
@@ -191,8 +191,8 @@ static ssize_t block_read(struct cdev *cdev, void *buf, size_t count,
size_t now = BLOCKSIZE(blk) - (offset & mask);
void *iobuf = block_get(blk, block);
- if (!iobuf)
- return -EIO;
+ if (IS_ERR(iobuf))
+ return PTR_ERR(iobuf);
now = min(count, now);
@@ -207,8 +207,8 @@ static ssize_t block_read(struct cdev *cdev, void *buf, size_t count,
while (blocks) {
void *iobuf = block_get(blk, block);
- if (!iobuf)
- return -EIO;
+ if (IS_ERR(iobuf))
+ return PTR_ERR(iobuf);
memcpy(buf, iobuf, BLOCKSIZE(blk));
buf += BLOCKSIZE(blk);
@@ -220,8 +220,8 @@ static ssize_t block_read(struct cdev *cdev, void *buf, size_t count,
if (count) {
void *iobuf = block_get(blk, block);
- if (!iobuf)
- return -EIO;
+ if (IS_ERR(iobuf))
+ return PTR_ERR(iobuf);
memcpy(buf, iobuf, count);
}
@@ -244,8 +244,8 @@ static int block_put(struct block_device *blk, const void *buf, int block)
return -EINVAL;
data = block_get(blk, block);
- if (!data)
- BUG();
+ if (IS_ERR(data))
+ return PTR_ERR(data);
memcpy(data, buf, 1 << blk->blockbits);
@@ -270,8 +270,8 @@ static ssize_t block_write(struct cdev *cdev, const void *buf, size_t count,
now = min(count, now);
- if (!iobuf)
- return -EIO;
+ if (IS_ERR(iobuf))
+ return PTR_ERR(iobuf);
memcpy(iobuf + (offset & mask), buf, now);
ret = block_put(blk, iobuf, block);
@@ -299,8 +299,8 @@ static ssize_t block_write(struct cdev *cdev, const void *buf, size_t count,
if (count) {
void *iobuf = block_get(blk, block);
- if (!iobuf)
- return -EIO;
+ if (IS_ERR(iobuf))
+ return PTR_ERR(iobuf);
memcpy(iobuf, buf, count);
ret = block_put(blk, iobuf, block);
diff --git a/common/bootargs.c b/common/bootargs.c
new file mode 100644
index 0000000000..60e936da37
--- /dev/null
+++ b/common/bootargs.c
@@ -0,0 +1,83 @@
+/*
+ * bootargs.c - concatenate Linux bootargs
+ *
+ * Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <common.h>
+#include <boot.h>
+#include <malloc.h>
+#include <magicvar.h>
+#include <globalvar.h>
+#include <environment.h>
+
+static char *linux_bootargs;
+static int linux_bootargs_overwritten;
+
+/*
+ * This returns the Linux bootargs
+ *
+ * There are two ways to handle bootargs. The old legacy way is to use the
+ * 'bootargs' environment variable. The new and more flexible way is to use
+ * global variables beginning with "global.linux.bootargs." and
+ * "global.linux.mtdparts.". These variables will be concatenated together to
+ * the resulting bootargs. If there are no "global.linux.bootargs." variables
+ * we fall back to "bootargs"
+ */
+const char *linux_bootargs_get(void)
+{
+ char *bootargs, *mtdparts;
+
+ if (linux_bootargs_overwritten)
+ return linux_bootargs;
+
+ free(linux_bootargs);
+
+ bootargs = globalvar_get_match("linux.bootargs.", " ");
+ if (!strlen(bootargs))
+ return getenv("bootargs");
+
+ mtdparts = globalvar_get_match("linux.mtdparts.", ";");
+
+ if (strlen(mtdparts)) {
+ linux_bootargs = asprintf("%s mtdparts=%s", bootargs, mtdparts);
+ free(bootargs);
+ free(mtdparts);
+ } else {
+ free(mtdparts);
+ linux_bootargs = bootargs;
+ }
+
+ return linux_bootargs;
+}
+
+int linux_bootargs_overwrite(const char *bootargs)
+{
+ if (bootargs) {
+ free(linux_bootargs);
+ linux_bootargs = xstrdup(bootargs);
+ linux_bootargs_overwritten = 1;
+ } else {
+ linux_bootargs_overwritten = 0;
+ }
+
+ return 0;
+}
+
+BAREBOX_MAGICVAR_NAMED(global_linux_bootargs_, global.linux.bootargs.*, "Linux bootargs variables");
+BAREBOX_MAGICVAR_NAMED(global_linux_mtdparts_, global.linux.mtdparts.*, "Linux mtdparts variables");
diff --git a/common/env.c b/common/env.c
index e57a520a35..a01a27e24f 100644
--- a/common/env.c
+++ b/common/env.c
@@ -219,7 +219,7 @@ int setenv(const char *_name, const char *value)
else
ret = -ENODEV;
- errno = ret;
+ errno = -ret;
if (ret < 0)
perror("set parameter");
diff --git a/common/environment.c b/common/environment.c
index 0fdbd03e00..52ce0de1da 100644
--- a/common/environment.c
+++ b/common/environment.c
@@ -187,7 +187,7 @@ int envfs_load(char *filename, char *dir)
ret = read(envfd, &super, sizeof(struct envfs_super));
if ( ret < sizeof(struct envfs_super)) {
perror("read");
- ret = errno;
+ ret = -errno;
goto out;
}
@@ -210,7 +210,7 @@ int envfs_load(char *filename, char *dir)
ret = read(envfd, buf, size);
if (ret < size) {
perror("read");
- ret = errno;
+ ret = -errno;
goto out;
}
@@ -256,7 +256,7 @@ int envfs_load(char *filename, char *dir)
inode_size);
if (ret < inode_size) {
perror("write");
- ret = errno;
+ ret = -errno;
close(fd);
goto out;
}
diff --git a/common/filetype.c b/common/filetype.c
index 15a37325df..39c2098862 100644
--- a/common/filetype.c
+++ b/common/filetype.c
@@ -78,6 +78,8 @@ enum filetype file_detect_type(void *_buf)
return filetype_oftree;
if (strncmp(buf8, "ANDROID!", 8) == 0)
return filetype_aimage;
+ if (strncmp(buf8 + 0x10, "barebox", 7) == 0)
+ return filetype_mips_barebox;
return filetype_unknown;
}
diff --git a/common/globalvar.c b/common/globalvar.c
new file mode 100644
index 0000000000..71296ff5a3
--- /dev/null
+++ b/common/globalvar.c
@@ -0,0 +1,65 @@
+#include <common.h>
+#include <malloc.h>
+#include <globalvar.h>
+#include <init.h>
+
+static struct device_d global_device = {
+ .name = "global",
+ .id = DEVICE_ID_SINGLE,
+};
+
+int globalvar_add(const char *name,
+ int (*set)(struct device_d *dev, struct param_d *p, const char *val),
+ const char *(*get)(struct device_d *, struct param_d *p),
+ unsigned long flags)
+{
+ return dev_add_param(&global_device, name, set, get, flags);
+}
+
+/*
+ * globalvar_get_match
+ *
+ * get a concatenated string of all globalvars beginning with 'match'.
+ * This adds whitespaces between the different globalvars
+ */
+char *globalvar_get_match(const char *match, const char *seperator)
+{
+ char *val = NULL;
+ struct param_d *param;
+
+ list_for_each_entry(param, &global_device.parameters, list) {
+ if (!strncmp(match, param->name, strlen(match))) {
+ const char *p = dev_get_param(&global_device, param->name);
+ if (val) {
+ char *new = asprintf("%s%s%s", val, seperator, p);
+ free(val);
+ val = new;
+ } else {
+ val = xstrdup(p);
+ }
+ }
+ }
+
+ if (!val)
+ val = xstrdup("");
+
+ return val;
+}
+
+/*
+ * globalvar_add_simple
+ *
+ * add a new globalvar named 'name'
+ */
+int globalvar_add_simple(const char *name)
+{
+ return globalvar_add(name, NULL, NULL, 0);
+}
+
+static int globalvar_init(void)
+{
+ register_device(&global_device);
+
+ return 0;
+}
+postconsole_initcall(globalvar_init);
diff --git a/common/hush.c b/common/hush.c
index 3d51e4cc19..3ac1d10195 100644
--- a/common/hush.c
+++ b/common/hush.c
@@ -757,13 +757,14 @@ static int run_pipe_real(struct p_context *ctx, struct pipe *pi)
if (child->sp) {
char * str = NULL;
struct p_context ctx1;
+ int rcode;
str = make_string((child->argv + i));
- parse_string_outer(&ctx1, str, FLAG_EXIT_FROM_LOOP | FLAG_REPARSING);
+ rcode = parse_string_outer(&ctx1, str, FLAG_EXIT_FROM_LOOP | FLAG_REPARSING);
release_context(&ctx1);
free(str);
- return last_return_code;
+ return rcode;
}
do_glob_in_argv(&globbuf, child->argc - i, &child->argv[i]);
@@ -1603,7 +1604,7 @@ static int parse_stream_outer(struct p_context *ctx, struct in_str *inp, int fla
}
if (code < -1) { /* exit */
b_free(&temp);
- return -code - 2;
+ return code;
}
} else {
if (ctx->old_flag != 0) {
@@ -1612,7 +1613,6 @@ static int parse_stream_outer(struct p_context *ctx, struct in_str *inp, int fla
}
if (inp->__promptme == 0)
printf("<INTERRUPT>\n");
- inp->__promptme = 1;
temp.nonnull = 0;
temp.quote = 0;
free_pipe_list(ctx->list_head,0);
@@ -1643,11 +1643,12 @@ static int parse_string_outer(struct p_context *ctx, const char *s, int flag)
setup_string_in_str(&input, p);
rcode = parse_stream_outer(ctx, &input, flag);
free(p);
- return rcode;
} else {
setup_string_in_str(&input, s);
- return parse_stream_outer(ctx, &input, flag);
+ rcode = parse_stream_outer(ctx, &input, flag);
}
+
+ return rcode;
}
static char *insert_var_value(char *inp)
@@ -1794,6 +1795,8 @@ static int source_script(const char *path, int argc, char *argv[])
}
ret = parse_string_outer(&ctx, script, FLAG_PARSE_SEMICOLON);
+ if (ret < -1)
+ ret = -ret - 2;
release_context(&ctx);
free(script);
@@ -1807,9 +1810,14 @@ int run_shell(void)
struct in_str input;
struct p_context ctx;
- setup_file_in_str(&input);
- rcode = parse_stream_outer(&ctx, &input, FLAG_PARSE_SEMICOLON);
- release_context(&ctx);
+ do {
+ setup_file_in_str(&input);
+ rcode = parse_stream_outer(&ctx, &input, FLAG_PARSE_SEMICOLON);
+ if (rcode < -1)
+ rcode = -rcode - 2;
+ release_context(&ctx);
+ } while (!input.__promptme);
+
return rcode;
}
diff --git a/common/misc.c b/common/misc.c
index b31a45c1a4..01e1b19e0d 100644
--- a/common/misc.c
+++ b/common/misc.c
@@ -112,7 +112,7 @@ EXPORT_SYMBOL(strerror);
const char *errno_str(void)
{
- return strerror(-errno);
+ return strerror(errno);
}
EXPORT_SYMBOL(errno_str);
diff --git a/common/oftree.c b/common/oftree.c
index a657d31664..49758a9ddf 100644
--- a/common/oftree.c
+++ b/common/oftree.c
@@ -11,6 +11,7 @@
#include <errno.h>
#include <getopt.h>
#include <init.h>
+#include <boot.h>
#define MAX_LEVEL 32 /* how deeply nested we will go */
@@ -257,7 +258,7 @@ static int of_fixup_bootargs(struct fdt_header *fdt)
if (nodeoffset < 0)
return nodeoffset;
- str = getenv("bootargs");
+ str = linux_bootargs_get();
if (str) {
err = fdt_setprop(fdt, nodeoffset,
"bootargs", str, strlen(str)+1);
diff --git a/defaultenv-2/base/bin/boot b/defaultenv-2/base/bin/boot
new file mode 100644
index 0000000000..c5ad73dde8
--- /dev/null
+++ b/defaultenv-2/base/bin/boot
@@ -0,0 +1,18 @@
+#!/bin/sh
+
+if [ $# = 0 ]; then
+ scr="$global.boot.default"
+else
+ scr="$1"
+fi
+
+if [ -n "$scr" ]; then
+ if [ ! -f /env/boot/$scr ]; then
+ echo -e "/env/boot/$scr does not exist.\nValid choices:"
+ ls /env/boot
+ exit
+ fi
+ /env/boot/$scr
+fi
+
+bootm
diff --git a/defaultenv-2/base/bin/bootargs-ip b/defaultenv-2/base/bin/bootargs-ip
new file mode 100644
index 0000000000..15041c6359
--- /dev/null
+++ b/defaultenv-2/base/bin/bootargs-ip
@@ -0,0 +1,11 @@
+#!/bin/sh
+
+# pass either static ip or dhcp to kernel based on barebox settings
+
+. /env/network/eth0
+
+if [ $ip = dhcp ]; then
+ global.linux.bootargs.ip="ip=dhcp"
+else
+ global.linux.bootargs.ip="ip=$ipaddr:$serverip:$gateway:$netmask::eth0:"
+fi
diff --git a/defaultenv-2/base/bin/bootargs-ip-barebox b/defaultenv-2/base/bin/bootargs-ip-barebox
new file mode 100644
index 0000000000..986c142286
--- /dev/null
+++ b/defaultenv-2/base/bin/bootargs-ip-barebox
@@ -0,0 +1,7 @@
+#!/bin/sh
+
+# pass barebox ip settings for eth0 to Linux
+
+ifup eth0
+
+global.linux.bootargs.ip="ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask::eth0:"
diff --git a/defaultenv-2/base/bin/bootargs-ip-dhcp b/defaultenv-2/base/bin/bootargs-ip-dhcp
new file mode 100644
index 0000000000..c542b248f0
--- /dev/null
+++ b/defaultenv-2/base/bin/bootargs-ip-dhcp
@@ -0,0 +1,5 @@
+#!/bin/sh
+
+# Do dhcp in Linux
+
+global.linux.bootargs.ip="ip=dhcp"
diff --git a/defaultenv-2/base/bin/bootargs-ip-none b/defaultenv-2/base/bin/bootargs-ip-none
new file mode 100644
index 0000000000..c010154650
--- /dev/null
+++ b/defaultenv-2/base/bin/bootargs-ip-none
@@ -0,0 +1,5 @@
+#!/bin/sh
+
+# disable ip setup in Linux
+
+global.linux.bootargs.ip="ip=none"
diff --git a/defaultenv-2/base/bin/bootargs-root-initrd b/defaultenv-2/base/bin/bootargs-root-initrd
new file mode 100644
index 0000000000..4c596252ee
--- /dev/null
+++ b/defaultenv-2/base/bin/bootargs-root-initrd
@@ -0,0 +1,11 @@
+#!/bin/sh
+
+rdinit="/sbin/init"
+
+while getopt "i:" opt; do
+ if [ ${opt} = i ]; then
+ rdinit=${OPTARG}
+ fi
+done
+
+global.linux.bootargs.root="root=/dev/ram0 rdinit=${rdinit}"
diff --git a/defaultenv-2/base/bin/bootargs-root-jffs2 b/defaultenv-2/base/bin/bootargs-root-jffs2
new file mode 100644
index 0000000000..db036dac6f
--- /dev/null
+++ b/defaultenv-2/base/bin/bootargs-root-jffs2
@@ -0,0 +1,9 @@
+#!/bin/sh
+
+while getopt "m:" opt; do
+ if [ ${opt} = m ]; then
+ mtd=${OPTARG}
+ fi
+done
+
+global.linux.bootargs.root="root=$mtd rootfstype=jffs2"
diff --git a/defaultenv-2/base/bin/bootargs-root-nfs b/defaultenv-2/base/bin/bootargs-root-nfs
new file mode 100644
index 0000000000..bf97555f44
--- /dev/null
+++ b/defaultenv-2/base/bin/bootargs-root-nfs
@@ -0,0 +1,15 @@
+#!/bin/sh
+
+while getopt "n:s:" opt; do
+ if [ ${opt} = n ]; then
+ nfsroot=${OPTARG}
+ elif [ ${opt} = s ]; then
+ serverip=${OPTARG}
+ fi
+done
+
+if [ -n ${serverip} ]; then
+ nfsroot="$serverip:$nfsroot"
+fi
+
+global.linux.bootargs.root="root=/dev/nfs nfsroot=$nfsroot,v3,tcp"
diff --git a/defaultenv-2/base/bin/bootargs-root-ubi b/defaultenv-2/base/bin/bootargs-root-ubi
new file mode 100644
index 0000000000..ef891041da
--- /dev/null
+++ b/defaultenv-2/base/bin/bootargs-root-ubi
@@ -0,0 +1,13 @@
+#!/bin/sh
+
+ubiroot=root
+
+while getopt "m:r:" opt; do
+ if [ ${opt} = r ]; then
+ ubiroot=${OPTARG}
+ elif [ ${opt} = m ]; then
+ mtd=${OPTARG}
+ fi
+done
+
+global.linux.bootargs.root="root=ubi0:$ubiroot ubi.mtd=$mtd rootfstype=ubifs"
diff --git a/defaultenv-2/base/bin/ifup b/defaultenv-2/base/bin/ifup
new file mode 100644
index 0000000000..9f6fd6bc49
--- /dev/null
+++ b/defaultenv-2/base/bin/ifup
@@ -0,0 +1,59 @@
+#!/bin/sh
+
+mkdir -p /tmp/network
+
+if [ $# != 1 ]; then
+ echo "usage: ifup <interface>"
+ exit 1
+fi
+
+interface="$1"
+
+if [ -f /tmp/network/$interface ]; then
+ exit 0
+fi
+
+cmd=/env/network/$interface
+
+if [ ! -e $cmd ]; then
+ echo "$f: no such file"
+ exit 1
+fi
+
+ip=
+ipaddr=
+netmask=
+gateway=
+serverip=
+ethaddr=
+
+. $cmd
+
+if [ $? != 0 ]; then
+ echo "failed to bring up $interface"
+ exit 1
+fi
+
+if [ -f /env/network/${interface}-discover ]; then
+ /env/network/${interface}-discover
+ if [ $? != 0 ]; then
+ echo "failed to discover eth0"
+ exit 1
+ fi
+fi
+
+if [ -n "$ethaddr" ]; then
+ ${interface}.ethaddr=$ethaddr
+fi
+
+if [ "$ip" = static ]; then
+ ${interface}.ipaddr=$ipaddr
+ ${interface}.netmask=$netmask
+ ${interface}.serverip=$serverip
+ ${interface}.gateway=$gateway
+elif [ "$ip" = dhcp ]; then
+ dhcp
+ exit $?
+fi
+
+echo -o /tmp/network/$interface up
diff --git a/defaultenv-2/base/bin/init b/defaultenv-2/base/bin/init
new file mode 100644
index 0000000000..e293c62b01
--- /dev/null
+++ b/defaultenv-2/base/bin/init
@@ -0,0 +1,46 @@
+#!/bin/sh
+
+export PATH=/env/bin
+
+global hostname=generic
+global user=none
+global tftp.server
+global tftp.path=/mnt/tftp-dhcp
+global autoboot_timeout=3
+global boot.default=net
+global allow_color=true
+global linux.bootargs.base
+global linux.bootargs.ip
+global linux.bootargs.root
+global editcmd=sedit
+
+/env/init/general
+
+if [ -e /env/menu ]; then
+ echo -e -n "\nHit m for menu or any other key to stop autoboot: "
+else
+ echo -e -n "\nHit any key to stop autoboot: "
+fi
+
+timeout -a $global.autoboot_timeout -v key
+autoboot="$?"
+
+if [ "${key}" = "q" ]; then
+ exit
+fi
+
+for i in /env/init/*; do
+ . $i
+done
+
+if [ "$autoboot" = 0 ]; then
+ boot
+fi
+
+if [ -e /env/menu ]; then
+ if [ "${key}" != "m" ]; then
+ echo -e "\ntype exit to get to the menu"
+ sh
+ fi
+ /env/menu/mainmenu
+fi
diff --git a/defaultenv-2/base/bin/mtdparts-add b/defaultenv-2/base/bin/mtdparts-add
new file mode 100644
index 0000000000..58c9fa7a21
--- /dev/null
+++ b/defaultenv-2/base/bin/mtdparts-add
@@ -0,0 +1,49 @@
+#!/bin/sh
+
+mkdir -p /tmp/mtdparts
+
+parts=
+device=
+kernelname=
+bbdev=
+
+while getopt "p:d:k:b" opt; do
+ if [ ${opt} = p ]; then
+ parts=${OPTARG}
+ elif [ ${opt} = d ]; then
+ device=${OPTARG}
+ elif [ ${opt} = k ]; then
+ kernelname=${OPTARG}
+ elif [ ${opt} = b ]; then
+ bbdev=true
+ fi
+done
+
+if [ -z "${device}" ]; then
+ echo "$0: no device given"
+ exit
+fi
+
+if [ -z "${parts}" ]; then
+ echo "$0: no partitions given"
+ exit
+fi
+
+if [ -e /tmp/mtdparts/${device} ]; then
+ if [ -n "/dev/${device}.*.bb" ]; then
+ nand -d /dev/${device}.*.bb
+ fi
+ delpart /dev/${device}.*
+fi
+
+addpart -n /dev/${device} "$parts" || exit
+mkdir -p /tmp/mtdparts/${device}
+
+if [ -n "${bbdev}" ]; then
+ nand -a /dev/${device}.*
+fi
+
+if [ -n ${kernelname} ]; then
+ global linux.mtdparts.${device}
+ global.linux.mtdparts.${device}="${kernelname}:${parts}"
+fi
diff --git a/defaultenv-2/base/boot/initrd b/defaultenv-2/base/boot/initrd
new file mode 100644
index 0000000000..1a1e629bcf
--- /dev/null
+++ b/defaultenv-2/base/boot/initrd
@@ -0,0 +1,16 @@
+#!/bin/sh
+
+if [ "$1" = menu ]; then
+ boot-menu-add-entry "$0" "kernel + initrd via tftp"
+ exit
+fi
+
+global.bootm.image="${global.tftp.path}/${global.user}-linux-${global.hostname}"
+global.bootm.initrd="${global.tftp.path}/initramfs"
+bootargs-root-initrd
+#global.bootm.oftree=<path to oftree>
+
+global.linux.bootargs.root="root=/dev/ram0"
+
+#bootargs-root-nfs -n "<path on server>" -s <serverip>
+#bootargs-root-ubi -r <volume> -m <mtdname>
diff --git a/defaultenv-2/base/boot/net b/defaultenv-2/base/boot/net
new file mode 100644
index 0000000000..2684c20a6c
--- /dev/null
+++ b/defaultenv-2/base/boot/net
@@ -0,0 +1,12 @@
+#!/bin/sh
+
+if [ "$1" = menu ]; then
+ boot-menu-add-entry "$0" "network (tftp, nfs)"
+ exit
+fi
+
+global.bootm.image="${global.tftp.path}/${global.user}-linux-${global.hostname}"
+#global.bootm.oftree="${global.tftp.path}/${global.user}-oftree-${global.hostname}"
+nfsroot="/home/${global.user}/nfsroot/${global.hostname}"
+bootargs-ip
+bootargs-root-nfs -n "$nfsroot"
diff --git a/defaultenv-2/base/data/ansi-colors b/defaultenv-2/base/data/ansi-colors
new file mode 100644
index 0000000000..c71b6b7998
--- /dev/null
+++ b/defaultenv-2/base/data/ansi-colors
@@ -0,0 +1,26 @@
+#!/bin/sh
+
+# Colors
+export RED='\e[1;31m'
+export BLUE='\e[1;34m'
+export GREEN='\e[1;32m'
+export CYAN='\e[1;36m'
+export YELLOW='\e[1;33m'
+export PINK='\e[1;35m'
+export WHITE='\e[1;37m'
+
+export DARK_RED='\e[2;31m'
+export DARK_BLUE='\e[2;34m'
+export DARK_GREEN='\e[2;32m'
+export DARK_CYAN='\e[2;36m'
+export DARK_YELLOW='\e[2;33m'
+export DARK_PINK='\e[2;35m'
+export DARK_WHITE='\e[2;37m'
+
+export RED_INV='\e[1;41m'
+export BLUE_INV='\e[1;44m'
+export GREEN_INV='\e[1;42m'
+export CYAN_INV='\e[1;46m'
+export ORANGE_INV='\e[1;43m'
+export PINK_INV='\e[1;45m'
+export NC='\e[0m' # No Color
diff --git a/defaultenv-2/base/data/boot-template b/defaultenv-2/base/data/boot-template
new file mode 100644
index 0000000000..1cacf18bf7
--- /dev/null
+++ b/defaultenv-2/base/data/boot-template
@@ -0,0 +1,16 @@
+#!/bin/sh
+
+if [ "$1" = menu ]; then
+ boot-menu-add-entry "$0" "<menu text here>"
+ exit
+fi
+
+global.bootm.image=<path to image>
+#global.bootm.oftree=<path to oftree>
+#global.bootm.initrd=<path to initrd>
+
+#bootargs-ip
+
+#bootargs-root-nfs -n "<path on server>" -s <serverip>
+#bootargs-root-jffs2 -m <mtdname>
+#bootargs-root-ubi -r <volume> -m <mtdname>
diff --git a/defaultenv-2/base/init/automount b/defaultenv-2/base/init/automount
new file mode 100644
index 0000000000..63099f9c38
--- /dev/null
+++ b/defaultenv-2/base/init/automount
@@ -0,0 +1,27 @@
+#!/bin/sh
+
+if [ "$1" = menu ]; then
+ init-menu-add-entry "$0" "Automountpoints"
+ exit
+fi
+
+# automount server returned from dhcp server
+
+mkdir -p /mnt/tftp-dhcp
+automount /mnt/tftp-dhcp 'ifup eth0 && mount $eth0.serverip tftp /mnt/tftp-dhcp'
+
+# automount nfs server example
+
+#nfshost=somehost
+#mkdir -p /mnt/${nfshost}
+#automount /mnt/$nfshost "ifup eth0 && mount ${nfshost}:/tftpboot nfs /mnt/${nfshost}"
+
+# static tftp server example
+
+#mkdir -p /mnt/tftp
+#automount -d /mnt/tftp 'ifup eth0 && mount $serverip tftp /mnt/tftp'
+
+# FAT on usb disk example
+
+#mkdir -p /mnt/fat
+#automount -d /mnt/fat 'usb && [ -e /dev/disk0.0 ] && mount /dev/disk0.0 fat /mnt/fat'
diff --git a/defaultenv-2/base/init/bootargs-base b/defaultenv-2/base/init/bootargs-base
new file mode 100644
index 0000000000..8e588ad43d
--- /dev/null
+++ b/defaultenv-2/base/init/bootargs-base
@@ -0,0 +1,8 @@
+#!/bin/sh
+
+if [ "$1" = menu ]; then
+ init-menu-add-entry "$0" "Base bootargs"
+ exit
+fi
+
+global.linux.bootargs.base="console=ttyS0,115200"
diff --git a/defaultenv-2/base/init/general b/defaultenv-2/base/init/general
new file mode 100644
index 0000000000..ad6c8600a0
--- /dev/null
+++ b/defaultenv-2/base/init/general
@@ -0,0 +1,18 @@
+#!/bin/sh
+
+if [ "$1" = menu ]; then
+ init-menu-add-entry "$0" "general config settings"
+ exit
+fi
+
+# user (used for network filenames)
+global.user=sha
+
+# timeout in seconds before the default boot entry is started
+global.autoboot_timeout=3
+
+# default boot entry (one of /env/boot/*)
+global.boot.default=net
+
+# default tftp path
+global.tftp.path=/mnt/tftp-dhcp
diff --git a/defaultenv-2/base/init/hostname b/defaultenv-2/base/init/hostname
new file mode 100644
index 0000000000..57a2c94798
--- /dev/null
+++ b/defaultenv-2/base/init/hostname
@@ -0,0 +1,8 @@
+#!/bin/sh
+
+if [ "$1" = menu ]; then
+ init-menu-add-entry "$0" "hostname"
+ exit
+fi
+
+global.hostname=generic
diff --git a/defaultenv-2/base/init/prompt b/defaultenv-2/base/init/prompt
new file mode 100644
index 0000000000..11dce9fe0e
--- /dev/null
+++ b/defaultenv-2/base/init/prompt
@@ -0,0 +1,7 @@
+#!/bin/sh
+
+if [ ${global.allow_color} = "true" ]; then
+ export PS1="\e[1;32mbarebox@\e[1;36m\h:\w\e[0m "
+else
+ export PS1="barebox@\h:\w "
+fi
diff --git a/defaultenv-2/base/network/eth0 b/defaultenv-2/base/network/eth0
new file mode 100644
index 0000000000..048a288245
--- /dev/null
+++ b/defaultenv-2/base/network/eth0
@@ -0,0 +1,15 @@
+#!/bin/sh
+
+# ip setting (static/dhcp)
+ip=dhcp
+
+# static setup used if ip=static
+ipaddr=
+netmask=
+gateway=
+serverip=
+
+# MAC address if needed
+#ethaddr=xx:xx:xx:xx:xx:xx
+
+# put code to discover eth0 (i.e. 'usb') to /env/network/eth0-discover
diff --git a/defaultenv-2/menu/menu/boot-entries-collect b/defaultenv-2/menu/menu/boot-entries-collect
new file mode 100644
index 0000000000..c066c930ab
--- /dev/null
+++ b/defaultenv-2/menu/menu/boot-entries-collect
@@ -0,0 +1,13 @@
+#!/bin/sh
+
+cd /env/boot
+
+./$global.boot.default menu
+
+for i in *; do
+ if [ "$i" != "$global.boot.default" ]; then
+ ./$i menu
+ fi
+done
+
+cd /
diff --git a/defaultenv-2/menu/menu/boot-entries-edit b/defaultenv-2/menu/menu/boot-entries-edit
new file mode 100644
index 0000000000..c4e1c3d5fd
--- /dev/null
+++ b/defaultenv-2/menu/menu/boot-entries-edit
@@ -0,0 +1,20 @@
+#!/bin/sh
+
+export menu_exit=false
+
+while true; do
+ menu -a -m boot_entries_edit -d "\e[1;36mEdit boot entries\e[0m"
+
+ boot-entries-collect
+
+ menu -e -a -m boot_entries_edit -c "boot-menu-new-boot-entry" -d "Add a new entry"
+ menu -e -a -m boot_entries_edit -c "boot-entries-remove" -d "Remove an entry"
+ menu -e -a -m boot_entries_edit -c "menu_exit=true" -d "back"
+
+ menu -s -m boot_entries_edit
+ menu -r -m boot_entries_edit
+
+ if [ $menu_exit = true ]; then
+ exit
+ fi
+done
diff --git a/defaultenv-2/menu/menu/boot-entries-remove b/defaultenv-2/menu/menu/boot-entries-remove
new file mode 100644
index 0000000000..566be9dd6e
--- /dev/null
+++ b/defaultenv-2/menu/menu/boot-entries-remove
@@ -0,0 +1,18 @@
+#!/bin/sh
+
+export menu_exit=false
+
+while true; do
+ menu -a -m boot_entries_remove -d "\e[1;36mRemove Boot entry\e[0m"
+
+ boot-entries-collect
+
+ menu -e -a -m boot_entries_remove -c "menu_exit=true" -d "back"
+
+ menu -s -m boot_entries_remove
+ menu -r -m boot_entries_remove
+
+ if [ $menu_exit = true ]; then
+ exit
+ fi
+done
diff --git a/defaultenv-2/menu/menu/boot-menu-add-entry b/defaultenv-2/menu/menu/boot-menu-add-entry
new file mode 100644
index 0000000000..7e1d9c6d58
--- /dev/null
+++ b/defaultenv-2/menu/menu/boot-menu-add-entry
@@ -0,0 +1,5 @@
+#!/bin/sh
+
+menu -e -a -m boot -c "boot $1" -d "Boot: ${GREEN}$2${NC}"
+menu -e -a -m boot_entries_edit -c "$global.editcmd /env/boot/$1" -d "${GREEN}$2${NC}"
+menu -e -a -m boot_entries_remove -c "rm /env/boot/$1" -d "${GREEN}$2${NC}"
diff --git a/defaultenv-2/menu/menu/boot-menu-new-boot-entry b/defaultenv-2/menu/menu/boot-menu-new-boot-entry
new file mode 100644
index 0000000000..c5e982cdb2
--- /dev/null
+++ b/defaultenv-2/menu/menu/boot-menu-new-boot-entry
@@ -0,0 +1,21 @@
+#!/bin/sh
+
+name=
+
+readline "Name of the new entry: " name
+
+if [ -z "$name" ]; then
+ exit 1
+fi
+
+if [ -e "/env/boot/$name" ]; then
+ echo "entry $name already exists"
+ readline "<enter>" unused
+ exit 1
+fi
+
+cp /env/data/boot-template /env/boot/$name
+
+edit /env/boot/$name
+
+boot-menu-show rebuild
diff --git a/defaultenv-2/menu/menu/init-entries-collect b/defaultenv-2/menu/menu/init-entries-collect
new file mode 100644
index 0000000000..dbb775779a
--- /dev/null
+++ b/defaultenv-2/menu/menu/init-entries-collect
@@ -0,0 +1,9 @@
+#!/bin/sh
+
+cd /env/init
+
+for i in *; do
+ ./$i menu
+done
+
+cd /
diff --git a/defaultenv-2/menu/menu/init-entries-edit b/defaultenv-2/menu/menu/init-entries-edit
new file mode 100644
index 0000000000..fc02b327d9
--- /dev/null
+++ b/defaultenv-2/menu/menu/init-entries-edit
@@ -0,0 +1,20 @@
+#!/bin/sh
+
+export menu_exit=false
+
+while true; do
+ menu -a -m init_entries_edit -d "\e[1;36mEdit init entries\e[0m"
+
+ menu -e -a -m init_entries_edit -R -c "true" -d ">> Reset board to let changes here take effect <<"
+
+ init-entries-collect
+
+ menu -e -a -m init_entries_edit -c "menu_exit=true" -d "back"
+
+ menu -s -m init_entries_edit
+ menu -r -m init_entries_edit
+
+ if [ $menu_exit = true ]; then
+ exit
+ fi
+done
diff --git a/defaultenv-2/menu/menu/init-menu-add-entry b/defaultenv-2/menu/menu/init-menu-add-entry
new file mode 100644
index 0000000000..7cb5686402
--- /dev/null
+++ b/defaultenv-2/menu/menu/init-menu-add-entry
@@ -0,0 +1,3 @@
+#!/bin/sh
+
+menu -e -a -m init_entries_edit -c "$global.editcmd /env/init/$1" -d "\e[1;32m$2\e[0m"
diff --git a/defaultenv-2/menu/menu/mainmenu b/defaultenv-2/menu/menu/mainmenu
new file mode 100644
index 0000000000..d7b0033220
--- /dev/null
+++ b/defaultenv-2/menu/menu/mainmenu
@@ -0,0 +1,28 @@
+#!/bin/sh
+
+savepath=$PATH
+export menupath=$PATH:/env/menu
+
+if [ ${global.allow_color} = "true" ]; then
+ . /env/data/ansi-colors
+fi
+
+while true; do
+ export PATH=${menupath}
+
+ echo $PATH
+
+ menu -a -m boot -d "${CYAN}Welcome to Barebox${NC}"
+
+ boot-entries-collect
+
+ menu -e -a -R -m boot -c "$global.editcmd /env/network/eth0" -d "Network settings"
+ menu -e -a -m boot -c "boot-entries-edit" -d "Edit boot entries"
+ menu -e -a -m boot -c "init-entries-edit" -d "Edit init entries"
+ menu -e -a -R -m boot -c "saveenv || echo \"failed to save environment\" && sleep 2" -d "Save settings"
+ menu -e -a -m boot -c 'PATH=$savepath; echo "enter exit to return to menu"; sh' -d "${DARK_YELLOW}Shell${NC}"
+ menu -e -a -m boot -c reset -d "${RED}Reset${NC}"
+
+ menu -s -m boot
+ menu -r -m boot
+done
diff --git a/defaultenv/config b/defaultenv/config
index 3e4c2eef6c..7b61d29730 100644
--- a/defaultenv/config
+++ b/defaultenv/config
@@ -1,7 +1,9 @@
#!/bin/sh
hostname=FIXME
-#user=
+if [ -z "$user" ]; then
+# user=
+fi
# Enter MAC address here if not retrieved automatically
#eth0.ethaddr=de:ad:be:ef:00:00
diff --git a/drivers/base/resource.c b/drivers/base/resource.c
index b31c7d7e1a..347b2f01f0 100644
--- a/drivers/base/resource.c
+++ b/drivers/base/resource.c
@@ -113,8 +113,10 @@ struct device_d *add_usb_ehci_device(int id, resource_size_t hccr,
res = xzalloc(sizeof(struct resource) * 2);
res[0].start = hccr;
+ res[0].size = 0x40;
res[0].flags = IORESOURCE_MEM;
res[1].start = hcor;
+ res[1].size = 0xc0;
res[1].flags = IORESOURCE_MEM;
return add_generic_device_res("ehci", id, res, 2, pdata);
diff --git a/drivers/mtd/nand/nand_imx.c b/drivers/mtd/nand/nand_imx.c
index 85cfbeda95..e75ffbc819 100644
--- a/drivers/mtd/nand/nand_imx.c
+++ b/drivers/mtd/nand/nand_imx.c
@@ -1135,7 +1135,7 @@ static int __init imxnd_probe(struct device_d *dev)
this->ecc.layout = oob_smallpage;
- /* NAND bus width determines access funtions used by upper layer */
+ /* NAND bus width determines access functions used by upper layer */
if (pdata->width == 2) {
this->options |= NAND_BUSWIDTH_16;
this->ecc.layout = &nandv1_hw_eccoob_smallpage;
diff --git a/drivers/mtd/nand/nand_s3c24xx.c b/drivers/mtd/nand/nand_s3c24xx.c
index dbf2e1420e..c6297011a3 100644
--- a/drivers/mtd/nand/nand_s3c24xx.c
+++ b/drivers/mtd/nand/nand_s3c24xx.c
@@ -36,7 +36,7 @@
#include <io.h>
#include <asm-generic/errno.h>
-#ifdef CONFIG_S3C24XX_NAND_BOOT
+#ifdef CONFIG_S3C_NAND_BOOT
# define __nand_boot_init __bare_init
# ifndef BOARD_DEFAULT_NAND_TIMING
# define BOARD_DEFAULT_NAND_TIMING 0x0737
@@ -49,7 +49,7 @@
* Define this symbol for testing purpose. It will add a command to read an
* image from the NAND like it the boot strap code will do.
*/
-#define CONFIG_NAND_S3C24XX_BOOT_DEBUG
+#define CONFIG_NAND_S3C_BOOT_DEBUG
/* NAND controller's register */
@@ -497,7 +497,7 @@ static struct driver_d s3c24x0_nand_driver = {
.probe = s3c24x0_nand_probe,
};
-#ifdef CONFIG_S3C24XX_NAND_BOOT
+#ifdef CONFIG_S3C_NAND_BOOT
static void __nand_boot_init wait_for_completion(void __iomem *host)
{
@@ -603,7 +603,7 @@ void __nand_boot_init s3c24x0_nand_load_image(void *dest, int size, int page)
disable_nand_controller(host);
}
-#ifdef CONFIG_NAND_S3C24XX_BOOT_DEBUG
+#ifdef CONFIG_NAND_S3C_BOOT_DEBUG
#include <command.h>
static int do_nand_boot_test(int argc, char *argv[])
@@ -636,7 +636,7 @@ BAREBOX_CMD_START(nand_boot_test)
BAREBOX_CMD_END
#endif
-#endif /* CONFIG_S3C24XX_NAND_BOOT */
+#endif /* CONFIG_S3C_NAND_BOOT */
/*
* Main initialization routine
diff --git a/drivers/nor/cfi_flash.h b/drivers/nor/cfi_flash.h
index df482b6c56..fec08940ab 100644
--- a/drivers/nor/cfi_flash.h
+++ b/drivers/nor/cfi_flash.h
@@ -30,7 +30,17 @@
#include <linux/mtd/mtd.h>
typedef unsigned long flash_sect_t;
+
+#if defined(CONFIG_DRIVER_CFI_BANK_WIDTH_8)
typedef u64 cfiword_t;
+#elif defined(CONFIG_DRIVER_CFI_BANK_WIDTH_4)
+typedef u32 cfiword_t;
+#elif defined(CONFIG_DRIVER_CFI_BANK_WIDTH_2)
+typedef u16 cfiword_t;
+#else
+typedef u8 cfiword_t;
+#endif
+
struct cfi_cmd_set;
/*-----------------------------------------------------------------------
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 186b59638f..a9383da9d7 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -80,7 +80,7 @@ config DRIVER_SERIAL_PL010
config DRIVER_SERIAL_S3C
bool "Samsung S3C serial driver"
- depends on ARCH_S3C24xx
+ depends on ARCH_SAMSUNG
default y
help
Say Y here if you want to use the CONS on a Samsung S3C CPU
diff --git a/drivers/serial/serial_s3c.c b/drivers/serial/serial_s3c.c
index 2bdc1df696..7a9b355704 100644
--- a/drivers/serial/serial_s3c.c
+++ b/drivers/serial/serial_s3c.c
@@ -40,6 +40,17 @@
#define UTXH 0x20 /* transmitt */
#define URXH 0x24 /* receive */
#define UBRDIV 0x28 /* baudrate generator */
+#ifdef S3C_UART_HAS_UBRDIVSLOT
+# define UBRDIVSLOT 0x2c /* baudrate slot generator */
+#endif
+#ifdef S3C_UART_HAS_UINTM
+# define UINTM 0x38 /* interrupt mask register */
+#endif
+
+#ifndef S3C_UART_CLKSEL
+/* Use pclk */
+# define S3C_UART_CLKSEL 0
+#endif
struct s3c_uart {
void __iomem *regs;
@@ -51,26 +62,32 @@ struct s3c_uart {
static unsigned s3c_get_arch_uart_input_clock(void __iomem *base)
{
unsigned reg = readw(base + UCON);
-
- switch (reg & 0xc00) {
- case 0x000:
- case 0x800:
- return s3c_get_pclk();
- case 0x400:
- break; /* TODO UEXTCLK */
- case 0xc00:
- break; /* TODO FCLK/n */
- }
-
- return 0; /* not nice, but we can't emit an error message! */
+ reg = (reg >> 10) & 0x3;
+ return s3c_get_uart_clk(reg);
}
+#ifdef S3C_UART_HAS_UBRDIVSLOT
+/*
+ * This table takes the fractional value of the baud divisor and gives
+ * the recommended setting for the UDIVSLOT register. Refer the datasheet
+ * for further details
+ */
+static const uint16_t udivslot_table[] __maybe_unused = {
+ 0x0000, 0x0080, 0x0808, 0x0888, 0x2222, 0x4924, 0x4A52, 0x54AA,
+ 0x5555, 0xD555, 0xD5D5, 0xDDD5, 0xDDDD, 0xDFDD, 0xDFDF, 0xFFDF,
+};
+#endif
+
static int s3c_serial_setbaudrate(struct console_device *cdev, int baudrate)
{
struct s3c_uart *priv = to_s3c_uart(cdev);
void __iomem *base = priv->regs;
unsigned val;
+#ifdef S3C_UART_HAS_UBRDIVSLOT
+ val = s3c_get_arch_uart_input_clock(base) / baudrate;
+ writew(udivslot_table[val & 15], base + UBRDIVSLOT);
+#endif
val = s3c_get_arch_uart_input_clock(base) / (16 * baudrate) - 1;
writew(val, base + UBRDIV);
@@ -88,11 +105,15 @@ static int s3c_serial_init_port(struct console_device *cdev)
/* Normal,No parity,1 stop,8 bit */
writeb(0x03, base + ULCON);
- /*
- * tx=level,rx=edge,disable timeout int.,enable rx error int.,
- * normal,interrupt or polling
- */
- writew(0x0245, base + UCON);
+
+ /* tx=level,rx=edge,disable timeout int.,enable rx error int.,
+ * normal, interrupt or polling, no pre-divider */
+ writew(0x0245 | ((S3C_UART_CLKSEL) << 10), base + UCON);
+
+#ifdef S3C_UART_HAS_UINTM
+ /* 'interrupt or polling mode' for both directions */
+ writeb(0xf, base + UINTM);
+#endif
#ifdef CONFIG_DRIVER_SERIAL_S3C_AUTOSYNC
writeb(0x10, base + UMCON); /* enable auto flow control */
diff --git a/drivers/spi/imx_spi.c b/drivers/spi/imx_spi.c
index 3b33b669fb..42358f2e6a 100644
--- a/drivers/spi/imx_spi.c
+++ b/drivers/spi/imx_spi.c
@@ -145,6 +145,10 @@ struct spi_imx_devtype_data {
static int imx_spi_setup(struct spi_device *spi)
{
+ struct imx_spi *imx = container_of(spi->master, struct imx_spi, master);
+
+ imx->chipselect(spi, 0);
+
debug("%s mode 0x%08x bits_per_word: %d speed: %d\n",
__FUNCTION__, spi->mode, spi->bits_per_word,
spi->max_speed_hz);
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 7a8aed42e2..a7fe10cba0 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -78,6 +78,8 @@ struct spi_device *spi_new_device(struct spi_master *master,
proxy->bits_per_word = chip->bits_per_word ? chip->bits_per_word : 8;
proxy->dev.platform_data = chip->platform_data;
strcpy(proxy->dev.name, chip->name);
+ /* allocate a free id for this chip */
+ proxy->dev.id = DEVICE_ID_DYNAMIC;
proxy->dev.type_data = proxy;
dev_add_child(master->dev, &proxy->dev);
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index ae2b41ed53..a2473a9141 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -858,7 +858,7 @@ static int ehci_probe(struct device_d *dev)
uint32_t reg;
struct ehci_platform_data *pdata = dev->platform_data;
- ehci = xmalloc(sizeof(struct ehci_priv));
+ ehci = xzalloc(sizeof(struct ehci_priv));
host = &ehci->host;
dev->priv = ehci;
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index f103101464..05e4094386 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -859,6 +859,8 @@ static void td_fill(struct ohci *ohci, unsigned int info,
td->hwNextTD = virt_to_phys((void *)m32_swap((unsigned long)td_pt));
+ dma_flush_range((unsigned long)data, (unsigned long)(data + len));
+
/* append to queue */
td->ed->hwTailP = td->hwNextTD;
}
@@ -1555,6 +1557,8 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
dev->status = stat;
dev->act_len = urb->actual_length;
+ dma_inv_range((unsigned long)buffer, (unsigned long)(buffer + transfer_len));
+
pkt_print(urb, dev, pipe, buffer, transfer_len,
setup, "RET(ctlr)", usb_pipein(pipe));
diff --git a/drivers/usb/storage/usb.c b/drivers/usb/storage/usb.c
index fa3691af15..2adc2ef508 100644
--- a/drivers/usb/storage/usb.c
+++ b/drivers/usb/storage/usb.c
@@ -613,7 +613,7 @@ static struct usb_device_id usb_storage_usb_ids[] = {
***********************************************************************/
static struct usb_driver usb_storage_driver = {
- .driver.name = "usb-storage",
+ .name = "usb-storage",
.id_table = usb_storage_usb_ids,
.probe = usb_stor_probe,
.disconnect = usb_stor_disconnect,
diff --git a/fs/Kconfig b/fs/Kconfig
index ee82039f04..34fcdf319c 100644
--- a/fs/Kconfig
+++ b/fs/Kconfig
@@ -24,6 +24,10 @@ config FS_TFTP
prompt "tftp support"
depends on NET
+config FS_NFS
+ bool
+ prompt "nfs support"
+
source fs/fat/Kconfig
config PARTITION_NEED_MTD
diff --git a/fs/Makefile b/fs/Makefile
index d2040939b5..1b52beefbf 100644
--- a/fs/Makefile
+++ b/fs/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_FS_DEVFS) += devfs.o
obj-$(CONFIG_FS_FAT) += fat/
obj-y += fs.o
obj-$(CONFIG_FS_TFTP) += tftp.o
+obj-$(CONFIG_FS_NFS) += nfs.o
diff --git a/fs/fs.c b/fs/fs.c
index 04dace49d2..9cda1d9968 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -211,8 +211,8 @@ static void put_file(FILE *f)
static int check_fd(int fd)
{
if (fd < 0 || fd >= MAX_FILES || !files[fd].in_use) {
- errno = -EBADF;
- return errno;
+ errno = EBADF;
+ return -errno;
}
return 0;
@@ -361,7 +361,7 @@ static int dir_is_empty(const char *pathname)
dir = opendir(pathname);
if (!dir) {
- errno = -ENOENT;
+ errno = ENOENT;
return -ENOENT;
}
@@ -389,47 +389,42 @@ static int path_check_prereq(const char *path, unsigned int flags)
{
struct stat s;
unsigned int m;
-
- errno = 0;
+ int ret = 0;
if (stat(path, &s)) {
- if (flags & S_UB_DOES_NOT_EXIST) {
- errno = 0;
+ if (flags & S_UB_DOES_NOT_EXIST)
goto out;
- }
- errno = -ENOENT;
+ ret = -ENOENT;
goto out;
}
if (flags & S_UB_DOES_NOT_EXIST) {
- errno = -EEXIST;
+ ret = -EEXIST;
goto out;
}
- if (flags == S_UB_EXISTS) {
- errno = 0;
+ if (flags == S_UB_EXISTS)
goto out;
- }
m = s.st_mode;
if (S_ISDIR(m)) {
if (flags & S_IFREG) {
- errno = -EISDIR;
+ ret = -EISDIR;
goto out;
}
if ((flags & S_UB_IS_EMPTY) && !dir_is_empty(path)) {
- errno = -ENOTEMPTY;
+ ret = -ENOTEMPTY;
goto out;
}
}
if ((flags & S_IFDIR) && S_ISREG(m)) {
- errno = -ENOTDIR;
+ ret = -ENOTDIR;
goto out;
}
out:
- return errno;
+ return ret;
}
const char *getcwd(void)
@@ -441,9 +436,11 @@ EXPORT_SYMBOL(getcwd);
int chdir(const char *pathname)
{
char *p = normalise_path(pathname);
- errno = 0;
+ int ret;
+
- if (path_check_prereq(p, S_IFDIR))
+ ret = path_check_prereq(p, S_IFDIR);
+ if (ret)
goto out;
strcpy(cwd, p);
@@ -451,7 +448,10 @@ int chdir(const char *pathname)
out:
free(p);
- return errno;
+ if (ret)
+ errno = -ret;
+
+ return ret;
}
EXPORT_SYMBOL(chdir);
@@ -461,24 +461,34 @@ int unlink(const char *pathname)
struct fs_driver_d *fsdrv;
char *p = normalise_path(pathname);
char *freep = p;
+ int ret;
- if (path_check_prereq(pathname, S_IFREG))
+ ret = path_check_prereq(pathname, S_IFREG);
+ if (ret) {
+ ret = -EINVAL;
goto out;
+ }
fsdev = get_fs_device_and_root_path(&p);
- if (!fsdev)
+ if (!fsdev) {
+ ret = -ENOENT;
goto out;
+ }
fsdrv = fsdev->driver;
if (!fsdrv->unlink) {
- errno = -ENOSYS;
+ ret = -ENOSYS;
goto out;
}
- errno = fsdrv->unlink(&fsdev->dev, p);
+ ret = fsdrv->unlink(&fsdev->dev, p);
+ if (ret)
+ errno = -ret;
out:
free(freep);
- return errno;
+ if (ret)
+ errno = -ret;
+ return ret;
}
EXPORT_SYMBOL(unlink);
@@ -491,28 +501,31 @@ int open(const char *pathname, int flags, ...)
struct stat s;
char *path = normalise_path(pathname);
char *freep = path;
+ int ret;
exist_err = stat(path, &s);
if (!exist_err && S_ISDIR(s.st_mode)) {
- errno = -EISDIR;
+ ret = -EISDIR;
goto out1;
}
if (exist_err && !(flags & O_CREAT)) {
- errno = exist_err;
+ ret = exist_err;
goto out1;
}
f = get_file();
if (!f) {
- errno = -EMFILE;
+ ret = -EMFILE;
goto out1;
}
fsdev = get_fs_device_and_root_path(&path);
- if (!fsdev)
+ if (!fsdev) {
+ ret = -ENOENT;
goto out;
+ }
fsdrv = fsdev->driver;
@@ -520,28 +533,28 @@ int open(const char *pathname, int flags, ...)
f->flags = flags;
if ((flags & O_ACCMODE) && !fsdrv->write) {
- errno = -EROFS;
+ ret = -EROFS;
goto out;
}
if (exist_err) {
if (NULL != fsdrv->create)
- errno = fsdrv->create(&fsdev->dev, path,
+ ret = fsdrv->create(&fsdev->dev, path,
S_IFREG | S_IRWXU | S_IRWXG | S_IRWXO);
else
- errno = -EROFS;
- if (errno)
+ ret = -EROFS;
+ if (ret)
goto out;
}
- errno = fsdrv->open(&fsdev->dev, f, path);
- if (errno)
+ ret = fsdrv->open(&fsdev->dev, f, path);
+ if (ret)
goto out;
if (flags & O_TRUNC) {
- errno = fsdrv->truncate(&fsdev->dev, f, 0);
+ ret = fsdrv->truncate(&fsdev->dev, f, 0);
f->size = 0;
- if (errno)
+ if (ret)
goto out;
}
@@ -555,7 +568,9 @@ out:
put_file(f);
out1:
free(freep);
- return errno;
+ if (ret)
+ errno = -ret;
+ return ret;
}
EXPORT_SYMBOL(open);
@@ -570,19 +585,22 @@ int ioctl(int fd, int request, void *buf)
struct device_d *dev;
struct fs_driver_d *fsdrv;
FILE *f = &files[fd];
+ int ret;
if (check_fd(fd))
- return errno;
+ return -errno;
dev = f->dev;
fsdrv = dev_to_fs_driver(dev);
if (fsdrv->ioctl)
- errno = fsdrv->ioctl(dev, f, request, buf);
+ ret = fsdrv->ioctl(dev, f, request, buf);
else
- errno = -ENOSYS;
- return errno;
+ ret = -ENOSYS;
+ if (ret)
+ errno = -ret;
+ return ret;
}
int read(int fd, void *buf, size_t count)
@@ -590,9 +608,10 @@ int read(int fd, void *buf, size_t count)
struct device_d *dev;
struct fs_driver_d *fsdrv;
FILE *f = &files[fd];
+ int ret;
if (check_fd(fd))
- return errno;
+ return -errno;
dev = f->dev;
@@ -604,11 +623,13 @@ int read(int fd, void *buf, size_t count)
if (!count)
return 0;
- errno = fsdrv->read(dev, f, buf, count);
+ ret = fsdrv->read(dev, f, buf, count);
- if (errno > 0)
- f->pos += errno;
- return errno;
+ if (ret > 0)
+ f->pos += ret;
+ if (ret < 0)
+ errno = -ret;
+ return ret;
}
EXPORT_SYMBOL(read);
@@ -617,30 +638,33 @@ ssize_t write(int fd, const void *buf, size_t count)
struct device_d *dev;
struct fs_driver_d *fsdrv;
FILE *f = &files[fd];
+ int ret;
if (check_fd(fd))
- return errno;
+ return -errno;
dev = f->dev;
fsdrv = dev_to_fs_driver(dev);
if (f->pos + count > f->size) {
- errno = fsdrv->truncate(dev, f, f->pos + count);
- if (errno) {
- if (errno != -ENOSPC)
- return errno;
+ ret = fsdrv->truncate(dev, f, f->pos + count);
+ if (ret) {
+ if (ret != -ENOSPC)
+ goto out;
count = f->size - f->pos;
if (!count)
- return errno;
+ goto out;
} else {
f->size = f->pos + count;
}
}
- errno = fsdrv->write(dev, f, buf, count);
-
- if (errno > 0)
- f->pos += errno;
- return errno;
+ ret = fsdrv->write(dev, f, buf, count);
+ if (ret > 0)
+ f->pos += ret;
+out:
+ if (ret < 0)
+ errno = -ret;
+ return ret;
}
EXPORT_SYMBOL(write);
@@ -649,19 +673,23 @@ int flush(int fd)
struct device_d *dev;
struct fs_driver_d *fsdrv;
FILE *f = &files[fd];
+ int ret;
if (check_fd(fd))
- return errno;
+ return -errno;
dev = f->dev;
fsdrv = dev_to_fs_driver(dev);
if (fsdrv->flush)
- errno = fsdrv->flush(dev, f);
+ ret = fsdrv->flush(dev, f);
else
- errno = 0;
+ ret = 0;
+
+ if (ret)
+ errno = -ret;
- return errno;
+ return ret;
}
off_t lseek(int fildes, off_t offset, int whence)
@@ -670,20 +698,21 @@ off_t lseek(int fildes, off_t offset, int whence)
struct fs_driver_d *fsdrv;
FILE *f = &files[fildes];
off_t pos;
+ int ret;
if (check_fd(fildes))
return -1;
- errno = 0;
-
dev = f->dev;
fsdrv = dev_to_fs_driver(dev);
if (!fsdrv->lseek) {
- errno = -ENOSYS;
- return -1;
+ ret = -ENOSYS;
+ goto out;
}
- switch(whence) {
+ ret = -EINVAL;
+
+ switch (whence) {
case SEEK_SET:
if (offset > f->size)
goto out;
@@ -706,7 +735,9 @@ off_t lseek(int fildes, off_t offset, int whence)
return fsdrv->lseek(dev, f, pos);
out:
- errno = -EINVAL;
+ if (ret)
+ errno = -ret;
+
return -1;
}
EXPORT_SYMBOL(lseek);
@@ -716,9 +747,10 @@ int erase(int fd, size_t count, unsigned long offset)
struct device_d *dev;
struct fs_driver_d *fsdrv;
FILE *f = &files[fd];
+ int ret;
if (check_fd(fd))
- return errno;
+ return -errno;
dev = f->dev;
@@ -728,11 +760,14 @@ int erase(int fd, size_t count, unsigned long offset)
count = f->size - f->pos;
if (fsdrv->erase)
- errno = fsdrv->erase(dev, f, count, offset);
+ ret = fsdrv->erase(dev, f, count, offset);
else
- errno = -ENOSYS;
+ ret = -ENOSYS;
+
+ if (ret)
+ errno = -ret;
- return errno;
+ return ret;
}
EXPORT_SYMBOL(erase);
@@ -741,9 +776,10 @@ int protect(int fd, size_t count, unsigned long offset, int prot)
struct device_d *dev;
struct fs_driver_d *fsdrv;
FILE *f = &files[fd];
+ int ret;
if (check_fd(fd))
- return errno;
+ return -errno;
dev = f->dev;
@@ -753,11 +789,14 @@ int protect(int fd, size_t count, unsigned long offset, int prot)
count = f->size - f->pos;
if (fsdrv->protect)
- errno = fsdrv->protect(dev, f, count, offset, prot);
+ ret = fsdrv->protect(dev, f, count, offset, prot);
else
- errno = -ENOSYS;
+ ret = -ENOSYS;
+
+ if (ret)
+ errno = -ret;
- return errno;
+ return ret;
}
EXPORT_SYMBOL(protect);
@@ -781,21 +820,25 @@ void *memmap(int fd, int flags)
struct device_d *dev;
struct fs_driver_d *fsdrv;
FILE *f = &files[fd];
- void *ret = (void *)-1;
+ void *retp = (void *)-1;
+ int ret;
if (check_fd(fd))
- return ret;
+ return retp;
dev = f->dev;
fsdrv = dev_to_fs_driver(dev);
if (fsdrv->memmap)
- errno = fsdrv->memmap(dev, f, &ret, flags);
+ ret = fsdrv->memmap(dev, f, &retp, flags);
else
- errno = -EINVAL;
+ ret = -EINVAL;
- return ret;
+ if (ret)
+ errno = -ret;
+
+ return retp;
}
EXPORT_SYMBOL(memmap);
@@ -804,17 +847,22 @@ int close(int fd)
struct device_d *dev;
struct fs_driver_d *fsdrv;
FILE *f = &files[fd];
+ int ret;
if (check_fd(fd))
- return errno;
+ return -errno;
dev = f->dev;
fsdrv = dev_to_fs_driver(dev);
- errno = fsdrv->close(dev, f);
+ ret = fsdrv->close(dev, f);
put_file(f);
- return errno;
+
+ if (ret)
+ errno = -ret;
+
+ return ret;
}
EXPORT_SYMBOL(close);
@@ -893,23 +941,22 @@ int mount(const char *device, const char *fsname, const char *_path)
int ret;
char *path = normalise_path(_path);
- errno = 0;
-
debug("mount: %s on %s type %s\n", device, path, fsname);
if (fs_dev_root) {
fsdev = get_fsdevice_by_path(path);
if (fsdev != fs_dev_root) {
printf("sorry, no nested mounts\n");
- errno = -EBUSY;
+ ret = -EBUSY;
goto err_free_path;
}
- if (path_check_prereq(path, S_IFDIR))
+ ret = path_check_prereq(path, S_IFDIR);
+ if (ret)
goto err_free_path;
} else {
/* no mtab, so we only allow to mount on '/' */
if (*path != '/' || *(path + 1)) {
- errno = -ENOTDIR;
+ ret = -ENOTDIR;
goto err_free_path;
}
}
@@ -924,22 +971,19 @@ int mount(const char *device, const char *fsname, const char *_path)
if (!strncmp(device, "/dev/", 5))
fsdev->cdev = cdev_by_name(device + 5);
- if ((ret = register_device(&fsdev->dev))) {
- errno = ret;
+ ret = register_device(&fsdev->dev);
+ if (ret)
goto err_register;
- }
if (!fsdev->dev.driver) {
/*
* Driver didn't accept the device or no driver for this
* device. Bail out
*/
- errno = -EINVAL;
+ ret = -EINVAL;
goto err_no_driver;
}
- errno = 0;
-
return 0;
err_no_driver:
@@ -949,7 +993,9 @@ err_register:
err_free_path:
free(path);
- return errno;
+ errno = -ret;
+
+ return ret;
}
EXPORT_SYMBOL(mount);
@@ -968,13 +1014,13 @@ int umount(const char *pathname)
free(p);
if (f == fs_dev_root && !list_is_singular(&fs_device_list)) {
- errno = -EBUSY;
- return errno;
+ errno = EBUSY;
+ return -EBUSY;
}
if (!fsdev) {
- errno = -EFAULT;
- return errno;
+ errno = EFAULT;
+ return -EFAULT;
}
unregister_device(&fsdev->dev);
@@ -990,13 +1036,17 @@ DIR *opendir(const char *pathname)
struct fs_driver_d *fsdrv;
char *p = normalise_path(pathname);
char *freep = p;
+ int ret;
- if (path_check_prereq(pathname, S_IFDIR))
+ ret = path_check_prereq(pathname, S_IFDIR);
+ if (ret)
goto out;
fsdev = get_fs_device_and_root_path(&p);
- if (!fsdev)
+ if (!fsdev) {
+ ret = -ENOENT;
goto out;
+ }
fsdrv = fsdev->driver;
debug("opendir: fsdrv: %p\n",fsdrv);
@@ -1005,31 +1055,54 @@ DIR *opendir(const char *pathname)
if (dir) {
dir->dev = &fsdev->dev;
dir->fsdrv = fsdrv;
+ } else {
+ /*
+ * FIXME: The fs drivers should return ERR_PTR here so that
+ * we are able to forward the error
+ */
+ ret = -EINVAL;
}
out:
free(freep);
+
+ if (ret)
+ errno = -ret;
+
return dir;
}
EXPORT_SYMBOL(opendir);
struct dirent *readdir(DIR *dir)
{
+ struct dirent *ent;
+
if (!dir)
return NULL;
- return dir->fsdrv->readdir(dir->dev, dir);
+ ent = dir->fsdrv->readdir(dir->dev, dir);
+
+ if (!ent)
+ errno = EBADF;
+
+ return ent;
}
EXPORT_SYMBOL(readdir);
int closedir(DIR *dir)
{
+ int ret;
+
if (!dir) {
- errno = -EBADF;
- return -1;
+ errno = EBADF;
+ return -EBADF;
}
- return dir->fsdrv->closedir(dir->dev, dir);
+ ret = dir->fsdrv->closedir(dir->dev, dir);
+ if (ret)
+ errno = -ret;
+
+ return ret;
}
EXPORT_SYMBOL(closedir);
@@ -1040,6 +1113,7 @@ int stat(const char *filename, struct stat *s)
struct fs_device_d *fsdev;
char *f = normalise_path(filename);
char *freep = f;
+ int ret;
automount_mount(f, 1);
@@ -1047,7 +1121,7 @@ int stat(const char *filename, struct stat *s)
fsdev = get_fsdevice_by_path(f);
if (!fsdev) {
- errno = -ENOENT;
+ ret = -ENOENT;
goto out;
}
@@ -1062,10 +1136,14 @@ int stat(const char *filename, struct stat *s)
if (*f == 0)
f = "/";
- errno = fsdrv->stat(dev, f, s);
+ ret = fsdrv->stat(dev, f, s);
out:
free(freep);
- return errno;
+
+ if (ret)
+ errno = -ret;
+
+ return ret;
}
EXPORT_SYMBOL(stat);
@@ -1075,24 +1153,30 @@ int mkdir (const char *pathname, mode_t mode)
struct fs_device_d *fsdev;
char *p = normalise_path(pathname);
char *freep = p;
+ int ret;
- if (path_check_prereq(pathname, S_UB_DOES_NOT_EXIST))
+ ret = path_check_prereq(pathname, S_UB_DOES_NOT_EXIST);
+ if (ret)
goto out;
fsdev = get_fs_device_and_root_path(&p);
- if (!fsdev)
- goto out;
- fsdrv = fsdev->driver;
-
- if (fsdrv->mkdir) {
- errno = fsdrv->mkdir(&fsdev->dev, p);
+ if (!fsdev) {
+ ret = -ENOENT;
goto out;
}
+ fsdrv = fsdev->driver;
- errno = -EROFS;
+ if (fsdrv->mkdir)
+ ret = fsdrv->mkdir(&fsdev->dev, p);
+ else
+ ret = -EROFS;
out:
free(freep);
- return errno;
+
+ if (ret)
+ errno = -ret;
+
+ return ret;
}
EXPORT_SYMBOL(mkdir);
@@ -1102,24 +1186,30 @@ int rmdir (const char *pathname)
struct fs_device_d *fsdev;
char *p = normalise_path(pathname);
char *freep = p;
+ int ret;
- if (path_check_prereq(pathname, S_IFDIR | S_UB_IS_EMPTY))
+ ret = path_check_prereq(pathname, S_IFDIR | S_UB_IS_EMPTY);
+ if (ret)
goto out;
fsdev = get_fs_device_and_root_path(&p);
- if (!fsdev)
- goto out;
- fsdrv = fsdev->driver;
-
- if (fsdrv->rmdir) {
- errno = fsdrv->rmdir(&fsdev->dev, p);
+ if (!fsdev) {
+ ret = -ENOENT;
goto out;
}
+ fsdrv = fsdev->driver;
- errno = -EROFS;
+ if (fsdrv->rmdir)
+ ret = fsdrv->rmdir(&fsdev->dev, p);
+ else
+ ret = -EROFS;
out:
free(freep);
- return errno;
+
+ if (ret)
+ errno = -ret;
+
+ return ret;
}
EXPORT_SYMBOL(rmdir);
@@ -1184,4 +1274,3 @@ ssize_t mem_write(struct cdev *cdev, const void *buf, size_t count, ulong offset
return size;
}
EXPORT_SYMBOL(mem_write);
-
diff --git a/fs/nfs.c b/fs/nfs.c
new file mode 100644
index 0000000000..75a8f25066
--- /dev/null
+++ b/fs/nfs.c
@@ -0,0 +1,1054 @@
+/*
+ * nfs.c - barebox NFS driver
+ *
+ * Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ * Copyright (c) Masami Komiya <mkomiya@sonare.it> 2004
+ *
+ * Based on U-Boot NFS code which is based on NetBSD code
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <net.h>
+#include <driver.h>
+#include <fs.h>
+#include <errno.h>
+#include <libgen.h>
+#include <fcntl.h>
+#include <fs.h>
+#include <init.h>
+#include <linux/stat.h>
+#include <linux/err.h>
+#include <kfifo.h>
+#include <sizes.h>
+
+#define SUNRPC_PORT 111
+
+#define PROG_PORTMAP 100000
+#define PROG_NFS 100003
+#define PROG_MOUNT 100005
+
+#define MSG_CALL 0
+#define MSG_REPLY 1
+
+#define PORTMAP_GETPORT 3
+
+#define MOUNT_ADDENTRY 1
+#define MOUNT_UMOUNT 3
+
+#define NFS_GETATTR 1
+#define NFS_LOOKUP 4
+#define NFS_READLINK 5
+#define NFS_READ 6
+#define NFS_READDIR 16
+
+#define NFS_FHSIZE 32
+
+enum nfs_stat {
+ NFS_OK = 0,
+ NFSERR_PERM = 1,
+ NFSERR_NOENT = 2,
+ NFSERR_IO = 5,
+ NFSERR_NXIO = 6,
+ NFSERR_ACCES = 13,
+ NFSERR_EXIST = 17,
+ NFSERR_NODEV = 19,
+ NFSERR_NOTDIR = 20,
+ NFSERR_ISDIR = 21,
+ NFSERR_FBIG = 27,
+ NFSERR_NOSPC = 28,
+ NFSERR_ROFS = 30,
+ NFSERR_NAMETOOLONG=63,
+ NFSERR_NOTEMPTY = 66,
+ NFSERR_DQUOT = 69,
+ NFSERR_STALE = 70,
+ NFSERR_WFLUSH = 99,
+};
+
+static void *nfs_packet;
+static int nfs_len;
+
+struct rpc_call {
+ uint32_t id;
+ uint32_t type;
+ uint32_t rpcvers;
+ uint32_t prog;
+ uint32_t vers;
+ uint32_t proc;
+ uint32_t data[0];
+};
+
+struct rpc_reply {
+ uint32_t id;
+ uint32_t type;
+ uint32_t rstatus;
+ uint32_t verifier;
+ uint32_t v2;
+ uint32_t astatus;
+ uint32_t data[0];
+};
+
+#define NFS_TIMEOUT (2 * SECOND)
+#define NFS_MAX_RESEND 5
+
+struct nfs_priv {
+ struct net_connection *con;
+ IPaddr_t server;
+ char *path;
+ int mount_port;
+ int nfs_port;
+ unsigned long rpc_id;
+ char rootfh[NFS_FHSIZE];
+};
+
+struct file_priv {
+ struct kfifo *fifo;
+ void *buf;
+ char filefh[NFS_FHSIZE];
+ struct nfs_priv *npriv;
+};
+
+static uint64_t nfs_timer_start;
+
+static int nfs_state;
+#define STATE_DONE 1
+#define STATE_START 2
+
+enum ftype {
+ NFNON = 0,
+ NFREG = 1,
+ NFDIR = 2,
+ NFBLK = 3,
+ NFCHR = 4,
+ NFLNK = 5
+};
+
+struct fattr {
+ uint32_t type;
+ uint32_t mode;
+ uint32_t nlink;
+ uint32_t uid;
+ uint32_t gid;
+ uint32_t size;
+ uint32_t blocksize;
+ uint32_t rdev;
+ uint32_t blocks;
+};
+
+struct readdirargs {
+ char filefh[NFS_FHSIZE];
+ uint32_t cookie;
+ uint32_t count;
+};
+
+struct xdr_stream {
+ __be32 *p;
+ void *buf;
+ __be32 *end;
+};
+
+#define xdr_zero 0
+#define XDR_QUADLEN(l) (((l) + 3) >> 2)
+
+static void xdr_init(struct xdr_stream *stream, void *buf, int len)
+{
+ stream->p = stream->buf = buf;
+ stream->end = stream->buf + len;
+}
+
+static __be32 *__xdr_inline_decode(struct xdr_stream *xdr, size_t nbytes)
+{
+ __be32 *p = xdr->p;
+ __be32 *q = p + XDR_QUADLEN(nbytes);
+
+ if (q > xdr->end || q < p)
+ return NULL;
+ xdr->p = q;
+ return p;
+}
+
+static __be32 *xdr_inline_decode(struct xdr_stream *xdr, size_t nbytes)
+{
+ __be32 *p;
+
+ if (nbytes == 0)
+ return xdr->p;
+ if (xdr->p == xdr->end)
+ return NULL;
+ p = __xdr_inline_decode(xdr, nbytes);
+
+ return p;
+}
+
+static int decode_filename(struct xdr_stream *xdr,
+ char *name, u32 *length)
+{
+ __be32 *p;
+ u32 count;
+
+ p = xdr_inline_decode(xdr, 4);
+ if (!p)
+ goto out_overflow;
+ count = be32_to_cpup(p);
+ if (count > 255)
+ goto out_nametoolong;
+ p = xdr_inline_decode(xdr, count);
+ if (!p)
+ goto out_overflow;
+ memcpy(name, p, count);
+ name[count] = 0;
+ *length = count;
+ return 0;
+out_nametoolong:
+ printk("NFS: returned filename too long: %u\n", count);
+ return -ENAMETOOLONG;
+out_overflow:
+ printf("%s overflow\n",__func__);
+ return -EIO;
+}
+
+/*
+ * rpc_add_credentials - Add RPC authentication/verifier entries
+ */
+static uint32_t *rpc_add_credentials(uint32_t *p)
+{
+ int hl;
+ int hostnamelen = 0;
+
+ /*
+ * Here's the executive summary on authentication requirements of the
+ * various NFS server implementations: Linux accepts both AUTH_NONE
+ * and AUTH_UNIX authentication (also accepts an empty hostname field
+ * in the AUTH_UNIX scheme). *BSD refuses AUTH_NONE, but accepts
+ * AUTH_UNIX (also accepts an empty hostname field in the AUTH_UNIX
+ * scheme). To be safe, use AUTH_UNIX and pass the hostname if we have
+ * it (if the BOOTP/DHCP reply didn't give one, just use an empty
+ * hostname).
+ */
+
+ hl = (hostnamelen + 3) & ~3;
+
+ /* Provide an AUTH_UNIX credential. */
+ *p++ = htonl(1); /* AUTH_UNIX */
+ *p++ = htonl(hl + 20); /* auth length */
+ *p++ = htonl(0); /* stamp */
+ *p++ = htonl(hostnamelen); /* hostname string */
+
+ if (hostnamelen & 3)
+ *(p + hostnamelen / 4) = 0; /* add zero padding */
+
+ /* memcpy(p, hostname, hostnamelen); */ /* empty hostname */
+
+ p += hl / 4;
+ *p++ = 0; /* uid */
+ *p++ = 0; /* gid */
+ *p++ = 0; /* auxiliary gid list */
+
+ /* Provide an AUTH_NONE verifier. */
+ *p++ = 0; /* AUTH_NONE */
+ *p++ = 0; /* auth length */
+
+ return p;
+}
+
+static int rpc_check_reply(unsigned char *pkt, int rpc_prog, unsigned long rpc_id, int *nfserr)
+{
+ uint32_t *data;
+ struct rpc_reply rpc;
+
+ *nfserr = 0;
+
+ if (!pkt)
+ return -EAGAIN;
+
+ memcpy(&rpc, pkt, sizeof(rpc));
+
+ if (ntohl(rpc.id) != rpc_id)
+ return -EINVAL;
+
+ if (rpc.rstatus ||
+ rpc.verifier ||
+ rpc.astatus ) {
+ return -EINVAL;
+ }
+
+ if (rpc_prog == PROG_PORTMAP)
+ return 0;
+
+ data = (uint32_t *)(pkt + sizeof(struct rpc_reply));
+ *nfserr = ntohl(net_read_uint32(data));
+ *nfserr = -*nfserr;
+
+ debug("%s: state: %d, err %d\n", __func__, nfs_state, *nfserr);
+
+ return 0;
+}
+
+/*
+ * rpc_req - synchronous RPC request
+ */
+static int rpc_req(struct nfs_priv *npriv, int rpc_prog, int rpc_proc,
+ uint32_t *data, int datalen)
+{
+ struct rpc_call pkt;
+ unsigned long id;
+ int dport;
+ int ret;
+ unsigned char *payload = net_udp_get_payload(npriv->con);
+ int nfserr;
+ int tries = 0;
+
+ npriv->rpc_id++;
+ id = npriv->rpc_id;
+
+ pkt.id = htonl(id);
+ pkt.type = htonl(MSG_CALL);
+ pkt.rpcvers = htonl(2); /* use RPC version 2 */
+ pkt.prog = htonl(rpc_prog);
+ pkt.vers = htonl(2); /* portmapper is version 2 */
+ pkt.proc = htonl(rpc_proc);
+
+ memcpy(payload, &pkt, sizeof(pkt));
+ memcpy(payload + sizeof(pkt), data, datalen * sizeof(uint32_t));
+
+ if (rpc_prog == PROG_PORTMAP)
+ dport = SUNRPC_PORT;
+ else if (rpc_prog == PROG_MOUNT)
+ dport = npriv->mount_port;
+ else
+ dport = npriv->nfs_port;
+
+ npriv->con->udp->uh_dport = htons(dport);
+
+again:
+ ret = net_udp_send(npriv->con, sizeof(pkt) + datalen * sizeof(uint32_t));
+
+ nfs_timer_start = get_time_ns();
+
+ nfs_state = STATE_START;
+ nfs_packet = NULL;
+
+ while (nfs_state != STATE_DONE) {
+ if (ctrlc()) {
+ ret = -EINTR;
+ break;
+ }
+ net_poll();
+
+ if (is_timeout(nfs_timer_start, NFS_TIMEOUT)) {
+ tries++;
+ if (tries == NFS_MAX_RESEND)
+ return -ETIMEDOUT;
+ goto again;
+ }
+
+ ret = rpc_check_reply(nfs_packet, rpc_prog,
+ npriv->rpc_id, &nfserr);
+ if (!ret) {
+ ret = nfserr;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+/*
+ * rpc_lookup_req - Lookup RPC Port numbers
+ */
+static int rpc_lookup_req(struct nfs_priv *npriv, int prog, int ver)
+{
+ uint32_t data[16];
+ int ret;
+ uint32_t port;
+
+ data[0] = 0; data[1] = 0; /* auth credential */
+ data[2] = 0; data[3] = 0; /* auth verifier */
+ data[4] = htonl(prog);
+ data[5] = htonl(ver);
+ data[6] = htonl(17); /* IP_UDP */
+ data[7] = 0;
+
+ ret = rpc_req(npriv, PROG_PORTMAP, PORTMAP_GETPORT, data, 8);
+ if (ret)
+ return ret;
+
+ port = net_read_uint32((uint32_t *)(nfs_packet + sizeof(struct rpc_reply)));
+
+ switch (prog) {
+ case PROG_MOUNT:
+ npriv->mount_port = ntohl(port);
+ debug("mount port: %d\n", npriv->mount_port);
+ break;
+ case PROG_NFS:
+ npriv->nfs_port = ntohl(port);
+ debug("nfs port: %d\n", npriv->nfs_port);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/*
+ * nfs_mount_req - Mount an NFS Filesystem
+ */
+static int nfs_mount_req(struct nfs_priv *npriv)
+{
+ uint32_t data[1024];
+ uint32_t *p;
+ int len;
+ int pathlen;
+ int ret;
+
+ pathlen = strlen(npriv->path);
+
+ debug("%s: %s\n", __func__, npriv->path);
+
+ p = &(data[0]);
+ p = rpc_add_credentials(p);
+
+ *p++ = htonl(pathlen);
+ if (pathlen & 3)
+ *(p + pathlen / 4) = 0;
+
+ memcpy (p, npriv->path, pathlen);
+ p += (pathlen + 3) / 4;
+
+ len = p - &(data[0]);
+
+ ret = rpc_req(npriv, PROG_MOUNT, MOUNT_ADDENTRY, data, len);
+ if (ret)
+ return ret;
+
+ memcpy(npriv->rootfh, nfs_packet + sizeof(struct rpc_reply) + 4, NFS_FHSIZE);
+
+ return 0;
+}
+
+/*
+ * nfs_umountall_req - Unmount all our NFS Filesystems on the Server
+ */
+static void nfs_umount_req(struct nfs_priv *npriv)
+{
+ uint32_t data[1024];
+ uint32_t *p;
+ int len;
+ int pathlen;
+
+ pathlen = strlen(npriv->path);
+
+ p = &(data[0]);
+ p = rpc_add_credentials(p);
+
+ *p++ = htonl(pathlen);
+ if (pathlen & 3)
+ *(p + pathlen / 4) = 0;
+
+ memcpy (p, npriv->path, pathlen);
+ p += (pathlen + 3) / 4;
+
+ len = p - &(data[0]);
+
+ rpc_req(npriv, PROG_MOUNT, MOUNT_UMOUNT, data, len);
+}
+
+/*
+ * nfs_lookup_req - Lookup Pathname
+ */
+static int nfs_lookup_req(struct file_priv *priv, const char *filename,
+ int fnamelen)
+{
+ uint32_t data[1024];
+ uint32_t *p;
+ int len;
+ int ret;
+
+ p = &(data[0]);
+ p = rpc_add_credentials(p);
+
+ memcpy(p, priv->filefh, NFS_FHSIZE);
+
+ p += (NFS_FHSIZE / 4);
+ *p++ = htonl(fnamelen);
+
+ if (fnamelen & 3)
+ *(p + fnamelen / 4) = 0;
+
+ memcpy(p, filename, fnamelen);
+ p += (fnamelen + 3) / 4;
+
+ len = p - &(data[0]);
+
+ ret = rpc_req(priv->npriv, PROG_NFS, NFS_LOOKUP, data, len);
+ if (ret)
+ return ret;
+
+ memcpy(priv->filefh, nfs_packet + sizeof(struct rpc_reply) + 4, NFS_FHSIZE);
+
+ return 0;
+}
+
+static int nfs_attr_req(struct file_priv *priv, struct stat *s)
+{
+ uint32_t data[1024];
+ uint32_t *p;
+ int len;
+ int ret;
+ struct fattr *fattr;
+ uint32_t type;
+
+ p = &(data[0]);
+ p = rpc_add_credentials(p);
+
+ memcpy(p, priv->filefh, NFS_FHSIZE);
+ p += (NFS_FHSIZE / 4);
+ *p++ = 0;
+
+ len = p - &(data[0]);
+
+ ret = rpc_req(priv->npriv, PROG_NFS, NFS_GETATTR, data, len);
+ if (ret)
+ return ret;
+
+ fattr = nfs_packet + sizeof(struct rpc_reply) + 4;
+
+ type = ntohl(net_read_uint32(&fattr->type));
+
+ s->st_size = ntohl(net_read_uint32(&fattr->size));
+ s->st_mode = ntohl(net_read_uint32(&fattr->mode));
+
+ return 0;
+}
+
+static void *nfs_readdirattr_req(struct file_priv *priv, int *plen, uint32_t cookie)
+{
+ uint32_t data[1024];
+ uint32_t *p;
+ int len;
+ int ret;
+ void *buf;
+
+ p = &(data[0]);
+ p = rpc_add_credentials(p);
+
+ memcpy(p, priv->filefh, NFS_FHSIZE);
+ p += (NFS_FHSIZE / 4);
+ *p++ = htonl(cookie); /* cookie */
+ *p++ = htonl(1024); /* count */
+ *p++ = 0;
+
+ len = p - &(data[0]);
+
+ ret = rpc_req(priv->npriv, PROG_NFS, NFS_READDIR, data, len);
+ if (ret)
+ return NULL;
+
+ *plen = nfs_len - sizeof(struct rpc_reply) + 4;
+
+ buf = xzalloc(*plen);
+
+ memcpy(buf, nfs_packet + sizeof(struct rpc_reply) + 4, *plen);
+
+ return buf;
+}
+
+/*
+ * nfs_read_req - Read File on NFS Server
+ */
+static int nfs_read_req(struct file_priv *priv, int offset, int readlen)
+{
+ uint32_t data[1024];
+ uint32_t *p;
+ uint32_t *filedata;
+ int len;
+ int ret;
+ int rlen;
+
+ p = &(data[0]);
+ p = rpc_add_credentials(p);
+
+ memcpy (p, priv->filefh, NFS_FHSIZE);
+ p += (NFS_FHSIZE / 4);
+ *p++ = htonl(offset);
+ *p++ = htonl(readlen);
+ *p++ = 0;
+
+ len = p - &(data[0]);
+
+ ret = rpc_req(priv->npriv, PROG_NFS, NFS_READ, data, len);
+ if (ret)
+ return ret;
+
+ filedata = (uint32_t *)(nfs_packet + sizeof(struct rpc_reply));
+
+ rlen = ntohl(net_read_uint32(filedata + 18));
+
+ kfifo_put(priv->fifo, (char *)(filedata + 19), rlen);
+
+ return 0;
+}
+
+#if 0
+static int nfs_readlink_reply(unsigned char *pkt, unsigned len)
+{
+ uint32_t *data;
+ char *path;
+ int rlen;
+// int ret;
+
+ data = (uint32_t *)(pkt + sizeof(struct rpc_reply));
+
+ data++;
+
+ rlen = ntohl(net_read_uint32(data)); /* new path length */
+
+ data++;
+ path = (char *)data;
+
+ if (*path != '/') {
+ strcat(nfs_path, "/");
+ strncat(nfs_path, path, rlen);
+ } else {
+ memcpy(nfs_path, path, rlen);
+ nfs_path[rlen] = 0;
+ }
+ return 0;
+}
+#endif
+
+static void nfs_handler(void *ctx, char *packet, unsigned len)
+{
+ char *pkt = net_eth_to_udp_payload(packet);
+
+ nfs_state = STATE_DONE;
+ nfs_packet = pkt;
+ nfs_len = len;
+}
+
+static int nfs_create(struct device_d *dev, const char *pathname, mode_t mode)
+{
+ return -ENOSYS;
+}
+
+static int nfs_unlink(struct device_d *dev, const char *pathname)
+{
+ return -ENOSYS;
+}
+
+static int nfs_mkdir(struct device_d *dev, const char *pathname)
+{
+ return -ENOSYS;
+}
+
+static int nfs_rmdir(struct device_d *dev, const char *pathname)
+{
+ return -ENOSYS;
+}
+
+static int nfs_truncate(struct device_d *dev, FILE *f, ulong size)
+{
+ return -ENOSYS;
+}
+
+static struct file_priv *nfs_do_open(struct device_d *dev, const char *filename)
+{
+ struct file_priv *priv;
+ struct nfs_priv *npriv = dev->priv;
+ int ret;
+ const char *fname, *tok;
+
+ priv = xzalloc(sizeof(*priv));
+
+ priv->npriv = npriv;
+
+ if (!*filename) {
+ memcpy(priv->filefh, npriv->rootfh, NFS_FHSIZE);
+ return priv;
+ }
+
+ filename++;
+
+ fname = filename;
+
+ memcpy(priv->filefh, npriv->rootfh, NFS_FHSIZE);
+
+ while (*fname) {
+ int flen;
+
+ tok = strchr(fname, '/');
+ if (tok)
+ flen = tok - fname;
+ else
+ flen = strlen(fname);
+
+ ret = nfs_lookup_req(priv, fname, flen);
+ if (ret)
+ goto out;
+
+ if (tok)
+ fname += flen + 1;
+ else
+ break;
+ }
+
+ return priv;
+
+out:
+ free(priv);
+
+ return ERR_PTR(ret);
+}
+
+static void nfs_do_close(struct file_priv *priv)
+{
+ if (priv->fifo)
+ kfifo_free(priv->fifo);
+
+ free(priv);
+}
+
+static struct file_priv *nfs_do_stat(struct device_d *dev, const char *filename, struct stat *s)
+{
+ struct file_priv *priv;
+ int ret;
+
+ priv = nfs_do_open(dev, filename);
+ if (IS_ERR(priv))
+ return priv;
+
+ ret = nfs_attr_req(priv, s);
+ if (ret) {
+ nfs_do_close(priv);
+ return ERR_PTR(ret);
+ }
+
+ return priv;
+}
+
+static int nfs_open(struct device_d *dev, FILE *file, const char *filename)
+{
+ struct file_priv *priv;
+ struct stat s;
+
+ priv = nfs_do_stat(dev, filename, &s);
+ if (IS_ERR(priv))
+ return PTR_ERR(priv);
+
+ file->inode = priv;
+ file->size = s.st_size;
+
+ priv->fifo = kfifo_alloc(1024);
+ if (!priv->fifo) {
+ free(priv);
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+static int nfs_close(struct device_d *dev, FILE *file)
+{
+ struct file_priv *priv = file->inode;
+
+ nfs_do_close(priv);
+
+ return 0;
+}
+
+static int nfs_write(struct device_d *_dev, FILE *file, const void *inbuf,
+ size_t insize)
+{
+ return -ENOSYS;
+}
+
+static int nfs_read(struct device_d *dev, FILE *file, void *buf, size_t insize)
+{
+ struct file_priv *priv = file->inode;
+ int now, outsize = 0, ret, pos = file->pos;
+
+ while (insize) {
+ now = kfifo_get(priv->fifo, buf, insize);
+ outsize += now;
+ buf += now;
+ insize -= now;
+
+ if (insize) {
+ now = 1024;
+
+ if (pos + now > file->size)
+ now = file->size - pos;
+
+ ret = nfs_read_req(priv, pos, now);
+ if (ret)
+ return ret;
+ pos += now;
+ }
+ }
+
+ return outsize;
+}
+
+static off_t nfs_lseek(struct device_d *dev, FILE *file, off_t pos)
+{
+ struct file_priv *priv = file->inode;
+
+ file->pos = pos;
+ kfifo_reset(priv->fifo);
+
+ return file->pos;
+}
+
+struct nfs_dir {
+ DIR dir;
+ struct xdr_stream stream;
+ struct dirent ent;
+ struct file_priv *priv;
+ uint32_t cookie;
+};
+
+static DIR *nfs_opendir(struct device_d *dev, const char *pathname)
+{
+ struct file_priv *priv;
+ struct stat s;
+ int ret;
+ void *buf;
+ struct nfs_dir *dir;
+ int len;
+
+ priv = nfs_do_open(dev, pathname);
+ if (IS_ERR(priv))
+ return NULL;
+
+ ret = nfs_attr_req(priv, &s);
+ if (ret)
+ return NULL;
+
+ if (!S_ISDIR(s.st_mode))
+ return NULL;
+
+ dir = xzalloc(sizeof(*dir));
+ dir->priv = priv;
+
+ buf = nfs_readdirattr_req(priv, &len, 0);
+ if (!buf)
+ return NULL;
+
+ xdr_init(&dir->stream, buf, len);
+
+ return &dir->dir;
+}
+
+static struct dirent *nfs_readdir(struct device_d *dev, DIR *dir)
+{
+ struct nfs_dir *ndir = (void *)dir;
+ __be32 *p;
+ int ret;
+ int len;
+ struct xdr_stream *xdr = &ndir->stream;
+
+again:
+ p = xdr_inline_decode(xdr, 4);
+ if (!p)
+ goto out_overflow;
+
+ if (*p++ == xdr_zero) {
+ p = xdr_inline_decode(xdr, 4);
+ if (!p)
+ goto out_overflow;
+ if (*p++ == xdr_zero) {
+ void *buf;
+ int len;
+
+ /*
+ * End of current entries, read next chunk.
+ */
+
+ free(ndir->stream.buf);
+
+ buf = nfs_readdirattr_req(ndir->priv, &len, ndir->cookie);
+ if (!buf)
+ return NULL;
+
+ xdr_init(&ndir->stream, buf, len);
+
+ goto again;
+ }
+ return NULL; /* -EINVAL */
+ }
+
+ p = xdr_inline_decode(xdr, 4);
+ if (!p)
+ goto out_overflow;
+
+ ret = decode_filename(xdr, ndir->ent.d_name, &len);
+ if (ret)
+ return NULL;
+
+ /*
+ * The type (size and byte order) of nfscookie isn't defined in
+ * RFC 1094. This implementation assumes that it's an XDR uint32.
+ */
+ p = xdr_inline_decode(xdr, 4);
+ if (!p)
+ goto out_overflow;
+
+ ndir->cookie = be32_to_cpup(p);
+
+ return &ndir->ent;
+
+out_overflow:
+
+ printf("nfs: overflow error\n");
+
+ return NULL;
+
+}
+
+static int nfs_closedir(struct device_d *dev, DIR *dir)
+{
+ struct nfs_dir *ndir = (void *)dir;
+
+ nfs_do_close(ndir->priv);
+ free(ndir->stream.buf);
+ free(ndir);
+
+ return 0;
+}
+
+static int nfs_stat(struct device_d *dev, const char *filename, struct stat *s)
+{
+ struct file_priv *priv;
+
+ priv = nfs_do_stat(dev, filename, s);
+ if (IS_ERR(priv)) {
+ return PTR_ERR(priv);
+ } else {
+ nfs_do_close(priv);
+ return 0;
+ }
+}
+
+static int nfs_probe(struct device_d *dev)
+{
+ struct fs_device_d *fsdev = dev_to_fs_device(dev);
+ struct nfs_priv *npriv = xzalloc(sizeof(struct nfs_priv));
+ char *tmp = xstrdup(fsdev->backingstore);
+ char *path;
+ int ret;
+
+ dev->priv = npriv;
+
+ debug("nfs: mount: %s\n", fsdev->backingstore);
+
+ path = strchr(tmp, ':');
+ if (!path) {
+ ret = -EINVAL;
+ goto err;
+ }
+
+ *path = 0;
+
+ npriv->path = xstrdup(path + 1);
+
+ npriv->server = resolv(tmp);
+
+ debug("nfs: server: %s path: %s\n", tmp, npriv->path);
+
+ npriv->con = net_udp_new(npriv->server, 0, nfs_handler, npriv);
+ if (IS_ERR(npriv->con)) {
+ ret = PTR_ERR(npriv->con);
+ goto err1;
+ }
+
+ /* Need a priviliged source port */
+ net_udp_bind(npriv->con, 1000);
+
+ ret = rpc_lookup_req(npriv, PROG_MOUNT, 1);
+ if (ret) {
+ printf("lookup mount port failed with %d\n", ret);
+ goto err2;
+ }
+
+ ret = rpc_lookup_req(npriv, PROG_NFS, 2);
+ if (ret) {
+ printf("lookup nfs port failed with %d\n", ret);
+ goto err2;
+ }
+
+ ret = nfs_mount_req(npriv);
+ if (ret) {
+ printf("mounting failed with %d\n", ret);
+ goto err2;
+ }
+
+ free(tmp);
+
+ return 0;
+
+err2:
+ net_unregister(npriv->con);
+err1:
+ free(npriv->path);
+err:
+ free(tmp);
+ free(npriv);
+
+ return ret;
+}
+
+static void nfs_remove(struct device_d *dev)
+{
+ struct nfs_priv *npriv = dev->priv;
+
+ nfs_umount_req(npriv);
+
+ net_unregister(npriv->con);
+ free(npriv->path);
+ free(npriv);
+}
+
+static struct fs_driver_d nfs_driver = {
+ .open = nfs_open,
+ .close = nfs_close,
+ .read = nfs_read,
+ .lseek = nfs_lseek,
+ .opendir = nfs_opendir,
+ .readdir = nfs_readdir,
+ .closedir = nfs_closedir,
+ .stat = nfs_stat,
+ .create = nfs_create,
+ .unlink = nfs_unlink,
+ .mkdir = nfs_mkdir,
+ .rmdir = nfs_rmdir,
+ .write = nfs_write,
+ .truncate = nfs_truncate,
+ .flags = 0,
+ .drv = {
+ .probe = nfs_probe,
+ .remove = nfs_remove,
+ .name = "nfs",
+ }
+};
+
+static int nfs_init(void)
+{
+ return register_fs_driver(&nfs_driver);
+}
+coredevice_initcall(nfs_init);
diff --git a/fs/ramfs.c b/fs/ramfs.c
index 83ab6dfc06..cec5e769b0 100644
--- a/fs/ramfs.c
+++ b/fs/ramfs.c
@@ -48,6 +48,10 @@ struct ramfs_inode {
ulong size;
struct ramfs_chunk *data;
+
+ /* Points to recently used chunk */
+ int recent_chunk;
+ struct ramfs_chunk *recent_chunkp;
};
struct ramfs_priv {
@@ -297,6 +301,35 @@ static int ramfs_close(struct device_d *dev, FILE *f)
return 0;
}
+static struct ramfs_chunk *ramfs_find_chunk(struct ramfs_inode *node, int chunk)
+{
+ struct ramfs_chunk *data;
+ int left = chunk;
+
+ if (chunk == 0)
+ return node->data;
+
+ if (node->recent_chunk == chunk)
+ return node->recent_chunkp;
+
+ if (node->recent_chunk < chunk && node->recent_chunk != 0) {
+ /* Start at last known chunk */
+ data = node->recent_chunkp;
+ left -= node->recent_chunk;
+ } else {
+ /* Start at first chunk */
+ data = node->data;
+ }
+
+ while (left--)
+ data = data->next;
+
+ node->recent_chunkp = data;
+ node->recent_chunk = chunk;
+
+ return data;
+}
+
static int ramfs_read(struct device_d *_dev, FILE *f, void *buf, size_t insize)
{
struct ramfs_inode *node = (struct ramfs_inode *)f->inode;
@@ -311,11 +344,7 @@ static int ramfs_read(struct device_d *_dev, FILE *f, void *buf, size_t insize)
debug("%s: reading from chunk %d\n", __FUNCTION__, chunk);
/* Position ourself in stream */
- data = node->data;
- while (chunk) {
- data = data->next;
- chunk--;
- }
+ data = ramfs_find_chunk(node, chunk);
ofs = f->pos % CHUNK_SIZE;
/* Read till end of current chunk */
@@ -364,11 +393,7 @@ static int ramfs_write(struct device_d *_dev, FILE *f, const void *buf, size_t i
debug("%s: writing to chunk %d\n", __FUNCTION__, chunk);
/* Position ourself in stream */
- data = node->data;
- while (chunk) {
- data = data->next;
- chunk--;
- }
+ data = ramfs_find_chunk(node, chunk);
ofs = f->pos % CHUNK_SIZE;
/* Write till end of current chunk */
@@ -429,6 +454,8 @@ static int ramfs_truncate(struct device_d *dev, FILE *f, ulong size)
ramfs_put_chunk(data);
data = tmp;
}
+ if (node->recent_chunk > newchunks)
+ node->recent_chunk = 0;
}
if (newchunks > oldchunks) {
diff --git a/include/boot.h b/include/boot.h
index a17bf25a4c..3ce0de125b 100644
--- a/include/boot.h
+++ b/include/boot.h
@@ -5,6 +5,7 @@
#include <filetype.h>
#include <of.h>
#include <linux/list.h>
+#include <environment.h>
struct image_data {
/* simplest case. barebox has already loaded the os here */
@@ -71,4 +72,19 @@ static inline int bootm_verbose(struct image_data *data)
}
#endif
+#ifdef CONFIG_FLEXIBLE_BOOTARGS
+const char *linux_bootargs_get(void);
+int linux_bootargs_overwrite(const char *bootargs);
+#else
+static inline const char *linux_bootargs_get(void)
+{
+ return getenv("bootargs");
+}
+
+static inline int linux_bootargs_overwrite(const char *bootargs)
+{
+ return setenv("bootargs", bootargs);
+}
+#endif
+
#endif /* __BOOT_H */
diff --git a/include/envfs.h b/include/envfs.h
index b5849d9b8d..67b890222c 100644
--- a/include/envfs.h
+++ b/include/envfs.h
@@ -1,7 +1,9 @@
#ifndef _ENVFS_H
#define _ENVFS_H
+#ifdef __BAREBOX__
#include <asm/byteorder.h>
+#endif
#define ENVFS_MAGIC 0x798fba79 /* some random number */
#define ENVFS_INODE_MAGIC 0x67a8c78d
diff --git a/include/filetype.h b/include/filetype.h
index 93387938be..f5de8ed2b5 100644
--- a/include/filetype.h
+++ b/include/filetype.h
@@ -17,6 +17,7 @@ enum filetype {
filetype_oftree,
filetype_aimage,
filetype_sh,
+ filetype_mips_barebox,
};
const char *file_type_to_string(enum filetype f);
diff --git a/include/globalvar.h b/include/globalvar.h
new file mode 100644
index 0000000000..7cc3976f6b
--- /dev/null
+++ b/include/globalvar.h
@@ -0,0 +1,12 @@
+#ifndef __GLOBALVAR_H
+#define __GLOBALVAR_H
+
+int globalvar_add_simple(const char *name);
+
+int globalvar_add(const char *name,
+ int (*set)(struct device_d *dev, struct param_d *p, const char *val),
+ const char *(*get)(struct device_d *, struct param_d *p),
+ unsigned long flags);
+char *globalvar_get_match(const char *match, const char *seperator);
+
+#endif /* __GLOBALVAR_H */
diff --git a/include/image.h b/include/image.h
index 35ff01b1c0..027b5f2520 100644
--- a/include/image.h
+++ b/include/image.h
@@ -31,8 +31,8 @@
#ifndef __IMAGE_H__
#define __IMAGE_H__
-#include <linux/types.h>
#ifdef __BAREBOX__
+#include <linux/types.h>
#include <asm/byteorder.h>
#include <stdio.h>
#include <string.h>
diff --git a/include/io.h b/include/io.h
index 39b5e614b7..8d885de68f 100644
--- a/include/io.h
+++ b/include/io.h
@@ -4,20 +4,11 @@
#include <asm/io.h>
/* cpu_read/cpu_write: cpu native io accessors */
-#if __BYTE_ORDER == __BIG_ENDIAN
-#define cpu_readb(a) readb(a)
-#define cpu_readw(a) in_be16(a)
-#define cpu_readl(a) in_be32(a)
-#define cpu_writeb(v, a) writeb((v), (a))
-#define cpu_writew(v, a) out_be16((a), (v))
-#define cpu_writel(v, a) out_be32((a), (v))
-#else
-#define cpu_readb(a) readb(a)
-#define cpu_readw(a) readw(a)
-#define cpu_readl(a) readl(a)
-#define cpu_writeb(v, a) writeb((v), (a))
-#define cpu_writew(v, a) writew((v), (a))
-#define cpu_writel(v, a) writel((v), (a))
-#endif
+#define cpu_readb(a) __raw_readb(a)
+#define cpu_readw(a) __raw_readw(a)
+#define cpu_readl(a) __raw_readl(a)
+#define cpu_writeb(v, a) __raw_writeb((v), (a))
+#define cpu_writew(v, a) __raw_writew((v), (a))
+#define cpu_writel(v, a) __raw_writel((v), (a))
#endif /* __IO_H */
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 8e208765f7..2a1c4ff67b 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -313,7 +313,7 @@ struct nand_buffers {
* @select_chip: [REPLACEABLE] select chip nr
* @block_bad: [REPLACEABLE] check, if the block is bad
* @block_markbad: [REPLACEABLE] mark the block bad
- * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling
+ * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
* ALE/CLE/nCE. Also used to write command and address
* @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
* If set to NULL no access to ready/busy is available and the ready/busy information
diff --git a/include/linux/types.h b/include/linux/types.h
index 16cc3ce128..76c6b670a2 100644
--- a/include/linux/types.h
+++ b/include/linux/types.h
@@ -144,8 +144,10 @@ typedef __u32 __bitwise __wsum;
#ifdef CONFIG_PHYS_ADDR_T_64BIT
typedef u64 phys_addr_t;
+typedef u64 phys_size_t;
#else
typedef u32 phys_addr_t;
+typedef u32 phys_size_t;
#endif
typedef phys_addr_t resource_size_t;
diff --git a/include/magicvar.h b/include/magicvar.h
index d27a2e32a3..bb5bd2591f 100644
--- a/include/magicvar.h
+++ b/include/magicvar.h
@@ -18,14 +18,18 @@ extern struct magicvar __barebox_magicvar_end;
#endif
#ifdef CONFIG_CMD_MAGICVAR
-#define BAREBOX_MAGICVAR(_name, _description) \
+#define BAREBOX_MAGICVAR_NAMED(_name, _varname, _description) \
extern const struct magicvar __barebox_magicvar_##_name; \
const struct magicvar __barebox_magicvar_##_name \
__attribute__ ((unused,section (".barebox_magicvar_" __stringify(_name)))) = { \
- .name = #_name, \
+ .name = #_varname, \
.description = MAGICVAR_DESCRIPTION(_description), \
};
+
+#define BAREBOX_MAGICVAR(_name, _description) \
+ BAREBOX_MAGICVAR_NAMED(_name, _name, _description)
#else
+#define BAREBOX_MAGICVAR_NAMED(_name, _varname, _description)
#define BAREBOX_MAGICVAR(_name, _description)
#endif
diff --git a/include/net.h b/include/net.h
index 25d7b6e024..08f897e958 100644
--- a/include/net.h
+++ b/include/net.h
@@ -64,8 +64,13 @@ void eth_halt(void); /* stop SCC */
* board code for boards which store their MAC address at some unusual
* place.
*/
+#if !defined(CONFIG_NET)
+static inline void eth_register_ethaddr(int ethid, const char *ethaddr)
+{
+}
+#else
void eth_register_ethaddr(int ethid, const char *ethaddr);
-
+#endif
/*
* Ethernet header
*/
diff --git a/include/param.h b/include/param.h
index e7b66a4d68..a855102d15 100644
--- a/include/param.h
+++ b/include/param.h
@@ -14,7 +14,6 @@ struct param_d {
int (*set)(struct device_d *, struct param_d *param, const char *val);
unsigned int flags;
char *name;
- struct param_d *next;
char *value;
struct list_head list;
};
diff --git a/include/partition.h b/include/partition.h
index 4eac8de86b..0827bb40c6 100644
--- a/include/partition.h
+++ b/include/partition.h
@@ -3,9 +3,6 @@
struct device_d;
-#define PARTITION_FIXED (1 << 0)
-#define PARTITION_READONLY (1 << 1)
-
struct partition {
int num;
diff --git a/include/qsort.h b/include/qsort.h
new file mode 100644
index 0000000000..bbb23595b2
--- /dev/null
+++ b/include/qsort.h
@@ -0,0 +1,7 @@
+#ifndef __QSORT_H
+#define __QSORT_H
+
+void qsort(void *base, size_t nel, size_t width,
+ int (*comp)(const void *, const void *));
+
+#endif /* __QSORT_H */
diff --git a/include/usb/usb.h b/include/usb/usb.h
index a61a00865e..296e4e8ea8 100644
--- a/include/usb/usb.h
+++ b/include/usb/usb.h
@@ -38,7 +38,7 @@
#define USB_MAX_DEVICE 32
#define USB_MAXCONFIG 8
-#define USB_MAXINTERFACES 8
+#define USB_MAXINTERFACES 16
#define USB_MAXENDPOINTS 16
#define USB_MAXCHILDREN 8 /* This is arbitrary */
#define USB_MAX_HUB 16
diff --git a/lib/Kconfig b/lib/Kconfig
index f886e6e2a5..3bcde5c1ff 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -35,4 +35,7 @@ config BCH
config BITREV
bool
+config QSORT
+ bool
+
endmenu
diff --git a/lib/Makefile b/lib/Makefile
index 01a01b5966..4e6b1ee90d 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -33,3 +33,4 @@ obj-$(CONFIG_FDT) += fdt/
obj-$(CONFIG_UNCOMPRESS) += uncompress.o
obj-$(CONFIG_BCH) += bch.o
obj-$(CONFIG_BITREV) += bitrev.o
+obj-$(CONFIG_QSORT) += qsort.o
diff --git a/lib/glob.c b/lib/glob.c
index 74d2b123e3..c4c60674b6 100644
--- a/lib/glob.c
+++ b/lib/glob.c
@@ -22,6 +22,7 @@ Cambridge, MA 02139, USA. */
#include <malloc.h>
#include <xfuncs.h>
#include <fnmatch.h>
+#include <qsort.h>
#define _GNU_SOURCE
#include <glob.h>
@@ -75,12 +76,10 @@ int glob_pattern_p(const char *pattern, int quote)
#ifdef CONFIG_GLOB_SORT
/* Do a collated comparison of A and B. */
-static int collated_compare(a, b)
-const __ptr_t a;
-const __ptr_t b;
+static int collated_compare(const void *a, const void *b)
{
- const char *const s1 = *(const char *const *)a;
- const char *const s2 = *(const char *const *)b;
+ const char *s1 = a;
+ const char *s2 = b;
if (s1 == s2)
return 0;
@@ -266,7 +265,7 @@ int glob(const char *pattern, int flags,
/* Sort the vector. */
qsort((__ptr_t) & pglob->gl_pathv[oldcount],
pglob->gl_pathc - oldcount,
- sizeof(char *), (__compar_fn_t) collated_compare);
+ sizeof(char *), collated_compare);
#endif
status = 0;
out:
diff --git a/lib/make_directory.c b/lib/make_directory.c
index 274bc146cf..c14c86d45b 100644
--- a/lib/make_directory.c
+++ b/lib/make_directory.c
@@ -12,6 +12,7 @@ int make_directory(const char *dir)
char *s = strdup(dir);
char *path = s;
char c;
+ int ret = 0;
do {
c = 0;
@@ -33,12 +34,10 @@ int make_directory(const char *dir)
/* If we failed for any other reason than the directory
* already exists, output a diagnostic and return -1.*/
-#ifdef __BAREBOX__
- if (errno != -EEXIST)
-#else
- if (errno != EEXIST)
-#endif
+ if (errno != EEXIST) {
+ ret = -errno;
break;
+ }
}
if (!c)
goto out;
@@ -50,7 +49,9 @@ int make_directory(const char *dir)
out:
free(path);
- return errno;
+ if (ret)
+ errno = -ret;
+ return ret;
}
#ifdef __BAREBOX__
EXPORT_SYMBOL(make_directory);
diff --git a/lib/parameter.c b/lib/parameter.c
index baf7720cb4..b2b8d945a6 100644
--- a/lib/parameter.c
+++ b/lib/parameter.c
@@ -54,7 +54,7 @@ const char *dev_get_param(struct device_d *dev, const char *name)
struct param_d *param = get_param_by_name(dev, name);
if (!param) {
- errno = -EINVAL;
+ errno = EINVAL;
return NULL;
}
@@ -87,26 +87,30 @@ int dev_set_param_ip(struct device_d *dev, char *name, IPaddr_t ip)
int dev_set_param(struct device_d *dev, const char *name, const char *val)
{
struct param_d *param;
+ int ret;
if (!dev) {
- errno = -ENODEV;
+ errno = ENODEV;
return -ENODEV;
}
param = get_param_by_name(dev, name);
if (!param) {
- errno = -EINVAL;
+ errno = EINVAL;
return -EINVAL;
}
if (param->flags & PARAM_FLAG_RO) {
- errno = -EACCES;
+ errno = EACCES;
return -EACCES;
}
- errno = param->set(dev, param, val);
- return errno;
+ ret = param->set(dev, param, val);
+ if (ret)
+ errno = -ret;
+
+ return ret;
}
/**
@@ -135,7 +139,7 @@ int dev_param_set_generic(struct device_d *dev, struct param_d *p,
static const char *param_get_generic(struct device_d *dev, struct param_d *p)
{
- return p->value;
+ return p->value ? p->value : "";
}
static struct param_d *__dev_add_param(struct device_d *dev, const char *name,
diff --git a/lib/qsort.c b/lib/qsort.c
new file mode 100644
index 0000000000..f64871489d
--- /dev/null
+++ b/lib/qsort.c
@@ -0,0 +1,79 @@
+/*
+ * Code adapted from uClibc-0.9.30.3
+ *
+ * It is therefore covered by the GNU LESSER GENERAL PUBLIC LICENSE
+ * Version 2.1, February 1999
+ *
+ * Wolfgang Denk <wd@denx.de>
+ */
+
+/* This code is derived from a public domain shell sort routine by
+ * Ray Gardner and found in Bob Stout's snippets collection. The
+ * original code is included below in an #if 0/#endif block.
+ *
+ * I modified it to avoid the possibility of overflow in the wgap
+ * calculation, as well as to reduce the generated code size with
+ * bcc and gcc. */
+
+#include <linux/types.h>
+#include <common.h>
+#include <qsort.h>
+
+void qsort(void *base,
+ size_t nel,
+ size_t width,
+ int (*comp)(const void *, const void *))
+{
+ size_t wgap, i, j, k;
+ char tmp;
+
+ if (nel < 2 || width == 0)
+ return;
+
+ /* check for overflow */
+ if (nel <= ((size_t)(-1)) / width)
+ return;
+
+ wgap = 0;
+ do {
+ wgap = 3 * wgap + 1;
+ } while (wgap < (nel - 1) / 3);
+
+ /*
+ * From the above, we know that either wgap == 1 < nel or
+ * ((wgap-1) / 3 < (int) ((nel - 1) / 3) <= (nel - 1) / 3 ==> wgap < nel.
+ */
+ wgap *= width; /* So this can not overflow if wnel doesn't. */
+ nel *= width; /* Convert nel to 'wnel' */
+ do {
+ i = wgap;
+ do {
+ j = i;
+ do {
+ char *a;
+ char *b;
+
+ j -= wgap;
+ a = j + ((char *)base);
+ b = a + wgap;
+
+ if (comp(a, b) <= 0)
+ break;
+
+ k = width;
+ do {
+ tmp = *a;
+ *a++ = *b;
+ *b++ = tmp;
+ } while (--k);
+ } while (j >= wgap);
+ i += width;
+ } while (i < nel);
+ wgap = (wgap - width) / 3;
+ } while (wgap);
+}
+
+int strcmp_compar(const void *p1, const void *p2)
+{
+ return strcmp((const char *)p1, (const char *)p2);
+}
diff --git a/scripts/Makefile b/scripts/Makefile
index cb049fd6df..784d205023 100644
--- a/scripts/Makefile
+++ b/scripts/Makefile
@@ -10,6 +10,7 @@ hostprogs-y += mkimage
hostprogs-y += bareboxenv
hostprogs-$(CONFIG_ARCH_NETX) += gen_netx_image
hostprogs-$(CONFIG_ARCH_OMAP) += omap_signGP
+hostprogs-$(CONFIG_ARCH_S5PCxx) += s5p_cksum
always := $(hostprogs-y) $(hostprogs-m)
diff --git a/scripts/bareboxenv.c b/scripts/bareboxenv.c
index b0d5818bac..866e345b9b 100644
--- a/scripts/bareboxenv.c
+++ b/scripts/bareboxenv.c
@@ -34,6 +34,8 @@
#include <getopt.h>
#include <libgen.h>
+#include "compiler.h"
+
#define debug(...)
void *xmalloc(size_t size)
diff --git a/scripts/compiler.h b/scripts/compiler.h
index f4b1432355..53f84b6d1b 100644
--- a/scripts/compiler.h
+++ b/scripts/compiler.h
@@ -45,6 +45,9 @@
# include <byteswap.h>
#elif defined(__MACH__)
# include <machine/endian.h>
+# define __BYTE_ORDER BYTE_ORDER
+# define __LITTLE_ENDIAN LITTLE_ENDIAN
+# define __BIG_ENDIAN BIG_ENDIAN
typedef unsigned long ulong;
typedef unsigned int uint;
#endif
diff --git a/scripts/genenv b/scripts/genenv
index 7b279c8e6e..c84af0c015 100755
--- a/scripts/genenv
+++ b/scripts/genenv
@@ -8,7 +8,7 @@ objtree=$2
cd $1 || exit 1
shift 2
-tempdir=$(mktemp -d)
+tempdir=$(mktemp -d tmp.XXXXXX)
for i in $*; do
cp -r $i/* $tempdir
diff --git a/scripts/mod/modpost.c b/scripts/mod/modpost.c
index e99448602c..795ee8d09b 100644
--- a/scripts/mod/modpost.c
+++ b/scripts/mod/modpost.c
@@ -604,7 +604,7 @@ static int strrcmp(const char *s, const char *sub)
* Whitelist to allow certain references to pass with no warning.
*
* Pattern 0:
- * Do not warn if funtion/data are marked with __init_refok/__initdata_refok.
+ * Do not warn if function/data are marked with __init_refok/__initdata_refok.
* The pattern is identified by:
* fromsec = .text.init.refok | .data.init.refok
*
diff --git a/scripts/mod/modpost.h b/scripts/mod/modpost.h
index 0c23259836..497d614118 100644
--- a/scripts/mod/modpost.h
+++ b/scripts/mod/modpost.h
@@ -17,7 +17,7 @@
#define Elf_Shdr Elf32_Shdr
#define Elf_Sym Elf32_Sym
#define Elf_Addr Elf32_Addr
-#define Elf_Section Elf32_Section
+#define Elf_Section Elf32_Half
#define ELF_ST_BIND ELF32_ST_BIND
#define ELF_ST_TYPE ELF32_ST_TYPE
@@ -31,7 +31,7 @@
#define Elf_Shdr Elf64_Shdr
#define Elf_Sym Elf64_Sym
#define Elf_Addr Elf64_Addr
-#define Elf_Section Elf64_Section
+#define Elf_Section Elf64_Half
#define ELF_ST_BIND ELF64_ST_BIND
#define ELF_ST_TYPE ELF64_ST_TYPE
diff --git a/scripts/s5p_cksum.c b/scripts/s5p_cksum.c
new file mode 100644
index 0000000000..7142532875
--- /dev/null
+++ b/scripts/s5p_cksum.c
@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) 2012 Alexey Galakhov
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stddef.h>
+#include <errno.h>
+
+#define DEFAULT_BUF_SIZE 8192
+
+static int usage(const char* me)
+{
+ printf("Usage: %s <input> <output> [<bufsize]\n", me);
+ return 1;
+}
+
+static void put32(uint8_t *ptr, uint32_t value)
+{
+ ptr[0] = value & 0xFF;
+ ptr[1] = (value >> 8) & 0xFF;
+ ptr[2] = (value >> 16) & 0xFF;
+ ptr[3] = (value >> 24) & 0xFF;
+}
+
+static size_t safe_fread(void *buf, size_t len, FILE* file)
+{
+ size_t rd = fread(buf, 1, len, file);
+ if (! rd) {
+ if (ferror(file))
+ fprintf(stderr, "Error reading file: %s\n", strerror(errno));
+ else
+ fprintf(stderr, "Unexpected end of file\n");
+ }
+ return rd;
+}
+
+static size_t safe_fwrite(const void *buf, size_t len, FILE* file)
+{
+ size_t wr = fwrite(buf, 1, len, file);
+ if (wr != len) {
+ fprintf(stderr, "Error writing file: %s\n", strerror(errno));
+ return 0;
+ }
+ return wr;
+}
+
+static int process(FILE *input, FILE *output, uint8_t *buf, unsigned bufsize)
+{
+ size_t rd;
+ unsigned i;
+ uint32_t cksum;
+ /* Read first chunk */
+ rd = safe_fread(buf + 16, bufsize - 16, input);
+ if (! rd)
+ return 4;
+ /* Calculate header */
+ put32(buf + 0, bufsize);
+ cksum = 0;
+ for (i = 16; i < bufsize; ++i)
+ cksum += (uint32_t)buf[i];
+ put32(buf + 8, cksum);
+ if (! safe_fwrite(buf, bufsize, output))
+ return 4;
+ /* Copy the rest of file */
+ while (! feof(input)) {
+ rd = safe_fread(buf, bufsize, input);
+ if (! rd)
+ return 4;
+ if (! safe_fwrite(buf, rd, output))
+ return 4;
+ }
+ return 0;
+}
+
+static int work(const char* me, const char *infile, const char *outfile, unsigned bufsize)
+{
+ uint8_t *buf;
+ FILE *input;
+ FILE *output;
+ int ret;
+ if (bufsize < 512 || bufsize > 65536)
+ return usage(me);
+ buf = calloc(1, bufsize);
+ if (! buf) {
+ fprintf(stderr, "Unable to allocate %u bytes of memory\n", bufsize);
+ return 2;
+ }
+ input = fopen(infile, "r");
+ if (! input) {
+ fprintf(stderr, "Cannot open `%s' for reading\n", infile);
+ free(buf);
+ return 3;
+ }
+ output = fopen(outfile, "w");
+ if (! output) {
+ fprintf(stderr, "Cannot open `%s' for writing\n", outfile);
+ fclose(input);
+ free(buf);
+ return 3;
+ }
+
+ ret = process(input, output, buf, bufsize);
+
+ fclose(output);
+ fclose(input);
+ free(buf);
+ return ret;
+}
+
+int main(int argc, char** argv)
+{
+ switch (argc) {
+ case 3:
+ return work(argv[0], argv[1], argv[2], DEFAULT_BUF_SIZE);
+ case 4:
+ return work(argv[0], argv[1], argv[2], atoi(argv[3]));
+ default:
+ return usage(argv[0]);
+ }
+}