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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2013-12-12 16:34:14 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2013-12-20 09:35:38 +0100 |
| commit | 4e64bcac453bd7225bbd597a07c2fcc4bd40e20e (patch) | |
| tree | 1eb74754e9197e928a7b7de328681b7476ace7b8 | |
| parent | 53bbcf85aabe581f8e42877d898f661286d87927 (diff) | |
| download | barebox-4e64bcac453bd7225bbd597a07c2fcc4bd40e20e.tar.gz barebox-4e64bcac453bd7225bbd597a07c2fcc4bd40e20e.tar.xz | |
video: ipufb: Allow to disable fractional pixelclock divider
The IPU has a fractional pixelclock divider. When used, this produces
clock jitter which especially LVDS transceivers can't handle. Allow
to disable it via platform_data.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| -rw-r--r-- | arch/arm/mach-imx/include/mach/imx-ipu-fb.h | 5 | ||||
| -rw-r--r-- | drivers/video/imx-ipu-fb.c | 11 |
2 files changed, 14 insertions, 2 deletions
diff --git a/arch/arm/mach-imx/include/mach/imx-ipu-fb.h b/arch/arm/mach-imx/include/mach/imx-ipu-fb.h index 43b3bda98b..ee1a9b5839 100644 --- a/arch/arm/mach-imx/include/mach/imx-ipu-fb.h +++ b/arch/arm/mach-imx/include/mach/imx-ipu-fb.h @@ -47,6 +47,11 @@ struct imx_ipu_fb_platform_data { void __iomem *framebuffer_ovl; /** hook to enable backlight and stuff */ void (*enable)(int enable); + /* + * Fractional pixelclock divider causes jitter which some displays + * or LVDS transceivers can't handle. Disable it if necessary. + */ + int disable_fractional_divider; }; #endif /* __MACH_IMX_IPU_FB_H__ */ diff --git a/drivers/video/imx-ipu-fb.c b/drivers/video/imx-ipu-fb.c index 8b43515801..2e65fdefa8 100644 --- a/drivers/video/imx-ipu-fb.c +++ b/drivers/video/imx-ipu-fb.c @@ -43,6 +43,7 @@ struct ipu_fb_info { struct device_d *dev; unsigned int alpha; + int disable_fractional_divider; }; /* IPU DMA Controller channel definitions. */ @@ -409,7 +410,7 @@ static int sdc_init_panel(struct fb_info *info, enum disp_data_mapping fmt) struct fb_videomode *mode = info->mode; u32 reg, old_conf, div; enum ipu_panel panel = IPU_PANEL_TFT; - unsigned long pixel_clk; + unsigned long pixel_clk, rate; /* Init panel size and blanking periods */ reg = ((mode->hsync_len - 1) << 26) | @@ -466,7 +467,12 @@ static int sdc_init_panel(struct fb_info *info, enum disp_data_mapping fmt) * i.MX31 it (HSP_CLK) is <= 178MHz. Currently 128.267MHz */ pixel_clk = PICOS2KHZ(mode->pixclock) * 1000UL; - div = clk_get_rate(fbi->clk) * 16 / pixel_clk; + rate = clk_get_rate(fbi->clk); + + if (fbi->disable_fractional_divider) + div = DIV_ROUND_CLOSEST(rate, pixel_clk) * 16; + else + div = rate * 16 / pixel_clk; if (div < 0x40) { /* Divider less than 4 */ dev_dbg(&info->dev, @@ -1000,6 +1006,7 @@ static int imxfb_probe(struct device_d *dev) fbi->dev = dev; fbi->enable = pdata->enable; fbi->disp_data_fmt = pdata->disp_data_fmt; + fbi->disable_fractional_divider = pdata->disable_fractional_divider; info->priv = fbi; info->fbops = &imxfb_ops; info->num_modes = pdata->num_modes; |