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authorSascha Hauer <s.hauer@pengutronix.de>2017-01-19 10:30:22 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2017-01-20 09:10:30 +0100
commit595da7d68cb6a6826e6aceb690cbd6f0fc77d69a (patch)
treeeb02bbdb779fec9d5652fb0e7e2a57a5d2c6f70e
parenteb101add591bfdf531e125df4e665047de108896 (diff)
downloadbarebox-595da7d68cb6a6826e6aceb690cbd6f0fc77d69a.tar.gz
ARM: i.MX7: initialize architected timer
This is the same that U-Boot does. The registers are not documented. Without this the architected timer on the i.MX7 does not work. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--arch/arm/mach-imx/imx7.c35
1 files changed, 35 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/imx7.c b/arch/arm/mach-imx/imx7.c
index fde66d8..ca094fe 100644
--- a/arch/arm/mach-imx/imx7.c
+++ b/arch/arm/mach-imx/imx7.c
@@ -46,6 +46,39 @@ void imx7_init_lowlevel(void)
writel(0, aips2 + 0x50);
}
+#define SC_CNTCR 0x0
+#define SC_CNTSR 0x4
+#define SC_CNTCV1 0x8
+#define SC_CNTCV2 0xc
+#define SC_CNTFID0 0x20
+#define SC_CNTFID1 0x24
+#define SC_CNTFID2 0x28
+#define SC_counterid 0xfcc
+
+#define SC_CNTCR_ENABLE (1 << 0)
+#define SC_CNTCR_HDBG (1 << 1)
+#define SC_CNTCR_FREQ0 (1 << 8)
+#define SC_CNTCR_FREQ1 (1 << 9)
+
+static int imx7_timer_init(void)
+{
+ void __iomem *sctr = IOMEM(MX7_SCTR_BASE_ADDR);
+ unsigned long val, freq;
+
+ freq = 8000000;
+ asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
+
+ writel(freq, sctr + SC_CNTFID0);
+
+ /* Enable system counter */
+ val = readl(sctr + SC_CNTCR);
+ val &= ~(SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1);
+ val |= SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG;
+ writel(val, sctr + SC_CNTCR);
+
+ return 0;
+}
+
int imx7_init(void)
{
const char *cputypestr;
@@ -53,6 +86,8 @@ int imx7_init(void)
imx7_init_lowlevel();
+ imx7_timer_init();
+
imx7_boot_save_loc();
imx7_silicon_revision = imx7_cpu_revision();